Pixel circuit

Abstract

A pixel circuit is provided. The pixel circuit includes a light emitting element, a reference capacitor, a reset circuit, an input circuit, and a drive circuit. The reference capacitor is coupled between a first node and a second node. The reset circuit is coupled to the first node. The reset circuit provides a first reference bias to the first node during a reset period. The input circuit is coupled to the second node. The input circuit provides a second reference bias to the second node during the reset period and provides a data voltage during a data input period. A control terminal of a drive transistor of the drive circuit is coupled to the first node. The drive circuit compensates a voltage value at the first node using the drive transistor and a drive voltage during a compensation period. The drive circuit drives the light emitting element according to the data voltage and the drive voltage during a light emitting period.

Description

Technical Field

[0001] This invention relates to a pixel circuit, and more particularly to a pixel circuit with a compensation function. Background Technology

[0002] Each pixel circuit in a current display device includes a driving circuit and a light-emitting element. The light-emitting element can be any type of light-emitting diode (LED). The driving circuit drives the light-emitting element based on a light-emitting enable signal. However, the driving transistor in the driving circuit has a threshold voltage (Vth) value. Due to differences in manufacturing processes, the threshold voltage values ​​of the driving transistors in the multiple pixel circuits of the display device may differ. Therefore, in order to improve the light emission uniformity of the display device, the driving circuit must compensate the voltage value at the control terminal of the driving transistor according to the threshold voltage value of the driving transistor.

[0003] Please also refer to Figure 1 as well as Figure 2 , Figure 1 This is the circuit diagram of the current pixel circuit. Figure 2 It is based on Figure 1The signal timing diagram is shown. Pixel circuit 10 includes a light-emitting element LE, transistors T1 to T9, and capacitors C1 and C2. The first terminal of transistor T1 is coupled to the driving voltage VDD. The second terminal of transistor T1 is coupled to node P. The control terminal of transistor T1 receives the light-emitting enable signal EM(n). Transistor T2 is the driving transistor in pixel circuit 10. The first terminal of transistor T2 is coupled to node P. The first terminal of transistor T3 is coupled to the second terminal of transistor T2. The second terminal of transistor T3 is coupled to the control terminal of transistor T2. The control terminal of transistor T3 receives the scan signal SN(n). The first terminal of transistor T4 is coupled to the second terminal of transistor T2. The second terminal of transistor T4 is coupled to the anode of the light-emitting element LE. The control terminal of transistor T4 receives the light-emitting enable signal EM(n). The first terminal of transistor T5 is coupled to the control terminal of transistor T2. The second terminal of transistor T5 is coupled to the reference voltage VREF1. The control terminal of transistor T5 receives the scan signal SN(n-1). Capacitor C1 is coupled between the control terminal of transistor T2 and node Q. Capacitor C2 is coupled between node P and node Q. The first terminal of transistor T6 is coupled to node Q. The second terminal of transistor T6 is coupled to the reference voltage VREF1. The control terminal of transistor T6 receives the scan signal SN(n-1). The first terminal of transistor T7 is coupled to node Q. The second terminal of transistor T7 is coupled to the reference voltage VREF1. The control terminal of transistor T7 receives the scan signal SN(n). The first terminal of transistor T8 receives the data voltage VDATA. The second terminal of transistor T8 is coupled to node Q. The control terminal of transistor T8 receives the scan signal SN(n+1). The first terminal of transistor T9 is coupled to the reference voltage VREF2. The second terminal of transistor T8 is coupled to node P. The control terminal of transistor T8 receives the auxiliary scan signal VC(n).

[0004] Based on such Figure 2 During the reset period PR, the voltage values ​​at node P, node Q, and the control terminal Vg of transistor T2 are reset. During the compensation period PC, the voltage value Vg at the control terminal of transistor T2 is equal to the voltage difference between the reference voltage VREF2 and the critical voltage value of transistor T2. That is, Vg = Vr2 - |Vth|. “Vr2” is the voltage value of the reference voltage VREF2. “Vth” is the critical voltage value of transistor T2. During the data input period PD, the voltage value Vg at the control terminal of transistor T2 is as shown in formula (1).

[0005] Vg=Vr2-|Vth|+(Vd-Vr1)×Cc1 / (Cc1+Ct1)…Formula (1)

[0006] “Vd” is the data voltage VDATA. “Vr1” is the reference voltage VREF1. “Cc1” is the capacitance of capacitor C1. “Ct1” is the calibration capacitance at the control terminal of transistor T2.

[0007] During the light emission period TE, the voltage value Vg at the control terminal of transistor T2 is as shown in formula (2).

[0008] Vg=Vr2-|Vth|+(Vd-Vr1)×Cc1 / (Cc1+Ct1)+(vVDD-Vr2)×Cc2 / (Cc1+Cc2+Ct2)×Cc1 / (Cc1+Ct1)…Formula (2)

[0009] “vVDD” is the driving voltage VDD. “Vr1” is the reference voltage VREF1. “Cc2” is the capacitance of capacitor C2. “Ct2” is the calibrated capacitance at node Q.

[0010] Pixel circuit 10 can eliminate the critical voltage value of transistor T2 based on the compensation in formula (2). It should be noted that the equivalent capacitance value at the control terminal of transistor T2 (i.e., equivalent capacitance value Ct1) and the equivalent capacitance value at node Q (i.e., equivalent capacitance value Ct2) are generated. Therefore, to eliminate the equivalent capacitance value at the control terminal of transistor T2 and the equivalent capacitance value at node Q, the areas of capacitors C1 and C2 must be increased. In fact, Cc2 / (Cc1+Cc2+Ct2) in formula (2) cannot be equal to 1 or 0. Therefore, the equivalent capacitance value at the control terminal of transistor T2 and the equivalent capacitance value at node Q cannot be significantly eliminated (or ignored). Therefore, pixel circuit 10 cannot provide accurate compensation. Thus, the equivalent capacitance value at the control terminal of transistor T2 and the equivalent capacitance value at node Q still affect the operation of transistor T2. Pixel circuit cannot provide accurate compensation.

[0011] Therefore, how to provide pixel circuits with accurate compensation functions is one of the key research focuses for those skilled in the art. Summary of the Invention

[0012] This invention provides a pixel circuit with precise compensation function.

[0013] The pixel circuit of the present invention includes a light-emitting element, a reference capacitor, a reset circuit, an input circuit, and a driving circuit. The reference capacitor is coupled between a first node and a second node. The reset circuit is coupled to the first node. During reset, the reset circuit provides a first reference bias voltage to the first node. The input circuit is coupled to the second node. During reset, the input circuit provides a second reference bias voltage to the second node and provides a data voltage during data input. The driving circuit is coupled to the driving voltage, the first node, and the light-emitting element. The driving circuit includes a driving transistor. The control terminal of the driving transistor is coupled to the first node. During a compensation period after the reset period, the driving circuit uses the driving transistor and the driving voltage to compensate for the voltage value at the first node. During the data input period after the compensation period, the input circuit provides a data voltage to the second node. During the light-emitting period, the driving circuit drives the light-emitting element according to the data voltage and the driving voltage.

[0014] Based on the above, the pixel circuit includes a single capacitor (i.e., a reference capacitor). This allows the influence of the calibration capacitance value located at the first node to be significantly reduced. The calibration capacitance value located at the first node is ignored. In this way, the pixel circuit can provide accurate compensation functionality. Attached Figure Description

[0015] Figure 1 This is the circuit diagram of the current pixel circuit.

[0016] Figure 2 It is based on Figure 1 The signal timing diagram shown is shown.

[0017] Figure 3 This is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

[0018] Figure 4 This is a circuit diagram of the pixel circuit shown according to the first embodiment of the present invention.

[0019] Figure 5 It is based on Figure 4 The signal timing diagram of the pixel circuit is shown.

[0020] Figure 6 This is a circuit diagram of the pixel circuit shown according to the second embodiment of the present invention.

[0021] Figure 7 It is based on Figure 6 The signal timing diagram of the pixel circuit is shown.

[0022] Figure 8 It is based on Figure 4 The circuit diagram of the shift register unit is shown.

[0023] Figure 9 It is based on Figure 6The circuit diagram of the shift register unit is shown.

[0024] Explanation of reference numerals in the attached figures:

[0025] 10, 100, 200, 300: Pixel circuit

[0026] 110, 210: Reset circuit

[0027] 120, 220, 320: Input circuit

[0028] 130, 230: Drive circuit

[0029] A(n), B(n), P, Q: Nodes

[0030] C1, C2, CB, CC1, CC2: Capacitors

[0031] CA: Reference capacitor

[0032] CK1, CK3: Clock signals

[0033] EM(n): Light emission enable signal

[0034] LE: Light-emitting element

[0035] PC: Compensation Period

[0036] PD: During data input

[0037] PE: During luminescence

[0038] PR: During the reset

[0039] SN(n-1), SN(n), SN(n+1): Scan signals

[0040] SR(n): Shift register unit

[0041] T1~T9, TS1~TS8: Transistors

[0042] TB1, TB2: Bias transistors

[0043] TC1, TC2: Compensation transistors

[0044] TD: Driving transistor

[0045] TE1, TE2: Enable transistors

[0046] TI: Input Transistor

[0047] tp1~tp6: Time points

[0048] TR: Reset transistor

[0049] V1: Voltage difference

[0050] V2: Operating voltage value

[0051] VC(n-1), VC(n): Auxiliary scanning signals

[0052] VDATA: Data voltage

[0053] VDD, VSS: Drive voltage

[0054] VGH, VGL: Gate voltages

[0055] VREF1: First reference bias voltage

[0056] VREF2: Second reference bias Detailed Implementation

[0057] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description, when appearing in different drawings, are considered to be the same or similar components. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples within the scope of the present invention's patent application.

[0058] Please refer to Figure 3 , Figure 3 This is a schematic diagram of a pixel circuit according to a first embodiment of the present invention. In this embodiment, the pixel circuit 100 includes a light-emitting element LE, a reference capacitor CA, a reset circuit 110, an input circuit 120, and a driving circuit 130. The light-emitting element LE can be any form of light-emitting diode element. The light-emitting element LE may include, for example, an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro light-emitting diode (micro LED), or a quantum dot light-emitting diode (quantum dot LED). The anode of the light-emitting element LE is coupled to the driving circuit 130. The cathode of the light-emitting element LE is coupled to the driving voltage VSS.

[0059] In this embodiment, a reference capacitor CA is coupled between nodes P and Q. A reset circuit 110 is coupled to node P. During reset, the reset circuit 110 provides a first reference bias voltage VREF1 to node P. An input circuit 120 is coupled to node Q. During reset, the input circuit 120 provides a second reference bias voltage VREF2 to node Q. During data input, the input circuit 120 provides a data voltage VDATA.

[0060] In this embodiment, the driving circuit 130 is coupled to the driving voltage VDD, node P, and the light-emitting element LE. The driving circuit 130 includes a driving transistor TD. The control terminal of the driving transistor TD is coupled to node P. During the compensation period, the driving circuit 130 uses the driving transistor TD and the driving voltage VDD to compensate for the voltage value at node P. In this embodiment, the compensation period is after the reset period. The input circuit 120 provides a data voltage VDATA to node Q during the data input period. In this embodiment, the data input period is after the compensation period. Furthermore, during the light-emitting period, the driving circuit 130 drives the light-emitting element LE according to the data voltage VDATA and the driving voltage VDD.

[0061] It is worth mentioning that the pixel circuit 100 includes a single capacitor (i.e., a reference capacitor CA). Using the reference capacitor CA, the influence of the calibration capacitance value at node P can be significantly reduced. The calibration capacitance value at node P (i.e., the calibration capacitance value at the control terminal of the driving transistor TD) is ignored. In this way, the pixel circuit 100 can provide accurate compensation functionality.

[0062] In this embodiment, the driving transistor TD is implemented as a P-type field-effect transistor (FET). However, this invention is not limited to the FET form of this embodiment. The driving transistor TD of this invention can be implemented using any form of FET.

[0063] In this embodiment, during the compensation period, the voltage value at node P is the voltage difference V1 between the absolute value of the driving voltage VDD and the critical voltage value of the driving transistor TD. Specifically, during the compensation period, the voltage value at node P is as shown in formula (3).

[0064] Vg=vVDD-|Vth|=V1…Formula (3)

[0065] “Vg” is the voltage value at node P, which is also the voltage value at the control terminal of the driving transistor TD. “vVDD” is the driving voltage VDD. “Vth” is the critical voltage value of the driving transistor TD.

[0066] During data input, the voltage at node P is the sum of the voltage difference V1 and the operating voltage V2. The operating voltage V2 is generated based on the data voltage VDATA, the second reference bias voltage VREF2, the capacitance of the reference capacitor CA, and the equalization capacitance at node P.

[0067] Specifically, during the data input period, the operating voltage value V2 is as shown in formula (4).

[0068] V2=(Vd-Vr2)×Cc1 / (Cc1+Ct1)…Formula (4)

[0069] “Vd” is the data voltage VDATA. “Vr2” is the reference voltage VREF2. “Cc1” is the capacitance of capacitor C1. “Ct1” is the calibration capacitance at node P. “Ct1” is also the calibration capacitance at the control terminal of the driving transistor TD.

[0070] Therefore, the voltage value at node P is as shown in formula (5).

[0071] Vg=V1+V2=(vVDD-|Vth|)+(Vd-Vr2)×Cc1 / (Cc1+Ct1)…Formula (5)

[0072] Furthermore, during the light emission period, the driving circuit 130 uses the voltage value generated by formula (6) to drive the light-emitting element LE.

[0073] Vdr=V1+V2-vVDD-Vth=V2…Formula(6)

[0074] "Vdr" is the voltage value at which the driving circuit 130 drives the light-emitting element LE. It should be noted that in this embodiment, the threshold voltage value of the driving transistor TD is negative. Therefore, the driving circuit 130 drives the light-emitting element LE according to the operating voltage value V2. The influence of the driving voltage VDD and the threshold voltage value of the driving transistor TD is reduced. In other words, the pixel circuit 100 is not affected by changes in the driving voltage VDD and the threshold voltage value of the driving transistor TD, thus preventing the light-emitting element LE from emitting light.

[0075] It should also be noted that, as shown in Equation (4), the operating voltage value V2 is related to the data voltage VDATA, the second reference bias voltage VREF2, the capacitance of the reference capacitor CA, and the calibrating capacitance at node P. Furthermore, the capacitance of the reference capacitor CA is designed to be significantly larger than the calibrating capacitance at node P. Therefore, the calibrating capacitance at node P can be ignored.

[0076] Please refer to Figure 4 , Figure 4This is a circuit diagram of a pixel circuit according to a first embodiment of the present invention. In this embodiment, the pixel circuit 200 includes a light-emitting element LE, a reference capacitor CA, a reset circuit 210, an input circuit 220, and a driving circuit 230. The reference capacitor CA is coupled between node P and node Q. The reset circuit 210 includes a reset transistor TR. A first terminal of the reset transistor TR is coupled to node P. A second terminal of the reset transistor TR is coupled to a first reference bias voltage VREF1. The control terminal of the reset transistor TR receives a scan signal SN(n-1) (or, the first scan signal). In this embodiment, the reset transistor TR is turned on during reset in response to pulses of the scan signal SN(n-1).

[0077] Input circuit 220 includes an input transistor TI. A first terminal of the input transistor TI receives a data voltage VDATA. A second terminal of the input transistor TI is coupled to node Q. A control terminal of the input transistor TI receives a scan signal SN(n+1) (or, a second scan signal). In this embodiment, the input transistor TI is turned on during data input in response to pulses of the scan signal SN(n+1) to provide the data voltage VDATA to node Q.

[0078] The input circuit 220 also includes a bias transistor TB1. A first terminal of the bias transistor TB1 is coupled to a second reference bias voltage VREF2. A second terminal of the bias transistor TB1 is coupled to node Q. The control terminal of the bias transistor TB1 receives an auxiliary scan signal VC(n-1). The bias transistor TB1 is turned on in response to the auxiliary scan signal VC(n-1) during reset and compensation periods to provide the second reference bias voltage VREF2 to node Q.

[0079] The input circuit 220 also includes a capacitor CB. The capacitor CB is coupled between the second reference bias voltage VREF2 and node Q. The capacitor CB is used to maintain the voltage difference between the second reference bias voltage VREF2 and node Q. However, the present invention is not limited to the capacitor CB coupling method of this embodiment. One end of the capacitor CB of the present invention is coupled to node Q. The other end of the capacitor CB can be coupled to any voltage source. The voltage source can be one of the drive voltage VDD, VSS, the first reference bias voltage VREF1, and the second reference bias voltage VREF2. In some embodiments, the capacitor CB can be omitted.

[0080] In this embodiment, the driving circuit 230 includes a driving transistor TD, compensation transistors TC1 and TC2, and enable transistors TE1 and TE2. The control terminal of the driving transistor TD is coupled to node P. The first terminal of the compensation transistor TC1 is coupled to the driving voltage VDD. The second terminal of the compensation transistor TC1 is coupled to the first terminal of the driving transistor TD. The control terminal of the compensation transistor TC1 receives a scan signal SN(n) (or, the third scan signal). The first terminal of the compensation transistor TC2 is coupled to the second terminal of the driving transistor TD. The second terminal of the compensation transistor TC2 is coupled to the control terminal of the driving transistor TD. The control terminal of the compensation transistor TC2 receives the scan signal SN(n). The compensation transistors TC1 and TC2 are turned on during the compensation period in response to the pulses of the scan signal SN(n).

[0081] Taking this embodiment as an example, the scan signal SN(n-1) is the previous scan signal of the scan signal SN(n). The scan signal SN(n+1) is the next scan signal of the scan signal SN(n).

[0082] In this embodiment, the first terminal of enable transistor TE1 is coupled to the driving voltage VDD. The second terminal of enable transistor TE1 is coupled to the first terminal of driving transistor TD. The control terminal of enable transistor TE1 receives the light-emitting enable signal EM(n). The first terminal of enable transistor TE2 is coupled to the second terminal of driving transistor TD. The second terminal of enable transistor TE2 is coupled to the light-emitting element LE. The control terminal of enable transistor TE2 receives the light-emitting enable signal EM(n). In this embodiment, the second terminal of enable transistor TE2 is coupled to the anode of the light-emitting element LE. The cathode of the light-emitting element LE is coupled to the driving voltage VSS. Enable transistors TE1 and TE2 are turned on in response to the pulse of the light-emitting enable signal EM(n) during light emission.

[0083] In this embodiment, the driving voltage VDD can be the system high voltage. The driving voltage VSS can be the system low voltage.

[0084] In this embodiment, the reset transistor TR, input transistor TI, bias transistor TB1, drive transistor TD, compensation transistors TC1 and TC2, and enable transistors TE1 and TE2 are implemented using P-type FETs. This invention is not limited to the FET configuration of this embodiment.

[0085] Please also refer to Figure 4 as well as Figure 5 , Figure 5 It is based on Figure 4The signal timing diagram of the pixel circuit is shown. In this embodiment, at time point tp1, the auxiliary scan signal VC(n-1) begins to have a negative pulse. Therefore, the reset period PR begins. Between time points tp1 and tp3, the bias transistor TB1 is turned on in response to the negative pulse of the auxiliary scan signal VC(n-1). Therefore, the voltage value at node Q is approximately equal to the voltage value of the second reference bias voltage VREF2. During the reset period PR, between time points tp2 and tp3, the reset transistor TR is turned on in response to the negative pulse of the scan signal SN(n-1). Therefore, the voltage value at node P is approximately equal to the voltage value of the first reference bias voltage VREF1. Based on the above, during the reset period PR, the voltage value at node P is reset to the voltage value of the first reference bias voltage VREF1. The first reference bias voltage VREF1 is, for example, a low voltage value or a negative voltage value. The voltage value at node Q is reset to the voltage value of the second reference bias voltage VREF2.

[0086] At time tp3, the reset period PR ends. The reset transistor TR is turned off. During the compensation period PC between time tp3 and time tp4, the scan signal SN(n) has a negative pulse. Compensation transistors TC1 and TC2 are both turned on. Therefore, the drive circuit 230 uses the charging path formed by the compensation transistors TC1 and TC2 and the drive transistor TD to charge node P (i.e., the control terminal of the drive transistor TD). When the voltage value at node P satisfies formula (3), the drive transistor TD is turned off. Therefore, when the charging operation ends, the voltage value at node P is the voltage difference V1 between the drive voltage VDD and the critical voltage value of the drive transistor TD.

[0087] At time tp4, the compensation period PC ends. Bias transistor TB1 and compensation transistors TC1 and TC2 are turned off. During the data input period PD between time tp4 and time tp5, the scan signal SN(n+1) has a negative pulse. Therefore, input transistor TI is turned on. The turned-on input transistor TI provides the data voltage VDATA to node Q.

[0088] At time tp5, the data input period PD ends. The input transistor TI is turned off. During the light emission period PE between time tp5 and time tp6, the light emission enable signal EM(n) has a negative pulse. Enable transistors TE1 and TE2 are turned on. Therefore, the voltage value at node P satisfies formula (5). Thus, the drive circuit 230 drives the light-emitting element LE according to the operating voltage value (i.e., the operating voltage value V2 in formula (5)). The operating voltage value is shown in formula (4). When the capacitance value of the reference capacitor CA is designed to be significantly greater than the calibrated capacitance value at node P, the calibrated capacitance value at node P can be ignored.

[0089] It should be noted that the number of transistors coupled to node Q in this embodiment is less than [number missing]. Figure 1 The number of transistors coupled to node Q is shown. Therefore, in this embodiment, the equipotential capacitance value at node Q is low. Furthermore, the known capacitance value of capacitor CB in this embodiment is designed to be significantly larger than the parasitic capacitance values ​​of the input transistor TI and the bias transistor TB1 coupled to node Q. For example, the capacitance value of capacitor CB can be designed to be more than 100 times greater than the parasitic capacitance value. Therefore, the parasitic capacitance values ​​of the input transistor TI and the bias transistor TB1 can be ignored.

[0090] Please refer to Figure 6 , Figure 6 This is a circuit diagram of a pixel circuit according to a second embodiment of the present invention. In this embodiment, the pixel circuit 300 includes a light-emitting element LE, a reference capacitor CA, a reset circuit 210, an input circuit 320, and a driving circuit 230. In this embodiment, the implementation of the light-emitting element LE, the reference capacitor CA, the reset circuit 210, and the driving circuit 230 has already been described. Figure 4 The embodiments are clearly illustrated and will not be repeated here.

[0091] In this embodiment, the input circuit 320 includes an input transistor TI, bias transistors TB1 and TB2, and a capacitor CB. The first terminal of the input transistor TI receives the data voltage VDATA. The second terminal of the input transistor TI is coupled to node Q. The control terminal of the input transistor TI receives a scan signal SN(n+1). The first terminal of the bias transistor TB1 is coupled to a second reference bias voltage VREF2. The second terminal of the bias transistor TB1 is coupled to node Q. The control terminal of the bias transistor TB1 receives a scan signal SN(n-1). The first terminal of the bias transistor TB2 is coupled to the second reference bias voltage VREF2. The second terminal of the bias transistor TB2 is coupled to node Q. The control terminal of the bias transistor TB2 receives a scan signal SN(n). Bias transistor TB1 is turned on in response to the scan signal SN(n-1). Bias transistor TB2 is turned on in response to the scan signal SN(n). The capacitor CB is coupled between the second reference bias voltage VREF2 and node Q.

[0092] Please also refer to Figure 6 as well as Figure 7 , Figure 7 It is based on Figure 6The signal timing diagram of the pixel circuit is shown. In this embodiment, during the reset period PR at time points tp1 and tp2, the scan signal SN(n-1) has a negative pulse. The bias transistor TB1 and the reset transistor TR are turned on in response to the negative pulse of the scan signal SN(n-1). Therefore, the voltage value at node Q is approximately equal to the voltage value of the second reference bias voltage VREF2. The voltage value at node P is approximately equal to the voltage value of the first reference bias voltage VREF1.

[0093] At time tp2, the reset period PR ends. Bias transistor TB1 and reset transistor TR are turned off. During the compensation period between time tp2 and time tp3, the scan signal SN(n) has a negative pulse. Bias transistor TB2 and compensation transistors TC1 and TC2 are both turned on. The drive circuit 230 uses the charging path formed by the compensation transistors TC1 and TC2 and the drive transistor TD to charge node P (i.e., the control terminal of the drive transistor TD). Therefore, when the charging operation ends, the voltage at node P is the voltage difference V1 between the drive voltage VDD and the critical voltage of the drive transistor TD.

[0094] At time tp3, the compensation period PC ends. Bias transistor TB2 and compensation transistors TC1 and TC2 are turned off. During the data input period PD between time tp3 and time tp4, the scan signal SN(n+1) has a negative pulse. Therefore, input transistor TI is turned on. The turned-on input transistor TI provides the data voltage VDATA to node Q.

[0095] At time tp4, the data input period PD ends. The input transistor TI is turned off. During the light emission period PE between time tp4 and time tp5, the light emission enable signal EM(n) has a negative pulse. Enable transistors TE1 and TE2 are turned on. Therefore, the voltage value at node P satisfies formula (5). Thus, the drive circuit 230 drives the light-emitting element LE according to the operating voltage value (i.e., the operating voltage value V2 in formula (5)). The operating voltage value is shown in formula (4). When the capacitance value of the reference capacitor CA is designed to be significantly larger than the calibrated capacitance value at node P, the calibrated capacitance value at node P can be ignored.

[0096] Please also refer to Figure 4 as well as Figure 8 , Figure 8 It is based on Figure 4The circuit diagram of the shift register unit is shown. In this embodiment, the shift register unit SR(n) is applied to the pixel circuit 200. In this embodiment, the shift register unit SR(n) includes transistors TS1 to TS8 and capacitors CC1 and CC2. The first terminal and control terminal of transistor TS1 receive the scan signal SN(n-1). The second terminal of transistor TS1 is coupled to node A(n). The first terminal of transistor TS2 receives the clock signal CK1. The second terminal of transistor TS2 is used to output the scan signal SN(n). The control terminal of transistor TS2 is coupled to node A(n). Capacitor CC1 is coupled between the second terminal and the control terminal of transistor TS2. The first terminal of transistor TS3 is coupled to node B(n). The second terminal and control terminal of transistor TS3 receive the clock signal CK3. The first terminal of transistor TS4 is coupled to node B(n). The second terminal of transistor TS4 receives the gate voltage VGH. The control terminal of transistor TS4 is coupled to node A(n). The first terminal of transistor TS5 is coupled to node A(n). The second terminal of transistor TS5 receives the gate voltage VGH. The control terminal of transistor TS5 is coupled to node B(n). The first terminal of transistor TS6 is coupled to the second terminal of transistor TS2. The second terminal of transistor TS6 receives the gate voltage VGH. The control terminal of transistor TS6 is coupled to node B(n).

[0097] Transistor TS7's first terminal receives the gate voltage VGL. Transistor TS7's second terminal outputs the auxiliary scan signal VC(n). Transistor TS7's control terminal is coupled to node A(n). Capacitor CC2 is coupled between transistor TS7's second terminal and its control terminal. Transistor TS8's first terminal is coupled to transistor TS7's second terminal. Transistor TS8's second terminal receives the gate voltage VGH. Transistor TS8's control terminal is coupled to node B(n).

[0098] In this embodiment, transistors TS1 to TS8 are implemented as P-type FETs. This invention is not limited to the FET form of this embodiment. Gate voltage VGH is the gate high voltage. Gate voltage VGL is the gate low voltage. In this embodiment, the negative pulse width of the auxiliary scan signal VC(n) is equal to the duration of the low voltage value at node A(n). The negative pulse width of the scan signal SN(n) is equal to the negative pulse width of the clock signal CK1. Therefore, the negative pulse width of the auxiliary scan signal VC(n) is greater than the negative pulse width of the scan signal SN(n).

[0099] In this embodiment, the shift register unit SR(n) can use the negative pulse of the clock signal CK3 to reset the voltage value at node A(n) to a high voltage value. Simultaneously, the voltage value at node B(n) is set to a low voltage value. Therefore, transistors TS5, TS6, and TS8 respond to the low voltage value at node B(n) to suppress noise at node A(n), noise at the second terminal of transistor TS2, and noise at the second terminal of transistor TS7.

[0100] It should be understood that the preceding shift register unit SR(n-1) (not shown) of the shift register unit SR(n) provides the auxiliary scan signal VC(n-1) and the scan signal SN(n-1). The following shift register unit SR(n+1) (not shown) of the shift register unit SR(n) provides at least the scan signal SN(n+1).

[0101] Please also refer to Figure 6 as well as Figure 9 , Figure 9 It is based on Figure 6 The circuit diagram of the shift register unit is shown. In this embodiment, the shift register unit SR(n) is applied to the pixel circuit 300. In this embodiment, the shift register unit SR(n) includes transistors TS1 to TS6 and capacitor CC1. The coupling method of transistors TS1 to TS6 and capacitor CC1 in this embodiment is the same as... Figure 8 The coupling method of transistors TS1 to TS6 and capacitor CC1 shown is not repeated here.

[0102] In this embodiment, the shift register unit SR(n) can use the negative pulse of the clock signal CK3 to reset the voltage value at node A(n) to a high voltage value. Simultaneously, the voltage value at node B(n) is set to a low voltage value. Therefore, transistors TS5 and TS6 respond to the low voltage value at node B(n) to suppress noise at node A(n) and noise at the second terminal of transistor TS2.

[0103] It should be understood that the preceding shift register unit SR(n-1) (not shown) of the shift register unit SR(n) provides the scan signal SN(n-1). The following shift register unit SR(n+1) (not shown) of the shift register unit SR(n) provides the scan signal SN(n+1).

[0104] In summary, the pixel circuit includes a single capacitor (i.e., a reference capacitor). Using the reference capacitor, the influence of the calibrated capacitance value at the first node can be significantly reduced. The calibrated capacitance value at the first node is ignored. In this way, the pixel circuit can provide accurate compensation functionality.

[0105] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A pixel circuit, comprising: A light-emitting element; A reference capacitor is coupled between a first node and a second node; A reset circuit, coupled to the first node, is configured to provide a first reference bias to the first node during a reset; An input circuit, coupled to the second node, is configured to provide a second reference bias to the second node during the reset and to provide a data voltage during a data input. as well as A driving circuit is coupled to a driving voltage, the first node, and the light-emitting element. The driving circuit includes a driving transistor, the control terminal of which is coupled to the first node. During a compensation period following a reset period, the driving circuit uses the driving transistor and the driving voltage to compensate for the voltage value at the first node. The input circuit provides a data voltage to the second node during the data input period after the compensation period, and The driving circuit drives the light-emitting element according to the data voltage and the driving voltage during a light-emitting period. During this compensation period, the voltage value at the first node is a voltage difference between the absolute value of the driving voltage and the threshold voltage value of the driving transistor. The driving circuit also includes: A first compensation transistor, the first terminal of which is coupled to the driving voltage, the second terminal of which is coupled to the first terminal of the driving transistor, and the control terminal of which receives a third scan signal. as well as A second compensation transistor, the first terminal of which is coupled to the second terminal of the driving transistor, the second terminal of which is coupled to the control terminal of the driving transistor, and the control terminal of the second compensation transistor receiving the third scan signal.

2. The pixel circuit as described in claim 1, wherein: During this data input period, the voltage value at the first node is the sum of the voltage difference and an operating voltage value, and The operating voltage value is generated based on the data voltage value, the second reference bias voltage value, the reference capacitor value, and the first calibration capacitor value located at the first node.

3. The pixel circuit of claim 2, wherein during the light emission period, the driving circuit drives the light-emitting element according to the operating voltage value.

4. The pixel circuit of claim 1, wherein the reset circuit comprises: A reset transistor, wherein a first terminal of the reset transistor is coupled to the first node, a second terminal of the reset transistor is coupled to the first reference bias, and a control terminal of the reset transistor receives a first scan signal. The reset transistor is turned on during the reset period in response to the pulse of the first scan signal.

5. The pixel circuit of claim 4, wherein the input circuit comprises: An input transistor has a first terminal that receives the data voltage, a second terminal that is coupled to the second node, and a control terminal that receives a second scan signal.

6. The pixel circuit of claim 5, wherein the input circuit further comprises: A bias transistor, the first terminal of which is coupled to the second reference bias voltage, the second terminal of which is coupled to the second node, and the control terminal of which receives an auxiliary scan signal.

7. The pixel circuit of claim 6, wherein the input circuit further comprises: A capacitor is coupled between a voltage source and the second node. The voltage source is one of the driving voltage, the first reference bias voltage, and the second reference bias voltage.

8. The pixel circuit of claim 6, wherein the bias transistor is turned on in response to the auxiliary scan signal during the reset and compensation periods to provide the second reference bias to the second node.

9. The pixel circuit of claim 5, wherein the input circuit further comprises: A first bias transistor, the first terminal of which is coupled to the second reference bias, the second terminal of which is coupled to the second node, and the control terminal of which receives the first scan signal; as well as A second bias transistor, the first terminal of which is coupled to the second reference bias voltage, the second terminal of which is coupled to the second node, and the control terminal of which receives a third scan signal.

10. The pixel circuit as claimed in claim 9, wherein: The first bias transistor is turned on in response to the first scan signal during the reset, and The second bias transistor is turned on in response to the third scan signal during the compensation period.

11. The pixel circuit of claim 1, wherein the first compensation transistor and the second compensation transistor are respectively turned on in response to the pulse of the third scan signal during the compensation period.

12. The pixel circuit of claim 1, wherein the driving circuit further comprises: A first enabling transistor, the first terminal of which is coupled to the driving voltage, the second terminal of which is coupled to the first terminal of the driving transistor, and the control terminal of the first enabling transistor receiving a light emission enabling signal. A second enabling transistor, the first terminal of which is coupled to the second terminal of the driving transistor, the second terminal of which is coupled to the light-emitting element, and the control terminal of the second enabling transistor receiving the light-emitting enabling signal.

13. The pixel circuit of claim 12, wherein the first enable transistor and the second enable transistor are respectively turned on in response to the pulse of the light emission enable signal during the light emission period.

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