Display device

Abstract

A display device is disclosed. The display device includes a display module and a plurality of light emitting driving circuits. Each of the light emitting driving circuits includes a timing control circuit and a driving circuit. The timing control circuit receives a plurality of clock signals and a previous light emitting timing signal to provide a light emitting timing signal and an internal voltage. The driving circuit receives a first phase signal of a plurality of phase signals and the internal voltage to provide a light emitting driving signal to the display module based on the first phase signal and the internal voltage. The phase signals all present a disabled level during a vertical blanking period.

Description

Technical Field

[0001] This invention relates to a display device, and more particularly to a light-emitting diode display device. Background Technology

[0002] In modern times, due to the self-emissive nature of LED displays, backlight modules can be omitted, thereby reducing size and weight and making them thinner, giving them a greater competitive edge in the future. Compared to Organic Light-Emitting Diode (OLED) displays, LED displays offer advantages such as higher material stability, longer lifespan, higher brightness, nanosecond-level high-speed response, high-speed modulation, and signal carrying capacity, thus gradually becoming the mainstream technology for next-generation displays.

[0003] Unlike liquid crystal displays (LCDs) which are voltage-driven, micro-LEDs are current-driven light-emitting elements. Therefore, the driving mode of micro-LEDs is an important design issue in LED displays. Summary of the Invention

[0004] The present invention provides a display device that can make pixels stop emitting light during vertical blank periods under multiple light emission operation, so as to perform abnormal detection of the panel.

[0005] The display device of the present invention includes a display module and a plurality of light-emitting driving circuits. Each light-emitting driving circuit includes a timing control circuit and a driving circuit. The timing control circuit receives a plurality of clock signals and a preceding light-emitting timing signal to provide a light-emitting timing signal and an internal voltage. The driving circuit receives a first phase signal from a plurality of phase signals and an internal voltage to provide a light-emitting driving signal to the display module based on the first phase signal and the internal voltage. These phase signals all present a disabled level during a vertical blank period.

[0006] Based on the above, in the display device of this embodiment, the light-emitting driver provides multiple enabled light-emitting driving signals based on a phase signal, and the phase signal presents a disabled level during the vertical blank period, so that the light-emitting driving signals provided by the light-emitting driving circuit are simultaneously disabled. Therefore, the display device can stop the pixels from emitting light during the vertical blank period under multiple light-emitting operation, thereby performing abnormal detection of the panel in the display module.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a system schematic diagram of a display device according to an embodiment of the present invention.

[0009] Figure 2 This is a circuit diagram of a light-emitting driving circuit according to an embodiment of the present invention.

[0010] Figure 3 This is a schematic diagram of the driving timing of a light-emitting driving circuit according to an embodiment of the present invention.

[0011] Figure 4 This is a circuit diagram of a timing control circuit according to an embodiment of the present invention.

[0012] Figure 5 This is a circuit diagram of a timing control circuit according to another embodiment of the present invention.

[0013] Figure 6 This is a circuit diagram of a timing control circuit according to another embodiment of the present invention.

[0014] Figure 7 This is a circuit diagram of a timing control circuit according to another embodiment of the present invention.

[0015] Figure 8 This is a circuit diagram of a timing control circuit according to a further embodiment of the present invention.

[0016] Figure 9 This is a circuit diagram of a displacement register according to an embodiment of the present invention.

[0017] Figure 10 This is a system schematic diagram of a display module according to an embodiment of the present invention.

[0018] Figure 11 This is a schematic diagram of the scanning timing of a display module according to an embodiment of the present invention.

[0019] Figure 12 This is a circuit diagram of a pixel according to an embodiment of the present invention.

[0020] Figure 13 This is a circuit diagram of a pixel according to another embodiment of the present invention.

[0021] Figure 14 This is a circuit diagram of a pixel according to another embodiment of the present invention.

[0022] Figure 15 This is a circuit diagram of a pixel according to another embodiment of the present invention.

[0023] In the attached figures, the following labels are used:

[0024] 100: Display device

[0025] 110: Gate driver

[0026] 120, 120a: Display module

[0027] 130: Light-emitting driver

[0028] 131-133: Light-emitting driving circuit

[0029] C1: First capacitor

[0030] C2: Second capacitor

[0031] C3: Third capacitor

[0032] C4: Fourth capacitor

[0033] C5, C6, C7: Capacitors

[0034] CK, XCK, CK1~CK4: Clock signals

[0035] CTC, CTCa~CTCe: Timing control circuit

[0036] CTD: Drive Circuit

[0037] D2U: Second direction scan signal

[0038] EMST: Light emission start signal

[0039] EMT[1]~EMT[3]、EMT[n]: Light emission timing signals

[0040] EMT[n+1]: Subsequent emission timing signal

[0041] EMT[n-1]: Pre-sequence emission timing signal

[0042] EPAM[1]~EPAM[3], EPAM[n], EPAM[i-2]~EPAM[i+1]: Light emission driving signals

[0043] fx11~fx43: Screen scanning timing

[0044] G[1]~G[3]、G[n]、G[i]~G[i+2]:Gate drive signals

[0045] Gtest: Global Test Signal

[0046] P[i]: First phase signal

[0047] P_VBK: Vertical blank period

[0048] P1~P6: Phase signals

[0049] P11~P43: Display Panel

[0050] PCTD: Pixel Driving Circuit

[0051] PX, PXa~PXd: pixels

[0052] Q: Internal voltage

[0053] Reset: Reset signal

[0054] SR1~SR3, SR: Displacement registers

[0055] T[1]~T[3]、T[n]: Gate timing signals

[0056] T[n+1]: Subsequent gate timing signal

[0057] T[n-1]: Pre-sequence gate timing signal

[0058] T1~T19, T21~T33, T41~T53: Transistors

[0059] U2D: First direction scan signal

[0060] Vdata: Data voltage

[0061] VDD: System high voltage

[0062] VGH: Second gate voltage

[0063] VGL: First gate voltage

[0064] VH: High voltage level

[0065] Vini: Initial voltage

[0066] Vref, Vref2: Reference voltages

[0067] VSS: System Low Voltage

[0068] XDE1: Light Emitting Diode Detailed Implementation

[0069] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0070] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, "first element," "component," "region," "layer," or "part" discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this document.

[0071] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “Or” signifies “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms “comprising” and / or “comprising” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0072] Figure 1 This is a system schematic diagram of a display device according to an embodiment of the present invention. Please refer to... Figure 1 In this embodiment, the display device 100 includes at least a gate driver 110, a display module 120, and a light-emitting driver 130, wherein the gate driver 110 includes a plurality of shift registers (such as SR1 to SR3), and the light-emitting driver 130 includes a plurality of light-emitting driving circuits (such as 131 to 133).

[0073] Each shift register (such as SR1 to SR3) receives multiple clock signals (such as CK1 to CK4) and provides multiple gate drive signals (such as G[1] to G[3]) and multiple gate timing signals (such as T[1] to T[3]) based on the received clock signals (such as CK1 to CK4). The gate drive signals (such as G[1] to G[3]) are provided to the display module 120, and the gate drive signals (such as G[1] to G[3]) are enabled sequentially to turn on (or enable) the pixels PX on the display module 120 line by line.

[0074] Each light-emitting driving circuit (such as 131 to 133) includes a timing control circuit CTC and a driving circuit CTD. The timing control circuit CTC receives clock signals CK and XCK, and receives the preceding light-emitting timing signal (EMT[1] to EMT[3]) or the light-emitting start signal EMST, so as to provide the light-emitting timing signal (such as EMT[1] to EMT[3]) and the internal voltage Q.

[0075] The driving circuit CTD receives one of multiple phase signals (such as P1 to P6) (corresponding to the first phase signal) and an internal voltage Q, and provides light-emitting driving signals (such as EPAM[1] to EPAM[3]) to the display module 120 based on the received phase signal (such as P1 to P6) and the internal voltage Q.

[0076] In this embodiment, the phase signals (such as P1 to P6) can be provided only to the light-emitting driving circuit (such as 131 to 133) of the light-emitting driver 130, while the light-emitting driving signals (such as EPAM[1] to EPAM[3]) will be enabled multiple times during a frame period according to the phase signals (such as P1 to P6) received by the driving circuit CTD, so that the pixels of a row are lit multiple times during a frame. Furthermore, these phase signals P1 to P6 are activated during the vertical blank period (such as...). Figure 3 The P_VBK shown are all disabled, so that the light-emitting driving signals (such as EPAM[1] to EPAM[3]) provided by the light-emitting driving circuit (such as 131 to 133) will be disabled simultaneously. In this way, the display device 100 can make the pixel PX in the vertical blank period (such as 131 to 133) under multiple light-emitting operation. Figure 3 The P_VBK indicator is stopped emitting light to detect abnormalities in the panel of the display module 120.

[0077] In this embodiment, the pixels PX of the display module 120 are arranged in an array, and the pixels PX in the display module 120 can be configured on one or more panels (i.e., one or more substrates), depending on the circuit design, and this embodiment of the present invention is not limited thereto.

[0078] Figure 2 This is a circuit diagram of a light-emitting driving circuit according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 In this embodiment, the timing control circuit CTC includes transistors T1 to T10 (corresponding to the first to the tenth transistors), a first capacitor C1, and a second capacitor C2. Transistors T1 to T10 are P-type transistors, but this embodiment of the invention is not limited thereto.

[0079] Transistor T1 has a first terminal for receiving the preceding light-emitting timing signal EMT[n-1], a control terminal for receiving the first direction scan signal U2D, and a second terminal, where n is a positive integer. Transistor T2 has a first terminal coupled to the second terminal of transistor T1, a control terminal for receiving the second direction scan signal D2U, and a second terminal for receiving the following light-emitting timing signal EMT[n+1]. Transistor T3 has a first terminal coupled to the second terminal of transistor T1, a control terminal for receiving one of the clock signals CK and XCK (corresponding to the first clock signal), and a second terminal coupled to the internal voltage Q.

[0080] Transistor T4 has a first terminal receiving a first gate voltage VGL, a control terminal receiving an internal voltage Q, and a second terminal providing a light emission timing signal EMT[n]. A first capacitor C1 is coupled between the control terminal of transistor T4 and the other of the clock signals CK and XCK (corresponding to the second clock signal). Transistor T5 has a first terminal, a control terminal coupled to the second terminal of transistor T1, and a second terminal receiving a second gate voltage VGH, wherein the second gate voltage VGH may be higher than the first gate voltage VGL, but this is not a limitation of the embodiments of the present invention; it depends on the circuit design.

[0081] The second capacitor C2 is coupled between one of the clock signals CK and XCK and the first terminal of transistor T5. Transistor T6 has a first terminal that receives the first gate voltage VGL, a control terminal coupled to the first terminal of transistor T5, and a second terminal. Transistor T7 has a first terminal coupled to the second terminal of transistor T6, a control terminal that receives the internal voltage Q, and a second terminal that receives the second gate voltage VGH.

[0082] Transistor T8 has a first terminal receiving an internal voltage Q, a control terminal coupled to the second terminal of a sixth transistor T6, and a second terminal receiving a second gate voltage VGH. Transistor T9 has a first terminal coupled to the second terminal of transistor T4, a control terminal coupled to the second terminal of transistor T6, and a second terminal receiving the second gate voltage VGH. Transistor T10 has a first terminal receiving a first gate voltage VGL, a control terminal receiving a reset signal Reset, and a second terminal coupled to the second terminal of transistor T6.

[0083] In this embodiment, the driving circuit CTD includes transistors T11 to T15 (corresponding to the fifteenth to nineteenth transistors), a third capacitor C3, and a fourth capacitor C4. Transistors T11 to T15 are examples of P-type transistors, but this embodiment of the invention is not limited thereto.

[0084] Transistor T11 has a first terminal receiving a first gate voltage VGL, a control terminal receiving an internal voltage Q, and a second terminal. Transistor T12 has a first terminal coupled to the second terminal of transistor T11, a control terminal receiving the first gate voltage VGL, and a second terminal. Transistor T13 has a first terminal receiving a first phase signal P[i] (i.e., one of phase signals P1 to P6), a control terminal coupled to the second terminal of transistor T12, and a second terminal providing a light-emitting drive signal EPAM[n]. A third capacitor C3 is coupled between the control terminal of transistor T13 and the second terminal of transistor T13. Transistor T14 has a first terminal coupled to the second terminal of transistor T11, a control terminal coupled to the second terminal of transistor T6, and a second terminal receiving a second gate voltage VGH. A fourth capacitor C4 is coupled between the second terminal of transistor T11 and the second gate voltage VGH. Transistor T15 has a first terminal coupled to the second terminal of the seventeenth transistor T13, a control terminal coupled to the second terminal of transistor T6, and a second terminal receiving the second gate voltage VGH.

[0085] Figure 3 This is a schematic diagram of the driving timing of a light-emitting driving circuit according to an embodiment of the present invention. Please refer to... Figures 1 to 3 In this embodiment, the driving circuit CTD directly outputs the received phase signals (such as P1 to P6) as corresponding light-emitting driving signals (such as EPAM[i-2] to EPAM[i+1]), where i is a leading number. For example, the driving circuit CTD directly outputs phase signal P1 as the light-emitting driving signal EPAM[i-2], and the driving circuit CTD directly outputs phase signal P2 as the light-emitting driving signal EPAM[i-1]. Then, during the vertical blank period P_VBK, phase signals P1 to P6 are disabled throughout the entire period (e.g., high voltage level VH), causing pixel PX to stop emitting light during the vertical blank period P_VBK.

[0086] Figure 4 This is a circuit diagram of a timing control circuit according to an embodiment of the present invention. Please refer to... Figure 2 and Figure 4 In this embodiment, compared to the timing control circuit CTC, the timing control circuit CTCa further includes transistor T16 (corresponding to the eleventh transistor), wherein transistor T16 is a P-type transistor, but the embodiments of the present invention are not limited thereto. Transistor T16 has a first terminal for receiving the other of the clock signals CK and XCK, a control terminal for receiving the internal voltage Q, and a second terminal, wherein the first capacitor C1 is coupled between the second terminal of transistor T16 and the control terminal of transistor T4.

[0087] When the timing control circuit CTC is not operating, the internal voltage Q causes transistor T16 to be cut off, thereby disconnecting the other of the clock signals CK and XCK from the first capacitor C1. This completely eliminates the high-frequency transient current of transistor T8, thereby suppressing the degradation of transistor T8.

[0088] Figure 5 This is a circuit diagram of a timing control circuit according to another embodiment of the present invention. Please refer to... Figure 2 , Figure 4 and Figure 5 In this embodiment, compared to the timing control circuit CTCa, the timing control circuit CTCb further includes transistor T17 (corresponding to the twelfth transistor), wherein transistor T17 is a P-type transistor as an example, but the embodiments of the present invention are not limited thereto. Transistor T17 has a first terminal receiving an internal voltage Q, a control terminal receiving a first gate voltage VGL, and a second terminal coupled to the control terminal of transistor T4, wherein transistor T17 can be used to block the voltage between the second terminal of transistor T3 and the control terminal of transistor T4.

[0089] Figure 6 This is a circuit diagram of a timing control circuit according to another embodiment of the present invention. Please refer to... Figure 2 , Figures 4 to 6 In this embodiment, compared to the timing control circuit CTCb, the timing control circuit CTCc further includes transistor T18 (corresponding to the thirteenth transistor), wherein transistor T18 is a P-type transistor as an example, but the embodiments of the present invention are not limited thereto. Transistor T18 has a first terminal receiving an internal voltage Q, a control terminal receiving a first gate voltage VGL, and a second terminal coupled to the control terminal of transistor T16, wherein the addition of transistor T18 can prevent the degradation of transistors T7 and T8 due to their large voltage across voltage.

[0090] Figure 7 This is a circuit diagram of a timing control circuit according to another embodiment of the present invention. Please refer to... Figure 2 , Figure 4 and Figure 7 In this embodiment, compared to the timing control circuit CTCa, the timing control circuit CTCd omits transistor T10, but can still prevent the degradation of transistor T8 due to its large voltage across the transistor.

[0091] Figure 8 This is a circuit diagram of a timing control circuit according to a further embodiment of the present invention. Please refer to... Figure 2 , Figure 4 and Figure 8In this embodiment, compared to the timing control circuit CTCa, the timing control circuit CTCe further includes transistor T19 (corresponding to the fourteenth transistor), wherein transistor T19 is a P-type transistor as an example, but the embodiments of the present invention are not limited thereto. Transistor T19 has a first terminal coupled to the control terminal of the eighth transistor T8, a second terminal coupled to the control terminal of the first transistor T1, and a second terminal coupled to the control terminal of the fourth transistor T4, wherein turning on transistor T19 can turn off transistor T8 to avoid the competition between transistors T3 and T8.

[0092] Figure 9 This is a circuit diagram of a displacement register according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 9 In this embodiment, the shift register SR (e.g., one of the shift registers SR1 to SR3) includes transistors T21 to T32 and capacitor C5. Transistors T21 to T32 are P-type transistors, but this embodiment of the invention is not limited thereto.

[0093] Transistor T21 has a first terminal for receiving the preceding gate timing signal T[n-1], a control terminal for receiving the first direction scan signal U2D, and a second terminal, where n is a positive integer. Transistor T22 has a first terminal coupled to the second terminal of transistor T21, a control terminal for receiving the second direction scan signal D2U, and a second terminal for receiving the following gate timing signal T[n+1]. Transistor T23 has a first terminal for receiving the first gate voltage VGL, a control terminal coupled to the second terminal of transistor T21, and a second terminal.

[0094] Transistor T24 has a first terminal coupled to the second terminal of transistor T23, a control terminal receiving a first gate voltage VGL, and a second terminal. Transistor T25 has a first terminal receiving one of a plurality of clock signals (such as CK1 to CK4), a control terminal coupled to the second terminal of transistor T24, and a second terminal providing a gate timing signal T[n]. Capacitor C5 is coupled between the control terminal of transistor T25 and the second terminal of transistor T25. Transistor T26 has a first terminal receiving one of a plurality of clock signals (such as CK1 to CK4), a control terminal coupled to the second terminal of transistor T24, and a second terminal providing a gate drive signal G[n].

[0095] Transistor T27 has a first terminal, a control terminal coupled to the second terminal of transistor T21, and a second terminal receiving a second gate voltage VGH. Transistor T28 has a first terminal receiving a first gate voltage VGL, a control terminal receiving another of a plurality of received clock signals (such as CK1 to CK4), and a second terminal coupled to the first terminal of transistor T27. In this embodiment of the invention, when one of the plurality of received clock signals (such as CK1 to CK4) is clock signal CK1, the other of the plurality of received clock signals (such as CK1 to CK4) can be clock signal CK3; when one of the plurality of received clock signals (such as CK1 to CK4) is clock signal CK2, the other of the plurality of received clock signals (such as CK1 to CK4) can be clock signal CK2, and so on. In other words, one of the multiple received clock signals (such as CK1 to CK4) and another of the multiple received clock signals (such as CK1 to CK4) may be complementary (or out of phase) or have a phase difference of 180 degrees. This can be determined according to the circuit design, and the embodiments of the present invention are not limited thereto.

[0096] Transistor T29 has a first terminal coupled to the second terminal of transistor T28, a control terminal for receiving a gate timing signal T[n], and a second terminal for receiving a second gate voltage VGH. Transistor T30 has a first terminal for receiving a first gate voltage VGL, a control terminal for receiving a reset signal Reset, and a second terminal coupled to the second terminal of transistor T28.

[0097] Transistor T31 has a first terminal coupled to the second terminal of transistor T23, a control terminal coupled to the second terminal of transistor T28, and a second terminal receiving the second gate voltage VGH. Transistor T32 has a first terminal coupled to the second terminal of transistor T25, a control terminal coupled to the second terminal of transistor T28, and a second terminal receiving the second gate voltage VGH. Transistor T33 has a first terminal coupled to the second terminal of transistor T26, a control terminal coupled to the second terminal of transistor T28, and a second terminal receiving the second gate voltage VGH.

[0098] Figure 10 This is a system schematic diagram of a display module according to an embodiment of the present invention. Figure 11 This is a schematic diagram of the scanning timing of a display module according to an embodiment of the present invention. Please refer to... Figure 1 , Figure 10 and Figure 11In this embodiment, the display module 120a includes multiple display panels P11 to P43 arranged in an array, as shown in the image scanning sequence fx11 to fx43. The scanning direction of these display panels P11 to P43 in the odd-numbered rows is different from that of the display panels P11 to P43 in the even-numbered rows. For example, the display panels P11 to P13 and P31 to P33 in the odd-numbered rows can perform image scanning (i.e., image display) (or forward scanning) from top to bottom, while the display panels P21 to P23 and P41 to P43 in the even-numbered rows can perform image scanning (or reverse scanning) from bottom to top. This prevents obvious image breaks at the junctions of the display panels P11 to P43, thereby improving the jagged image situation.

[0099] Figure 12 This is a circuit diagram of a pixel according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 12 In this embodiment, each pixel PX can be referred to as pixel PXa, and pixel PXa includes pixel driving circuit PCTD, light-emitting diode XDE1, and transistor T50 (corresponding to the first test transistor). The transistor T50 is a P-type transistor, but the embodiments of the present invention are not limited thereto.

[0100] The light-emitting diode XDE1 has an anode and a cathode that receives the system low voltage VSS. The pixel driving circuit PCTD is coupled between the system high voltage VDD and the anode of the light-emitting diode XDE1. Transistor T50 has a first terminal coupled to the anode of the light-emitting diode XDE1, a control terminal that receives the global test signal Gtest, and a second terminal that receives the data voltage Vdata. Thus, defects / short circuits in the light-emitting diode XDE1 can be detected on a vertical line-by-vertical basis using transistor T50.

[0101] In this embodiment, the pixel driving circuit PCTD includes transistors T41 to T49 and capacitors C6 and C7. Transistors T41 to T49 are examples of P-type transistors, but this embodiment of the invention is not limited thereto.

[0102] Transistor T41 has a first terminal for receiving the system high voltage VDD, a control terminal for receiving the corresponding light-emitting drive signal EPAM[i], and a second terminal. Transistor T42 has a first terminal coupled to the second terminal of transistor T41, a control terminal, and a second terminal. Transistor T43 has a first terminal coupled to the control terminal of transistor T42, a control terminal for receiving the corresponding gate drive signal G[i+1], and a second terminal coupled to the second terminal of transistor T42.

[0103] Transistor T44 has a first terminal coupled to the second terminal of transistor T42, a control terminal receiving the corresponding light-emitting drive signal EPAM[i], and a second terminal coupled to the anode of light-emitting diode XDE1. Transistor T45 has a first terminal coupled to the control terminal of transistor T42, a control terminal receiving the corresponding gate drive signal G[i], and a second terminal receiving the initial voltage Vini. Transistor T46 has a first terminal, a control terminal receiving the corresponding gate drive signal G[i], and a second terminal receiving the initial voltage Vini.

[0104] Capacitor C6 is coupled between the control terminal of transistor T42 and the first terminal of transistor T46. Transistor T47 has a first terminal coupled to the first terminal of transistor T46, a control terminal receiving the corresponding gate drive signal G[i+1], and a second terminal receiving the initial voltage Vini. Transistor T48 has a first terminal receiving the data voltage Vdata, a control terminal receiving the corresponding gate drive signal G[i+2], and a second terminal coupled to the first terminal of transistor T46.

[0105] Transistor T49 has a first terminal that receives a reference voltage Vref, a control terminal that receives the corresponding light-emitting drive signal EPAM[i], and a second terminal. Capacitor C7 is coupled between the second terminal of transistor T42 and the first terminal of transistor T46.

[0106] Figure 13 This is a circuit diagram of a pixel according to another embodiment of the present invention. Please refer to... Figure 1 , Figure 12 and Figure 13 In this embodiment, pixel PXb is substantially the same as pixel PXa, with identical or similar elements using the same or similar designations. The difference between pixel PXb and pixel PXa lies in transistors T50 and T51 (corresponding to the fourth test transistor). The control terminal of transistor T50 receives the global test signal Gtest, but it also receives the corresponding light-emitting drive signal EPAM[i]. Therefore, through transistor T51, defects / short circuits in the light-emitting diode XDE1 can be detected on a per-pixel PXb basis.

[0107] Figure 14 This is a circuit diagram of a pixel according to another embodiment of the present invention. Please refer to... Figure 1 , Figure 12 and Figure 14In this embodiment, pixel PXc is substantially the same as pixel PXa, wherein the same or similar elements are labeled with the same or similar designations. In this embodiment, pixel PXc further includes transistor T52 (corresponding to the second test transistor). Transistor T52 has a first terminal coupled to the second terminal of transistor T50, a control terminal receiving the corresponding light-emitting drive signal EPAM[i], and a second terminal receiving the data voltage Vdata. Thus, through transistor T52, defects / short circuits in the light-emitting diode XDE1 can be detected on a per-pixel PXb basis.

[0108] Figure 15 This is a circuit diagram of a pixel according to another embodiment of the present invention. Please refer to... Figure 1 , Figure 12 , Figure 14 and Figure 15 In this embodiment, pixel PXd is substantially the same as pixel PXc, wherein the same or similar elements are labeled with the same or similar designations. In this embodiment, pixel PXd further includes transistor T53 (corresponding to the third test transistor). Transistor T53 has a first terminal coupled to the anode of light-emitting diode XDE1, a control terminal receiving a reset signal Reset, and a second terminal receiving a reference voltage Vref2. Thus, through transistor T52, defects / short circuits in light-emitting diode XDE1 can be detected on a per-pixel PXb basis, and through transistor T53, the voltage level of the anode can be reset.

[0109] In summary, in the display device of this invention, the light-emitting driver provides multiple enabled light-emitting driving signals based on a phase signal, and the phase signal presents a disabled level during the vertical blank period, so that the light-emitting driving signals provided by the light-emitting driving circuit are simultaneously disabled. Therefore, the display device can stop pixels from emitting light during the vertical blank period under multiple light-emitting operation, thereby enabling abnormal detection of the panel in the display module.

[0110] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A display device, characterized in that, include: One display module; Multiple light-emitting driving circuits, each of which includes: A timing control circuit receives multiple clock signals and a preceding light-emitting timing signal to provide a light-emitting timing signal and an internal voltage; and A driving circuit receives a first phase signal from a plurality of phase signals and an internal voltage, and provides a light-emitting driving signal to the display module based on the first phase signal and the internal voltage. These phase signals all exhibit a disabled level during a vertical blank period; The timing control circuit includes: A first transistor has a first terminal for receiving the preceding light emission timing signal, a control terminal for receiving a first direction scanning signal, and a second terminal; A second transistor has a first terminal coupled to the second terminal of the first transistor, a control terminal for receiving a second direction scanning signal, and a second terminal for receiving a subsequent light emission timing signal; A third transistor has a first terminal coupled to the second terminal of the first transistor, a control terminal for receiving the clock signals as a first clock signal, and a second terminal coupled to the internal voltage; A fourth transistor has a first terminal for receiving a first gate voltage, a control terminal for receiving the internal voltage, and a second terminal for providing the light emission timing signal; A first capacitor is coupled between a second clock signal of the clock signals and the control terminal of the fourth transistor; A fifth transistor has a first terminal, a control terminal coupled to the second terminal of the first transistor, and a second terminal receiving a second gate voltage; A second capacitor is coupled between the first clock signal and the first terminal of the fifth transistor; A sixth transistor has a first terminal for receiving the first gate voltage, a control terminal coupled to the first terminal of the fifth transistor, and a second terminal; A seventh transistor has a first terminal coupled to the second terminal of the sixth transistor, a control terminal receiving the internal voltage, and a second terminal receiving the second gate voltage; An eighth transistor has a first terminal for receiving the internal voltage, a control terminal coupled to the second terminal of the sixth transistor, and a second terminal for receiving the second gate voltage; A ninth transistor has a first terminal coupled to the second terminal of the fourth transistor, a control terminal coupled to the second terminal of the sixth transistor, and a second terminal receiving the second gate voltage; and A tenth transistor has a first terminal for receiving the first gate voltage, a control terminal for receiving a reset signal, and a second terminal coupled to the second terminal of the sixth transistor.

2. The display device as claimed in claim 1, characterized in that, The timing control circuit further includes: An eleventh transistor has a first terminal for receiving the second clock signal, a control terminal for receiving the internal voltage, and a second terminal, wherein the first capacitor is coupled between the second terminal of the eleventh transistor and the control terminal of the fourth transistor.

3. The display device as claimed in claim 2, characterized in that, The timing control circuit further includes: A twelfth transistor has a first terminal for receiving the internal voltage, a control terminal for receiving the first gate voltage, and a second terminal coupled to the control terminal of the fourth transistor.

4. The display device as claimed in claim 3, characterized in that, The timing control circuit further includes: A thirteenth transistor has a first terminal for receiving the internal voltage, a control terminal for receiving the first gate voltage, and a second terminal coupled to the control terminal of the eleventh transistor.

5. The display device as claimed in claim 1, characterized in that, The timing control circuit further includes: A fourteenth transistor has a first terminal coupled to the control terminal of the eighth transistor, a control terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the control terminal of the fourth transistor.

6. The display device as claimed in claim 1, characterized in that, The driving circuit includes: A fifteenth transistor has a first terminal for receiving the first gate voltage, a control terminal for receiving the internal voltage, and a second terminal; A sixteenth transistor has a first terminal coupled to the second terminal of the fifteenth transistor, a control terminal receiving the first gate voltage, and a second terminal; A seventeenth transistor has a first terminal for receiving the first phase signal, a control terminal coupled to the second terminal of the sixteenth transistor, and a second terminal for providing the light-emitting drive signal; A third capacitor is coupled between the control terminal of the seventeenth transistor and the second terminal of the seventeenth transistor; An eighteenth transistor has a first terminal coupled to the second terminal of the fifteenth transistor, a control terminal coupled to the second terminal of the sixth transistor, and a second terminal for receiving the second gate voltage; A fourth capacitor is coupled between the second terminal of the fifteenth transistor and the second gate voltage; and A nineteenth transistor has a first terminal coupled to the second terminal of the seventeenth transistor, a control terminal coupled to the second terminal of the sixth transistor, and a second terminal for receiving the second gate voltage.

7. The display device as claimed in claim 1, characterized in that, The display module includes multiple display panels arranged in an array, wherein the scanning direction of the display panels in the odd-numbered rows is different from that of the display panels in the even-numbered rows.

8. The display device as claimed in claim 1, characterized in that, The display module includes multiple pixels arranged in an array, wherein each of the pixels includes: A light-emitting diode having an anode and a cathode for receiving a low voltage from a system; A pixel driving circuit is coupled between a system high voltage and the anode; A first test transistor has a first terminal coupled to the anode, a control terminal for receiving a global test signal, and a second terminal for receiving a data voltage.

9. The display device as claimed in claim 8, characterized in that, Each of these pixels further includes: A second test transistor has a first terminal coupled to the second terminal of the first test transistor, a control terminal for receiving a corresponding light emission driving signal, and a second terminal for receiving the data voltage.

10. The display device as claimed in claim 9, characterized in that, Each of these pixels further includes: A third test transistor has a first terminal coupled to the anode, a control terminal that receives a reset signal, and a second terminal that receives a reference voltage.

11. The display device as claimed in claim 1, characterized in that, The display module includes multiple pixels arranged in an array, wherein each of the pixels includes: A light-emitting diode having an anode and a cathode for receiving a low voltage from a system; A pixel driving circuit is coupled between a system high voltage and the anode; A fourth test transistor has a first terminal coupled to the anode, a control terminal that receives a corresponding light-emitting drive signal, and a second terminal that receives a data voltage.

12. A display device, characterized in that, include: One display module; Multiple light-emitting driving circuits are coupled to the display module, wherein each of the light-emitting driving circuits includes: A first transistor has a first terminal for receiving a preceding light emission timing signal, a control terminal for receiving a first direction scanning signal, and a second terminal; A second transistor has a first terminal coupled to the second terminal of the first transistor, a control terminal for receiving a second direction scanning signal, and a second terminal for receiving a subsequent light emission timing signal; A third transistor has a first terminal coupled to the second terminal of the first transistor, a control terminal receiving a first clock signal, and a second terminal coupled to an internal voltage; A fourth transistor has a first terminal for receiving a first gate voltage, a control terminal for receiving the internal voltage, and a second terminal for providing a light emission timing signal; A first capacitor is coupled between a second clock signal and the control terminal of the fourth transistor; A fifth transistor has a first terminal, a control terminal coupled to the second terminal of the first transistor, and a second terminal receiving a second gate voltage; A second capacitor is coupled between the first clock signal and the first terminal of the fifth transistor; A sixth transistor has a first terminal for receiving the first gate voltage, a control terminal coupled to the first terminal of the fifth transistor, and a second terminal; A seventh transistor has a first terminal coupled to the second terminal of the sixth transistor, a control terminal receiving the internal voltage, and a second terminal receiving the second gate voltage; An eighth transistor has a first terminal receiving the internal voltage, a control terminal coupled to the second terminal of the sixth transistor, and a second terminal receiving the second gate voltage; and A ninth transistor has a first terminal coupled to the second terminal of the fourth transistor, a control terminal coupled to the second terminal of the sixth transistor, and a second terminal for receiving the second gate voltage.

13. The display device as claimed in claim 12, characterized in that, Each of these light-emitting driving circuits further includes: The tenth transistor has a first terminal for receiving the first gate voltage, a control terminal for receiving a reset signal, and a second terminal coupled to the second terminal of the sixth transistor.

14. The display device as claimed in claim 12, characterized in that, Each of these light-emitting driving circuits further includes: An eleventh transistor has a first terminal for receiving the second clock signal, a control terminal for receiving the internal voltage, and a second terminal, wherein the first capacitor is coupled between the second terminal of the eleventh transistor and the control terminal of the fourth transistor.

15. The display device as claimed in claim 14, characterized in that, Each of these light-emitting driving circuits further includes: A twelfth transistor has a first terminal for receiving the internal voltage, a control terminal for receiving the first gate voltage, and a second terminal coupled to the control terminal of the fourth transistor.

16. The display device as claimed in claim 15, characterized in that, Each of these light-emitting driving circuits further includes: A thirteenth transistor has a first terminal for receiving the internal voltage, a control terminal for receiving the first gate voltage, and a second terminal coupled to the control terminal of the eleventh transistor.

17. The display device as claimed in claim 12, characterized in that, Each of these light-emitting driving circuits further includes: A fourteenth transistor has a first terminal coupled to the control terminal of the eighth transistor, a control terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the control terminal of the fourth transistor.

Images