Drive circuit

Abstract

A driving circuit includes a driving transistor, a first capacitor, a first switching transistor, a second capacitor, a second switching transistor, and a third capacitor. The driving transistor is electrically connected between a first driving voltage terminal and a second driving voltage terminal to control a driving current provided to a light emitting element. A first terminal of the first capacitor is electrically connected to a gate terminal of the driving transistor. A first terminal of the first switching transistor is electrically connected to a first terminal of the driving transistor, and a second terminal of the first switching transistor is electrically connected to a second terminal of the first capacitor. A first terminal of the second capacitor is electrically connected to a gate terminal of the first switching transistor. The second switching transistor is electrically connected between a second terminal of the second capacitor and a first reference voltage terminal. The third capacitor is electrically connected between a gate terminal of the second switching transistor and a sweep signal line.

Description

Technical Field

[0001] This case relates to a driving circuit, and more particularly to a driving circuit that achieves grayscale dimming through pulse width modulation. Background Technology

[0002] In current display panel technology, multiple pixel circuits are arranged in an array on a substrate, and each pixel circuit provides driving current to the light-emitting element, thereby driving the light-emitting element to emit light. In some cases, grayscale dimming is achieved by modulating the pulse width of the driving current, and the light-emitting element can be controlled to operate at a point with better luminous efficiency based on the pulse amplitude of the driving current.

[0003] However, to achieve grayscale dimming by modulating the pulse width of the drive current, multiple transistors may be configured in the current path of the pixel circuit's drive current (e.g., four or more transistors, where two transistors control the current path of the drive current, one transistor controls the pulse amplitude of the drive current, and another transistor controls the pulse width of the drive current). In such a case, during the light-emitting phase, to ensure that the drive transistors can operate in the saturation region and considering the voltage difference between the drain and source terminals of each transistor, the required drive voltage of the pixel circuit increases, leading to increased power consumption.

[0004] Furthermore, the grayscale control accuracy of pulse width modulation is highly correlated with the transition time of the drive current (e.g., rise time / fall time). If the transition time of the drive current is long, it will cause the current waveform to be distorted at low grayscale, reducing the accuracy of grayscale control. In addition, the current waveform of the drive current may not be able to reach the current value of the high-efficiency light-emitting point at low grayscale, resulting in a decrease in the operating efficiency of the light-emitting element.

[0005] Therefore, how to provide a driving circuit to solve the above problems is an important issue in this field. Summary of the Invention

[0006] This disclosure provides a driving circuit. The driving circuit includes a driving transistor, a first capacitor, a first switching transistor, a second capacitor, a second switching transistor, and a third capacitor. The driving transistor is electrically connected between a first driving voltage terminal and a second driving voltage terminal to control the driving current supplied to the light-emitting element. A first terminal of the first capacitor is electrically connected to the gate terminal of the driving transistor. A first terminal of the first switching transistor is electrically connected to the first terminal of the driving transistor, and a second terminal of the first switching transistor is electrically connected to the second terminal of the first capacitor. A first terminal of the second capacitor is electrically connected to the gate terminal of the first switching transistor. The second switching transistor is electrically connected between the second terminal of the second capacitor and a first reference voltage terminal. The third capacitor is electrically connected between the gate terminal of the second switching transistor and a sweep frequency signal line.

[0007] In summary, the driving circuit of this disclosure provides a second capacitor between the gate terminal of the first switching transistor and the first reference voltage terminal. This prevents the potential at the gate terminal of the first switching transistor from being directly cleared by the potential at the first reference voltage terminal when the second switching transistor turns on the current path from the gate terminal of the first switching transistor to the first reference voltage terminal. As a result, when the first switching transistor is set once, the setting voltage of the first switching transistor can be retained through the second capacitor during multiple light emission periods. Attached Figure Description

[0008] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below:

[0009] Figure 1 This is a schematic diagram of a driving circuit according to an embodiment of the present disclosure.

[0010] Figure 2 This is a schematic diagram of a driving circuit according to an embodiment of the present disclosure.

[0011] Figure 3 This is a timing diagram of control signals according to an embodiment of the present disclosure.

[0012] Figure 4A This is a schematic diagram of the operation of a drive circuit during a reset according to an embodiment of the present disclosure.

[0013] Figure 4B This is a schematic diagram of the operation of a drive circuit during compensation according to an embodiment of the present disclosure.

[0014] Figure 4C This is a schematic diagram of the operation of a driving circuit according to an embodiment of the present disclosure during the first stable period of a display cycle.

[0015] Figure 4D as well as Figure 4E This is a schematic diagram of the operation of a driving circuit during light emission according to an embodiment of the present disclosure.

[0016] Figure 4F This is a schematic diagram of the operation of a driving circuit according to an embodiment of the present disclosure during the second and subsequent stabilization period and the off period in a display cycle.

[0017] Figures 5A to 5D This is a schematic diagram of the drive current, sweep frequency signal, and multiple emission control signal of the drive circuit during multiple emission periods according to an embodiment of this disclosure.

[0018] Figure 6 This is a schematic diagram of the drive current provided by the drive circuit in the event of a change in the critical voltage of the switching transistor according to an embodiment of this disclosure.

[0019] Figures 7A to 7B This is a schematic diagram of the driving current during a single emission period according to an embodiment of the present disclosure.

[0020] Figures 8A to 8C This is a schematic diagram of the driving current of a driving circuit according to an embodiment of the present disclosure during a single light emission period.

[0021] 100: Drive circuit

[0022] 112, 122, 126: Reset circuit

[0023] 114, 124, 127: Compensation circuits

[0024] 116: Data setting circuit

[0025] 125, 128: Stabilizing circuits

[0026] PAM: Pulse Amplitude Modulation Circuit

[0027] PWM: Pulse Width Modulation Circuit

[0028] VDD, VSS: Drive voltage terminals

[0029] L1: Light-emitting element

[0030] TD: Driving transistor

[0031] TS1, TS2: Switching transistors

[0032] T1, T2, T3, T4, T5, T6, T7, T8, T9: Transistors

[0033] T10, T11, T12, T13, T14, T15, T16: Transistors

[0034] C1, C2, C3, C4, C5: Capacitors

[0035] V1, V2, V3: Reference voltage terminals

[0036] V SWEEP Frequency sweep signal

[0037] SWPL: Sweep frequency signal line

[0038] mEM: Multiple emission control signal

[0039] S1[n-1], S1[n]: Control signals

[0040] DATA1, DATA2: Data signals

[0041] P OFF During the closure

[0042] P RES During the reset

[0043] P COM Compensation period

[0044] P STA During the stable period

[0045] P EM During the luminescence period Detailed Implementation

[0046] The following detailed description provides examples with reference to the accompanying drawings. However, the provided examples are not intended to limit the scope of this disclosure, and the description of the structural operation is not intended to limit the order of execution. Any structure resulting from the recombination of elements and producing a device with equivalent functionality is within the scope of this disclosure. Furthermore, the illustrations are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same or similar elements will be designated with the same symbols in the following description.

[0047] Unless otherwise specified, the terms used throughout this specification and the scope of the patent application generally have their ordinary meaning in the context of the art, the disclosure, and the specific content. Furthermore, the terms “comprising,” “including,” “having,” “containing,” etc., used herein are open-ended terms, meaning “including but not limited to.” Additionally, the term “and / or” as used herein includes any one or more of the related listed items and all combinations thereof.

[0048] Please see Figure 1 , Figure 1 This is a schematic diagram of a driving circuit 100 according to an embodiment of the present disclosure. In some embodiments, the driving circuit 100 is used to control the driving current provided to the light-emitting element L1. In some embodiments, the light-emitting element L1 is a microscopic light-emitting diode (micro-LED).

[0049] like Figure 1As shown, the driving circuit 100 includes a pulse amplitude modulation (PAM) circuit, a pulse width modulation (PWM) circuit, and a transistor T16. In some embodiments, the light-emitting element L1 is electrically connected to the current path of the driving current to emit light according to the driving current. In some embodiments, the pulse amplitude modulation (PAM) circuit is electrically connected to the current path of the driving current to control the amplitude of the driving current. In some embodiments, the driving circuit 100 corresponding to the driving circuit in the red, blue, or green sub-pixels depends on the emission color of the light-emitting element L1 (e.g., a red, green, or blue micro-light-emitting diode), and the pulse amplitude modulation (PAM) circuit controls the amplitude of the driving current according to the corresponding sub-pixel to make the light-emitting element L1 operate at a better efficiency point.

[0050] In some embodiments, the pulse width modulation (PWM) circuit is electrically connected to the pulse amplitude modulation (PAM) circuit, and the PWM circuit is used to control the current path of the PAM circuit to turn on the drive current. In some embodiments, the PWM circuit determines the timing of the PAM circuit to turn on the drive current during the light emission period based on grayscale data. In some embodiments, the PWM circuit controls the timing of the light-emitting element L1 to change from non-operational to operation during the light emission period (off-then-on method) based on grayscale data. That is, the drive circuit 100 operates the light-emitting element L1 using the off-then-on method during the light emission period.

[0051] In some embodiments, transistor T16 is electrically connected to the current path of the drive current, and transistor T16 is used to control the current path of the drive current to turn off at the end of the emission period according to the multiple emission control signals EM. In some embodiments, a turn-off-on method is used during the emission period, and by using transistor T16 to turn off the current path of the drive current at the end of the emission period, the fall time of the drive current can be effectively reduced, thereby improving the light leakage phenomenon.

[0052] The operation of the pulse amplitude modulation (PAM) circuit and pulse width modulation (PWM) circuit of the drive circuit 100 will be described in detail in subsequent embodiments. Please refer to them for easier understanding. Figure 1 as well as Figure 2 .

[0053] In some embodiments, the pulse amplitude modulation circuit PAM includes a drive transistor TD, a compensation circuit 114, a reset circuit 112, a data setting circuit 116, and a capacitor C1.

[0054] In some embodiments, the driving transistor TD is electrically connected to the current path of the driving current flowing through the light-emitting element L1. In some embodiments, the driving transistor TD is used to control the timing of the current path of the driving current being turned on, thereby modulating the pulse width of the driving current, and the driving transistor TD is further used to control the pulse amplitude of the driving current according to the potential at its gate terminal.

[0055] In terms of architecture, the driving transistor TD, the light-emitting element L1, and the transistor T16 are electrically connected in the current path of the driving current. In some embodiments, the driving transistor TD, the light-emitting element L1, and the transistor T16 are connected in series between the driving voltage terminals VDD and VSS. In some embodiments, the first terminal of the light-emitting element L1 is electrically connected to the driving voltage terminal VDD, and the second terminal of the light-emitting element L1 is electrically connected to the first terminal of the driving transistor TD. The second terminal of the driving transistor TD is electrically connected to the first terminal of the transistor T16. The second terminal of the transistor T16 is electrically connected to the driving voltage terminal VSS. Thus, the current path of the driving current has only two transistors (driving transistor TD and transistor T16), which can reduce the voltage difference between the driving voltage terminals VDD and VSS required for the operation of the driving circuit 100, thereby reducing power consumption.

[0056] In some embodiments, a reset circuit 112 is electrically connected to the gate of a driving transistor TD to reset the potential of the gate of the driving transistor TD. In some embodiments, the reset circuit 112 includes a transistor T8. Architecturally, a first terminal of transistor T8 is electrically connected to the gate of the driving transistor TD, a second terminal of transistor T8 is electrically connected to a reference voltage terminal V1, and the gate of transistor T8 is used to receive a control signal S1[n-1]. In some embodiments, transistor T8 conducts the current path from the gate of the driving transistor TD to the reference voltage terminal V1 according to the control signal S1[n-1], thereby resetting the voltage of the gate of the driving transistor TD to the potential of the reference voltage terminal V1, and then using the voltage of the reference voltage terminal V1 to turn on the driving transistor TD.

[0057] In some embodiments, compensation circuit 114 is electrically connected to the gate of driving transistor TD to compensate for the critical voltage of driving transistor TD. In some embodiments, compensation circuit 114 includes transistors T10 and T11. Architecturally, the first terminal of transistor T10 is electrically connected to the first terminal of driving transistor TD, and the second terminal of transistor T10 is electrically connected to the reference voltage terminal V3. The first terminal of transistor T11 is electrically connected to the second terminal of driving transistor TD, and the second terminal of transistor T11 is electrically connected to the gate of driving transistor TD. Furthermore, the gate terminals of transistors T10 and T11 are used to receive control signal S1[n]. In some embodiments, transistors T10 and T11 are turned on according to control signal S1[n] to transmit the voltage of reference voltage terminal V3 through transistor T10, driving transistor TD, and transistor T11 to the gate terminal of driving transistor TD until driving transistor TD is turned off, thereby compensating for the critical voltage of driving transistor TD.

[0058] In some embodiments, the first terminal of capacitor C1 is electrically connected to the gate terminal of the driving transistor TD, and the second terminal of capacitor C1 is electrically connected to the data setting circuit 116. In some embodiments, the second terminal of capacitor C1 is used to store the data voltage of the data signal DATA1 transmitted by the data setting circuit 116. In some embodiments, capacitor C1 is used to transmit the potential change of its second terminal to the gate terminal of the driving transistor TD through capacitive coupling, and the potential change includes the data voltage of the data signal DATA1.

[0059] In some embodiments, the data setting circuit 116 includes a transistor T6. Architecturally, a first terminal of transistor T6 is electrically connected to a second terminal of capacitor C1. The second terminal of transistor T6 is used to receive a data signal DATA1, and the gate terminal of transistor T6 is used to receive a multiple emission control signal mEM. In some embodiments, transistor T6 is used to conduct a current path from the data signal DATA1 to the second terminal of capacitor C1 according to the multiple emission control signal mEM, thereby transmitting the data voltage of the data signal DATA1 to the second terminal of capacitor C1, thereby performing data setting.

[0060] In some embodiments, capacitor C4 is electrically connected between the second terminal of capacitor C1 and the reference voltage terminal V1. In some embodiments, the first terminal of capacitor C4 is electrically connected to the second terminal of capacitor C1, and the second terminal of capacitor C4 is electrically connected to the reference voltage terminal V1. In some embodiments, capacitor C4 is used to stabilize the potential of capacitor C1.

[0061] In some embodiments, the pulse width modulation (PWM) circuit includes switching transistors TS1 and TS2, capacitors C2 to C5, transistors T1 to T7, T9 and T12 to T15, reset circuits 122 and 126, compensation circuits 124 and 127, and stabilization circuits 125 and 128.

[0062] In some embodiments, switching transistor TS1 is electrically connected between the driving voltage terminal VDD and the second terminal of capacitor C1. In some embodiments, the first terminal of switching transistor TS1 is electrically connected to the driving voltage terminal VDD via light-emitting element L1, and the second terminal of switching transistor TS1 is electrically connected to the gate terminal of driving transistor TD via capacitor C1. In some embodiments, the first terminal of switching transistor TS1 is electrically connected to the second terminal of light-emitting element L1, and the second terminal of switching transistor TS1 is electrically connected to the second terminal of capacitor C1. In some embodiments, switching transistor TS1 is used to conduct the current path between the driving voltage terminal VDD and the second terminal of capacitor C1 according to the potential of its gate terminal, thereby changing the potential of the second terminal of capacitor C1. This causes capacitor C1 to change the potential of the gate terminal of driving transistor TD according to the potential change of its second terminal, wherein the potential change includes the data voltage of data signal DATA1, thereby determining the conduction level of driving transistor TD and controlling the amplitude of the driving current flowing through light-emitting element L1.

[0063] In some embodiments, a reset circuit 126 is electrically connected to the gate of the switching transistor TS1 to reset the potential of the gate of the switching transistor TS1. In some embodiments, the reset circuit 126 includes a transistor T7. In some embodiments, a first terminal of the transistor T7 is electrically connected to the gate of the switching transistor TS1, a second terminal of the transistor T7 is electrically connected to a reference voltage terminal V1, and the gate of the transistor T7 is used to receive a control signal S1[n-1]. In some embodiments, the transistor T7 is turned on according to the control signal S1[n-1] to transfer the potential of the reference voltage terminal V1 to the gate of the switching transistor TS1, thereby resetting the switching transistor TS1.

[0064] In some embodiments, compensation circuit 127 is electrically connected to the gate of switching transistor TS1 to compensate for the threshold voltage of switching transistor TS1. In some embodiments, compensation circuit 124 includes transistor T2 and transistor T3. In some embodiments, the second terminal of transistor T3 is electrically connected to reference voltage terminal V2, and the first terminal and gate terminal of transistor T3 are electrically connected to the second terminal of transistor T2. In some embodiments, the first terminal of transistor T2 is electrically connected to the gate of switching transistor TS1, the second terminal of transistor T2 is electrically connected to the first terminal of transistor T3, and the gate terminal of transistor T2 is used to receive control signal S1[n]. In some embodiments, transistor T2 is used to conduct the current path from the first terminal of transistor T3 to the first terminal of capacitor C2 according to control signal S1[n]. In some embodiments, when transistor T2 is turned on, the reset potential stored at the first terminal of capacitor C2 is transmitted to the gate terminal of transistor T3 via transistor T2 to turn on transistor T3. When transistor T3 is turned on, the potential of the reference voltage terminal V2 is transmitted to the gate terminal of transistor T3 via transistor T3, and then to the first terminal of capacitor C2 via transistors T3 and T2, until transistor T3 is turned off. At this time, the potential of the first terminal of capacitor C2 (that is, the potential of the gate terminal of switching transistor TS1) includes the critical voltage factor of transistor T3, thereby matching and compensating the critical voltage of switching transistor TS1 through transistor T3.

[0065] In some embodiments, the first terminal of capacitor C2 is electrically connected to the gate terminal of switching transistor TS1, and the second terminal of capacitor C2 is electrically connected to the reference voltage terminal V1 via transistor T1 and switching transistor TS2. In some embodiments, switching transistor TS1 is used to conduct the current path between the driving voltage terminal VDD and the second terminal of capacitor C1 according to the potential of the first terminal of capacitor C2, so that capacitor C1 changes the potential of the gate terminal of driving transistor TD through capacitive coupling effect, thereby turning on driving transistor TD. In some embodiments, by placing capacitor C2 between the gate terminal of switching transistor TS1 and the first terminal of switching transistor TS2, the matching compensation factor of switching transistor TS1 can be prevented from being eliminated by the voltage of reference voltage terminal V1 after one light emission, thereby retaining the compensation factor of switching transistor TS1 during each light emission period after one compensation operation.

[0066] In some embodiments, a stabilizing circuit 128 is electrically connected to the second terminal of capacitor C2 to stabilize the potential of the second terminal of capacitor C2. In some embodiments, the stabilizing circuit 128 includes a transistor T4. In some embodiments, a first terminal of transistor T4 is electrically connected to the second terminal of capacitor C2, a second terminal of transistor T4 is electrically connected to a reference voltage terminal V2, and the gate terminal of transistor T4 is used to receive a multiple emission control signal mEM. In some embodiments, transistor T4 is used to conduct a current path from the reference voltage terminal V2 to the second terminal of capacitor C2 according to the multiple emission control signal mEM.

[0067] In some embodiments, capacitor C5 is electrically connected between the second terminal of capacitor C2 and the reference voltage terminal V1. In some embodiments, the first terminal of capacitor C5 is electrically connected to the second terminal of capacitor C2, and the second terminal of capacitor C5 is electrically connected to the reference voltage terminal V1. In some embodiments, capacitor C5 is used to stabilize the potential of capacitor C2.

[0068] In some embodiments, transistor T1 is electrically connected between the second terminal of capacitor C2 and the first terminal of switching transistor TS2. In some embodiments, the first terminal of transistor T1 is electrically connected to the second terminal of capacitor C2, the second terminal of transistor T1 is electrically connected to the first terminal of switching transistor TS2, and the gate terminal of transistor T1 is used to receive control signal S1[n]. In some embodiments, transistor T1 electrically isolates capacitor C2 from switching transistor TS2 during compensation according to control signal S1[n], to avoid the coupling phenomenon of capacitor C2 affecting the matching compensation of switching transistor TS1.

[0069] In some embodiments, the switching transistor TS2 is electrically connected to the current path between the reference voltage terminal V1 and the capacitor C2, so as to conduct the current path from the reference voltage terminal V1 to the capacitor C2 according to the potential of its gate terminal, thereby changing the potential of the second terminal of the capacitor C2. The potential change of the second terminal of the capacitor C2 changes the potential of the gate terminal of the switching transistor TS1 through capacitive coupling, thereby turning on the switching transistor TS1.

[0070] In some embodiments, a reset circuit 122 is electrically connected to the gate of the switching transistor TS2 to reset the potential of the gate of the switching transistor TS2. In some embodiments, the reset circuit 122 includes a transistor T9. In some embodiments, a first terminal of the transistor T9 is electrically connected to the gate of the switching transistor TS2, a second terminal of the transistor T9 is electrically connected to a reference voltage terminal V2, and the gate of the transistor T9 is used to receive a control signal S1[n-1]. In some embodiments, the transistor T9 is used to turn on the current path from the reference voltage terminal V2 to the gate of the switching transistor TS2 according to the control signal S1[n-1], thereby performing a reset operation on the switching transistor TS2.

[0071] In some embodiments, compensation circuit 124 is electrically connected to the gate of switching transistor TS2 to compensate for the critical voltage of switching transistor TS2. In some embodiments, compensation circuit 124 includes transistors T12 and T13. In some embodiments, the first terminal of transistor T12 is electrically connected to the second terminal of switching transistor TS2, the second terminal of transistor T12 is used to receive data signal DATA2, and the gate of transistor T12 is used to receive control signal S1[n]. In some embodiments, the first terminal of transistor T13 is electrically connected to the first terminal of switching transistor TS2, the second terminal of transistor T13 is electrically connected to the gate of switching transistor TS2, and the gate of transistor T13 is used to receive control signal S1[n]. In some embodiments, transistors T12 and T13 are turned on according to control signal S1[n] to transmit the data voltage of data signal DATA2 to the gate of switching transistor TS2 via transistor T12, switching transistor TS2, and transistor T13 until switching transistor TS2 is turned off, thereby compensating for the critical voltage of switching transistor TS2.

[0072] In some embodiments, capacitor C3 is electrically connected between the gate of switching transistor TS2 and the sweep signal line SWPL. In some embodiments, the first end of capacitor C3 is electrically connected to the gate of switching transistor TS2, and the first end of capacitor C3 is electrically connected to the sweep signal line SWPL via transistor T14. In some embodiments, the sweep signal line SWPL is used to transmit the sweep signal V. SWEEP In some embodiments, the sweep frequency signal V SWEEP The voltage increases linearly during the emission period. In some embodiments, the switching transistor TS2 is used to switch according to the sweep signal V of the sweep signal line SWPL. SWEEP The potential change of the reference voltage terminal V1 is turned on to conduct the current path between the reference voltage terminal V1 and the second terminal of the capacitor C2, so as to change the potential of the gate terminal of the switching transistor TS1 through the capacitive coupling effect of the capacitor C2, thereby turning on the switching transistor TS1.

[0073] In some embodiments, the stabilizing circuit 125 is electrically connected to the second terminal of capacitor C3, and the stabilizing circuit 125 is used to stabilize the potential of the second terminal of capacitor C3. In some embodiments, the stabilizing circuit 125 includes transistor T5. In some embodiments, the first terminal of transistor T5 is electrically connected to the second terminal of capacitor C3, the second terminal of transistor T5 is electrically connected to a reference voltage terminal V2, and the gate terminal of transistor T5 is used to receive a multiple emission control signal mAM. In some embodiments, transistor T5 is turned on according to the multiple emission control signal mAM to transfer the voltage of the reference voltage terminal V2 to the second terminal of capacitor C3, thereby stabilizing the potential of the second terminal of capacitor C3.

[0074] In some embodiments, the first terminal of transistor T14 is electrically connected to the second terminal of capacitor C3, the second terminal of transistor T14 is electrically connected to the sweep frequency signal line SWPL, and the gate terminal of transistor T14 is used to receive the multiple emission control signal mEM. In some embodiments, transistor T14 is used to electrically isolate the second terminal of capacitor C3 from the sweep frequency signal line SWPL according to the time when the multiple emission control signal mEM is outside the emission period, so as to avoid the coupling phenomenon of capacitor C3 affecting the waveform of the sweep frequency signal VSWEEP.

[0075] In some embodiments, the first terminal of transistor T15 is electrically connected to the second terminal of switching transistor TS2, the second terminal of transistor T15 is electrically connected to reference voltage terminal V1, and the gate terminal of transistor T15 is used to receive a multiple emission control signal mEM. In some embodiments, transistor T15 is used to turn on the current path from reference voltage terminal V1 to the second terminal of switching transistor TS2 during emission according to the multiple emission control signal mEM.

[0076] In some embodiments, the aforementioned transistors each have a first terminal, a second terminal, and a gate terminal. When the first terminal of one transistor is the drain / source terminal, the second terminal of the transistor is the source / drain terminal. Similarly, the aforementioned capacitors also each have a first terminal and a second terminal. When the first terminal of one capacitor is the anode / cathode, the second terminal of the capacitor is the cathode / anode.

[0077] Please see Figure 3 . Figure 3 This is a timing diagram of control signals according to an embodiment of this disclosure. Figure 3 As shown, a display cycle in the control timing of the drive circuit 100 can be divided into five periods, namely the reset period P. RES During the compensation period P COM During the stable period, P STA During the luminescence period P EM and P during the closure period OFF In some embodiments, a display cycle in the control timing of the drive circuit 100 includes a reset period P. RES During the period of one compensation P COM Multiple stable periods P STA And P during multiple luminescence periods EM During each two adjacent emission periods, P EM From a stable period P STA The interval. In some embodiments, P is during the reset period. RES and the compensation period P COMThe duration of each phase is one horizontal scan period. In some embodiments, the duration of the emission period (PEM) is two horizontal scan periods. It should be noted that... Figure 3 The durations of these periods are for illustrative purposes only and are not intended to limit this disclosure.

[0078] To make the overall operation of the drive circuit 100 clearer and easier to understand, please refer to the following: Figure 2 , Figure 3 as well as Figures 4A to 4F . Figure 4A According to an embodiment of the present disclosure, the drive circuit 100 operates during reset P. RES A diagram illustrating the operation. Figure 4B According to an embodiment of the present disclosure, the driving circuit 100 during the compensation period P COM A diagram illustrating the operation. Figure 4C To ensure that the driving circuit 100 according to an embodiment of this disclosure operates during the stable period P STA A diagram illustrating the operation. Figure 4D as well as Figure 4E According to an embodiment of the present disclosure, the driving circuit 100 illuminates P during the light emission period. EM A diagram illustrating the operation. Figure 4F According to an embodiment of the present disclosure, the drive circuit 100 operates during the off period P OFF A diagram illustrating the operation.

[0079] like Figure 3 As shown, the control signal S1[n-1] is in the reset period P RES Having a first logic level (e.g., a low logic level); control signal S1[n-1] during compensation period P COM During the stable period, P STA During the luminescence period P EM and P during the closure period OFF It has a second logic level (e.g., a high logic level).

[0080] In some embodiments, the control signal S1[n] is during the compensation period P COM It has a low logic level; the control signal S1[n-1] is P during the reset period. RES During the stable period, P STA During the luminescence period P EM and P during the closure period OFF It has a high logic level.

[0081] In some embodiments, the multiple emission control signal mEM is used during the emission period P. EM It has a low logic level; the multiple emission control signal mEM during the reset period P RES During the compensation period P COM During the stable period, PSTA and P during the closure period OFF It has a high logic level.

[0082] In some embodiments, the sweep frequency signal V SWEEP P during reset RES During the compensation period P COM During the stable period, P STA and P during the closure period OFF It has an initial voltage; the sweep frequency signal V SWEEP The potential P during luminescence EM It increases linearly, and P reaches a steady state during the plateau period. STA Return to the initial voltage.

[0083] It should be noted that, Yu Figure 2 , Figure 3 , Figures 4A to 4F In one embodiment, transistors T1, T4-T6, and switching transistor TS2 are N-type transistors, and transistors T2-T3, T7-T16, driving transistor TD, and switching transistor TS1 are P-type transistors. In other embodiments, transistors T1, T4-T6, and switching transistor TS2 may be implemented using P-type transistors, and transistors T2-T3, T7-T16, driving transistor TD, and switching transistor TS1 may be implemented using N-type transistors. In this case, adjustments can be made accordingly. Figure 3 In the embodiments, the control signals S1[n-1] and S1[n], and the sweep frequency signal V SWEEP The logic level of the multiple emission control signal mEM can be adjusted to achieve the same function as in this embodiment. Therefore, this invention is not limited thereto.

[0084] like Figure 4A As shown, during the reset P RES A control signal S1[n-1] applied to the first logic level (e.g., low logic level) is sent to the gate terminals of transistors T7 to T9 to turn on the current path from the reference voltage terminal V1 to the gate terminal of the driving transistor TD and the gate terminal of the switching transistor TS1, and to the current path from the reference voltage terminal V2 to the gate terminal of the switching transistor TS2, thereby resetting the gate terminal potentials of the driving transistor TD and the switching transistors TS1 to TS2.

[0085] In some embodiments, P during reset RES A multiple emission control signal mAM, applied to the second logic level (e.g., high logic level), is sent to the gate of transistor T5 to conduct the current path from the reference voltage terminal V2 to the second terminal of capacitor C3, thereby stabilizing the potential of the second terminal of capacitor C3.

[0086] In some embodiments, P during resetRES A multi-emission control signal mAM at a high logic level is applied to the gate of transistor T6 to turn on transistor T6. This allows the data voltage of the data signal DATA1 to be transmitted to the second terminal of capacitor C1 via transistor T6, thereby stabilizing the potential of the second terminal of capacitor C1. Furthermore, the data voltage of the data signal DATA1 is transmitted to the first terminal of the driving transistor TD via transistor T6 and switching transistor TS1, thereby stabilizing the potential of the first terminal of the driving transistor TD.

[0087] In some embodiments, P during reset RES A multi-emission control signal mAM at a high logic level is applied to the gate of transistor T4 to turn on transistor T4, thereby conducting the current path from capacitor C2 to the reference voltage terminal V2 of transistor TS2, thereby stabilizing the potential of the second terminal of capacitor C2 and the second terminal of transistor TS2.

[0088] During the reset P RES A control signal S1[n] at a high logic level is applied to the gate terminals of transistors T2 and T10-T13 to turn off transistors T2 and T10-T13. Furthermore, a multiple emission control signal mAM at a high logic level is applied to transistors T14-T16 to turn off transistors T14-T16.

[0089] In some embodiments, the voltages of the voltage terminals and signal terminals of the driving circuit 100 are ordered from largest to smallest as follows: the voltage of reference voltage terminal V2, the voltage of reference voltage terminal V3, the voltage of driving voltage terminal VDD, and the voltage of reference voltage terminal V1. That is, the voltages of reference voltage terminals V2 and V3 are greater than the voltage of driving voltage terminal VDD, and the voltage of reference voltage terminal V1 is less than the voltage of driving voltage terminal VDD. In some embodiments, the data voltage of the data signal DATA2 is less than the voltage of reference voltage terminal V2.

[0090] During the reset P RES Node N A (The connection between the gate of the driving transistor TD and the first terminal of capacitor C1) and node N C The voltage at the connection point between the gate of switching transistor TS1 and the first terminal of capacitor C2 is essentially equal to the potential of the reference voltage terminal V1. Node N B The voltage at the connection point between the second terminal of capacitor C1 and the first terminal of transistor T6 is essentially equal to the data voltage of the data signal DATA1. Node N D (The connection between the gate of switching transistor TS2 and the first terminal of capacitor C3), N E (The connection between the second terminal of capacitor C3 and the first terminal of transistor T5) and N FThe voltage at the connection point between the second terminal of capacitor C2 and the first terminal of transistor T1 is essentially equal to the potential of the reference voltage terminal V2.

[0091] like Figure 4B As shown, during the compensation period P COM In the process, a control signal S1[n] at a low logic level is applied to the gate of transistors T10 to T11 to turn on transistors T10 to T11. This allows the voltage of the reference voltage terminal V3 to be transmitted to the gate of the driving transistor TD via transistor T10, driving transistor TD, and transistor T11 until the gate of the driving transistor TD is turned off, thereby compensating for the critical voltage of the driving transistor TD.

[0092] During the compensation period P COM In this process, a control signal S1[n] at a low logic level is applied to the gate terminals of transistors T12-T13 to turn on transistors T12-T13. This causes the reset voltage at the first terminal of capacitor C3 (e.g., the voltage at the reference voltage terminal V2) to be pulled down by the data voltage of the data signal DATA2 via transistor T13, switching transistor TS2, and transistor T12 until switching transistor TS2 is turned off. At this time, the potential at the gate terminal of switching transistor TS2 is substantially equal to the sum of the data voltage of the data signal DATA2 and the threshold voltage of switching transistor TS2. Thus, the potential at the gate terminal of switching transistor TS2 includes the data voltage of the data signal DATA2 and the threshold voltage of switching transistor TS2. In some embodiments, the voltage at the reference voltage terminal V2 is greater than the data voltage of the data signal DATA2.

[0093] In some embodiments, during the compensation period P COM In the process, a control signal S1[n] at a low logic level is applied to the gate of transistor T2 to turn on transistor T2. This causes the reset voltage stored at the first terminal of capacitor C2 to be transferred to the gate of transistor T3 via transistor T2, thereby turning on transistor T3. When transistor T3 is turned on, the potential of the reference voltage terminal V2 is transferred to the first terminal of capacitor C2 and the gate of transistor T3 via transistor T3 until transistor T3 is turned off. Thus, node N... C The potential is essentially equal to the difference between the absolute value of the critical voltage of transistor T3 and the voltage at the reference voltage terminal V2. Therefore, the compensation circuit 127 performs matching compensation on the critical voltage of switching transistor TS1.

[0094] In some embodiments, during the compensation period P COM In this process, a multi-emission control signal mAM at a high logic level is applied to the gate of transistors T4-T5 to turn on transistors T4-T5, thereby stabilizing the potential at the second terminals of capacitors C2-C3. In some embodiments, during the compensation period P COMIn the process, a multi-emission control signal mAM at a high logic level is applied to the gate of transistor T6 to turn on transistor T6, thereby stabilizing the potential at the second end of capacitor C1.

[0095] During the compensation period P COM Node N B The voltage is essentially equal to the data voltage of the data signal DATA1. Node N E and N F The voltage at node N is essentially equal to the potential at the reference voltage terminal V2. A Node N C and node N D It can be expressed by the following formula.

[0096] V NA =V3-|V TH_TD |

[0097] V NC =V2-|V TH_T3 |

[0098] V ND =V DATA2 +V TH_TS2

[0099] In the above formula, V NA Representative node N A The potential, |V TH_TD | Represents the absolute value of the critical voltage of the driving transistor TD. V NC Representative node N C The potential, |V TH_T3 | Represents the absolute value of the critical voltage of transistor T3. V DATA2 The data voltage representing the data signal DATA2 and |V TH_TS2 | represents the absolute value of the threshold voltage of switching transistor TS2. In some embodiments disclosed herein, V2 is used to represent the reference voltage terminal V2 or the potential of the reference voltage terminal V2, and V3 is used to represent the reference voltage terminal V3 or the potential of the reference voltage terminal V3.

[0100] like Figure 4C As shown, during the steady period P STA A multi-emission control signal mAM at a high logic level is applied to the gate of transistor T6 to turn on transistor T6, thereby stabilizing the potential of the second terminal of capacitor C1 using the data voltage of data signal DATA1. In some embodiments, during the stabilization period, P... STAA multi-emission control signal mAM, applied to a high logic level, is sent to the gate terminals of transistors T4-T5 to conduct the current path from the reference voltage terminal V2 to the second terminals of capacitors C2 and C3, thereby stabilizing the potentials of the second terminals of capacitors C2 and C3. In some embodiments, during the stabilization period, P... STA In the process, a control signal S1[n] at a high logic level is applied to the gate of transistor T1 to turn on transistor T1, so that the voltage of reference voltage terminal V2 is transmitted to the first terminal of switching transistor TS2 via transistors T4 and T1 to stabilize the potential of the first terminal of switching transistor TS2.

[0101] During the stable period P STA A control signal S1[n] at a high logic level is applied to the gate terminals of transistors T2 and T10-T13 to turn off transistors T2 and T10-T13. A control signal S1[n-1] at a high logic level is applied to transistors T7-T9 to turn off transistors T7-T9. Furthermore, a multiple emission control signal mAM at a high logic level is applied to transistors T14-T16 to turn off transistors T14-T16.

[0102] In some embodiments, node N A ~N F During the stable period P STA The potentials in the nodes are similar to or equivalent to those in node N. A ~N F During the compensation period P COM The electrical potential at the end will not be described further here.

[0103] During the luminescence period P EM For the initial operation of the drive circuit 100, please refer to [link / reference]. Figure 4D .like Figure 4D As shown, by applying a multiple-emission control signal mAM at a low logic level to the gate terminals of transistors T15-T16, the current path from the second terminal of switching transistor TS2 to the reference voltage terminal V1 and the current path from the second terminal of driving transistor TD to the driving voltage terminal VSS are turned on. Furthermore, during the emission period P... EM By applying a control signal S1[n] at a high logic level to the gate of transistor T1, the current path from the second terminal of capacitor C2 to the first terminal of switching transistor TS2 is turned on.

[0104] During the luminescence period P EMTransistors T4 to T6 are turned off by applying a multiple-emission control signal mAM at a low logic level to the gate terminals of transistors T4 to T6. Transistors T2 and T10 to T13 are turned off by applying a control signal S1[n] at a high logic level to the gate terminals of transistors T2 and T10 to T13. Transistors T7 to T9 are turned off by applying a control signal S1[n-1] at a high logic level to the gate terminals of transistors T7 to T9.

[0105] During the luminescence period P EM The low-logic-level multiple emission control signal mEM is applied to the gate of transistor T14 to turn on the current path from the second terminal of capacitor C3 to the sweep signal line SWPL, thus enabling the sweep signal V... SWEEP The light is transmitted to the second terminal of capacitor C3 via transistor T14. During the light-emitting period, P... EM Initially, the potential at the second terminal of capacitor C3 is pulled down from the voltage at the reference voltage terminal V2 to the sweep frequency signal V. SWEEP The initial voltage is then used to pull down the gate potential of switching transistor TS2 via the coupling effect of capacitor C3. Next, the sweep frequency signal V... SWEEP The voltage during the emission period P EM As the capacitance increases linearly, the coupling effect of capacitor C3 gradually pulls up the potential of the gate terminal of switching transistor TS2.

[0106] During the luminescence period P EM Furthermore, when switching transistor TS2 is turned off, node N B The potential is essentially equal to the data voltage of the data signal DATA1. Node N E The potential is essentially equal to the sweep frequency signal V. SWEEP The voltage at node N. F The potential of node N is essentially equal to the potential of the reference voltage terminal V2. In some embodiments, node N A N C ~N D During the luminescence period P EM The voltage can be expressed by the following formula.

[0107] V NA =V3-|V TH_TD |

[0108] V NC =V2-|V TH_T3 |

[0109] V ND =V SWEEP -V2+V DATA2 +V TH_TS2

[0110] In the above formula, V NARepresentative node N A voltage, V NC Representative node N C voltage, V ND Representative node N D voltage, V DATA2 The data voltage, V, represents the data signal DATA2. TH_TD V represents the critical voltage for driving transistor TD. TH_T3 V represents the critical voltage of transistor T3. TH_TS2 This represents the critical voltage for switching transistor TS2. In some embodiments, V SWEEP Used to represent the sweep frequency signal V SWEEP The potential.

[0111] It is worth noting that the gate terminal of switching transistor TS1 (node ​​N) C The potential of the switching transistor TS1 includes the critical voltage of transistor T3. Therefore, by matching and compensating the switching transistor TS1 with the critical voltage of transistor T3, the influence of the critical voltage variation of switching transistor TS1 on the rising edge of the drive current is improved, thereby reducing the error of the area under the curve of the drive current and thus improving the accuracy of grayscale control.

[0112] During the luminescence period P EM Switching the gate of transistor TS2 (node ​​N) D The voltage across the second terminal (source terminal) of the switching transistor TS2 can be expressed by the following formula.

[0113] V GS_TS2 =(V SWEEP -V2+V DATA2 +V TH_TS2 )-V1

[0114] In the above formula, V GS_TS2 This represents the voltage across the gate and source terminals of the switching transistor TS2. In some embodiments, the switching transistor TS2 will turn on when the voltage across the gate and source terminals is greater than a threshold voltage, as can be expressed by the following conditional expression.

[0115] (V SWEEP -V2+V DATA2 +V TH_TS2 -V1>V TH_TS2

[0116] Based on the above formulas, the following formulas can be derived.

[0117] V SWEEP >V2-V DATA2 +V1

[0118] In detail, when the sweep frequency signal V SWEEP When the voltage change of the reference voltage terminal V2 is greater than the sum of the voltages of V2 and V1 minus the data voltage of the data signal DATA2, the switching transistor TS2 is turned on. Thus, by setting the data voltage of the data signal DATA2, the timing of the switching transistor TS2's onset can be controlled. In some embodiments, since the sweep frequency signal V... SWEEP The electrical position of P during luminescence EM The voltage of the data signal DATA2 increases linearly. A higher data voltage DATA2 requires less time to reach the aforementioned condition, causing the switching transistor TS2 to turn on earlier and resulting in a larger pulse width for the drive current. Conversely, a lower data voltage DATA2 requires more time to reach the condition, causing the switching transistor TS2 to turn on later and resulting in a smaller pulse width for the drive current. Thus, the drive circuit 100 controls the grayscale brightness through pulse width modulation.

[0119] P during luminescence EM Please refer to the instructions for switching transistor TS2 on. Figure 4E .like Figure 4E As shown, when switching transistor TS2 is turned on, the voltage at the reference voltage terminal V1 changes the potential at the second terminal of capacitor C2 through the current path of transistor T15, switching transistor TS2, and transistor T1. This, in turn, changes the potential at the gate terminal of switching transistor TS1 through the coupling effect of capacitor C2, thus turning on switching transistor TS1. When switching transistor TS1 is turned on, the voltage at the driving voltage terminal VDD is transmitted to the second terminal of capacitor C1 through the light-emitting element L1 and switching transistor TS1, changing the potential at the second terminal of capacitor C1. This, in turn, changes the potential at the gate terminal of driving transistor TD through the coupling effect of capacitor C1, thus turning on driving transistor TD.

[0120] Thus, through the capacitive coupling effect of capacitor C1, node N is connected... B The voltage change is transmitted to the gate of the driving transistor TD. During the light emission period, P EM Furthermore, when switching transistor TS2 is turned on, node N B The potential is essentially equal to the difference between the voltage at the driving voltage terminal VDD and the voltage drop across the light-emitting element L1. Node N C The potential is essentially equal to the sum of the potential of the reference voltage terminal V1 and the critical voltage of transistor T3. Node N E The potential is essentially equal to the sweep frequency signal V. SWEEP The voltage at node N. F The potential of the reference voltage terminal V1 is essentially equal to the potential of the reference voltage terminal V1. In some embodiments, the gate terminal (node ​​N) of the driving transistor TD... A) and the potential of the source terminal (in this operation, the potential of the source terminal can be determined by node N) B The potential (understanding) can be expressed by the following formula.

[0121] V NA =(VDD-V LED )-V DATA1 +(V3-|V TH_TD |)

[0122] V NB =(VDD-V LED )

[0123] In the above formula, VDD is used to represent the potential of the drive voltage terminal VDD. LED It is used to represent the voltage drop of the light-emitting element L1.

[0124] Therefore, based on the source end (node ​​N) of the driving transistor TD B and the gate terminal (node ​​N) A The formula for the driving current across the voltage () between the voltage and the voltage () can be expressed by the following formula.

[0125] I LED =K[(V NB -V NA )-|V TH_TD |] 2

[0126] ILED=K[V DATA1 -V3] 2

[0127] In the above formula, I LED K represents the amplitude of the drive current, and K represents a coefficient related to the characteristics of the drive transistor TD. Therefore, the critical voltage of the drive transistor TD has been removed from the factors affecting the amplitude of the drive current, thus compensating for the critical voltage of the drive transistor TD. Furthermore, by removing the voltage at the drive voltage terminal VDD from the factors affecting the amplitude of the drive current, the voltage drop at the drive voltage terminal VDD is compensated, thereby improving the uniformity of the drive current generated by the drive circuit in the overall panel. In some embodiments, since the drive current generated by the drive circuit 100 is less affected by the voltage drop at the drive voltage terminal VDD, the drive circuit 100 can be applied to a splicing display of micro-LEDs, wherein the splicing display is a matrix arrangement of multiple displays, and the compensation operation of the drive circuit 100 for the voltage drop at the drive voltage terminal VDD can improve the uniformity of the drive current in the overall panel.

[0128] like Figure 4F As shown, during the second and subsequent stable periods P in the display cycle STAThe high logic level multiple emission control signal mAM is applied to the gate terminals of transistors T4-T5, causing transistors T4-T5 to conduct the current path from the reference voltage terminal V2 to capacitors C2 and C3. This coupling effect restores the potential of the gate terminals of switching transistors TS1 and TS2 to the voltage after the compensation operation. Furthermore, the high logic level multiple emission control signal mAM is applied to the gate terminal of transistor T6, transmitting the data voltage of the data signal DATA1 to the second terminal of capacitor C1. This coupling effect of capacitor C1 restores the potential of the gate terminal of the driving transistor TD to the voltage after the compensation operation.

[0129] It is worth noting that by setting capacitor C1, the critical voltage compensation factor of the driving transistor TD can be avoided during a single light-emitting operation. By setting capacitor C2, the critical voltage compensation factor of P during a single light-emitting operation can be avoided. EM This eliminates the matching compensation factor for switching transistor TS1. By setting capacitor C3, the issue of P during a single emission can be avoided. EM This eliminates the impact of the critical voltage compensation of switching transistor TS2 and the voltage of data signal DATA2. Therefore, during each light emission period after a reset and compensation operation, P... EM In this circuit, the driving circuit 100 can retain the critical voltage compensation of the driving transistor TD, the matching compensation of the switching transistor TS1, the critical voltage compensation of the switching transistor TS2, and the voltage factor of the data signal DATA2.

[0130] In some embodiments, the drive circuit 100 is in the off period P OFF The operation is similar to that of drive circuit 100 during the stable period P STA The operation of the circuit. In some embodiments, the drive circuit 100 is in the off period P OFF Each node N A ~N E The potential is similar to / equal to that of the drive circuit 100 during the stable period P. STA Each node N A ~N E The potential. Therefore, this will not be elaborated further.

[0131] Please see Figure 2 as well as Figures 5A to 5D The driving current I of the driving circuit 100 during multiple light emission periods according to an embodiment of this disclosure. GL255 I GL127 and I GL32 Sweep signal V SWEEP And a schematic diagram of the multiple emission control signal mEM.

[0132] like Figure 5DAs shown, one display cycle of the driving circuit 100 includes multiple light-emitting periods, which correspond to multiple periods during which the light-emitting control signal mEM is at a low logic level. In some embodiments, the sweep frequency signal V SWEEP The voltage increases linearly during each emission period, and the sweep frequency signal V SWEEP The voltage returns to the initial potential at the end of each emission period.

[0133] like Figures 5A to 5C As shown, when the data voltage of the data signal DATA2 is set according to grayscale values ​​of 255, 127, and 32 respectively, the driving circuit 100 generates a driving current I respectively. GL255 I GL127 I GL32 To drive the light-emitting element L1. In some embodiments, the drive current I... GL255 I GL127 I GL32 The falling edge occurs at a time corresponding to the falling edge of the multiple emission control signal mEM, and the data voltage of the data signal DATA2 determines the drive current I. GL255 I GL127 I GL32 The timing of the rising edge of the current causes the drive current I to... GL255 I GL127 I GL8 The rise in current I occurs at different points in time during multiple emission periods. Thus, the driving current I... GL255 I GL127 I GL32 Different pulse widths are used to achieve grayscale dimming through pulse width modulation.

[0134] Please refer to Table 1 below for the compensation effect on the critical voltage of the driving transistor TD and the voltage drop at the driving voltage terminal VDD.

[0135] +0.3 -0.5 48.949 0.96 0 0 49.423 0 -0.3 -0.5 48.796 1.27

[0136] Table 1

[0137] As shown in Table 1, ΔV TH_TD This represents the critical voltage variation of the driving transistor TD. ΔV DD This represents the voltage drop at the drive voltage terminal VDD of the drive circuit 100. LEDThis represents the pulse amplitude of the drive current generated by the drive circuit 100. In some embodiments, when the voltage drop at the drive voltage terminal VDD is -0.5 volts and the critical voltage variation of the drive transistor TD is +0.3 volts, the error between the amplitude of the drive current (e.g., 48.949 μA) and the amplitude of the normal drive current (e.g., 49.423 μA) is 0.96%. In some embodiments, when the voltage drop at the drive voltage terminal VDD is -0.5 volts and the critical voltage variation of the drive transistor TD is -0.3 volts, the error between the amplitude of the drive current (e.g., 48.796 μA) and the amplitude of the normal drive current (e.g., 49.423 μA) is 1.27%. Therefore, when the critical voltage variation of the drive transistor TD is in the range of +0.3 to -0.3 volts and the voltage drop at the drive voltage terminal VDD is -0.5 volts, the error in the amplitude of the drive current can be reduced to below 1.3%. In other words, the architecture and operation of the drive circuit 100 can effectively compensate for the critical voltage variation of the drive transistor TD and the voltage drop at the drive voltage terminal VDD.

[0138] Please see Figure 6 This is a schematic diagram of the drive current provided by the drive circuit in the event of a critical voltage variation of the switching transistor TS2, according to an embodiment of this disclosure. Figure 6 As shown, in some embodiments, when the critical voltage variation of switching transistor TS2 is +0.3 volts, its drive current I +0.3 The rising edge of the current I0 precedes the rising edge of the normal drive current I0 by 38.4 nanoseconds. In some embodiments, when the critical voltage variation of the switching transistor TS2 is -0.3 volts, its drive current I0... -0.3 The rising edge of the current is delayed by 30.1 nanoseconds compared to the rising edge of the normal drive current I0. Thus, by Figure 6 As can be seen from the embodiments, the drive circuit 100 can effectively compensate for the critical voltage variation of the switching transistor TS2.

[0139] Please see Figure 7A as well as Figure 7B . Figures 7A to 7B According to an embodiment of this disclosure, the driving current I during a single emission period is... GL32 I GL16 A schematic diagram. In some embodiments, when the data voltage of the data signal DATA2 is set according to 32 gray levels, the drive current I... GL32 The area under the curve is 3.1815 × 10⁻⁶. -11Ampere-second. When the data voltage of data signal DATA2 is based on 32 gray levels, and the critical voltage variations of switching transistors TS1, T3, and T1 are considered, please refer to Table 2 below for the effect of matching compensation on switching transistor TS1.

[0140]

[0141] Table 2

[0142] As shown in Table 2, ΔV TH_TS1 This represents the critical voltage variation of the switching transistor TS1, ΔV TH_T3 This represents the critical voltage variation of transistor T3, and ΔV TH_T1 This represents the critical voltage variation of transistor T1. In some embodiments, when the data voltage of data signal DATA2 is set according to 32 gray levels, and the critical voltage variation of switching transistors TS1, T1, and T3 is +0.3 volts, the area under the curve of its drive current is 3.1525 × 10⁻⁶. -11 The area under the curve of ampere-second versus normal drive current (e.g., 3.1815 × 10⁻⁶) -11 The error (ampere-second) is 0.91%. In some embodiments, when the data voltage of data signal DATA2 is set according to 16 gray levels, and the critical voltage variation of switching transistors TS1, T1, and T3 is -0.3 volts, the area under the curve of its drive current is 3.2109 × 10⁻⁶. -11 The area under the curve of ampere-second versus normal drive current (e.g., 3.1815 × 10⁻⁶) -11 The error (ampere-second) is 0.92%. Therefore, at a grayscale of 32, when the critical voltage variations of switching transistors TS1, T1, and T3 are within the range of +0.3 to -0.3 volts, the error of the area under the curve of the drive current can be reduced to below 1%. In other words, the architecture and operation of the drive circuit 100 can effectively compensate for the critical voltage variations of switching transistor TS1 using transistor T3, thereby improving the waveform of the drive current at low grayscale levels.

[0143] In some embodiments, when the data voltage of the data signal DATA2 is set according to 16 gray levels, the drive current I... GL16 The area under the curve is 6.7781 × 10⁻⁶. -12 Ampere-second. When the data voltage of data signal DATA2 is set according to 16 gray levels, and the critical voltage variations of switching transistors TS1, T3, and T1 are considered, please refer to Table 3 below for the effect of matching compensation on switching transistor TS1.

[0144]

[0145] Table 3

[0146] As shown in Table 3, in some embodiments, when the data voltage of data signal DATA2 is set according to 16 gray levels, and the critical voltage variation of switching transistors TS1, T1, and T3 is +0.3 volts, the area under the curve of its drive current is 6.6584 × 10⁻⁶. -12 The area under the curve of ampere-second versus normal drive current (e.g., 6.7781 × 10⁻⁶) -12 The error (ampere-second) is 1.76%. In some embodiments, when the data voltage of data signal DATA2 is set according to 16 gray levels, and the critical voltage variation of switching transistors TS1, T1, and T3 is -0.3 volts, the area under the curve of its drive current is 6.9077 × 10⁻⁶. -12 The area under the curve of ampere-second versus normal drive current (e.g., 3.1815 × 10⁻⁶) -12 The error in ampere-seconds (A / s) is 0.91%. Therefore, at 16 grayscale, when the critical voltage variations of switching transistors TS1, T1, and T3 are within the range of +0.3 to -0.3 volts, the error in the area under the curve of the drive current can be reduced to below 2%. In other words, the architecture and operation of the drive circuit 100 can effectively compensate for the critical voltage variations of switching transistor TS1 using transistor T3, thereby improving the waveform of the drive current at low grayscale levels.

[0147] Please see Figures 8A to 8C . Figures 8A to 8C The drive current I of the drive circuit 100 according to an embodiment of this disclosure GL255 I GL127 and I GL8 A schematic diagram during a single emission. In some embodiments, when the data voltage of the data signal DATA2 (e.g., 10.2 volts) is set according to a grayscale of 255, the drive current I... GL255 The rise time is 1.55 microseconds. In some embodiments, when the data voltage of the data signal DATA2 (e.g., 3.2 volts) is set according to 127 grayscale levels, the drive current I... GL127 The rise time is 1.56 microseconds. When the data voltage of the data signal DATA2 (e.g., 1.445 volts) is set according to the grayscale of 8, the drive current I... GL8 The rise time is 0.662 microseconds. (By...) Figures 8A to 8C As can be seen from the embodiments, the driving circuit 100 can significantly improve the rise time of the driving current, thereby controlling the grayscale more accurately, and enabling the light-emitting element L1 to operate at the point of optimal luminous efficiency in the full grayscale.

[0148] In summary, the driving circuit 100 of this disclosure turns on the switching transistor TS1 through the coupling effect of capacitor C2, which avoids eliminating the matching compensation factor for the switching transistor TS1 during the light emission operation, thereby significantly reducing the error of the area under the curve of the driving current and increasing the accuracy of grayscale control. The compensation operation for the voltage drop at the driving voltage terminal VDD in this disclosure makes the driving circuit 100 suitable for splicing screens, improving overall uniformity. The driving circuit 100 of this disclosure can effectively compensate for the critical voltage variations of the driving transistor TD, the switching transistor TS1, and the switching transistor TS2, thereby improving the uniformity of the driving current.

[0149] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various modifications and alterations without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

Claims

1. A driving circuit, characterized in that, Include: A driving transistor is electrically connected between a first driving voltage terminal and a second driving voltage terminal to control a driving current supplied to a light-emitting element; A first capacitor, the first terminal of which is electrically connected to the gate terminal of the driving transistor; A first switching transistor, the first terminal of which is electrically connected to the first terminal of the driving transistor, and the second terminal of which is electrically connected to the second terminal of the first capacitor. A second capacitor, the first terminal of which is electrically connected to the gate terminal of the first switching transistor; A second switching transistor is electrically connected between the second terminal of the second capacitor and a first reference voltage terminal; and A third capacitor is electrically connected between the gate of the second switching transistor and a sweep signal line.

2. The driving circuit as described in claim 1, characterized in that, The second switching transistor is used to conduct the current path between the first reference voltage terminal and the second terminal of the second capacitor according to the potential change of a sweep signal of the sweep signal line, so that the second capacitor can change the potential of the gate terminal of the first switching transistor through capacitive coupling effect, thereby turning on the first switching transistor.

3. The driving circuit as described in claim 1, characterized in that, The first switching transistor is used to conduct the current path between the first driving voltage terminal and the second terminal of the first capacitor according to the potential of the first terminal of the second capacitor, so that the first capacitor changes the potential of the gate terminal of the driving transistor through the capacitive coupling effect, thereby turning on the driving transistor.

4. The driving circuit as described in claim 1, characterized in that, It also includes: A first transistor, the first terminal of which is electrically connected to the second terminal of the second capacitor, the second terminal of which is electrically connected to the first terminal of the second switching transistor, and the gate terminal of which is used to receive a first control signal. as well as A first compensation circuit is electrically connected to the gate terminal of the first switching transistor to compensate for the critical voltage of the first switching transistor.

5. The driving circuit as described in claim 4, characterized in that, The first compensation circuit includes: A second transistor, the first terminal of which is electrically connected to the gate terminal of the first switching transistor, the gate terminal being used to receive the first control signal; and A third transistor, the first terminal and the gate terminal of which are electrically connected to the second terminal of the second transistor, and the second terminal of which is electrically connected to a second reference voltage terminal.

6. The driving circuit as described in claim 1, characterized in that, It also includes: A first stabilizing circuit is electrically connected to the second terminal of the second capacitor to stabilize the potential at the second terminal of the second capacitor, wherein the first stabilizing circuit comprises: A fourth transistor, the first terminal of which is electrically connected to the second terminal of the second capacitor, the second terminal of which is electrically connected to a second reference voltage terminal, and the gate terminal of which is used to receive a multiple emission control signal; and A second stabilizing circuit is electrically connected to the second terminal of the third capacitor to stabilize the potential of the second terminal of the third capacitor, wherein the first terminal of the third capacitor is electrically connected to the gate terminal of the second switching transistor, and wherein the second stabilizing circuit includes: A fifth transistor, the first terminal of which is electrically connected to the second terminal of the third capacitor, the second terminal of which is electrically connected to the second reference voltage terminal, and the gate terminal of which is used to receive the multiple light emission control signal.

7. The driving circuit as described in claim 1, characterized in that, It also includes: A data setting circuit, electrically connected to the second terminal of the first capacitor, is used to transmit a first data voltage of a first data signal to the second terminal of the first capacitor, wherein the data setting circuit includes: A sixth transistor, the first terminal of which is electrically connected to the second terminal of the first capacitor, the second terminal of which is used to receive a first data signal, and the gate terminal of which is used to receive a multiple emission control signal.

8. The driving circuit as described in claim 1, characterized in that, It also includes: A first reset circuit, electrically connected to the gate terminal of the first switching transistor, is used to reset the potential of the gate terminal of the first switching transistor, wherein the first reset circuit includes: A seventh transistor, the first terminal of which is electrically connected to the gate terminal of the first switching transistor, the second terminal of which is electrically connected to the first reference voltage terminal, and the gate terminal of which is used to receive a second control signal. A second reset circuit, electrically connected to the gate terminal of the driving transistor, is used to reset the potential of the gate terminal of the driving transistor, wherein the second reset circuit includes: An eighth transistor, the first terminal of which is electrically connected to the gate terminal of the driving transistor, the second terminal of which is electrically connected to the first reference voltage terminal, and the gate terminal of which is used to receive the second control signal; and A third reset circuit, electrically connected to the gate terminal of the second switching transistor, is used to reset the potential of the gate terminal of the second switching transistor, wherein the third reset circuit includes: A ninth transistor, the first terminal of which is electrically connected to the gate terminal of the second switching transistor, and the second terminal of which is electrically connected to a second reference voltage terminal, the gate terminal of which is used to receive the second control signal.

9. The driving circuit as described in claim 1, characterized in that, It also includes: A first compensation circuit, electrically connected to the gate terminal of the driving transistor, is used to compensate for the critical voltage of the driving transistor, wherein the first compensation circuit includes: A tenth transistor, the first terminal of which is electrically connected to the first terminal of the driving transistor, the second terminal of which is electrically connected to a third reference voltage terminal, and the gate terminal of which is used to receive a first control signal; and An eleventh transistor, the first terminal of which is electrically connected to the second terminal of the driving transistor, and the second terminal of which is electrically connected to the gate terminal of the driving transistor, the gate terminal being used to receive the first control signal. as well as A second compensation circuit, electrically connected to the gate terminal of the second switching transistor, is used to compensate for the threshold voltage of the second switching transistor, wherein the second compensation circuit includes: A twelfth transistor, the first terminal of which is electrically connected to the second terminal of the second switching transistor, the second terminal of which is used to receive a second data signal, and the gate terminal of which is used to receive the first control signal; and A thirteenth transistor, the first terminal of which is electrically connected to the first terminal of the second switching transistor, and the second terminal of which is electrically connected to the gate terminal of the second switching transistor, the gate terminal being used to receive the first control signal.

10. The driving circuit as described in claim 1, characterized in that, It also includes: A fourteenth transistor, the first terminal of which is electrically connected to the second terminal of the third capacitor, the second terminal of which is used to receive a sweep frequency signal, and the gate terminal of which is used to receive a multiple emission control signal. A fifteenth transistor, the first terminal of which is electrically connected to the second terminal of the second switching transistor, the second terminal of which is electrically connected to the first reference voltage terminal, and the gate terminal of which is used to receive the multiple light emission control signal. A sixteenth transistor, the first terminal of which is electrically connected to the second terminal of the driving transistor, the second terminal of which is electrically connected to the second driving voltage terminal, and the gate terminal of which is used to receive the multiple light emission control signal. A fourth capacitor, the first terminal of which is electrically connected to the second terminal of the first capacitor, and the second terminal of which is electrically connected to the first reference voltage terminal; and A fifth capacitor, the first terminal of which is electrically connected to the second terminal of the second capacitor, and the second terminal of which is electrically connected to the first reference voltage terminal.

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