Scan driver and display device

Abstract

A scan driver and a display device are disclosed. The scan driver includes multiple stages. Each of the multiple stages includes a control circuit that controls the voltage of a first node and the voltage of a second node in response to an input signal, a first clock signal, and a second clock signal; a carry output circuit that outputs a carry signal in response to the voltage of the first node and the voltage of the second node; an enable node control circuit that controls the voltage of an enable node in response to the carry signal, an enable signal, and an inverted enable signal; a masking circuit that controls the voltage of a third node in response to the voltage of the second node and the voltage of the enable node; and a scan output circuit that outputs a scan signal in response to the voltage of the first node and the voltage of the third node.

Description

Technical Field

[0001] Embodiments of the present invention relate to display devices, and more specifically, to a scan driver in a display device performing multi-frequency drive (“MFD”) and a display device including a scan driver. Background Technology

[0002] In portable devices such as smartphones and tablets, reduced power consumption can be beneficial for display devices. To reduce power consumption, low-frequency driving technology can be used to drive or refresh the display panel at a frequency lower than the normal driving frequency. Summary of the Invention

[0003] In display devices employing low-frequency drive technology, when a still image is not displayed across the entire display panel, or when a still image is displayed only in a portion of the display panel, the entire display panel may be driven at the normal drive frequency. Therefore, in such cases, low-frequency drive may not be performed, and power consumption may not be reduced.

[0004] Some implementations provide a scan driver capable of providing multiple scan signals to corresponding areas of a display panel at different drive frequencies.

[0005] Some implementations provide a display device that includes a scan driver.

[0006] In embodiments of this disclosure, a scan driver comprising multiple stages is provided. Each of the multiple stages includes a control circuit that controls the voltage of a first node and the voltage of a second node in response to an input signal, a first clock signal, and a second clock signal; a carry output circuit that outputs a carry signal in response to the voltage of the first node and the voltage of the second node; an enable node control circuit that controls the voltage of an enable node in response to the carry signal, an enable signal, and an inverted enable signal; a masking circuit that controls the voltage of a third node in response to the voltage of the second node and the voltage of the enable node; and a scan output circuit that outputs a scan signal in response to the voltage of the first node and the voltage of the third node.

[0007] In this implementation, before outputting a carry signal with a first level, the enable node control circuit can control the voltage of the enable node to a second level when the enable signal has a first level. During the output of the carry signal with a first level, the masking circuit can control the voltage of the third node to a second level in response to the voltage of the enable node with a second level, and the scan output circuit can output a scan signal with a first level in response to the voltage of the third node with a second level.

[0008] In one implementation, during the output of a carry signal with a first level, if the enable signal changes from the first level to the second level, the enable node control circuit can maintain the voltage of the enable node at the second level until the output of the carry signal with the first level is completed.

[0009] In this implementation, before outputting a carry signal with a first level, if the enable signal has a second level, the enable node control circuit can control the voltage of the enable node to the first level. During the output of the carry signal with the first level, the masking circuit can control the voltage of the third node to the first level in response to the voltage of the enable node with the first level, and the scan output circuit can refrain from outputting a scan signal with the first level in response to the voltage of the third node with the first level.

[0010] In one implementation, during the output of a carry signal with a first level, if the enable signal changes from a second level to a first level, the enable node control circuit can maintain the voltage of the enable node at the first level until the output of the carry signal with the first level is completed.

[0011] In one implementation, during the output of a carry signal with a first level, the enable node control circuit can maintain the voltage of the enable node at the previous level.

[0012] In this implementation, when there is no output carry signal with a first level, the enable signal has a first level, and the inverted enable signal has a second level, the enable node control circuit can control the voltage of the enable node to the second level. When there is no output carry signal with a first level, the enable signal has a second level, and the inverted enable signal has a first level, the enable node control circuit can control the voltage of the enable node to the first level.

[0013] In an implementation, the enable node control circuit may include a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and second transistors are connected in series between a high gate voltage line (hereinafter referred to as the high gate voltage line) and the enable node. The first transistor turns on in response to a carry signal, and the second transistor turns on in response to an enable signal. The third and fourth transistors are connected in series between the enable node and a low gate voltage line (hereinafter referred to as the low gate voltage line). The third transistor turns on in response to an inverted enable signal, and the fourth transistor turns on in response to a carry signal.

[0014] In one embodiment, the first transistor may include a gate for receiving a carry signal, a first terminal coupled to a high gate voltage line, and a second terminal; the second transistor may include a gate for receiving an enable signal, a first terminal coupled to a second terminal of the first transistor, and a second terminal coupled to an enable node; the third transistor may include a gate for receiving an inverted enable signal, a first terminal coupled to an enable node, and a second terminal; and the fourth transistor may include a gate for receiving a carry signal, a first terminal coupled to a second terminal of the third transistor, and a second terminal coupled to a low gate voltage line.

[0015] In one implementation, the enable node control circuit may further include a first capacitor coupled between the enable node and the low gate voltage line.

[0016] In one implementation, the masking circuit can separate the second node from the third node when the voltage of the enable node has a first level, and can couple the second node to the third node when the voltage of the enable node has a second level.

[0017] In one implementation, the masking circuit may include a fifth transistor that selectively couples the second node to the third node in response to the voltage of the enable node.

[0018] In one implementation, the fifth transistor may include a gate coupled to an enable node, a first terminal coupled to a second node, and a second terminal coupled to a third node.

[0019] In an embodiment, the masking circuit may further include a second capacitor coupled between the high gate voltage line and the third node, and a sixth transistor and a seventh transistor coupled in series between the high gate voltage line and the third node, wherein the sixth transistor is turned on in response to a carry signal and the seventh transistor is turned on in response to an enable signal.

[0020] In one embodiment, the sixth transistor may include a gate for receiving a carry signal, a first terminal coupled to a high gate voltage line, and a second terminal, and the seventh transistor may include a gate for receiving an enable signal, a first terminal coupled to the second terminal of the sixth transistor, and a second terminal coupled to the third node.

[0021] In an implementation, the carry-out circuit may include an eighth transistor and a ninth transistor. The eighth transistor includes a gate coupled to the second node, a first terminal coupled to the high gate voltage line, and a second terminal coupled to the carry-out node. The ninth transistor includes a gate coupled to the first node, a first terminal coupled to the carry-out node, and a second terminal coupled to the low gate voltage line.

[0022] In one embodiment, the scan output circuit may include a tenth transistor and an eleventh transistor. The tenth transistor includes a gate coupled to a third node, a first terminal coupled to a high gate voltage line, and a second terminal coupled to the scan output node. The eleventh transistor includes a gate coupled to a first node, a first terminal coupled to the scan output node, and a second terminal coupled to a low gate voltage line.

[0023] In an implementation, the transistors included in each of the multiple stages may be implemented using p-type metal-oxide-semiconductor (“PMOS”) transistors.

[0024] In this implementation, the carry signal and the scan signal can be effective high signals with a high level as the effective level.

[0025] In embodiments of this disclosure, a display device is provided, comprising a display panel including a plurality of pixels, a data driver providing data signals to each of the plurality of pixels, a scan driver providing scan signals to each of the plurality of pixels, and a controller controlling the data driver and the scan driver. The scan driver includes multiple stages. Each of the multiple stages includes a control circuit that controls the voltage of a first node and the voltage of a second node in response to an input signal, a first clock signal, and a second clock signal; a carry output circuit that outputs a carry signal in response to the voltage of the first node and the voltage of the second node; an enable node control circuit that controls the voltage of an enable node in response to the carry signal, an enable signal, and an inverted enable signal; a masking circuit that controls the voltage of a third node in response to the voltage of the second node and the voltage of the enable node; and a scan output circuit that outputs a scan signal in response to the voltage of the first node and the voltage of the third node.

[0026] As described above, in the scan driver and display device of the embodiments, each stage may include an enable node control circuit that controls the voltage of an enable node according to an enable signal and maintains the voltage of the enable node during the output carry signal, and a masking circuit that selectively couples a second node and a third node in response to the voltage of the enable node. Therefore, each of the plurality of scan signals generated by the scan driver of the embodiments may have a time length corresponding to two or more horizontal times, and the plurality of scan signals may be provided to corresponding areas of the display panel at different drive frequencies. Attached Figure Description

[0027] The illustrative and non-limiting embodiments will be more clearly understood through the following detailed description in conjunction with the accompanying drawings.

[0028] Figure 1 This is a block diagram illustrating an implementation of the scan driver.

[0029] Figure 2This is a timing diagram used to describe an implementation of the operation of the scan driver.

[0030] Figure 3 This is a circuit diagram illustrating an implementation of each stage included in the scan driver.

[0031] Figure 4 It is used to describe when the enable signal has a first level. Figure 3 A timing diagram of the implementation method of the level operation.

[0032] Figure 5 It is a circuit diagram used to describe the operation of the enable node control circuit in the first time period.

[0033] Figure 6 It is a circuit diagram used to describe the operation of the enable node control circuit in the second time period.

[0034] Figure 7 This is a circuit diagram used to describe the operation of the masking circuit and the scan output circuit during the second time period.

[0035] Figure 8 It is used to describe when the enable signal has a second level. Figure 3 A timing diagram of the implementation method of the level operation.

[0036] Figure 9 It is a circuit diagram used to describe the operation of the enable node control circuit in the third time period.

[0037] Figure 10 This is a circuit diagram used to describe the operation of the enable node control circuit in the fourth time period.

[0038] Figure 11 This is a circuit diagram used to describe the operation of the masking circuit and the scan output circuit in the fourth time period.

[0039] Figure 12 It is used to describe the situation when the enable signal changes from the first level to the second level during the output carry signal. Figure 3 A timing diagram of the implementation method of the level operation.

[0040] Figure 13 This is a circuit diagram used to describe the operation of the enable node control circuit in the fifth time period.

[0041] Figure 14 This is a circuit diagram used to describe the operation of the masking circuit and the scan output circuit in the fifth time period.

[0042] Figure 15 It is used to describe the situation when the enable signal changes from the second level to the first level during the output carry signal. Figure 3A timing diagram of the implementation method of the level operation.

[0043] Figure 16 This is a circuit diagram used to describe the operation of the enable node control circuit in the sixth time period.

[0044] Figure 17 This is a circuit diagram used to describe the operation of the masking circuit and the scan output circuit in the sixth time period.

[0045] Figure 18 This is a block diagram illustrating an embodiment of a display device including a scan driver.

[0046] Figure 19 This is a circuit diagram illustrating an embodiment of pixels included in a display device.

[0047] Figure 20 This is a block diagram illustrating an embodiment of an electronic device including a display device.

[0048] Figure 21 This is a block diagram illustrating an embodiment of the electronic device. Detailed Implementation

[0049] In the following text, embodiments of the present invention will be explained in detail with reference to the accompanying drawings.

[0050] The invention will now be described more fully below with reference to the accompanying drawings, which illustrate various embodiments. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this specification, similar reference numerals refer to similar elements.

[0051] What will be understood is that when an element is referred to as being "on" another element, it can be directly on the other element, or there can be an intermediary element between them. Conversely, when an element is referred to as being "directly" on another element, there is no intermediary element.

[0052] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, “first element,” “first component,” “first area,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second area, second layer, or second part without departing from the teachings herein.

[0053] The technical terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. Unless otherwise clearly indicated, the singular forms “a,” “an,” and “the” as used herein are intended to include the plural forms, including “at least one.” “Or” means “and / or.” The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprises” and / or “comprising” or “includes” and / or “including” are used in this specification, they indicate the presence of the stated features, areas, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, and / or clusters thereof.

[0054] Furthermore, relative terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, the relative terms are also intended to cover different orientations of the device. For example, if a device in one of the figures is flipped, an element described as being “below” the other elements will subsequently be oriented “upper” the other elements. Thus, the exemplary term “lower” can cover both “lower” and “upper” orientations depending on the specific orientation of the figure. Similarly, if a device in one of the figures is flipped, an element described as being “below” or “below” the other elements will subsequently be oriented “above” the other elements. Thus, the exemplary terms “below” or “below” can cover both “upper” and “lower” orientations.

[0055] Taking into account the errors associated with measurements and a particular number of measurements (i.e., limitations of the measurement system), the terms "about" or "approximately" as used herein include the stated values ​​and mean within an acceptable range of deviation from the stated values ​​as determined by one of ordinary skill in the art. For example, the term "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated values.

[0056] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense.

[0057] Figure 1 This is a block diagram illustrating an implementation of the scan driver, and Figure 2 This is a timing diagram used to describe an implementation of the operation of the scan driver.

[0058] Reference Figure 1 The scan driver 100 in the embodiment may include multiple levels 110, 120, 130, 140, 150 and 160, ...

[0059] Multiple stages 110, 120, 130, 140, 150, and 160, ... can receive a first clock signal CLK1, a second clock signal CLK2, a scan start signal FLM, and an enable signal EN. In some embodiments, the multiple stages 110, 120, 130, 140, 150, and 160, ... can also receive an inverted enable signal as an inverted signal of the enable signal EN. The first clock signal CLK1 and the second clock signal CLK2 may have different phases from each other. In embodiments, for example, as... Figure 2 As shown, the first clock signal CLK1 and the second clock signal CLK2 may have opposite phases.

[0060] Multiple levels 110, 120, 130, 140, 150, and 160, ... can sequentially generate carry signals CR1, CR2, CR3, CR4, CR5, and CR6, ... In some embodiments, each odd-numbered level 110, 130, or 150, ... can receive an input signal with a first level (e.g., a relatively high level) (e.g., a scan start signal FLM or a previous carry signal CR2 or CR4, ...) in response to a first clock signal CLK1 with a second level (e.g., a relatively low level), and can initiate (or begin) the output of carry signals CR1, CR3, or CR5, ... with a first level in response to a second clock signal CLK2 with a second level. Hereinafter, for convenience, a relatively high level may be referred to as a high level, and a relatively low level may be referred to as a low level. Furthermore, each even-numbered level 120, 140, or 160, ... can receive an input signal with a first level (e.g., a previous carry signal CR1, CR3, or CR5, ...) in response to a second clock signal CLK2 with a second level, and can initiate the output of a carry signal CR2, CR4, or CR6, ... with a first level in response to a first clock signal CLK1 with a second level.

[0061] In implementation methods, for example, such as Figure 1As shown, the first stage STAGE1 or 110 can receive the scan start signal FLM in response to a first clock signal CLK1 with a low level, and can start outputting a first carry signal CR1 with a high level in response to a second clock signal CLK2 with a low level. Furthermore, the second stage STAGE2 or 120 can receive the first carry signal CR1 in response to the second clock signal CLK2 with a low level, and can start outputting a second carry signal CR2 with a high level in response to the first clock signal CLK1 with a low level. Furthermore, the third stage STAGE3 or 130 can receive the second carry signal CR2 in response to the first clock signal CLK1 with a low level, and can start outputting a third carry signal CR3 with a high level in response to the second clock signal CLK2 with a low level. Furthermore, the fourth stage STAGE4 or 140 can receive the third carry signal CR3 in response to the second clock signal CLK2 with a low level, and can start outputting a fourth carry signal CR4 with a high level in response to the first clock signal CLK1 with a low level. Furthermore, the fifth stage, STAGE5 or 150, can receive the fourth carry signal CR4 in response to a first clock signal CLK1 with a low level, and can initiate the output of a fifth carry signal CR5 with a high level in response to a second clock signal CLK2 with a low level. Additionally, the sixth stage, STAGE6 or 160, can receive the fifth carry signal CR5 in response to a second clock signal CLK2 with a low level, and can initiate the output of a sixth carry signal CR6 with a high level in response to a first clock signal CLK1 with a low level.

[0062] In some implementations, such as Figure 2 As shown, each carry signal CR1, CR2, CR3, CR4, CR5 or CR6, ... can be a valid high signal with a high level as the active level, and the effective period of each carry signal CR1, CR2, CR3, CR4, CR5 or CR6, ... can have a duration longer than a horizontal time 1H (i.e., the time allocated for each pixel row of the display panel). In an embodiment, for example, the effective period of each carry signal CR1, CR2, CR3, CR4, CR5 or CR6, ... can have a duration corresponding to two or more horizontal times. Therefore, the effective periods of adjacent carry signals (e.g., the first carry signal CR1, the second carry signal CR2, and the third carry signal CR3) can overlap in time. Although Figure 2 An embodiment is shown in which the effective period of each carry signal CR1, CR2, CR3, CR4, CR5 or CR6, ... has a time length corresponding to three horizontal times, but the time length of the effective period of each carry signal CR1, CR2, CR3, CR4, CR5 or CR6, ... can correspond to any number of horizontal times.

[0063] Multiple stages 110, 120, 130, 140, 150, and 160, ... can selectively output scan signals SS1, SS2, SS3, SS4, SS5, and SS6, ... respectively, depending on the level of the enable signal EN. In some embodiments, when the output of a carry signal with a first level is initiated (or started), each stage (e.g., the first stage 110) can output a scan signal (e.g., the first scan signal SS1) with a phase substantially the same as the phase of the carry signal (e.g., the first carry signal CR1) while the enable signal EN is at a first level (e.g., high). During the output of a carry signal with a first level or during the output of a scan signal with a first level, even when the enable signal EN changes from a first level to a second level (e.g., low), the stage can continue to output a scan signal with a first level until the output of a carry signal with a first level is completed. Furthermore, when a carry signal with a first level is output, each stage (e.g., the first stage 110) may not output a scan signal with the first level if the enable signal EN has a second level (e.g., low level). During the output of a carry signal with the first level, the stage may not output a scan signal even if the enable signal EN changes from the second level to the first level.

[0064] In implementation methods, for example, such as Figure 2As shown, when the first carry signal CR1 with a high level is output and when the second carry signal CR2 with a high level is output, with the enable signal EN at a high level, the first stage STAGE1 or 110 and the second stage STAGE2 or 120 can sequentially and respectively output the first scan signal SS1 with a high level and the second scan signal SS2 with a high level. During the output of the first carry signal CR1 and the second carry signal CR2, or during the output of the first scan signal SS1 and the second scan signal SS2, although the enable signal EN changes from a high level to a low level, the first stage STAGE1 or 110 can continue to output the first scan signal SS1 with a high level until the output of the first carry signal CR1 with a high level is completed, and the second stage STAGE2 or 120 can continue to output the second scan signal SS2 with a high level until the output of the second carry signal CR2 with a high level is completed. Furthermore, when the third carry signal CR3 is output with a high level and when the fourth carry signal CR4 is output with a high level, if the enable signal EN is low, the third stage STAGE3 or 130 and the fourth stage STAGE4 or 140 may not output the third scan signal SS3 and the fourth scan signal SS4 with a high level. During the output of the third carry signal CR3 and the fourth carry signal CR4, although the enable signal EN changes from low to high, the third stage STAGE3 or 130 and the fourth stage STAGE4 or 140 may not output the third scan signal SS3 and the fourth scan signal SS4 with a high level. Furthermore, when the fifth carry signal CR5 is output with a high level and when the sixth carry signal CR6 is output with a high level, if the enable signal EN is high, the fifth stage STAGE5 or 150 and the sixth stage STAGE6 or 160 may sequentially and respectively output the fifth scan signal SS5 and the sixth scan signal SS6 with a high level.

[0065] Furthermore, in some implementations, such as Figure 2 As shown, each scan signal SS1, SS2, SS3, SS4, SS5, or SS6, ... can be a valid high signal with a high level as the active level, and the effective period of each scan signal SS1, SS2, SS3, SS4, SS5, or SS6, ... can have a duration longer than a horizontal time 1H (i.e., the time allocated for each pixel row of the display panel). In an embodiment, for example, the effective period of each scan signal SS1, SS2, SS3, SS4, SS5, or SS6, ... can have a duration corresponding to two or more horizontal times. Therefore, the effective periods of adjacent scan signals (e.g., the first scan signal SS1 and the second scan signal SS2) can overlap in time. Although Figure 2An implementation is shown in which the effective time period of each scan signal SS1, SS2, SS3, SS4, SS5 or SS6, ... has a time length corresponding to three horizontal times, but the time length of the effective time period of each scan signal SS1, SS2, SS3, SS4, SS5 or SS6, ... can correspond to any number of horizontal times.

[0066] As described above, multiple levels 110, 120, 130, 140, 150 and 160, ... can selectively output scan signals SS1, SS2, SS3, SS4, SS5 and SS6, ... respectively, depending on the level of the enable signal EN. Therefore, the scan driver 100 in this embodiment can provide the scan signals SS1, SS2, SS3, SS4, SS5 and SS6, ... to the corresponding areas of the display panel at different drive frequencies.

[0067] Furthermore, as described above, when the enable signal EN has a first level when starting the output of the corresponding carry signal, even if the enable signal EN changes to a second level during the output of the corresponding carry signal, each stage 110, 120, 130, 140, 150 or 160, ... may output a scan signal with an effective time period of two or more horizontal time intervals. Furthermore, when the enable signal EN has a second level when starting the output of the corresponding carry signal, even if the enable signal EN changes to a first level during the output of the corresponding carry signal, each stage 110, 120, 130, 140, 150 or 160, ... may not output a scan signal with a first level. Therefore, the scan driver 100 in this embodiment can selectively provide scan signals SS1, SS2, SS3, SS4, SS5 and SS6, ... with an effective time period of two or more horizontal time intervals.

[0068] Figure 3 This is a circuit diagram illustrating an implementation of each stage included in the scan driver.

[0069] Reference Figure 3Each stage 200 of the scan driver in the embodiment may include a control circuit 210 that controls the voltage of a first node Q and the voltage of a second node QB in response to an input signal FLM / PCR, a first clock signal CLK1, and a second clock signal CLK2; a carry output circuit 220 that outputs a carry signal CR in response to the voltage of the first node Q and the voltage of the second node QB; an enable node control circuit 230 that controls the voltage of an enable node EN_NODE in response to the carry signal CR, an enable signal EN, and an inverted enable signal ENB; a masking circuit 240 that controls the voltage of a third node MQB in response to the voltage of the second node QB and the voltage of the enable node EN_NODE; and a scan output circuit 250 that outputs a scan signal SS in response to the voltage of the first node Q and the voltage of the third node MQB. In some embodiments, each stage 200 may also include a sixth capacitor C6 coupled to the carry output node CON that outputs the carry signal CR and / or a seventh capacitor (not shown) coupled to the scan output node SON that outputs the scan signal SS.

[0070] When no input signal FLM / PCR with a first level (e.g., high level) is received, the control circuit 210 can control the voltage of the first node Q to a second level (e.g., low level) and control the voltage of the second node QB to the first level. The input signal FLM / PCR can be the scan start signal FLM relative to the first stage, and can be the previous carry signal PCR relative to the subsequent stage or the carry signal CR of the previous stage.

[0071] In addition, such as Figure 3 and Figure 4 As shown, the control circuit 210 (of odd-numbered stages 200) can control the voltage of the first node Q to a first level in response to a first clock signal CLK1 having a second level and an input signal FLM / PCR having a first level, and can control the voltage of the second node QB to a second level in response to a second clock signal CLK2 having a second level and the voltage of the first node Q having a first level. In an alternative embodiment, relative to even-numbered stages, the control circuit 210 can control the voltage of the first node Q to a first level in response to a second clock signal CLK2 having a second level and an input signal FLM / PCR having a first level, and can control the voltage of the second node QB to a second level in response to a first clock signal CLK1 having a second level and the voltage of the first node Q having a first level.

[0072] The control circuit 210 may include twelfth transistors T12 to nineteenth transistors T19 and third capacitors C3 to fifth capacitors C5. In some embodiments, the control circuit 210 may also include a twentieth transistor T20 disposed at the fifth node N5, a twenty-first transistor T21 disposed at the first node Q, and a twenty-second transistor T22 that applies a high gate voltage VGH to the first node Q in response to a global control signal ESR.

[0073] The twelfth transistor T12 may apply the input signal FLM / PCR to the first node Q in response to a first clock signal CLK1 having a low level. In an embodiment, for example, the twelfth transistor T12 may include a gate that receives the first clock signal CLK1, a first terminal that receives the input signal FLM / PCR, and a second terminal coupled to the first node Q.

[0074] The fifth capacitor C5 may include (via the twenty-first transistor T21) a first electrode coupled to the first node Q and a second electrode coupled to the fourth node N4. The thirteenth transistor T13 may apply a high gate voltage VGH to the fourth node N4 in response to the voltage of the fifth node N5, and the fourteenth transistor T14 may (via the twenty-first transistor T21) apply a second clock signal CLK2 to the fourth node N4 in response to the voltage of the first node Q. Through the fifth capacitor C5, the thirteenth transistor T13, and the fourteenth transistor T14, as... Figure 4 As shown, when the second clock signal CLK2 goes high (H), the voltage of the first node Q can become lower than the low level (L). In an embodiment, for example, the thirteenth transistor T13 may include a gate coupled to the fifth node N5, a first terminal receiving a high gate voltage VGH, and a second terminal coupled to the fourth node N4, and the fourteenth transistor T14 may include (through the twenty-first transistor T21) a gate coupled to the first node Q, a first terminal coupled to the fourth node N4, and a second terminal receiving the second clock signal CLK2.

[0075] The fifteenth transistor T15 may apply a first clock signal CLK1 to the fifth node N5 in response to the voltage of the first node Q, and the sixteenth transistor T16 may apply a low gate voltage VGL to the fifth node N5 in response to the first clock signal CLK1. In an embodiment, for example, the fifteenth transistor T15 may include a gate coupled to the first node Q, a first terminal coupled to the fifth node N5, and a second terminal receiving the first clock signal CLK1, and the sixteenth transistor T16 may include a gate receiving the first clock signal CLK1, a first terminal coupled to the fifth node N5, and a second terminal receiving the low gate voltage VGL.

[0076] The third capacitor C3 may include a first electrode receiving a high gate voltage VGH and a second electrode coupled to the second node QB, and the fourth capacitor C4 may include a first electrode coupled to the fifth node N5 and a second electrode coupled to the sixth node N6 (through the twentieth transistor T20).

[0077] The seventeenth transistor T17 may couple the second node QB and the sixth node N6 in response to the second clock signal CLK2, and the eighteenth transistor T18 may apply the second clock signal CLK2 to the sixth node N6 in response to the voltage of the fifth node N5. In an embodiment, for example, the seventeenth transistor T17 may include a gate for receiving the second clock signal CLK2, a first terminal coupled to the second node QB, and a second terminal coupled to the sixth node N6, and the eighteenth transistor T18 may include (through the twentieth transistor T20) a gate coupled to the fifth node N5, a first terminal coupled to the sixth node N6, and a second terminal for receiving the second clock signal CLK2.

[0078] The nineteenth transistor T19 may apply a high gate voltage VGH to the second node QB in response to the voltage of the first node Q. In an embodiment, for example, the nineteenth transistor T19 may include a gate coupled to the first node Q, a first terminal receiving the high gate voltage VGH, and a second terminal coupled to the second node QB.

[0079] The twentieth transistor T20 may be arranged at the fifth node N5, and the twenty-first transistor T21 may be arranged at the first node Q. The gates of the twentieth transistor T20 and the twenty-first transistor T21 may receive a low gate voltage VGL.

[0080] The 22nd transistor T22 can control the voltage of the first node Q to a high level in response to the global control signal ESR. In some embodiments, the global control signal ESR can be applied substantially simultaneously to multiple stages of the scan driver, and the multiple stages can output scan signals SS substantially simultaneously in response to the global control signal ESR. In an embodiment, for example, the 22nd transistor T22 may include a gate that receives the global control signal ESR, a first terminal that receives a high gate voltage VGH, and a second terminal coupled to the first node Q.

[0081] although Figure 3 An embodiment of the control circuit 210, including twelfth transistor T12 to twenty-second transistor T22 and third capacitor C3 to fifth capacitor C5, is shown, but the configuration of the control circuit for each stage 200 of the scan driver in the embodiment is not limited to... Figure 3The implementation method is as follows. That is, the control circuit 210 may have any configuration that controls the voltage of the first node Q and the voltage of the second node QB in response to the input signal FLM / PCR, the first clock signal CLK1 and the second clock signal CLK2.

[0082] During a period when the voltage at the first node Q has a first level (e.g., high level) and the voltage at the second node QB has a second level (e.g., low level), the carry output circuit 220 may output a carry signal CR having the first level (e.g., high level). In some embodiments, the carry output circuit 220 may include an eighth transistor T8 that outputs a high gate voltage VGH as the carry signal CR in response to the voltage at the second node QB, and a ninth transistor T9 that outputs a low gate voltage VGL as the carry signal CR in response to the voltage at the first node Q. In embodiments, for example, the eighth transistor T8 may include a gate coupled to the second node QB, a first terminal coupled to a line of high gate voltage VGH (also referred to as the high gate voltage line), and a second terminal coupled to the carry output node CON that outputs the carry signal CR, and the ninth transistor T9 may include a gate coupled to the first node Q, a first terminal coupled to the carry output node CON, and a second terminal coupled to a line of low gate voltage VGL (also referred to as the low gate voltage line).

[0083] When there is no carry signal CR with a first level (e.g., high level), the enable signal EN has a first level, and the inverted enable signal ENB has a second level (e.g., low level), the enable node control circuit 230 can control the voltage of the enable node EN_NODE to the second level. In an alternative embodiment, when there is no carry signal CR with a first level, the enable signal EN has a second level, and the inverted enable signal ENB has a first level, the enable node control circuit 230 can control the voltage of the enable node EN_NODE to the first level. Furthermore, during the output of the carry signal CR with a first level, the enable node control circuit 230 can maintain the voltage of the enable node EN_NODE at the previous level.

[0084] In some embodiments, the enable node control circuit 230 may include a first transistor T1 and a second transistor T2 connected in series between the line of the high gate voltage VGH and the enable node EN_NODE, and a third transistor T3 and a fourth transistor T4 connected in series between the line of the enable node EN_NODE and the line of the low gate voltage VGL. The first transistor T1 may be turned on in response to a carry signal CR, the second transistor T2 may be turned on in response to an enable signal EN, the third transistor T3 may be turned on in response to an inverted enable signal ENB, and the fourth transistor T4 may be turned on in response to a carry signal CR. In an implementation, for example, the first transistor T1 may include a gate for receiving a carry signal CR, a first terminal coupled to a high gate voltage VGH, and a second terminal; the second transistor T2 may include a gate for receiving an enable signal EN, a first terminal coupled to a second terminal of the first transistor T1, and a second terminal coupled to an enable node EN_NODE; the third transistor T3 may include a gate for receiving an inverted enable signal ENB, a first terminal coupled to an enable node EN_NODE, and a second terminal; and the fourth transistor T4 may include a gate for receiving a carry signal CR, a first terminal coupled to a second terminal of the third transistor T3, and a second terminal coupled to a low gate voltage VGL.

[0085] In some embodiments, the enable node control circuit 230 may further include a first capacitor C1 coupled between the enable node EN_NODE and the line of the low gate voltage VGL. In some embodiments, for example, the first capacitor C1 may include a first electrode coupled to the enable node EN_NODE and a second electrode coupled to the line of the low gate voltage VGL.

[0086] The masking circuit 240 can separate the second node QB from the third node MQB when the voltage of the enable node EN_NODE has a first level (e.g., a high level), and can couple the second node QB to the third node MQB when the voltage of the enable node EN_NODE has a second level (e.g., a low level).

[0087] In some embodiments, the masking circuit 240 may include a fifth transistor T5 that selectively couples the second node QB to the third node MQB in response to the voltage of the enable node EN_NODE. In some embodiments, for example, the fifth transistor T5 may include a gate coupled to the enable node EN_NODE, a first terminal coupled to the second node QB, and a second terminal coupled to the third node MQB.

[0088] In some embodiments, the masking circuit 240 may further include a second capacitor C2 coupled between the line of the high gate voltage VGH and the third node MQB, and a sixth transistor T6 and a seventh transistor T7 coupled in series between the line of the high gate voltage VGH and the third node MQB. The sixth transistor T6 may be turned on in response to a carry signal CR, and the seventh transistor T7 may be turned on in response to an enable signal EN. In some embodiments, for example, the sixth transistor T6 may include a gate for receiving the carry signal CR, a first terminal coupled to the line of the high gate voltage VGH, and a second terminal, and the seventh transistor T7 may include a gate for receiving the enable signal EN, a first terminal connected to the second terminal of the sixth transistor T6, and a second terminal coupled to the third node MQB.

[0089] During a period when the voltage at the first node Q has a first level (e.g., high level) and the voltage at the third node MQB has a second level (e.g., low level), the scan output circuit 250 may output a scan signal SS having the first level (e.g., high level). In some embodiments, the scan output circuit 250 may include a tenth transistor T10 that outputs a high gate voltage VGH as the scan signal SS in response to the voltage at the third node MQB, and an eleventh transistor T11 that outputs a low gate voltage VGL as the scan signal SS in response to the voltage at the first node Q. In embodiments, for example, the tenth transistor T10 may include a gate coupled to the third node MQB, a first terminal line-coupled to the high gate voltage VGH, and a second terminal coupled to the scan output node SON that outputs the scan signal SS, and the eleventh transistor T11 may include a gate coupled to the first node Q, a first terminal coupled to the scan output node SON, and a second terminal line-coupled to the low gate voltage VGL.

[0090] In some embodiments, the first transistor T1 through the twenty-second transistor T22 in each stage 200 may be implemented using, but is not limited to, p-type metal-oxide-semiconductor (“PMOS”) transistors. Even when the first transistor T1 through the twenty-second transistor T22 are implemented using PMOS transistors, each stage 200 of the scan driver in the embodiments may generate a carry signal CR and a scan signal SS having a high level as an effective high signal as the effective level. In other embodiments, some or all of the first transistor T1 through the twenty-second transistor T22 may be implemented using, but is not limited to, n-type metal-oxide-semiconductor (“NMOS”) transistors.

[0091] In stage 200 with the above configuration, before outputting the carry signal CR with a first level, when the enable signal EN has a first level (e.g., high level), the enable node control circuit 230 can control the voltage of the enable node EN_NODE to a second level (e.g., low level). During the output of the carry signal CR with a first level, the masking circuit 240 can control the voltage of the third node MQB to the level of the voltage of the second node QB or control it to a second level in response to the voltage of the enable node EN_NODE with a second level, and the scan output circuit 250 can output a scan signal SS with a first level in response to the voltage of the third node MQB with a second level. During the output of the carry signal CR with a first level, even when the enable signal EN changes from a first level to a second level, the enable node control circuit 230 can maintain the voltage of the enable node EN_NODE at a second level until the output of the carry signal CR with a first level is completed. Therefore, a scan signal SS with a time length corresponding to two or more horizontal time periods can be output normally.

[0092] Furthermore, in stage 200, before outputting the carry signal CR with a first level, when the enable signal EN has a second level, the enable node control circuit 230 can control the voltage of the enable node EN_NODE to the first level. During the output of the carry signal CR with a first level, the masking circuit 240 can control the voltage of the third node MQB to a first level different from the level of the third node MQB in response to the voltage of the enable node EN_NODE with a first level, and the scan output circuit 250 can not output the scan signal SS with a first level in response to the voltage of the third node MQB with a first level. During the output of the carry signal CR with a first level, even when the enable signal EN changes from a second level to a first level, the enable node control circuit 230 can maintain the voltage of the enable node EN_NODE at the first level until the output of the carry signal CR with a first level is completed. Therefore, by changing the level of the enable signal EN, the undesirable output of the scan signal SS with a first level can be prevented.

[0093] Figure 4 It is used to describe when the enable signal has a first level. Figure 3 A timing diagram illustrating the implementation of the level-based operations. Figure 5 It is a circuit diagram used to describe the operation of the enable node control circuit in the first time period. Figure 6 This is a circuit diagram used to describe the operation of the enable node control circuit in the second time period, and Figure 7 This is a circuit diagram used to describe the operation of the masking circuit and the scan output circuit during the second time period.

[0094] Reference Figure 3 and Figure 4 During the period when no input signal FLM / PCR with a high level H is received and no carry signal CR with a high level H is output, the control circuit 210 can control the voltage of the first node Q to a low level L (or a level lower than low level L) and control the voltage of the second node QB to a high level H. In response to the voltage of the first node Q with a low level L, the carry output circuit 220 can output a carry signal CR with a low level L, and the scan output circuit 250 can output a scan signal SS with a low level L.

[0095] During the first time period TP1, an input signal FLM / PCR with a high level H can be received, and the first clock signal CLK1 can have a low level L. Control circuit 210 can apply the input signal FLM / PCR with a high level H to the first node Q in response to the first clock signal CLK1 with a low level L. Therefore, the voltage of the first node Q can have a high level H.

[0096] Furthermore, during the first time period TP1, when the enable signal EN has a high level H and the inverted enable signal ENB has a low level L, the enable node control circuit 230 can control the voltage of the enable node EN_NODE to a low level L. In an embodiment, for example, as... Figure 5 As shown, the first transistor T1 and the fourth transistor T4 are turned on in response to a carry signal CR with a low level L, the second transistor T2 is turned off in response to an enable signal EN with a high level H, and the third transistor T3 is turned on in response to an inverted enable signal ENB with a low level L. Therefore, the third transistor T3 and the fourth transistor T4 can apply a low gate voltage VGL to the enable node EN_NODE, and the voltage of the enable node EN_NODE can have a low level L.

[0097] During the second time period TP2 following the first time period TP1, the control circuit 210 can control the voltage of the second node QB to a low level L in response to the second clock signal CLK2 having a low level L. In an embodiment, for example, the seventeenth transistor T17 and the eighteenth transistor T18 can apply the second clock signal CLK2 having a low level L to the second node QB in response to the second clock signal CLK2 having a low level L. The carry output circuit 220 can output a carry signal CR having a high level H in response to the voltage of the second node QB having a low level L.

[0098] Furthermore, during the second time period TP2, the enable node control circuit 230 can maintain the voltage of the enable node EN_NODE at a low level L. In an implementation, for example, as... Figure 6As shown, the first transistor T1 and the fourth transistor T4 can be turned off in response to a carry signal CR with a high level H, the second transistor T2 can be turned off in response to an enable signal EN with a high level H, and the third transistor T3 can be turned on in response to an inverted enable signal ENB with a low level L. Therefore, the high gate voltage VGH and the low gate voltage VGL can not be applied to the enable node EN_NODE, and the first capacitor C1 can maintain the voltage of the enable node EN_NODE at the previous level or the low level L.

[0099] Furthermore, during the second time period TP2, the masking circuit 240 can control the voltage of the third node MQB to a low level L by coupling the second node QB to the third node MQB in response to the voltage of the enable node EN_NODE having a low level L, and the scan output circuit 250 can output a scan signal SS having a high level H in response to the voltage of the third node MQB having a low level L. In an embodiment, for example, as Figure 7 As shown, the fifth transistor T5 can couple the second node QB to the third node MQB in response to the voltage of the enable node EN_NODE with a low level L, and therefore the voltage of the third node MQB can have the voltage level of the second node QB or a low level L. Furthermore, the sixth transistor T6 can be turned off in response to a carry signal CR with a high level H, and the seventh transistor T7 can be turned off in response to an enable signal EN with a high level H. Additionally, the tenth transistor T10 can be turned on in response to the voltage of the third node MQB with a low level L, and the eleventh transistor T11 can be turned off in response to the voltage of the first node Q with a high level H. The tenth transistor T10 can apply a high gate voltage VGH to the scan output node SON, and therefore a scan signal SS with a high level H can be output at the scan output node SON.

[0100] As described above, at the time point when the carry signal CR with a high level H is output, or at the end time point of the first time period TP1 or the beginning time point of the second time period TP2, when the enable signal EN has a high level H, stage 200 can output a scan signal SS with a high level H.

[0101] Figure 8 It is used to describe when the enable signal has a second level. Figure 3 A timing diagram illustrating the implementation of the level-based operations. Figure 9 This is a circuit diagram used to describe the operation of the enable node control circuit in the third time period. Figure 10 This is a circuit diagram used to describe the operation of the enable node control circuit in the fourth time period, and Figure 11 This is a circuit diagram used to describe the operation of the masking circuit and the scan output circuit in the fourth time period.

[0102] Reference Figure 3 and Figure 8 During the third time period TP3, an input signal FLM / PCR with a high level H can be received, and the first clock signal CLK1 can have a low level L. Control circuit 210 can apply the input signal FLM / PCR with a high level H to the first node Q in response to the first clock signal CLK1 with a low level L. Therefore, the voltage of the first node Q can have a high level H.

[0103] Furthermore, during the third time period TP3, when the enable signal EN has a low level L and the inverting enable signal ENB has a high level H, the enable node control circuit 230 can control the voltage of the enable node EN_NODE to a high level H. In an embodiment, for example, as... Figure 9 As shown, the first transistor T1 and the fourth transistor T4 are turned on in response to a carry signal CR with a low level L, the second transistor T2 is turned on in response to an enable signal EN with a low level L, and the third transistor T3 is turned off in response to an inverted enable signal ENB with a high level H. Therefore, the first transistor T1 and the second transistor T2 can apply a high gate voltage VGH to the enable node EN_NODE, and the voltage of the enable node EN_NODE can have a high level H.

[0104] In the fourth time period TP4 following the third time period TP3, the control circuit 210 can control the voltage of the second node QB to a low level L in response to the second clock signal CLK2 having a low level L. The carry output circuit 220 can output a carry signal CR having a high level H in response to the voltage of the second node QB having a low level L.

[0105] Furthermore, during the fourth time period TP4, the enable node control circuit 230 can maintain the voltage of the enable node EN_NODE at a high level H. In an implementation, for example, as... Figure 10 As shown, the first transistor T1 and the fourth transistor T4 can be turned off in response to a carry signal CR with a high level H, the second transistor T2 can be turned on in response to an enable signal EN with a low level L, and the third transistor T3 can be turned off in response to an inverted enable signal ENB with a high level H. Therefore, the high gate voltage VGH and the low gate voltage VGL can not be applied to the enable node EN_NODE, and the first capacitor C1 can maintain the voltage of the enable node EN_NODE at the previous level or the high level H.

[0106] Furthermore, in the fourth time period TP4, the masking circuit 240 can control the voltage of the third node MQB to a high level H by separating the second node QB from the third node MQB in response to the voltage of the enable node EN_NODE with a high level H, and the scan output circuit 250 can not output a scan signal SS with a high level H in response to the voltage of the third node MQB with a high level H. In an embodiment, for example, as Figure 11 As shown, the fifth transistor T5 can separate the second node QB from the third node MQB in response to the voltage of the enable node EN_NODE with a high level H, and thus the voltage of the third node MQB can be maintained at the previous level or at a high level H. Furthermore, the sixth transistor T6 can be turned off in response to the carry signal CR with a high level H, and the seventh transistor T7 can be turned on in response to the enable signal EN with a low level L. Additionally, the tenth transistor T10 can be turned off in response to the voltage of the third node MQB with a high level H, and the eleventh transistor T11 can be turned off in response to the voltage of the first node Q with a high level H. Therefore, the voltage of the scan output node SON can be maintained at the previous level or at a low level L, and the scan signal SS with a high level H is not output at the scan output node SON.

[0107] As described above, at the time point when the carry signal CR with a high level H is output, or at the end time point of the third time period TP3 or the beginning time point of the fourth time period TP4, when the enable signal EN has a low level L, stage 200 may not output the scan signal SS with a high level H.

[0108] Figure 12 It is used to describe the situation when the enable signal changes from the first level to the second level during the output carry signal. Figure 3 A timing diagram illustrating the implementation of the level-based operations. Figure 13 This is a circuit diagram used to describe the operation of the enable node control circuit in the fifth time period, and Figure 14 This is a circuit diagram used to describe the operation of the masking circuit and the scan output circuit in the fifth time period.

[0109] Figure 12 The timing diagram can be compared with Figure 4 The timing diagram is similar, except that the enable signal EN changes from high level H to low level L and the inverting enable signal ENB changes from low level L to high level H during the carry signal CR with high level H at the output.

[0110] Reference Figure 3 and Figure 12During the fifth time period TP5, when the carry signal CR is at a high level H, the enable signal EN is at a low level L, and the inverted enable signal ENB is at a high level H, the enable node control circuit 230 can maintain the voltage of the enable node EN_NODE at a low level L. In an embodiment, for example, as... Figure 13 As shown, the first transistor T1 and the fourth transistor T4 can be turned off in response to a carry signal CR with a high level H, the second transistor T2 can be turned on in response to an enable signal EN with a low level L, and the third transistor T3 can be turned off in response to an inverted enable signal ENB with a high level H. That is, even when the second transistor T2 is turned on by the enable signal EN changing from a high level H to a low level L, because the first transistor T1 and the fourth transistor T4 are turned off, the high gate voltage VGH and the low gate voltage VGL are not applied to the enable node EN_NODE, and the first capacitor C1 can maintain the voltage of the enable node EN_NODE at the previous level or the low level L.

[0111] Furthermore, in the fifth time period TP5, the masking circuit 240 can control the voltage of the third node MQB to a low level L by coupling the second node QB to the third node MQB in response to the voltage of the enable node EN_NODE having a low level L, and the scan output circuit 250 can output a scan signal SS having a high level H in response to the voltage of the third node MQB having a low level L. In an embodiment, for example, as Figure 14 As shown, the fifth transistor T5 can couple the second node QB to the third node MQB in response to the voltage of the enable node EN_NODE with a low level L, and therefore the voltage of the third node MQB can have the voltage level of the second node QB or a low level L. Furthermore, the sixth transistor T6 can be turned off in response to a carry signal CR with a high level H, and the seventh transistor T7 can be turned on in response to an enable signal EN with a low level L. Additionally, the tenth transistor T10 can be turned on in response to the voltage of the third node MQB with a low level L, and the eleventh transistor T11 can be turned off in response to the voltage of the first node Q with a high level H. The tenth transistor T10 can apply a high gate voltage VGH to the scan output node SON, and therefore a scan signal SS with a high level H can be output at the scan output node SON.

[0112] As described above, during the output of the carry signal CR with a high level H, even when the enable signal EN changes from a high level H to a low level L, stage 200 can continue to output the scan signal SS with a high level H.

[0113] Figure 15 It is used to describe the situation when the enable signal changes from the second level to the first level during the output carry signal. Figure 3A timing diagram illustrating the implementation of the level-based operations. Figure 16 This is a circuit diagram used to describe the operation of the enable node control circuit in the sixth time period, and Figure 17 This is a circuit diagram used to describe the operation of the masking circuit and the scan output circuit in the sixth time period.

[0114] Figure 15 The timing diagram can be compared with Figure 8 The timing diagram is similar, except that the enable signal EN changes from low level L to high level H and the inverting enable signal ENB changes from high level H to low level L during the carry signal CR with high level H at the output.

[0115] Reference Figure 3 and Figure 15 During the sixth time period TP6, in which the carry signal CR has a high level H, the enable signal EN has a high level H, and the inverted enable signal ENB has a low level L, the enable node control circuit 230 can maintain the voltage of the enable node EN_NODE at a high level H. In an embodiment, for example, as... Figure 16 As shown, the first transistor T1 and the fourth transistor T4 can be turned off in response to a carry signal CR with a high level H, the second transistor T2 can be turned off in response to an enable signal EN with a high level H, and the third transistor T3 can be turned on in response to an inverted enable signal ENB with a low level L. That is, even when the third transistor T3 is turned on by the inverted enable signal ENB changing from a high level H to a low level L, since the first transistor T1 and the fourth transistor T4 are turned off, the high gate voltage VGH and the low gate voltage VGL may not be applied to the enable node EN_NODE, and the first capacitor C1 can maintain the voltage of the enable node EN_NODE at the previous level or the high level H.

[0116] Furthermore, during the sixth time period TP6, the masking circuit 240 can respond to the voltage of the enable node EN_NODE with a high level H by separating the second node QB from the third node MQB, thereby controlling the voltage of the third node MQB to a high level H, and the scan output circuit 250 can respond to the voltage of the third node MQB with a high level H by not outputting a scan signal SS with a high level H. In an embodiment, for example, as Figure 17As shown, the fifth transistor T5 can separate the second node QB from the third node MQB in response to the voltage of the enable node EN_NODE with a high level H, and thus the voltage of the third node MQB can be maintained at the previous level or at a high level H. Furthermore, the sixth transistor T6 can be turned off in response to the carry signal CR with a high level H, and the seventh transistor T7 can be turned off in response to the enable signal EN with a high level H. Additionally, the tenth transistor T10 can be turned off in response to the voltage of the third node MQB with a high level H, and the eleventh transistor T11 can be turned off in response to the voltage of the first node Q with a high level H. Therefore, the voltage of the scan output node SON can be maintained at the previous level or at a low level L, and the scan signal SS with a high level H may not be output at the scan output node SON.

[0117] As described above, during the output of the carry signal CR with a high level H, even when the enable signal EN changes from a low level L to a high level H, stage 200 may not output the scan signal SS with a high level H.

[0118] Figure 18 This is a block diagram illustrating an embodiment of a display device including a scan driver, and Figure 19 This is a circuit diagram illustrating an embodiment of pixels included in a display device.

[0119] Reference Figure 18 The display device 300 in the embodiments may include a display panel 310 comprising a plurality of pixels PX, a data driver 320 providing a data signal DS to the plurality of pixels PX, a scan driver 330 providing a scan signal SS to the plurality of pixels PX, and a controller 350 controlling the data driver 320 and the scan driver 330. In some embodiments, the display device 300 may further include a transmit driver 340 providing a transmit signal EM to the plurality of pixels PX.

[0120] Display panel 310 may include a plurality of scan lines, a plurality of data lines, and a plurality of pixels PX coupled to the plurality of scan lines and the plurality of data lines. In some embodiments, each pixel PX may include a light-emitting element, and display panel 310 may be a light-emitting display panel. However, display panel 310 is not limited to a light-emitting display panel and may be any suitable display panel.

[0121] In implementation methods, for example, such as Figure 19As shown, each pixel PX may include a drive transistor PXT1 that generates a drive current, a switching transistor PXT2 that transmits a data signal DS to the source of the drive transistor PXT1 in response to a write signal GW[n], a compensation transistor PXT3 that connects the drive transistor PXT1 to a diode in response to a compensation signal GC, a storage capacitor CST that stores the data signal DS transmitted through the switching transistor PXT2 and the diode-connected drive transistor PXT1, and a gate that provides an initialization voltage VINIT to the storage capacitor CST and the gate of the drive transistor PXT1 in response to an initialization signal GI. The system includes an initialization transistor PXT4, a first emitter transistor PXT5 that connects a line of the first power supply voltage ELVDD to the source of the driving transistor PXT1 in response to the emission signal EM, a second emitter transistor PXT6 that connects the drain of the driving transistor PXT1 to the light-emitting element EL in response to the emission signal EM, an anode initialization transistor PXT7 that provides an anode initialization voltage VAINIT to the light-emitting element EL in response to a previous write signal GW[n-1], and a light-emitting element EL that emits light based on a drive current from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS. In some embodiments, each pixel PX may also include a boost capacitor CBOOST coupled between the line of the write signal GW[n] and the gate of the driving transistor PXT1, and a bias transistor PXT8 that applies a bias voltage VBIAS to the source of the driving transistor PXT1 in response to a bias signal GB (or a bypass signal).

[0122] In some implementations, at least a portion of the transistors PXT1 to PXT8 of the pixel PX are implemented using NMOS transistors, and the remaining transistors PXT1 to PXT8 of the pixel PX are implemented using PMOS transistors. In some implementations, for example, as... Figure 19 As shown, the compensation transistor PXT3 and the gate initialization transistor PXT4 can be implemented using NMOS transistors, and the remaining transistors PXT1, PXT2, and PXT5 through PXT8 can be implemented using PMOS transistors. In other embodiments, all of the transistors PXT1 through PXT8 for each pixel PX can be implemented using NMOS transistors or PMOS transistors.

[0123] Furthermore, in some embodiments, the light-emitting element EL may be, but is not limited to, an organic light-emitting diode (“OLED”). In embodiments, for example, the light-emitting element EL may be a nano-light-emitting diode (“NED”), a quantum dot (“QD”) light-emitting diode, a micro-light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element.

[0124] although Figure 19An embodiment is shown where each pixel PX has an 8T2C structure comprising eight transistors PXT1 to PXT8 and two capacitors CST and CBOOST, but each pixel PX of the display device 300 in the embodiment is not limited to... Figure 19 The 8T2C structure shown can have any pixel structure.

[0125] Data driver 320 can generate a data signal DS based on output image data ODAT received from controller 350 and a data control signal DCTRL, and can provide the data signal DS to multiple pixels PX via multiple data lines. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a level start signal, and a load signal. In some embodiments, data driver 320 and controller 350 can be implemented using a single integrated circuit (“IC”), and the single IC may also be referred to as a timing controller embedded data driver (“TED”). In other embodiments, data driver 320 and controller 350 can be implemented using separate ICs.

[0126] The scan driver 330 can generate a scan signal SS based on a scan control signal received from the controller 350, and can provide the scan signal SS to multiple pixels PX via multiple scan lines. In some embodiments, the scan control signal may include, but is not limited to, a scan start signal FLM, a first clock signal CLK1, a second clock signal CLK2, and an enable signal EN. Furthermore, in some embodiments, the scan signal SS may include a write signal GW (e.g., a write signal GW[n] and a previous write signal GW[n-1]), a compensation signal GC, an initialization signal GI, and a bias signal GB. In some embodiments, at least one of the compensation signal GC and the initialization signal GI applied to the compensation transistor PXT3 and the gate initialization transistor PXT4 implemented by NMOS transistors may be provided by… Figure 3 The stage 200 shown is generated and output. Furthermore, in some embodiments, the scan driver 330 may be integrated into or formed in (or on) the peripheral portion of the display panel 310. In other embodiments, the scan driver 330 may be implemented using one or more ICs.

[0127] The transmit driver 340 can generate a transmit signal EM based on a transmit control signal EMCTRL received from the controller 350, and can provide the transmit signal EM to multiple pixels PX via multiple transmit lines. In some embodiments, the transmit signal EM can be provided in a basic sequential manner. In other embodiments, the transmit signal EM can be a global signal provided substantially simultaneously to multiple pixels PX. In some embodiments, the transmit driver 340 can be integrated or formed on (or in) a peripheral portion of the display panel 310. In other embodiments, the transmit driver 340 can be implemented using one or more ICs.

[0128] Controller 350 (e.g., a timing controller (“TCON”)) may receive input image data IDAT and control signal CTRL from an external host processor (e.g., a graphics processing unit (“GPU”) or graphics card). In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. Controller 350 may generate output image data ODAT, a data control signal DCTRL, a scan control signal, and a transmit control signal EMCTRL based on the input image data IDAT and the control signal CTRL. Controller 350 may control the operation of data driver 320 by providing the output image data ODAT and the data control signal DCTRL to data driver 320, control the operation of scan driver 330 by providing the scan control signal to scan driver 330, and control the operation of transmit driver 340 by providing the transmit control signal EMCTRL to transmit driver 340.

[0129] The display device 300 in this embodiment can perform multi-frequency driving (“MFD”) to drive multiple panel areas of the display panel 310 at multiple driving frequencies (which may be different from each other). To perform this MFD, as... Figure 18 As shown, the controller 350 may include a still image detection block 360, a drive frequency determination block 370, and a scan driver control block 380.

[0130] The still image detection block 360 can divide the input image data IDAT into multiple panel area data for multiple panel areas, each including at least one pixel row, and can determine whether each of the multiple panel area data represents a still image.

[0131] The drive frequency determination block 370 can determine multiple drive frequencies for multiple panel areas based on whether each of the multiple panel area data represents a still image. In some embodiments, when each panel area data represents a moving image, the drive frequency determination block 370 can determine the drive frequency of the panel area corresponding to the panel area data as the normal drive frequency. Here, the normal drive frequency may be the drive frequency in the normal drive of the display device 300. In embodiments, for example, the normal drive frequency may be the same as the input frame frequency of the input image data IDAT (e.g., about 60 Hz or about 120 Hz). Furthermore, when each panel area data represents a still image, the drive frequency determination block 370 can determine the drive frequency of the panel area corresponding to the panel area data as a low drive frequency lower than the normal drive frequency. Here, the low drive frequency may be any frequency lower than the normal drive frequency.

[0132] The scan driver control block 380 can generate an enable signal EN based on multiple drive frequencies for multiple panel areas. In some embodiments, the scan driver control block 380 can control the enable signal EN to have a first level (e.g., high level) when a scan signal SS is about to be output, and can control the enable signal EN to have a second level (e.g., low level) when no scan signal SS is about to be output. Therefore, a scan signal SS can be provided in each of the multiple frame periods relative to each panel area driven at a normal drive frequency. However, a scan signal SS can not be provided in at least one of the multiple frame periods relative to each panel area driven at a low drive frequency.

[0133] Figure 20 This is a block diagram illustrating an embodiment of an electronic device including a display device.

[0134] Reference Figure 20 The electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (“I / O”) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, other electrical devices, etc.

[0135] Processor 1110 can perform various computing functions or tasks. Processor 1110 may be an application processor (“AP”), a microprocessor, a central processing unit (“CPU”), etc. Processor 1110 may be coupled to other components via address buses, control buses, data buses, etc. In addition, in some embodiments, processor 1110 may also be coupled to an expansion bus, such as a peripheral component interconnect (“PCI”) bus.

[0136] The memory device 1120 may store data for the operation of the electronic device 1100. In embodiments, for example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, and / or at least one volatile memory device such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile dynamic random access memory (“Dynamic DRAM”) device, and so on.

[0137] Storage device 1130 may be a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, an optical disc read-only memory (“CD-ROM”) device, etc. I / O device 1140 may be an input device such as a keyboard, keypad, mouse, touchscreen, etc., and an output device such as a printer, speaker, etc. Power supply 1150 provides power for the operation of electronic device 1100. Display device 1160 may be coupled to other components via a bus or other communication link.

[0138] In the display device 1160, each stage of the scan driver may include an enable node control circuit that controls the voltage of an enable node according to an enable signal and maintains the voltage of the enable node during the output carry signal, and a masking circuit that selectively couples a second node and a third node in response to the voltage of the enable node. Therefore, each of the plurality of scan signals generated by the scan driver may have a time length corresponding to two or more horizontal times, and the plurality of scan signals may be provided to corresponding areas of the display panel at different drive frequencies.

[0139] The concepts of this invention can be applied to any display device 1160 and any electronic device 1100 including the display device 1160. In embodiments, the concepts of this invention can be applied to wearable electronic devices, mobile phones (e.g., smartphones), televisions (“TV”, e.g., digital TV, 3D TV), personal computers (“PC”, e.g., tablet computers, laptop computers), home appliances, personal digital assistants (“PDAs”), portable multimedia players (“PMPs”), digital cameras, music players, portable game consoles, navigation devices, etc.

[0140] Figure 21 This is a block diagram illustrating an embodiment of the electronic device.

[0141] The electronic device 2101 can output various information via the display module 2140 in the operating system. When the processor 2110 runs an application stored in the memory 2120, the display module 2140 can provide application information to the user via the display panel 2141.

[0142] The processor 2110 can obtain external input via the input module 2130 or the sensor module 2161, and can run an application corresponding to the external input. In one embodiment, for example, when a user selects a camera icon displayed on the display panel 2141, the processor 2110 can obtain user input via the input sensor 2161-2 and can activate the camera module 2171. The processor 2110 can then transmit image data corresponding to the image captured by the camera module 2171 to the display module 2140. The display module 2140 can display the image corresponding to the captured image via the display panel 2141.

[0143] In another embodiment, when personal information authentication is performed in the display module 2140, the fingerprint sensor 2161-1 can obtain input fingerprint information as input data. The processor 2110 can compare the input data obtained by the fingerprint sensor 2161-1 with the authentication data stored in the memory 2120, and can run the application based on the comparison result. The display module 2140 can display the information executed according to the application logic via the display panel 2141.

[0144] As another example, when a music stream icon displayed on display module 2140 is selected, processor 2110 obtains user input via input sensor 2161-2 and can activate the music stream application stored in memory 2120. When a music run command is entered in the music stream application, processor 2110 can activate sound output module 2163 to provide the user with sound information corresponding to the music run command.

[0145] The operation of electronic device 2101 has been briefly described above. The configuration of electronic device 2101 will be described in detail below. Some of the components of electronic device 2101 described below can be integrated and provided as a single component, or a single component can be provided separately as two or more components.

[0146] Reference Figure 21Electronic device 2101 can communicate with external electronic device 2102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). In some embodiments, electronic device 2101 may include processor 2110, memory 2120, input module 2130, display module 2140, power management module 2150, internal module 2160, and external module 2170. In some embodiments, at least one of these components may be omitted from electronic device 2101, or one or more other components may be added to electronic device 2101. In some embodiments, some of the multiple components (e.g., sensor module 2161, antenna module 2162, or voice output module 2163) may be implemented as a single component (e.g., display module 2140) (e.g., integrated into a single component (e.g., display module 2140)).

[0147] Processor 2110 can run software to control at least one other component (e.g., hardware or software component) of electronic device 2101 coupled to processor 2110, and can perform various data processing or calculations. In some embodiments, as at least part of data processing or calculation, processor 2110 can store commands or data received from another component (e.g., input module 2130, sensor module 2161, or communication module 2173) in volatile memory 2121, can process commands or data stored in volatile memory 2121, and can store result data in non-volatile memory 2122.

[0148] Processor 2110 may include a main processor 2111 and an auxiliary processor 2112. Main processor 2111 may include one or more of a central processing unit (“CPU”) 2111-1 and an application processor (“AP”). Main processor 2111 may also include any one or more of a graphics processing unit (“GPU”) 2111-2, a communication processor (“CP”), and an image signal processor (“ISP”). Main processor 2111 may also include a neural processing unit (“NPU”) 2111-3. NPU 2111-3 may be a processor dedicated to processing artificial intelligence models, and the artificial intelligence models may be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural network may be a deep neural network (“DNN”), a convolutional neural network (“CNN”), a recurrent neural network (“RNN”), a restricted Boltzmann machine (“RBM”), a deep belief network (“DBN”), a bidirectional recurrent deep neural network (“BRDNN”), a deep Q-network, or a combination of two or more thereof, but is not limited thereto. Artificial intelligence models may additionally or alternatively include software structures in addition to hardware structures. At least two of the aforementioned processing units and processors may be implemented as a single component (e.g., a single chip), or the corresponding processing units and processors may be implemented as multiple independent components (e.g., multiple chips).

[0149] The auxiliary processor 2112 may include a controller. The controller may include interface conversion circuitry and timing control circuitry. The controller may receive image signals from the main processor 2111, convert the data format of the image signals to meet the interface specifications with the display module 2140, and output image data. The controller may output various control signals required to drive the display module 2140.

[0150] The auxiliary processor 2112 may also include a data conversion circuit 2112-2, a gamma correction circuit 2112-3, a rendering circuit 2112-4, or similar circuitry. The data conversion circuit 2112-2 may receive image data from the controller. The data conversion circuit 2112-2 may compensate the image data according to the characteristics of the electronic device 2101 or user settings to display the image at a desired brightness, or may convert the image data to reduce power consumption or eliminate afterimages. The gamma correction circuit 2112-3 may convert the image data or a gamma reference voltage so that the image displayed on the electronic device 2101 has desired gamma characteristics. The rendering circuit 2112-4 may receive image data from the controller and may render the image data taking into account the pixel arrangement of the display panel 2141 in the electronic device 2101. At least one of the data conversion circuit 2112-2, the gamma correction circuit 2112-3, and the rendering circuit 2112-4 may be integrated into another component (e.g., the main processor 2111 or the controller). At least one of the data conversion circuit 2112-2, the gamma correction circuit 2112-3, and the rendering circuit 2112-4 may be integrated into the data driver 2143 described below.

[0151] Memory 2120 may store various data used by at least one component of electronic device 2101 (e.g., processor 2110 or sensor module 2161). For example, the various data may include input data or output data for commands associated with them. Memory 2120 may include at least one of volatile memory 2121 and non-volatile memory 2122.

[0152] The input module 2130 can receive commands or data from outside the electronic device 2101 (e.g., a user or external electronic device 2102) to be used by components of the electronic device 2101 (e.g., processor 2110, sensor module 2161, or sound output module 2163).

[0153] Input module 2130 may include a first input module 2131 for receiving commands or data from a user and a second input module 2132 for receiving commands or data from an external electronic device 2102. The first input module 2131 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 2132 may support a specified protocol that enables the electronic device 2101 to be connected to the external electronic device 2102 via wired or wireless means. In some embodiments, the second input module 2132 may include a High Definition Multimedia Interface (“HDMI”), a Universal Serial Bus (“USB”) interface, a Secure Digital (“SD”) card interface, or an audio interface. The second input module 2132 may include a connector that allows the electronic device 2101 to be physically connected to the external electronic device 2102. In embodiments, for example, the second input module 2132 may include an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0154] Display module 2140 provides information to the user visually. Display module 2140 may include display panel 2141, scan driver 2142, and data driver 2143. Display module 2140 may also include a window, frame, and bracket for protecting display panel 2141.

[0155] The display panel 2141 may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, but the type of display panel 2141 is not limited to these. The display panel 2141 may be a rigid type display panel or a flexible type display panel that can be rolled or folded. The display module 2140 may also include a support member, bracket, or heat dissipation member that supports the display panel 2141.

[0156] The scan driver 2142 may be disposed (e.g., mounted) on the display panel 2141 as a driver chip. In alternative embodiments, the scan driver 2142 may be integrated into the display panel 2141. In embodiments, for example, the scan driver 2142 may include an amorphous silicon TFT gate driver circuit (“ASG”), a low-temperature polycrystalline silicon (“LTPS”) TFT gate driver circuit, or an oxide semiconductor TFT gate driver circuit (“OSG”) embedded in the display panel 2141. The scan driver 2142 may receive control signals from a controller and may output scan signals to the display panel 2141 in response to the control signals.

[0157] The display panel 2141 may also include a transmitter driver. The transmitter driver can output a transmitter signal to the display panel 2141 in response to a control signal received from the controller. The transmitter driver may be formed separately from the scan driver 2142, or it may be integrated into the scan driver 2142.

[0158] The data driver 2143 can receive control signals from the controller, convert image data into analog voltages (e.g., data voltages) in response to the control signals, and then output the data voltages to the display panel 2141.

[0159] The data driver 2143 can be incorporated into other components (e.g., a controller). Furthermore, the functions of the controller's interface conversion circuitry and timing control circuitry described above can be integrated into the data driver 2143.

[0160] The display module 2140 may also include a transmitter driver, a voltage generator circuit, or the like. The voltage generator circuit can output various voltages required to drive the display panel 2141.

[0161] Power management module 2150 supplies power to components of electronic device 2101. Power management module 2150 may include a battery that is charged to a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable accumulator, or a fuel cell. Power management module 2150 may include a power management integrated circuit (“PMIC”). The PMIC can optimally supply power to each of the modules described above and below. Power management module 2150 may include a wireless power transmitting / receiving component electrically connected to the battery. The wireless power transmitting / receiving component may include multiple antenna radiators in the form of coils.

[0162] The electronic device 2101 may also include an internal module 2160 and an external module 2170. The internal module 2160 may include a sensor module 2161, an antenna module 2162, and a sound output module 2163. The external module 2170 may include a camera module 2171, an optical module 2172, and a communication module 2173.

[0163] Sensor module 2161 can detect input through a user's body or through a pen in the first input module 2131, and can generate an electrical signal or data value corresponding to the input. Sensor module 2161 may include at least one of fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3.

[0164] The fingerprint sensor 2161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 2161-1 may include either an optical fingerprint sensor or a capacitive fingerprint sensor.

[0165] Input sensor 2161-2 can generate data values ​​corresponding to the coordinate information of input from the user's body or a pen. Input sensor 2161-2 can convert capacitance changes caused by input into data values. Input sensor 2161-2 can detect input through a passive pen, or can send data to / receive data from an active pen.

[0166] Input sensor 2161-2 can measure biosignals such as blood pressure, water content, or body fat. In an implementation, for example, when a part of a user's body touches the sensor layer or sensing panel and remains stationary for a predetermined period of time, input sensor 2161-2 can detect the biosignal based on changes in the electric field caused by the part of the body and output the user's desired information to display module 2140.

[0167] The digitizer 2161-3 generates data values ​​corresponding to coordinate information input via a pen. The digitizer 2161-3 converts the amount of electromagnetic change caused by the input into data values. The digitizer 2161-3 can detect input via a passive pen, or send data to / receive data from an active pen.

[0168] At least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be implemented as a sensor layer formed on the display panel 2141 by a continuous process. The fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be arranged above the display panel 2141, or at least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be arranged below the display panel 2141.

[0169] Two or more of the fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 can be integrated into a single sensing panel through the same process. When integrated into a single sensing panel, the sensing panel can be positioned between the display panel 2141 and a window positioned above the display panel 2141. In some embodiments, the sensing panel can be positioned on the window, but the location of the sensing panel is not limited thereto.

[0170] At least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 may be embedded in the display panel 2141. That is, at least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 may be formed simultaneously by a process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 2141.

[0171] In addition, sensor module 2161 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device 2101. Sensor module 2161 may also include, for example, gesture sensors, gyroscope sensors, atmospheric pressure sensors, magnetic sensors, acceleration sensors, grip force sensors, proximity sensors, color sensors, infrared (“IR”) sensors, biometric sensors, temperature sensors, humidity sensors, or illuminance sensors.

[0172] Antenna module 2162 may include one or more antennas for transmitting or receiving signals or power to or from an external source. In some embodiments, communication module 2173 may transmit or receive signals to or from external electronic device 2102 via an antenna suitable for a communication method. The antenna pattern of antenna module 2162 may be integrated into a component of display module 2140 (e.g., display panel 2141) or input sensor 2161-2.

[0173] The sound output module 2163 can output sound signals to the outside of the electronic device 2101. The sound output module 2163 may include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as playing multimedia or playing recordings. The receiver can be used to receive incoming calls. In some embodiments, the receiver may be implemented separately from the speaker or as part of the speaker. The sound output mode of the sound output module 2163 may be integrated into the display module 2140.

[0174] Camera module 2171 can capture still images and moving images. In some embodiments, camera module 2171 may include one or more lenses, an image sensor, or an image signal processor. Camera module 2171 may also include an infrared camera capable of measuring the presence or absence of a user, the user's position, and the user's line of sight.

[0175] The light module 2172 can provide light. The light module 2172 may include a light-emitting diode or a xenon lamp. The light module 2172 can operate in conjunction with the camera module 2171, or it can operate independently of the camera module 2171.

[0176] Communication module 2173 can support the establishment of a wired or wireless communication channel between electronic device 2101 and external electronic device 2102, and perform communication via the established communication channel. Communication module 2173 may include a wireless communication module (e.g., a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (“GNSS”) communication module) or a wired communication module (e.g., a local area network (“LAN”) communication module or a power line communication (“PLC”) module). Communication module 2173 can be used via a short-range communication network (e.g., Bluetooth). TMThe communication module 2173 communicates with external electronic devices via a wireless fidelity (“Wi-Fi”) direct connection or infrared data association (“IrDA”) or long-range communication network (e.g., cellular network, Internet, or computer network (e.g., LAN or wide area network (“WAN”)). These various types of communication modules 2173 can be implemented as a single chip or as multiple chips separate from each other.

[0177] Input module 2130, sensor module 2161, camera module 2171 or the like can be used in conjunction with processor 2110 to control the operation of display module 2140.

[0178] The processor 2110 can output commands or data to the display module 2140, the sound output module 2163, the camera module 2171, or the optical module 2172 based on input data received from the input module 2130. In one embodiment, for example, the processor 2110 can generate image data corresponding to input data applied via a mouse or active pen, and can output the image data to the display module 2140. In an alternative embodiment, the processor 2110 can generate command data corresponding to the input data, and can output the command data to the camera module 2171 or the optical module 2172. When no input data is received from the input module 2130 within a predetermined time period, the processor 2110 can switch the operating mode of the electronic device 2101 to a low-power mode or a sleep mode, thereby reducing the power consumption of the electronic device 2101.

[0179] Processor 2110 can output commands or data to display module 2140, sound output module 2163, camera module 2171, or light module 2172 based on sensing data received from sensor module 2161. In some embodiments, for example, processor 2110 can compare authentication data applied by fingerprint sensor 2161-1 with authentication data stored in memory 2120, and then run an application based on the comparison result. Processor 2110 can run commands or output corresponding image data to display module 2140 based on sensing data sensed by input sensor 2161-2 or digitizer 2161-3. If sensor module 2161 includes a temperature sensor, processor 2110 can receive temperature data from sensor module 2161 and can further perform brightness correction on the image data based on the temperature data.

[0180] Processor 2110 can receive measurement data from camera module 2171 relating to the presence or absence of a user, the user's position, and the user's line of sight. Processor 2110 can also perform brightness correction on image data based on the measurement data. In an embodiment, for example, after processor 2110 determines the presence or absence of a user based on input from camera module 2171, data conversion circuit 2112-2 or gamma correction circuit 2112-3 can perform brightness correction on the image data, and processor 2110 can provide the brightness-corrected image data to display module 2140.

[0181] At least some of the aforementioned components may be coupled to each other and communicate (e.g., commands or data) between them via inter-peripheral communication schemes (e.g., bus, general purpose input and output (“GPIO”), serial peripheral interface (“SPI”), mobile industry processor interface (“MIPI”), or hyperpath interconnect (“UPI”)). Processor 2110 may communicate with display module 2140 via an agreed interface. Furthermore, any of the aforementioned communication methods may be used between processor 2110 and display module 2140, but the communication methods between processor 2110 and display module 2140 are not limited to those described above.

[0182] The electronic device 2101 according to the various embodiments described above can be of various types. In the embodiments, for example, the electronic device 2101 may include at least one of portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, and home appliances. However, the electronic device 2101 in the embodiments is not limited to the devices described above.

[0183] The foregoing is illustrative of the embodiments and is not to be construed as limiting them. Although some embodiments have been described, it will be readily apparent to those skilled in the art that many modifications are possible in the embodiments without departing from the novelty and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. It is therefore understood that the foregoing is illustrative of various embodiments and is not to be construed as limiting to the disclosed illustrative embodiments, and that modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A scan driver, the scan driver comprising a plurality of stages, each of the plurality of stages comprising: A control circuit that controls the voltage of the first node and the voltage of the second node in response to an input signal, a first clock signal, and a second clock signal; A carry output circuit, which outputs a carry signal in response to the voltage of the first node and the voltage of the second node; An enable node control circuit that controls the voltage of the enable node in response to the carry signal, the enable signal, and the inverted enable signal; A masking circuit that controls the voltage of a third node in response to the voltage of the second node and the voltage of the enabling node; as well as A scan output circuit that outputs a scan signal in response to the voltage of the first node and the voltage of the third node.

2. The scan driver of claim 1, wherein, Before outputting the carry signal with a first level, while the enable signal has the first level, the enable node control circuit controls the voltage of the enable node to a second level, and During the output of the carry signal having the first level, the masking circuit controls the voltage of the third node to the second level in response to the voltage of the enable node having the second level, and the scan output circuit outputs the scan signal having the first level in response to the voltage of the third node having the second level.

3. The scan driver according to claim 2, wherein, During the output of the carry signal having the first level, when the enable signal changes from the first level to the second level, the enable node control circuit maintains the voltage of the enable node at the second level until the output of the carry signal having the first level is completed.

4. The scan driver according to claim 1, wherein, Before outputting the carry signal with a first level, when the enable signal has a second level, the enable node control circuit controls the voltage of the enable node to the first level, and During the output of the carry signal having the first level, the masking circuit controls the voltage of the third node to the first level in response to the voltage of the enable node having the first level, and the scan output circuit does not output the scan signal having the first level in response to the voltage of the third node having the first level.

5. The scan driver according to claim 4, wherein, During the output of the carry signal having the first level, when the enable signal changes from the second level to the first level, the enable node control circuit maintains the voltage of the enable node at the first level until the output of the carry signal having the first level is completed.

6. The scan driver according to claim 1, wherein, During the output of the carry signal having a first level, the enable node control circuit maintains the voltage of the enable node at the previous level.

7. The scan driver according to claim 1, wherein, When there is no carry signal with a first level, the enable signal has the first level, and the inverted enable signal has a second level, the enable node control circuit controls the voltage of the enable node to the second level, and Specifically, when there is no carry signal with the first level, the enable signal has the second level, and the inverted enable signal has the first level, the enable node control circuit controls the voltage of the enable node to the first level.

8. The scan driver according to claim 1, wherein, The enabling node control circuit includes: A first transistor and a second transistor, the first transistor and the second transistor being coupled in series between a high gate voltage line and the enable node, the first transistor being turned on in response to the carry signal, and the second transistor being turned on in response to the enable signal; and A third transistor and a fourth transistor are coupled in series between the enable node and the low gate voltage line. The third transistor turns on in response to the inverted enable signal, and the fourth transistor turns on in response to the carry signal.

9. The scan driver according to claim 8, wherein, The first transistor includes a gate for receiving the carry signal, a first terminal coupled to the high gate voltage line, and a second terminal. The second transistor includes a gate for receiving the enable signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the enable node. The third transistor includes a gate for receiving the inverted enable signal, a first terminal coupled to the enable node, and a second terminal. The fourth transistor includes a gate for receiving the carry signal, a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to the low gate voltage line.

10. The scan driver according to claim 8, wherein, The enabling node control circuit also includes: A first capacitor is coupled between the enable node and the low gate voltage line.

11. The scan driver according to claim 1, wherein, The masking circuit separates the second node from the third node when the voltage of the enabling node has a first level, and couples the second node to the third node when the voltage of the enabling node has a second level.

12. The scan driver according to claim 1, wherein, The masking circuit includes: A fifth transistor, which selectively couples the second node to the third node in response to the voltage of the enable node.

13. The scan driver according to claim 12, wherein, The fifth transistor includes a gate coupled to the enable node, a first terminal coupled to the second node, and a second terminal coupled to the third node.

14. The scan driver according to claim 12, wherein, The masking circuit also includes: A second capacitor, coupled between the high gate voltage line and the third node; and A sixth transistor and a seventh transistor are coupled in series between the high gate voltage line and the third node. The sixth transistor turns on in response to the carry signal, and the seventh transistor turns on in response to the enable signal.

15. The scan driver according to claim 14, wherein, The sixth transistor includes a gate for receiving the carry signal, a first terminal coupled to the high gate voltage line, and a second terminal. The seventh transistor includes a gate for receiving the enable signal, a first terminal coupled to the second terminal of the sixth transistor, and a second terminal coupled to the third node.

16. The scan driver according to claim 1, wherein, The carry-out output circuit includes: An eighth transistor, the eighth transistor including a gate coupled to the second node, a first terminal coupled to a high gate voltage line, and a second terminal coupled to a carry-out node; and The ninth transistor includes a gate coupled to the first node, a first terminal coupled to the carry output node, and a second terminal coupled to a low gate voltage line.

17. The scan driver according to claim 1, wherein, The scan output circuit includes: A tenth transistor, the tenth transistor comprising a gate coupled to the third node, a first terminal coupled to a high gate voltage line, and a second terminal coupled to a scan output node; and The eleventh transistor includes a gate coupled to the first node, a first terminal coupled to the scan output node, and a second terminal coupled to a low gate voltage line.

18. The scan driver according to claim 1, wherein, The transistors included in each of the plurality of stages are implemented using p-type metal-oxide-semiconductor transistors.

19. The scan driver according to claim 18, wherein, The carry signal and the scan signal are both valid high signals with a high level as the effective level.

20. A display device, comprising: The display panel includes a plurality of pixels; A data driver that provides data signals to each of the plurality of pixels; A scan driver that provides a scan signal to each of the plurality of pixels; as well as The controller controls the data driver and the scan driver. The scan driver comprises multiple stages, and each of the multiple stages includes: A control circuit that controls the voltage of the first node and the voltage of the second node in response to an input signal, a first clock signal, and a second clock signal; A carry output circuit, which outputs a carry signal in response to the voltage of the first node and the voltage of the second node; An enable node control circuit that controls the voltage of the enable node in response to the carry signal, the enable signal, and the inverted enable signal; A masking circuit that controls the voltage of a third node in response to the voltage of the second node and the voltage of the enabling node; and A scan output circuit that outputs the scan signal in response to the voltage of the first node and the voltage of the third node.

Images