Gate driving circuit, array substrate and display panel

Abstract

This disclosure discloses a gate driving circuit, an array substrate, and a display panel, relating to the field of display technology. The gate driving circuit drives a display panel; the display panel has multiple row partitions, each row partition having at least one pixel row and scan lines driving each pixel row, as well as a common electrode for each pixel; the gate driving circuit includes a shift register group corresponding to each row partition and cascaded sequentially; the shift register group includes multiple shift register bodies cascaded sequentially and a common voltage controller; the output terminals of the shift register bodies output scan signals corresponding to the scan lines in each row partition; the control terminal of the common voltage controller is electrically connected to the output terminals of each shift register body, the input terminal of the common voltage controller is used to load the common voltage corresponding to the row partition, and the output terminal of the common voltage controller is electrically connected to each common electrode in the row partition. This gate driving circuit can improve the flicker problem of the panel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to gate driving circuits, array substrates, and display panels. Background Technology

[0002] If a normal product without a touchscreen has severe capacitive coupling in the panel, it can cause flickering, meaning that the panel flickers visibly to the naked eye under certain screen conditions.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and to provide a gate driving circuit, an array substrate, and a display panel that can improve the flicker problem of the panel.

[0005] According to one aspect of this disclosure, a gate driving circuit is provided for driving a display panel; the display panel has a plurality of row partitions, each row partition having at least one pixel row, scan lines driving each pixel row, and a common electrode for each pixel;

[0006] The gate drive circuit includes a group of shift registers that correspond one-to-one with each of the row partitions and are cascaded in sequence;

[0007] The shift register group includes multiple shift register bodies cascaded in sequence and a common voltage controller; the output terminal of the shift register body is connected one-to-one with the scan trace in the corresponding row partition to output a scan signal;

[0008] In the shift register group, the control terminal of the common voltage controller is electrically connected to the output terminal of each shift register body, the input terminal of the common voltage controller is used to load the common voltage corresponding to the row partition, and the output terminal of the common voltage controller is used to be electrically connected to each common electrode in the row partition;

[0009] The common voltage controller is configured to apply the common voltage to the common electrode of the row partition in response to a scan signal.

[0010] In one embodiment of this disclosure, the row partition has a pixel row; the shift register group includes a shift register body and a common voltage controller.

[0011] In one embodiment of this disclosure, the row partition also has a common voltage trace corresponding one-to-one with the common electrode of each pixel;

[0012] The output terminal of the common voltage controller is used to electrically connect to each common electrode in the row partition through the corresponding common voltage trace.

[0013] In one embodiment of this disclosure, the common voltage controller is a transistor;

[0014] In the shift register group, the gate of the transistor is electrically connected to the output terminal of each shift register body, the first stage of the transistor is used to load the common voltage corresponding to the row partition, and the second stage of the transistor is used to be electrically connected to each common electrode in the row partition.

[0015] According to another aspect of this disclosure, an array substrate is provided, the array substrate having a display area and a peripheral area;

[0016] The display area has multiple row partitions, and each row partition has at least one pixel row, a scan line that drives each pixel row, and a common electrode for each pixel.

[0017] At least one side of the peripheral region has the aforementioned gate driving circuit;

[0018] The output terminal of the common voltage controller is electrically connected to each common electrode in the row partition.

[0019] In one embodiment of this disclosure, the row partition also has a common voltage trace corresponding one-to-one with the common electrode of each pixel;

[0020] The output terminal of the common voltage controller is used to be electrically connected to each common electrode in the row partition through the corresponding common voltage line;

[0021] The impedance of the common voltage trace is 90%-110% of the impedance of the scan trace.

[0022] In one embodiment of this disclosure, the impedance of the common voltage trace is the same as the impedance of the scan trace.

[0023] In one embodiment of this disclosure, the array substrate includes a gate layer having the scan trace and the common voltage trace.

[0024] In one embodiment of this disclosure, the peripheral region has the aforementioned gate driving circuit on both sides along the row direction.

[0025] According to another aspect of this disclosure, a display panel is provided, including the aforementioned array substrate.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0028] Figure 1 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0029] Figure 2 This is a schematic diagram of the structure of the array substrate in one embodiment of the present disclosure.

[0030] Figure 3 This is a schematic diagram of the structure of the array substrate in one embodiment of the present disclosure.

[0031] Figure 4 This is a schematic diagram of the structure of the driving layer in one embodiment of the present disclosure.

[0032] Figure 5 This is a schematic diagram of the structure of the driving layer in one embodiment of the present disclosure.

[0033] Figure 6 This is an equivalent circuit diagram of the gate drive circuit in one embodiment of the present disclosure.

[0034] Figure 7 This is an equivalent circuit diagram of the gate drive circuit in one embodiment of the present disclosure.

[0035] Figure 8 This is an equivalent circuit diagram of a gate drive circuit cascade scheme in one embodiment of the present disclosure.

[0036] Figure 9 This is a schematic diagram of a portion of the film layer structure of an array substrate in one embodiment of the present disclosure.

[0037] Figure 10 This is a waveform diagram of the signal transmission of the near-end drive voltage (Pixel) and common voltage of the scan trace in one embodiment of this disclosure.

[0038] Figure 11 This is a waveform diagram of the signal transmission of the scanning trace's far-end drive voltage (Pixel) and common voltage in one embodiment of this disclosure.

[0039] Explanation of reference numerals in the attached figures:

[0040] PNL, Display Panel; ARR, Array Substrate; CF, Color Filter Substrate; LC, Liquid Crystal Layer; FSA, Sealing Agent; AA, Display Area; BB, Peripheral Area; UU, Display Unit; PP, Subpixel; PDC, Pixel Driver Circuit; DH, Row Direction; GL, Scan Line; DV, Column Direction; DL, Data Voltage Line; CL, Common Voltage Line; SW, Switching Transistor; PE, Pixel Electrode; COMP, Common Electrode; SBT, Substrate; GT, Gate Layer; GI, Gate Insulating Layer; SD, Source / Drain Metal Layer; CCL, Common Voltage Controller; Via, Via Connection Via; PA, Subpixel Area; SCL, Semiconductor Layer. Detailed Implementation

[0041] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0042] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0043] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” etc. are used only as markers and are not a limitation on the number of objects.

[0044] In this embodiment, a transistor is a device that includes at least three terminals: a gate, a source, and a drain. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the source, the channel region, and the drain. The channel region refers to the area through which current primarily flows. In this embodiment, when using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged; that is, the "source" and "drain" can be interchanged. In this embodiment, for any given transistor, one of the "source" and "drain" is referred to as the first terminal of the transistor, and the other is referred to as the second terminal of the transistor.

[0045] This disclosure provides a display panel PNL, see [link to relevant documentation]. Figure 1 The display panel PNL may include an array substrate (ARR) and a color filter substrate (CF) arranged in a cell, and a liquid crystal layer (LC) sandwiched between the ARR and CF. A backlight module is located on the side of the ARR away from the CF. The PNL also has a sealing adhesive (FSA) surrounding the LC. The ARR drives the deflection of the liquid crystal molecules in the LC to control the amount of light transmitted, achieving grayscale display. The CF allows light transmitted through the LC to pass through the CF and form corresponding colored light, thus achieving full-color display.

[0046] In one embodiment of this disclosure, see Figure 2 The display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. In this example, the peripheral area BB surrounds the display area AA.

[0047] Within the display area AA, the display panel PNL is equipped with an array of display units UU. Each display unit UU includes a sub-pixel PP and a pixel driving circuit PDC that drives the sub-pixel PP. The display panel PNL does not have display units UU in the peripheral area BB, or the displayed units UU there are not used for displaying images.

[0048] See Figure 2The display panel PNL has multiple scan lines GL extending along the row direction DH in the display area AA, with each scan line GL corresponding to a row of display units. The pixel drive circuit PDC of each display unit UU in a row is electrically connected to its corresponding scan line GL. The display panel PNL also has multiple data voltage lines DL extending along the column direction DV in the display area AA, with each data voltage line DL corresponding to a column of display units. The pixel drive circuit PDC of each display unit in a column is electrically connected to its corresponding data voltage line DL. Thus, each display unit's pixel drive circuit PDC is connected to one scan line GL and one data voltage line DL. When a scan signal is applied to the scan line GL, the driving voltage applied to the data voltage line DL can be written into the pixel drive circuit PDC, allowing the pixel drive circuit PDC to control the brightness of the sub-pixel PP based on the written driving voltage. See also... Figure 3 The array substrate (ARR) can also be provided with multiple common voltage traces (CLs) extending along the row direction. Each common voltage trace (CL) can be configured to correspond one-to-one with each display unit row. In other examples, multiple display unit rows can correspond to one common voltage trace (CL). In this example, see [link to example]. Figure 3 The pixel driving circuit PDC can be a thin-film transistor that acts as a switching transistor SW. The sub-pixel PP can include a pixel electrode PE and a common electrode COMP. The pixel electrode PE and the common electrode COMP at least partially overlap to form a capacitor.

[0049] The first terminal of the switching transistor SW is electrically connected to the data voltage line DL, the second terminal of the switching transistor SW is electrically connected to the pixel electrode PE, the gate of the switching transistor SW is electrically connected to the scan line GL, and the common electrode COMP is electrically connected to the common voltage line CL. During operation, the common voltage line CL can apply a common voltage to the common electrode COMP; the switching transistor SW can respond to the scan signal applied on the scan line GL by applying the driving voltage from the data voltage line DL to the pixel electrode PE. Thus, by controlling the electric field strength between the pixel electrode PE and the common electrode COMP, the degree of twisting or collapsing of the liquid crystal molecules within the corresponding range of the pixel electrode PE can be adjusted, thereby adjusting the polarization direction of the polarized light passing through the liquid crystal molecules, and ultimately adjusting the light extraction efficiency of the display panel PNL within the corresponding range of the pixel electrode PE, achieving brightness control of the sub-pixel PP.

[0050] In one embodiment of this disclosure, the array substrate ARR includes a common electrode layer and a substrate SBT, a driving layer, a passivation layer and a pixel electrode layer stacked together.

[0051] In one embodiment of this disclosure, the substrate SBT can be an inorganic material substrate SBT, an organic material substrate SBT, or a substrate SBT composed of alternating layers of organic and inorganic materials. For example, in one embodiment of this disclosure, the material of the substrate SBT can be soda-lime glass, quartz glass, sapphire glass, or other glass materials. In another embodiment of this disclosure, the material of the substrate SBT can be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), polyethersulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof. In another embodiment of this disclosure, the substrate SBT can also be a flexible substrate SBT, for example, the material of the substrate SBT can be polyimide (PI). The substrate SBT can also be a composite of multiple materials. For example, in one embodiment of this disclosure, the substrate SBT may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer and a second polyimide layer stacked sequentially.

[0052] In one embodiment of this disclosure, a pixel electrode PE is provided in the pixel electrode layer, and a common electrode COMP is provided in the common electrode layer.

[0053] In one embodiment of this disclosure, the driving layer has a switching transistor SW for controlling the pixel electrode PE. In this example, the switching transistor SW may be a bottom-gate switching transistor. It will be understood that in other embodiments of this disclosure, the switching transistor SW may also be a top-gate switching transistor. For example, see [link to relevant documentation]. Figure 4The driving layer includes a gate layer GT, a gate insulating layer GI, a semiconductor layer SCL, and a source / drain metal layer SD stacked on a substrate SBT. The gate layer GT has side branches that can serve as the gate of a switching transistor SW. The semiconductor layer SCL forms the active layer of the switching transistor SW, including a channel region of the switching transistor SW and a first electrode and a second electrode of the switching transistor SW located on either side of the channel region. The source / drain metal layer SD forms a data voltage trace DL and a first conductive portion and a second conductive portion; the first conductive portion electrically connects the data voltage trace DL to the first electrode of the switching transistor SW, and the second conductive portion electrically connects the second electrode of the switching transistor SW to the pixel electrode PE in the pixel electrode layer. For example, see [link to example]. Figure 5 The driving layer includes a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer, and a source / drain metal layer SD stacked on a substrate SBT. The gate layer GT has side branches that can serve as the gate of a switching transistor SW. The semiconductor layer SCL forms the active layer of the switching transistor SW, including a channel region of the switching transistor SW and a first electrode and a second electrode of the switching transistor SW located on either side of the channel region. The source / drain metal layer SD forms a data voltage trace DL and a first conductive portion and a second conductive portion; the first conductive portion electrically connects the data voltage trace DL to the first electrode of the switching transistor SW, and the second conductive portion electrically connects the second electrode of the switching transistor SW to the pixel electrode PE in the pixel electrode layer. The gate insulating layer GI has vias that expose local areas of the first and second electrodes of the switching transistor SW, respectively. The first conductive portion is electrically connected to the first electrode of the switching transistor SW through the vias in the gate insulating layer GI, and one end of the second conductive portion is electrically connected to the second electrode of the switching transistor SW through the vias in the gate insulating layer GI.

[0054] The pixel electrode PE is electrically connected to the second conductive part through multiple connection vias, and the common electrode COMP is electrically connected to the common voltage trace CL.

[0055] In one embodiment of this disclosure, the common electrode COMP may be located above the pixel electrode PE. In other examples, the common electrode COMP may also be located below the pixel electrode PE.

[0056] In one embodiment of this disclosure, both the pixel electrode PE and the common electrode COMP are made of indium tin oxide (ITO), meaning both the pixel electrode PE and the common electrode COMP are transparent electrodes. It is understood that in other embodiments of this disclosure, at least one of the pixel electrode PE and the common electrode COMP may be made of other conductive materials, particularly other transparent conductive metal oxide materials.

[0057] In one embodiment of this disclosure, the semiconductor layer SCL (active layer) is made of low-temperature polycrystalline silicon (LTPS) or low-temperature polycrystalline oxide (LTPO).

[0058] In one embodiment of this disclosure, the gate insulating layer GI can also be configured as a multilayer structure or directly adopt a single-layer structure as needed.

[0059] In one embodiment of this disclosure, the switching transistor SW is a thin-film transistor (TFT).

[0060] In one embodiment of this disclosure, the peripheral region BB of the array substrate ARR has a first peripheral region with a source drive circuit bonded thereon, and a second peripheral region with a gate drive circuit (GOA) disposed thereon. The first peripheral region is located at one end of the column direction DV of the array substrate ARR, and the second peripheral region is located at one end of the row direction DH of the array substrate ARR. The source drive circuit is electrically connected to the data voltage trace DL and is used to generate a data voltage based on the image synchronization data and apply it to the data voltage trace DL. The gate drive circuit is electrically connected to each scan trace GL and is used to apply a scan signal to the scan trace GL that turns on the switching transistor SW.

[0061] In one embodiment of this disclosure, see Figure 3 The gate drive circuit is located on one side of the display area AA along the row direction DH. In other examples, it can also be located on both sides of the display area AA along the row direction DH.

[0062] In related technologies, the gate driving circuit includes multiple cascaded shift registers. The output of each shift register is connected to a row of scan lines GL, used to load a scan signal that turns on the switching transistor SW onto the scan lines GL. Each shift register may include a charging unit, an output unit, and a reset unit. The charging unit is configured to write the input voltage to the output unit in response to a first clock signal and a start signal STV. The output unit is configured to load the scan signal onto the scan line in response to a second clock signal and the input voltage. The reset unit is configured to turn off the output unit in response to a reset signal RST. This gate driving circuit provides the scan signal to each row of scan lines GL through the output unit, which is input into the sub-pixel area PA of each row of the display area, controlling the gate switching of the switching transistor SW in each row.

[0063] If a display panel PNL using the aforementioned gate drive circuit has severe capacitive coupling, it can cause a flicker problem, meaning the display panel PNL will flicker visibly in certain scenes. Analysis revealed that the flicker issue stems from differences in the voltage difference between the pixel electrode (PE) and the common electrode (COMP) that drive the liquid crystal flipping across different frames, resulting in perceptible brightness differences due to these voltage variations. One cause is that the pixel voltage carried by the pixel electrode (PE) generates capacitive coupling when its gate is off. This capacitive coupling can cause voltage differences of several gray levels in the near-end (both sides are near-end in dual-sided driving) and far-end (center is far-end in dual-sided driving) regions. Another cause is the difference in the common voltage (VCOM) carried by the common electrode (COMP) between one side of the screen and the center (near and far ends). The common voltage (VCOM) on one side recovers easily after coupling, while the common voltage (VCOM) in the center recovers more slowly because pixel coupling in the center only begins to recover after it ends.

[0064] To address the aforementioned problems, in one embodiment of this disclosure, see [link to relevant documentation]. Figure 6 Based on the aforementioned shift registers, a common voltage controller (CCL) is added, corresponding to the common voltage of each pixel row. The common voltage controller (CCL) loads the common voltage of each pixel row onto the common electrode (COMP) of each pixel row in the display area AA. Specifically, at least one pixel row forms a row partition, that is, a row partition has at least one pixel row, a scan trace GL that drives each pixel row, and the common electrode (COMP) of each pixel. The gate driving circuit includes a shift register group that corresponds one-to-one with each row partition and is cascaded sequentially; the shift register group includes multiple shift register bodies cascaded sequentially and a common voltage controller (CCL); the output terminal of the shift register body is connected one-to-one with the scan trace GL in the corresponding row partition to output a scan signal; in the shift register group, the control terminal of the common voltage controller (CCL) is electrically connected to the output terminal of each shift register body, the input terminal of the common voltage controller (CCL) is used to load the common voltage corresponding to the row partition, and the output terminal of the common voltage controller (CCL) is used to electrically connect to the common electrode (COMP) of each row partition.

[0065] In one embodiment of this disclosure, the row partition has a single pixel row, see [link to relevant documentation]. Figure 6 and Figure 8The shift register group includes a shift register body and a common voltage controller CCL. It can be understood that the shift register body, the common voltage controller CCL, and the pixel rows correspond one-to-one. The m-th level shift register body is used to charge the m-th level scan line GL of the display area AA of the liquid crystal display panel PNL, and the m-th level common voltage controller CCL is used to control the common voltage line CL corresponding to the m-th pixel row of the display area AA of the liquid crystal display panel PNL, where m is a positive integer greater than or equal to 1. Specifically, the control terminal of the common voltage controller CCL is electrically connected to the output terminal of the shift register body, and the input terminal of the common voltage controller CCL is used to load the common voltage corresponding to the pixel row (generally the common voltage signal source given by the display panel's driver IC); the output terminal of the common voltage controller CCL is electrically connected to the corresponding common voltage line CL. Simultaneously, the common voltage controller CCL is configured to respond to the scan signal output from the output terminal of the shift register body, causing the common voltage to be loaded onto the common electrode COMP of the display panel PNL through the common voltage line CL. In this way, adopting a one-to-one control method can improve control accuracy and further reduce the possibility of in-plane flickering.

[0066] In one embodiment of this disclosure, see Figure 7 The common voltage controller CCL can be a transistor. It can be understood that the gate (control terminal) of the transistor is electrically connected to the output terminal of the corresponding shift register body, the first terminal of the transistor is used to load the common voltage corresponding to the pixel row, and the second terminal of the transistor is electrically connected to the corresponding common voltage trace CL.

[0067] In this disclosure, see the following embodiment: Figure 9 The gate layer GT has scan traces GL and common voltage traces CL. The common electrode COMP is electrically connected to the common voltage traces CL through multiple connection vias Via.

[0068] In one embodiment of this disclosure, see Figure 9 The impedance of the common voltage trace CL is 90%-110% of the impedance of the scan trace GL. In this way, the impedance of the common voltage trace CL is basically the same as that of the scan trace GL. This can further ensure the simultaneity of signal transmission in the plane while ensuring that the scan signal and the common voltage are applied simultaneously, and further reduce the voltage difference between the pixel electrode PE and the common electrode COMP.

[0069] In one embodiment of this disclosure, the impedance of the common voltage trace CL is controlled to be equal to the impedance of the scan trace GL, thereby completely improving the panel flicker problem of different sizes and types of products.

[0070] In other embodiments of this disclosure, a shift register group may include two shift register bodies, wherein the two shift register bodies are cascaded, and a row partition includes two pixel rows with the same number of shift register bodies. In this case, a common voltage controller CCL controls the common electrode COMP corresponding to the two pixel rows. That is, the output terminal of the common voltage controller CCL is electrically connected to each common electrode COMP in the row partition, and the control terminal of the common voltage controller CCL is electrically connected to the output terminals of the corresponding two shift register bodies.

[0071] In other embodiments of this disclosure, a shift register group may include multiple shift register bodies, wherein the multiple shift register bodies are cascaded.

[0072] In other embodiments of this disclosure, the structure of the shift register body is not limited and can be 4T1C, 8T1C, etc.

[0073] In this disclosure, see the following embodiment: Figure 8 Based on the characteristic of the scanning traces GL in the pixel row of the display panel PNL being turned on and output row by row, when the Nth row scanning trace GL is high, the Nth row scanning signal is input to the Nth row pixel row. At the same time, the Nth row scanning signal acts as the control terminal (gate) switch of the Nth row common voltage controller CCL (transistor), controlling the common voltage controller CCL (transistor) to turn on. The common voltage and the scanning signal can be simultaneously applied to the pixel row. The scanning signal is applied to the scanning trace GL of a pixel row, and the common voltage is applied to the common voltage trace CL of a pixel row.

[0074] See Figure 9 This is a partial structural diagram of the array substrate ARR, where the scan trace GL and the common voltage trace CL are both located on the gate layer GT, corresponding to... Figure 8 The common voltage input signal is input to the common voltage trace CL of the display area AA through the common voltage controller CCL, and is input to the common electrode COMP through the multi-level connection via Via; wherein, the scan trace GL and the common voltage trace CL are RC consistent to ensure that the transmission level is equivalent.

[0075] See Figure 10 and Figure 11 By using the display panel PNL of this disclosure, since the scanning signal and the common voltage input signal of each row are transmitted synchronously, the capacitive coupling at different positions in the display panel PNL is consistent. In this way, the difference between the pixel voltage and the common voltage in the middle and both sides (near end and far end) of the display panel PNL is consistent, and the flicker level in different areas of the display panel PNL is consistent, thus eliminating the flicker of the display panel PNL.

[0076] This invention targets low-temperature polycrystalline silicon (LTPS) and low-temperature polycrystalline oxide (LTPO) products of different sizes and categories without touch functionality, including VR products. It introduces a common voltage controller (CCL) into the existing gate drive circuit to synchronize the scan signal output of each row with the common voltage output in time. It also ensures the consistency of the RC (Resistor-Capacitance circuit) transmission between the scan trace GL and the common voltage trace CL in the plane, thereby controlling the capacitive coupling in different areas of the control panel. This results in uniform common voltage and drive signals for each pixel across different areas of the panel, and ensures consistent voltage differences between the pixel electrodes PE and COMP on one side and in the center of the screen. This improves the flicker stability of the entire display panel PNL, thus completely eliminating the flicker problem in products of different sizes and categories.

[0077] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An array substrate, characterized in that, The array substrate has a display area and a peripheral area; The display area has multiple row partitions, each row partition having a pixel row, a scan line driving the pixel row, and a common electrode for each pixel; At least one side of the peripheral region is a gate driving circuit; the gate driving circuit includes a shift register group that corresponds one-to-one with each of the row partitions and is cascaded in sequence; The shift register group includes a shift register body and a common voltage controller; the output terminal of the shift register body is connected to the scan trace in the corresponding row partition to output a scan signal; In the shift register group, the control terminal of the common voltage controller is electrically connected to the output terminal of the shift register body, the input terminal of the common voltage controller is used to load the common voltage corresponding to the row partition, and the output terminal of the common voltage controller is electrically connected to the common electrode in the row partition; The common voltage controller is configured to apply the common voltage to the common electrode of the row partition in response to a scan signal; The row partition also has a common voltage trace corresponding to the common electrode of the pixel; The output terminal of the common voltage controller is used to be electrically connected to the common electrode in the row partition through a common voltage trace; the impedance of the common voltage trace is the same as the impedance of the scan trace.

2. The array substrate according to claim 1, characterized in that, The array substrate includes a gate layer, which has the scan trace and the common voltage trace.

3. The array substrate according to claim 1, characterized in that, The outer perimeter region has the gate driving circuit on both sides along the row direction.

4. The array substrate according to any one of claims 1-3, characterized in that, The common voltage controller is a transistor; In the shift register group, the gate of the transistor is electrically connected to the output terminal of each shift register body, the first stage of the transistor is used to load the common voltage corresponding to the row partition, and the second stage of the transistor is used to be electrically connected to each common electrode in the row partition.

5. A display panel, characterized in that, Includes the array substrate described in any one of claims 1-4 above.

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