Driving circuit of display panel and display device

Abstract

The application discloses a driving circuit of a display panel and a display device. The driving circuit comprises a power output circuit, a gate driving circuit and a timing controller. The gate driving circuit is used for opening the row-by-row scanning under the control of a gate start voltage signal and closing the scanning under the control of a gate off voltage signal. The timing controller is used for detecting the voltage on the working voltage line when the display panel is started and closed, and controlling the voltage on the gate off voltage line to be zero when the voltage on the working voltage line is at a first potential, and controlling the gate driving voltage line and the gate off line signal to be short-circuited when the working voltage signal is at a second potential. The first potential is greater than the second potential. After the power-off, the residual charge is dissipated by controlling the gate driving circuit, so that the residual image phenomenon of the display panel is avoided, and the display effect of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving circuit and display device for a display panel. Background Technology

[0002] A Liquid Crystal Display (LCD) device includes an LCD panel for displaying images and a driving circuit for driving the LCD panel. The driving circuit typically provides pixel voltages and a common voltage to the display panel. These pixel voltages and common voltages are used to drive the liquid crystal molecules in the LCD panel. The liquid crystal molecules are deflected at different angles by different electric fields, resulting in varying brightness and image display.

[0003] However, because the horizontal driving technology of LCD panels requires storing the data voltage of the display panel in the pixel capacitors, residual charge remains in the pixel capacitors when the display panel is turned off or the power is turned off and the display stops, resulting in the problem of image retention. Summary of the Invention

[0004] The purpose of this application is to provide a driving circuit and display device for a display panel, which controls the gate driving circuit to dissipate residual charge after power-off, thereby avoiding the phenomenon of image retention on the display panel and improving the display effect of the display panel.

[0005] This application discloses a driving circuit for a display panel. The driving circuit includes a power output circuit, a gate driving circuit, and a timing controller. The power output circuit is connected to at least a working voltage line, a gate start line, and a gate turn-off line, and is used to output a working voltage signal on the working voltage line, a gate start voltage signal on the gate start line, and a gate turn-off voltage signal on the gate turn-off line. The gate driving circuit is connected to at least the working voltage line, the gate start line, and the gate turn-off line, and is used to enable progressive scanning under the control of the gate start voltage signal and disable scanning under the control of the gate turn-off voltage signal. The timing controller is used to detect the voltage on the working voltage line when the display panel is turned on or off, and when the voltage on the working voltage line is at a first potential, control the voltage on the gate turn-off voltage line to be set to zero, and when the working voltage signal is at a second potential, control the gate driving voltage line and the gate turn-off line signal to be short-circuited; wherein the first potential is greater than the second potential.

[0006] Optionally, the first potential is equal to 60% to 80% of the potential of the operating voltage signal, and the second potential is equal to the potential at which the chip is undervoltage shut off.

[0007] Optionally, the operating voltage signal is 3.3V, the first potential is 2.7V to 2V, and the second potential is 1.6V.

[0008] Optionally, the gate turn-off voltage is less than 0V, and the gate start-up voltage is greater than 0V; the gate turn-off voltage is -8V, and the gate start-up voltage is 30V.

[0009] Optionally, the timing controller includes a first detection circuit and a first active switch. The input terminal of the first active switch is connected to the gate turn-off voltage, the output terminal of the first active switch is grounded, and the control terminal of the first active switch is connected to the first detection circuit. When the first detection circuit detects that the potential of the working voltage signal is less than or equal to a first potential, it controls the first active switch to turn on.

[0010] Optionally, the timing controller further includes a first control circuit, which controls the first detection circuit to start when the display panel is turned on or off, and detects the potential of the working voltage signal. When the display panel remains in a closed state or a closed state, the first detection circuit is controlled to remain in a non-operating state.

[0011] Optionally, the gate turn-off voltage includes a first turn-off voltage and a second turn-off voltage. The power supply output voltage outputs the first turn-off voltage when the display panel is in the working state and outputs the second turn-off voltage when the display panel is turned on and off. The first turn-off voltage is less than 0V and the second turn-off voltage is equal to 0V.

[0012] Optionally, when the timing controller detects that the voltage on the working voltage line is at the first potential, it outputs a shutdown enable signal to the power output circuit. After receiving the shutdown enable signal, the power output circuit outputs a second shutdown voltage to the gate shutdown voltage line.

[0013] Optionally, the driving circuit further includes a delay circuit, which is used to control the voltage on the gate turn-off voltage line to zero after a first preset time when the display panel is turned on and off; and to control the gate drive voltage line and the gate turn-off line signal to be short-circuited after a second preset time. The timing controller is used to detect the voltage on the working voltage line after the first preset time when the display panel is turned on and off; if the voltage on the working voltage line is less than or equal to a first potential and greater than a second potential, it controls the voltage on the gate turn-off voltage line to zero; and after the second preset time after the display panel is turned on and off, if the voltage on the working voltage line is less than or equal to a second potential, it controls the gate drive voltage line and the gate turn-off line signal to be short-circuited.

[0014] This application also discloses a display device, including a display panel and a driving circuit for the display panel, wherein the driving circuit is used to drive the display panel to display.

[0015] This application divides the period from the start-up to the complete shutdown of the display panel into two stages. The first stage is when the voltage on the operating voltage line drops to a first potential and then to a second potential. The second stage is when the voltage on the operating voltage line drops from the second potential to zero. In the first stage, the voltage on the control gate turn-off line is set to zero, causing the potential on the gate turn-off line to rapidly discharge from a negative potential to 0. In the second stage, the control gate turn-off line is connected to the gate start-up line, causing the voltage on the gate turn-off line to be pulled up by the voltage on the gate start-up line, reaching a level higher than the threshold voltage of the thin-film transistor, thus turning on the thin-film transistors in the display panel and eliminating residual charge in the pixel capacitors of the display panel. During this process, because the potential on the gate turn-off line is rapidly raised from a negative potential to 0 in the first stage, the gate start-up voltage can rapidly raise the potential on the gate turn-off line to a level greater than the threshold voltage of the thin-film transistor in the second stage. On the one hand, when the gate start-up line and the gate turn-off line are connected, the potential of the gate turn-off line has already been raised from a negative potential to a zero potential, making the potential rise on the gate turn-off line more rapid. Moreover, compared to the scheme of raising the gate turn-off line from a negative potential to a positive potential, this reduces the attenuation of the gate start-up voltage signal. On the other hand, because the gate start-up voltage signal attenuates less, the potential on the gate turn-off line remains above the threshold voltage for a longer period, resulting in more complete charge release from the pixel capacitor. Based on the above, by controlling the gate drive circuit to dissipate residual charge after power-off, the power-off ghosting is eliminated, and power-on flicker is avoided, preventing ghosting on the display panel and improving the display effect. Attached Figure Description

[0016] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0017] Figure 1 This is a schematic diagram of the driving circuit of the display panel of this application;

[0018] Figure 2 This is a timing diagram of the operating voltage signal of this application;

[0019] Figure 3 This is a schematic diagram of the driving circuit of the first embodiment of this application;

[0020] Figure 4This is a timing diagram of the gate start voltage signal and the gate turn off voltage signal of the display panel of this application;

[0021] Figure 5 This is a schematic diagram of the driving circuit according to the second embodiment of this application;

[0022] Figure 6 This is a schematic diagram of the display device of this application.

[0023] Among them, 100 is the display panel; 110 is the driving circuit; 120 is the power output circuit; 121 is the working voltage line; 122 is the gate start line; 123 is the gate turn-off line; 130 is the gate driving circuit; 140 is the timing controller; 151 is the first detection circuit; 152 is the first active switch; 153 is the first voltage comparator; 154 is the second voltage comparator; 155 is the second active switch; 156 is the third active switch; 200 is the display device; V1 is the first potential; V2 is the second potential; DV dd 1. Operating voltage signal; VGH, gate start voltage signal; VGL, gate turn-off voltage signal; VSS_EN, turn-off enable signal. Detailed Implementation

[0024] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0025] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature specified as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. Furthermore, terms indicating orientation or positional relationships, such as "upper," "lower," "left," "right," "vertical," and "horizontal," are described based on the orientation or relative positional relationships shown in the accompanying drawings and are only for the purpose of simplifying the description of this application, not indicating that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0026] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0027] Figure 1 This is a schematic diagram of the driving circuit of the display panel of this application. See also: Figure 1As shown, this application discloses a driving circuit 110 for a display panel 100. The driving circuit 110 includes a power output circuit 120, a gate driving circuit 130, and a timing controller 140. The power output circuit 120 is connected to at least a working voltage line 121, a gate start line 122, and a gate turn-off line 123, and is used to output a working voltage signal DV on the working voltage line 121. dd The gate enable voltage signal VGH is output on the gate enable line 122, and the gate disable voltage signal VGL is output on the gate disable line 123. The gate drive circuit 130 is connected to at least the working voltage line 121, the gate enable line 122, and the gate disable line 123, and is used to enable progressive scan under the control of the gate enable voltage signal VGH and disable scan under the control of the gate disable voltage signal VGL. The timing controller 140 is used to detect the voltage on the working voltage line 121 when the display panel 100 is enabled or disabled, and when the voltage on the working voltage line 121 is at a first potential V1, control the voltage on the gate disable voltage line to be set to zero, and output the gate disable voltage signal VGL on the working voltage line VGH. dd When the voltage is at the second potential V2, the gate drive voltage line and the gate turn-off line 123 are short-circuited; wherein, the first potential V1 is greater than the second potential V2.

[0028] This application divides the period from the start-up to the complete shutdown of the display panel 100 into two stages. The first stage is when the voltage on the operating voltage line 121 drops to a first potential V1 and then to a second potential V2. The second stage is when the voltage on the operating voltage line 121 drops from the second potential V2 to zero. In the first stage, the voltage on the control gate turn-off line 123 is set to zero, causing the potential on the gate turn-off line 123 to rapidly discharge from a negative potential to 0. In the second stage, the control gate turn-off line 123 is connected to the gate start-up line 122, causing the voltage on the gate turn-off line 123 to be pulled up by the voltage on the gate start-up line 122, reaching a level higher than the threshold voltage of the thin-film transistor, thus turning on the thin-film transistors in the display panel 100 and eliminating residual charge in the pixel capacitors of the display panel 100. During this process, because the potential on the gate turn-off line 123 is rapidly raised from a negative potential to 0 in the first stage, the gate start-up voltage can rapidly raise the potential on the gate turn-off line 123 to a level greater than the threshold voltage of the thin-film transistor in the second stage. On the one hand, when the gate start-up line 122 and the gate turn-off line 123 are connected, the potential of the gate turn-off line 123 has already been raised from a negative potential to a zero potential, making the potential rise on the gate turn-off line 123 more rapid. Moreover, compared to the scheme of raising the gate turn-off line 123 from a negative potential to a positive potential, the attenuation of the gate start-up voltage signal VGH is reduced. On the other hand, since the gate start-up voltage signal VGH attenuates less, the potential on the gate turn-off line 123 remains above the threshold voltage for a longer period, resulting in more complete discharge of charge in the pixel capacitor. Based on the above, by controlling the gate drive circuit 130 to dissipate residual charge after power-off, the power-off ghosting is eliminated and power-on flicker is avoided, preventing ghosting on the display panel 100 and improving the display effect of the display panel 100.

[0029] Specifically, the gate enable voltage signal VGH and the gate disable voltage signal VGL serve as the on-state and off-state voltages of the thin-film transistor, respectively. The potential of the gate enable voltage signal VGH is generally greater than 0V, and the potential of the gate disable voltage signal VGL is generally less than 0V. In the second stage described above, since the gate enable line 122 and the gate disable line 123 are short-circuited, the output of the power output circuit 120 is turned off. As the voltage on the gate enable line 122 gradually decreases from the potential of the gate enable voltage signal VGH to 0V, the gate disable line 123 is briefly boosted above the threshold voltage due to the interaction with the gate enable voltage signal VGH, causing the thin-film transistor to be turned on again and removing the residual charge in the pixel capacitor.

[0030] Comparatively, the gate turn-off voltage signal VGL on gate turn-off line 123 will also decay over time after power-off. However, since the absolute value of the gate turn-off voltage signal VGL is greater than that of the operating voltage signal DV...dd The potential. Therefore, even in the working voltage signal DV dd Even when the voltage is zeroed out, a gate turn-off voltage signal VGL still remains on the gate turn-off line 123. Furthermore, during the second stage, when the gate turn-off line 123 and the gate start-up line 122 are shorted, the gate start-up voltage on the gate start-up line 122 needs to raise the gate turn-off line 123 from a negative voltage state to the threshold voltage. The slower the potential on the gate turn-off line 123 reaches the threshold voltage, and the shorter the time the potential on the gate turn-off line 123 remains at the threshold voltage, the limited time the thin-film transistor is on is insufficient to completely remove the residual charge in the pixel capacitor.

[0031] Therefore, in this solution, in the first stage, the gate turn-off line 123 is directly grounded, causing the gate turn-off voltage on the gate turn-off line 123 to quickly reach zero. In the second stage, the potential on the gate turn-off line 123 is rapidly raised above the threshold voltage by the gate start-up voltage signal VGH, causing the thin-film transistor to turn on and remove the charge stored in the pixel capacitor or circuit. Furthermore, because the gate start-up voltage signal VGH decays slowly, the thin-film transistor conducts for a longer period, completely clearing any residual charge within the display panel 100. This eliminates ghosting during power-off and prevents screen flickering during the next power-on.

[0032] Figure 2 This is a timing diagram of the operating voltage signal of this application. See [link / reference]. Figure 2 As shown, this is the working voltage signal DV on the working voltage line 121. dd The potential drop diagram after the display panel 100 is powered off. Specifically, the operating voltage signal DV. dd Also known as digital operating voltage signal (DV) dd Digital operating voltage signal DV dd The power supply circuit 120 provides digital operating voltage to the source drive circuit, gate drive circuit 130, and other components in the drive circuit 110. When the display panel 100 is powered off, the power output circuit 120 stops outputting the operating voltage signal DV. dd The gate start-up voltage signal VGH and the gate turn-off voltage signal VGL are used, but the potentials on the working voltage line 121, the gate start-up line 122, and the gate turn-off line 123 gradually decrease, eventually dropping to 0V within a short time. Although the time is short, this solution can clear the residual charge in the pixel capacitor during this period, while saving the potential decay of the gate start-up voltage signal VGH.

[0033] Specifically, for the display panel 100 of this application, the gate turn-off voltage can be -8V, and the gate start-up voltage can be 30V. Relatively speaking, different designs of the display panel 100 may have different gate turn-off and gate start-up voltages. The solution of this application is also applicable to all display panels 100 and falls within the scope of protection of this application.

[0034] Specifically, the first potential V1 must be at least greater than the chip's undervoltage lockout potential. Undervoltage lockout, also known as undervoltage lockout (UVLO), is a circuit in electronic devices that cuts off the power supply when the power supply voltage is lower than the normal engineering level. In embedded systems, UVLO is often used to monitor battery voltage; if the voltage falls below a certain value, it will directly cut off the power supply to protect the circuit.

[0035] In this scheme, the digital working voltage signal DV dd The standard voltage is 3.3V, and the undervoltage lockout voltage is 1.6V. Therefore, the first voltage V1 must be at least greater than 1.6V, in the operating voltage signal DV. dd Before the voltage drops to 1.6V, the voltage on gate turn-off line 123 is raised to 0V. The operating voltage signal DV... dd After the voltage is reduced to 1.6V, the gate turn-off line 123 and the gate start-up line 122 are shorted. The gate start-up voltage signal VGH raises the voltage of the gate turn-off line 123 to above the threshold voltage, causing the thin-film transistor to turn on and release the residual charge.

[0036] Specifically, considering that it takes a certain amount of time for the gate turn-off line 123 to rise from a negative voltage to zero potential, it is also necessary to ground the gate turn-off line 123 before reaching 1.6V. For example, the operating voltage signal DV dd The voltage is 3.3V, the first potential V1 is 2.7V to 2V, and the second potential V2 is 1.6V.

[0037] Of course, since different display panels 100 use different types of thin-film transistors, the corresponding operating voltage signal DV will vary. dd There may be some differences. In this case, in this embodiment, the first potential V1 can be equal to the working voltage signal DV. dd The potential is 60% to 80% of the original potential, and the second potential V2 is equal to the chip undervoltage turn-off potential. This chip undervoltage turn-off potential is the same as the chip undervoltage turn-off potential of the gate driver chip.

[0038] Figure 3 This is a schematic diagram of the driving circuit of the first embodiment of this application, see below. Figure 3As shown, specifically, the timing controller 140 includes a first detection circuit 151 and a first active switch 152. The input terminal of the first active switch 152 is connected to the gate turn-off voltage, the output terminal of the first active switch 152 is grounded, and the control terminal of the first active switch 152 is connected to the first detection circuit 151. The first detection circuit 151 detects the operating voltage signal DV. dd When the potential is less than or equal to the first potential V1, the first active switch 152 is turned on.

[0039] In this scheme, by setting a first active switch 152 in the timing controller 140, under the control of the first detection circuit 151, the gate turn-off line 123 is connected to the ground, thereby raising the potential on the gate turn-off line 123 to 0V.

[0040] It is understandable that the first detection circuit 151 detects the operating voltage signal DV dd Before the potential is less than or equal to the second potential V2, it is necessary to control the first active switch 152 to remain off so that the gate turn-off line 123 is no longer grounded. In the second stage, the gate start-up voltage signal VGH on the gate start-up line 122 is used to raise the potential of the gate turn-off line 123.

[0041] The process of raising the potential of the gate turn-off line 123 by the gate start-up voltage signal VGH on the gate start-up line 122 is also known as the XON function. The XON function is activated when the display panel 100 is turned off, and the gate start-up line 122 and the gate turn-off line 123 are shorted by the shift register circuit in the gate drive circuit 130.

[0042] Figure 4 This is a timing diagram of the gate enable voltage signal and gate disable voltage signal of the display panel of this application. See details below. Figure 4 As shown, the horizontal axis represents time, and the starting point of time is after the display panel 100 is turned off, i.e., the working voltage signal DV. dd A schematic diagram showing the potential of the gate start signal and the gate turn-off signal gradually decreasing to 0V.

[0043] In the first stage, the potential on the gate turn-off line 123 rises from a negative voltage to 0V. At this time, the potential on the gate start-up line 122 declines because there is no continuous output of the gate start-up voltage signal VGH from the power output circuit 120. However, the decline is limited and remains far above the threshold voltage. In the second stage, the potential on the gate turn-off line 123 is pulled up by the potential on the gate start-up line 122. During this pull-up process, the potential on the gate start-up line 122 continuously decreases, and when the potentials on the gate turn-off line 123 and the gate start-up line 122 are aligned, the potentials on both lines decrease synchronously, eventually reaching 0V. During the period when the gate turn-off line 123 is raised above the threshold voltage, the thin-film transistor turns on, releasing residual charge.

[0044] It is worth mentioning that the rate of voltage drop on the gate startup line 122 in the second stage is also related to the capacitance on the gate shutdown line 123. Generally, reducing the output capacitance on the gate shutdown line 123 can reduce the energy of the gate shutdown voltage signal VGL, thereby reducing the rate of voltage drop on the gate startup line 122. However, reducing the output capacitance will also introduce ripple. In this solution, the potential on the gate shutdown line 123 is directly raised to 0V using the grounding line in the first stage, saving the charge loss on the gate startup line 122. Therefore, this application does not need to reduce the output capacitance on the gate shutdown line 123.

[0045] Specifically, the first detection circuit 151 includes a first voltage comparator 153, which has a first input terminal and a second input terminal. The first input terminal is connected to the operating voltage line 121, and the second input terminal is set to a first potential V1. When the first input terminal is lower than or equal to the second input terminal, the first detection circuit 151 inputs a control signal to turn on the first active switch 152, thereby grounding the gate turn-off line 123 in the first stage. In other words, when the potential on the operating voltage line 121 is less than or equal to the first potential V1, the gate turn-off line 123 is grounded; when the potential on the operating voltage line 121 is greater than the first potential V1, the gate turn-off line 123 is disconnected from ground.

[0046] To ensure that the gate turn-off line 123 is no longer grounded in the second stage and needs to be shorted to the gate start-up line 122, this solution further includes a second voltage comparator 154, a second active switch 155, and a third active switch 156. Specifically, the first detection circuit 151 also includes a second voltage comparator 154, a second active switch 155, and a third active switch 156. The second voltage comparator 154 has a third input terminal and a fourth input terminal. The third input terminal is connected to the working voltage line 121, and the fourth input terminal is set to a second potential V2. When the first input terminal is lower than or equal to the second input terminal, it outputs a high level; when the first input terminal is higher than the second input terminal, it outputs a low level.

[0047] The second active switch 155 is a P-type active switch, and the third active switch 156 is an N-type active switch. The control terminals of the second active switch 155 and the third active switch 156 are respectively connected to the output terminal of the second voltage comparator 154. The input terminal of the second active switch 155 is grounded, and the output terminal of the second active switch 155 is connected to the input terminal of the first active switch 152. The output terminal of the first active switch 152 is connected to the gate turn-off line 123. The input terminal of the third active switch 156 is connected to the gate start-up line 122, and the output terminal of the third active switch 156 is connected to the input terminal of the first active switch 152.

[0048] When the working voltage signal DV dd When the voltage is greater than the second potential V2, the second voltage comparator 154 outputs a low level. At this time, the second active switch 155 is turned on, and the third active switch 156 is turned off, indicating that the system is still in the first stage. When the operating voltage signal DV... dd When the voltage is less than or equal to the second potential V2, the second voltage comparator 154 outputs a high level. At this time, the second active switch 155 is turned off, and the third active switch 156 is turned on, realizing the connection between the gate start line 122 and the gate turn-off line 123.

[0049] In one embodiment, the timing controller 140 further includes a first control circuit, which controls the first detection circuit 151 to start when the display panel 100 is turned on or off, and to detect the operating voltage signal DV. dd The potential is detected, and when the display panel 100 is in a closed state or an open state, the first detection circuit 151 is controlled to remain in a non-operating state. The first detection circuit 151 is controlled by the first control circuit to avoid the first detection circuit 151 starting and misjudging when the display panel 100 is working normally. The first detection circuit 151 is only controlled to start when the display panel 100 is turned off. This first control circuit can be implemented internally by the timing controller 140.

[0050] Figure 5 This is a schematic diagram of the driving circuit of the second embodiment of this application, see below. Figure 5 As shown, in addition to the above-mentioned method of grounding the gate turn-off line 123 and raising the potential on the gate turn-off line 123 in the first stage, another method can be used by changing the output to the gate turn-off line 123.

[0051] Specifically, the gate turn-off voltage includes a first turn-off voltage and a second turn-off voltage. The power supply output voltage outputs the first turn-off voltage when the display panel 100 is in the working state, and outputs the second turn-off voltage when the display panel 100 is turned on and off. The first turn-off voltage is less than 0V, and the second turn-off voltage is equal to 0V.

[0052] The power output circuit 120 outputs a negative voltage power signal (VSS) to the level shifter IC in the gate drive circuit 130, and the level shifter IC outputs a gate turn-off signal to the gate start line 122. The gate drive circuit 130 includes multiple level shifter circuits to enable multiple scan lines in the display panel 100 to turn on line by line. The gate turn-off signal output by the level shifter circuit is provided by the negative voltage power signal provided by the power output voltage.

[0053] When the display panel 100 is powered off, the timing controller 140 detects that the potential on the operating voltage line 121 has dropped to the second potential V2, and sends a gate turn-off voltage signal VGL to the power output circuit 120, by setting the negative voltage power signal to 0V and outputting it to the shift register circuit. In other words, when the timing controller 140 detects that the voltage on the operating voltage line 121 is at the first potential V1, it outputs the gate turn-off voltage signal VGL to the power output circuit 120, and after receiving the gate turn-off voltage signal VGL, the power output circuit 120 outputs a second turn-off voltage to the gate turn-off voltage line.

[0054] In another embodiment, the present solution may further include a delay circuit to implement the first stage and the second stage. Specifically, the driving circuit 110 further includes a delay circuit, which is used to control the voltage on the gate turn-off voltage line to zero after a first preset time when the display panel 100 is turned on and off; and after a second preset time, control the gate driving voltage line and the gate turn-off line 123 signal to be short-circuited.

[0055] However, considering that different display panels 100 of the same type may have subtle differences, namely that different thin-film transistors may have different thresholds and operating voltage signals DV dd The size, descent speed after shutdown, and other parameters differ. This application can control these differences using the aforementioned first detection circuit 151.

[0056] Specifically, the timing controller 140 is used to detect the voltage on the working voltage line 121 after a first preset time when the display panel 100 is turned on and off; if the voltage on the working voltage line 121 is less than or equal to the first potential V1 and greater than the second potential V2, the controller controls the voltage on the gate turn-off voltage line to be set to zero; after a second preset time after the display panel 100 is turned on and off, if the voltage on the working voltage line 121 is less than or equal to the second potential V2, the controller controls the gate drive voltage line and the gate turn-off line 123 signal to be short-circuited.

[0057] Figure 6 This is a schematic diagram of the display device of this application, see below. Figure 6 As shown, this application discloses a display device. The display device 200 includes a driving circuit 110 for the display panel 100 mentioned in any of the above embodiments and a display panel 100. The driving circuit 110 is used to drive the display panel 100 to display. The display panel 100 can be various types of display panels 100, such as TN (Twisted Nematic) display panel 100, IPS (In-Plane Switching) display panel 100, VA (Vertical Alignment) display panel 100, and MVA (Multi-Domain Vertical Alignment) display panel 100. All of these can be adapted to the above solutions.

[0058] This application divides the period from the start-up to the complete shutdown of the display panel 100 into two stages. In the first stage, the voltage on the control gate turn-off line 123 is set to zero, causing the potential on the gate turn-off line 123 to rapidly discharge from a negative potential to 0 potential. In the second stage, the control gate turn-off line 123 is connected to the gate start-up line 122, causing the voltage on the gate turn-off line 123 to be pulled up by the voltage on the gate start-up line 122, reaching a level higher than the threshold voltage of the thin-film transistor, thus turning on the thin-film transistor in the display panel 100 and eliminating residual charge in the pixel capacitors of the display panel 100. During this process, because the potential on the gate turn-off line 123 is rapidly raised from a negative potential to 0 potential in the first stage, the gate start-up voltage can rapidly raise the potential on the gate turn-off line 123 to a level greater than the threshold voltage of the thin-film transistor in the second stage. On one hand, when the gate start-up line 122 and the gate turn-off line 123 are connected, the potential of the gate turn-off line 123 has already been raised from a negative potential to a zero potential, making the potential rise on the gate turn-off line 123 more rapid. Furthermore, compared to the scheme of raising the gate turn-off line 123 from a negative potential to a positive potential, this reduces the attenuation of the gate start-up voltage signal VGH. On the other hand, because the gate start-up voltage signal VGH attenuates less, the potential on the gate turn-off line 123 remains above the threshold voltage for a longer period, resulting in more complete charge release from the pixel capacitor. Based on these factors, the shutdown ghosting is eliminated and the startup flicker is avoided.

[0059] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0060] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A driving circuit for a display panel, characterized in that, The driving circuit includes: The power output circuit is connected to at least a working voltage line, a gate start-up line, and a gate turn-off line, and is used to output a working voltage signal on the working voltage line, a gate start-up voltage signal on the gate start-up line, and a gate turn-off voltage signal on the gate turn-off line. A gate drive circuit, at least connected to the operating voltage line, the gate start line, and the gate turn-off line, is used to enable progressive scanning under the control of the gate start voltage signal and to disable scanning under the control of the gate turn-off voltage signal; and A timing controller is used to detect the voltage on the working voltage line when the display panel is turned on or off, and when the voltage on the working voltage line is at a first potential, control the voltage on the gate turn-off voltage line to be set to zero, and when the working voltage signal is at a second potential, control the gate start line and the gate turn-off line signals to be short-circuited. Wherein, the first potential is greater than the second potential; The timing controller includes a first detection circuit and a first active switch; The input terminal of the first active switch is connected to the gate turn-off voltage, the output terminal of the first active switch is grounded, and the control terminal of the first active switch is connected to the first detection circuit. When the first detection circuit detects that the potential of the working voltage signal is less than or equal to the first potential, it controls the first active switch to turn on. The first detection circuit includes a first voltage comparator, which has a first input terminal and a second input terminal. The first input terminal is connected to the working voltage line, and the second input terminal is set to a first potential. When the first input terminal is lower than or equal to the second input terminal, the first detection circuit inputs a control signal to turn on the first active switch, thereby grounding the gate turn-off line in the first stage. The first detection circuit further includes a second voltage comparator, a second active switch, and a third active switch. The second voltage comparator has a third input terminal and a fourth input terminal. The third input terminal is connected to the working voltage line, and the fourth input terminal is set to a second potential. The second active switch is a P-type active switch, and the third active switch is an N-type active switch. The control terminals of the second and third active switches are respectively connected to the output terminals of the second voltage comparator. The input terminal of the second active switch is grounded, and the output terminal of the second active switch is connected to the input terminal of the first active switch. The output terminal of the first active switch is connected to the gate turn-off line. The input terminal of the third active switch is connected to the gate start-up line, and the output terminal of the third active switch is connected to the input terminal of the first active switch. When the operating voltage signal is greater than the second potential, the second voltage comparator outputs a logic low level, the second active switch is turned on, and the third active switch is turned off. When the operating voltage signal is less than or equal to the second potential, the second voltage comparator outputs a logic high level, the second active switch is turned off, and the third active switch is turned on, thereby connecting the gate start line and the gate turn-off line.

2. The driving circuit for the display panel according to claim 1, characterized in that, The first potential is equal to 60% to 80% of the potential of the operating voltage signal, and the second potential is equal to the potential at which the chip is undervoltage shut off.

3. The driving circuit for the display panel according to claim 1, characterized in that, The operating voltage signal is 3.3V, the first potential is 2.7V to 2V, and the second potential is 1.6V.

4. The driving circuit for the display panel according to claim 1, characterized in that, The potential of the gate turn-off voltage is less than 0V, and the potential of the gate turn-on voltage is greater than 0V. The gate turn-off voltage is -8V, and the gate turn-on voltage is 30V.

5. The driving circuit for the display panel according to claim 1, characterized in that, The timing controller further includes a first control circuit. When the display panel is turned on or off, the first control circuit controls the first detection circuit to start and detect the potential of the working voltage signal. When the display panel remains off or on, the first detection circuit is controlled to remain inactive.

6. The driving circuit for the display panel according to claim 1, characterized in that, The gate turn-off voltage includes a first turn-off voltage and a second turn-off voltage. The power supply output voltage outputs the first turn-off voltage when the display panel is in working state and outputs the second turn-off voltage when the display panel is turned on and off. The first turn-off voltage is less than 0V and the second turn-off voltage is equal to 0V.

7. The driving circuit for the display panel according to claim 6, characterized in that, When the timing controller detects that the voltage on the working voltage line is at the first potential, it outputs a shutdown enable signal to the power output circuit. After receiving the shutdown enable signal, the power output circuit outputs a second shutdown voltage to the gate shutdown voltage line.

8. The driving circuit for the display panel according to claim 1, characterized in that, The driving circuit further includes a delay circuit, which is used to control the voltage on the gate turn-off voltage line to zero after a first preset time when the display panel is turned on and off; and to control the gate start-up line and the gate turn-off line signals to be short-circuited after a second preset time. The timing controller is used to detect the voltage on the working voltage line after a first preset time when the display panel is turned on and off. If the voltage on the working voltage line is less than or equal to the first potential and greater than the second potential, the controller controls the voltage on the gate turn-off voltage line to be set to zero. After a second preset time following the start-up and shutdown of the display panel, if the voltage on the working voltage line is less than or equal to the second potential, the gate start-up line and the gate turn-off line signals are short-circuited.

9. A display device, characterized in that, The device includes a display panel and a driving circuit for the display panel according to any one of claims 1-8, wherein the driving circuit is used to drive the display panel to display.

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