Implementation method of a PCIE communication link with a quadrature architecture

Abstract

A method for implementing an orthogonal architecture PCIe communication link, relating to the field of PCIe communication, is implemented based on a PSE packet switching device, including 3 rear expansion cards and 9 front expansion cards. The rear expansion cards employ a COME module, using 3 PCIe-x4 data links and 6 PCIe switch chips, with the 6 PCIe switch chips connected to orthogonal connectors L1 to L9 respectively. The front expansion cards use 2 PCIe switch chips, connected to orthogonal connectors SW1 to SW3 respectively. By configuring the PCIe switch chips, the front expansion cards in slots L1 to L9 select one PCIe-x4 communication link from the rear expansion cards in slots SW1 to SW3, thus establishing a PCIe communication link from the 3 rear expansion cards to the 9 front expansion cards, thereby meeting the PCIe communication link requirements between multiple cards in an orthogonal architecture.

Description

Technical Field

[0001] This invention relates to the field of PCIe communication, and in particular to a method for implementing an orthogonal PCIe communication link. Background Technology

[0002] In existing technologies, the PCIe communication link is single and unadjustable, which is determined by the technical characteristics of PCIe.

[0003] An orthogonal PCIe communication link refers to a PCIe communication link implemented using an orthogonal design. This type of communication link uses a backplane-less, direct-connection coupling method with orthogonal connectors. Compared to the traditional backplane architecture, devices using an orthogonal PCIe communication link do not need to run traces across the backplane, resulting in higher transmission rates. It overcomes the line rate bottleneck of the traditional backplane architecture, avoids the signal attenuation and delay problems of the traditional backplane architecture, and has higher transmission rates and better performance.

[0004] The orthogonal architecture PCIe communication link is a very flexible and configurable architecture. However, because the PCIe communication link is single and cannot be adjusted, it cannot meet the complex and variable requirements of the PCIe communication link under the orthogonal architecture and the PCIe communication needs of multiple boards in the orthogonal architecture. Summary of the Invention

[0005] To address the issue of a single PCIe communication link in orthogonal architecture, this invention provides a method for implementing PCIe communication links in orthogonal architecture. By using a COME module and a PCIe switch chip, and by switching the PCIe switch chip to different paths according to different slots, the connection of PCIe communication links for multiple boards in orthogonal architecture is achieved.

[0006] A method for implementing an orthogonal architecture PCIe communication link, the method being based on a PSE packet switching device, comprising 3 rear insert cards and 9 front insert cards. The rear insert cards use a COME module and are equipped with a PI3PCIE3413 PCIe switch chip; the front insert cards are equipped with a PI3PCIE3413 PCIe switch chip.

[0007] Step 1: The rear-mounted card uses a COME module and employs three PCIe-x4 data links, including three PCIe-TX<3..0> and three PCIe-RX<3..0>.

[0008] Step 2: The rear insertion card uses 6 PCIe switch chips, of which 3 are connected to PCIe-TX<3..0> and 3 are connected to PCIe-RX<3..0>;

[0009] Step 3: The six PCIe switch chips of the rear insert card are respectively connected to the L1 to L9 orthogonal connectors, corresponding to the front insert cards of the L1 to L9 slots of the PSE packet switching equipment. The rear insert card has nine PCIe-X4 communication links.

[0010] Step 4: The front insert card uses two PCIe switch chips, which are respectively connected to the orthogonal connectors SW1 to SW3, corresponding to the rear insert cards in slots SW1 to SW3 of the PSE packet switching equipment;

[0011] Step 5: For the front insert cards in slots L1 to L9, select one PCIE-X4 communication link from the rear insert cards in slots SW1 to SW3, and set a PCIE switch chip to establish a PCIE communication link between the rear insert cards in slots SW1 to SW3 and the front insert cards in slots L1 to L9.

[0012] Through the above steps, the PCIe communication link from 3 rear expansion cards to 9 front expansion cards under the orthogonal architecture was established;

[0013] The PCIe switch chip is model PI3PCIE3413.

[0014] For the front-mounted cards in slots L1 to L9 mentioned in step 5, select one PCIe-x4 communication link for the rear-mounted cards in slots SW1 to SW3, and configure the PCIe switch chip as follows:

[0015] Step 5-1: The two PCIe switch chips of the front insert card in slot L1 select the AB communication path. At the same time, the first and second PCIe switch chips of the rear insert card in slot SW1 select the AB communication path to establish the PCIe communication link between the rear insert card in slot SW1 and the front insert card in slot L1.

[0016] Step 5-2: The two PCIe switch chips of the front insert card in slot L2 are selected to select the AB communication path. At the same time, the third and fourth PCIe switch chips of the rear insert card in slot SW1 are used to select the AB communication path for establishing the PCIe communication link between the rear insert card in slot SW1 and the front insert card in slot L2.

[0017] Step 5-3: The two PCIe switch chips of the front insert card in slot L3 are selected to select the AB communication path. At the same time, the 5th and 6th PCIe switch chips of the rear insert card in slot SW1 are used to select the AB communication path for establishing the PCIe communication link between the rear insert card in slot SW1 and the front insert card in slot L3.

[0018] Step 5-4: The two PCIe switch chips of the front insert card in slot L4 select the AC communication path, and the first and second PCIe switch chips of the rear insert card in slot SW2 select the AC communication path for establishing the PCIe communication link between the rear insert card in slot SW2 and the front insert card in slot L4.

[0019] Step 5-5: The two PCIe switch chips of the front insert card in slot L5 select the AC communication path, and the third and fourth PCIe switch chips of the rear insert card in slot SW2 select the AC communication path for establishing the PCIe communication link between the rear insert card in slot SW2 and the front insert card in slot L5.

[0020] Steps 5-6: The two PCIe switch chips of the front insert card in slot L6 select the AC communication path, and the 5th and 6th PCIe switch chips of the rear insert card in slot SW2 select the AC communication path for establishing the PCIe communication link between the rear insert card in slot SW2 and the front insert card in slot L6.

[0021] Steps 5-7: The two PCIe switch chips of the front insert card in slot L7 select the AD communication path, and the first and second PCIe switch chips of the rear insert card in slot SW3 select the AD communication path for establishing the PCIe communication link between the rear insert card in slot SW3 and the front insert card in slot L7.

[0022] Steps 5-8: The two PCIe switch chips of the front insert card in slot L8 select the AD communication path, and the third and fourth PCIe switch chips of the rear insert card in slot SW3 select the AD communication path for establishing the PCIe communication link between the rear insert card in slot SW3 and the front insert card in slot L8.

[0023] Steps 5-9: The two PCIe switch chips of the front insert card in slot L9 select the AD communication path. At the same time, the 5th and 6th PCIe switch chips of the rear insert card in slot SW3 select the AD communication path to establish the PCIe communication link between the rear insert card in slot SW3 and the front insert card in slot L9.

[0024] (1) The connection of PCIe communication links of multiple boards under the orthogonal architecture was realized, which solved the problem of single PCIe communication link under the orthogonal architecture.

[0025] (2) By using a PCIE switch chip, a complex and dynamically adjustable PCIE data link can be built. All rear and front plug-in cards are designed in the same way. The complex PCIE data link can be realized by dynamic configuration, which saves design costs.

[0026] (3) Compared with the existing technology, the establishment of PCIE links is more flexible and comprehensive. This invention only uses the SW1 to SW3 slot cards, and can be upgraded to use the SW4 to SW6 slot cards to build more PCIE communication links. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of this invention, the invention will be further described below with reference to the accompanying drawings.

[0028] Figure 1 A block diagram showing the connection between the rear-mounted card's COME module and the PCIe switch chip;

[0029] Figure 2 A block diagram showing the connection between the PCIe switch chip of the rear expansion card and the quadrature connectors L1 to L9;

[0030] Figure 3 A block diagram showing the connection between the front-mount card's PCIe switch chip and the quadrature connectors SW1 to SW3;

[0031] Figure 4 The circuit diagram shows the PCIe switch chip for the rear-mounted card in slot SW1.

[0032] Figure 5 The circuit diagram shows the PCIe switch chip for the rear-mounted card in slot SW2.

[0033] Figure 6 The circuit diagram shows the PCIe switch chip for the rear-mounted card in slot SW3.

[0034] Figure 7 The circuit diagram shows the PCIe switch chip for the front-mounted card in slots L1, L2, and L3.

[0035] Figure 8 The circuit diagram shows the PCIe switch chip for the front-mounted card in slots L4, L5, and L6.

[0036] Figure 9 This is a circuit diagram of the PCIe switch chip in slots L7, L8, and L9 of the front-mounted card. Detailed Implementation

[0037] The present invention will now be explained in detail with reference to the accompanying drawings.

[0038] Orthogonal architecture devices are typically divided into front-mount cards and rear-mount cards. The method described in this invention is based on PSE packet switching equipment. The rear-mount card uses a COME module and is equipped with a PI3PCIE3413 PCIE switch chip. The front-mount card is equipped with a PI3PCIE3413 PCIE switch chip and can communicate with any slave device that has PCIE communication functionality.

[0039] This solution is based on a PSE packet-switching orthogonal architecture device, which can have up to 9 front-mounted cards, named L1 to L9, and up to 6 rear-mounted cards, named SW1 to SW6. Each slot's front-mounted card has a connector to connect to the 6 rear-mounted cards, named SW1 to SW6. These connectors can be connected to the SW1 to SW6 rear-mounted cards simultaneously. Similarly, each slot's rear-mounted card has a connector to connect to the front-mounted cards, named L1 to L9. These connectors can be connected to the L1 to L9 front-mounted cards simultaneously.

[0040] The L1 slot front insert card has SW1 to SW6 connectors, which connect to the L1 connectors of the SW1 to SW6 slot rear insert cards respectively; the L2 slot front insert card has SW1 to SW6 connectors, which connect to the L2 connectors of the SW1 to SW6 slot rear insert cards respectively; the L3 slot front insert card has SW1 to SW6 connectors, which connect to the L3 connectors of the SW1 to SW6 slot rear insert cards respectively; the L4 slot front insert card has SW1 to SW6 connectors, which connect to the L4 connectors of the SW1 to SW6 slot rear insert cards respectively; the L5 slot front insert card has SW1 to SW6 connectors, which connect to... The L5 connectors for the rear insert cards in slots SW1 to SW6 are connected to the L6 connectors for the front insert cards in slots L6; the L7 front insert card has SW1 to SW6 connectors, which are connected to the L7 connectors for the rear insert cards in slots SW1 to SW6; the L8 front insert card has SW1 to SW6 connectors, which are connected to the L8 connectors for the rear insert cards in slots SW1 to SW6; the L9 front insert card has SW1 to SW6 connectors, which are connected to the L9 connectors for the rear insert cards in slots SW1 to SW6.

[0041] The above describes all the connection relationships for this orthogonal architecture device. However, for the PCIE communication link in this invention, only the SW1 slot rear insert card to the SW3 slot rear insert card are needed.

[0042] Figure 1 This is a block diagram showing the connection between the rear-mounted card's COME module and the PCIe switch chip (referred to as PCIe switch in each diagram). Figure 1The COME module uses three PCIe-x4 data links. The PCIe-TX<3..0> link of the first PCIe-x4 data link is connected to port A of the first PCIe switch chip, and the PCIe-RX<3..0> link of the first PCIe-x4 data link is connected to port A of the second PCIe switch chip. The PCIe-TX<3..0> link of the second PCIe-x4 data link is connected to port A of the third PCIe switch chip, and the PCIe-RX<3..0> link of the second PCIe-x4 data link is connected to port A of the fourth PCIe switch chip. The PCIe-TX<3..0> link of the third PCIe-x4 data link is connected to port A of the fifth PCIe switch chip, and the PCIe-RX<3..0> link of the third PCIe-x4 data link is connected to port A of the sixth PCIe switch chip.

[0043] Figure 2 This is a block diagram illustrating the connection between the PCIe switch chips of the rear expansion card and the quadrature connectors L1 to L9, describing the connection relationships between them. The first PCIe switch chip has its B port connected to the PCIe-TX<3..0> connector of L1, its C port connected to the PCIe-TX<3..0> connector of L4, and its D port connected to the PCIe-TX<3..0> connector of L7; the second PCIe switch chip has its B port connected to the PCIe-RX<3..0> connector of L1, its C port connected to the PCIe-RX<3..0> connector of L4, and its D port connected to the PCIe-RX<3..0> connector of L7; the third PCIe switch chip has its B port connected to the PCIe-TX<3..0> connector of L2, its C port connected to the PCIe-TX<3..0> connector of L5, and its D port connected to the PCIe-TX<3..0> connector of L8. The fourth PCIe switch chip has its B port connected to the L2 connector's PCIe-RX<3..0>, its C port connected to the L5 connector's PCIe-RX<3..0>, and its D port connected to the L8 connector's PCIe-RX<3..0>; the fifth PCIe switch chip has its B port connected to the L3 connector's PCIe-TX<3..0>, its C port connected to the L6 connector's PCIe-TX<3..0>, and its D port connected to the L9 connector's PCIe-TX<3..0>; the sixth PCIe switch chip has its B port connected to the L3 connector's PCIe-RX<3..0>, its C port connected to the L6 connector's PCIe-RX<3..0>, and its D port connected to the L9 connector's PCIe-RX<3..0>.

[0044] On the rear-mount card, the first PCIe-x4 data link, after passing through the first and second PCIe switch chips, can be selected as either AB, AC, or AD, resulting in three selectable communication links. The second PCIe-x4 data link, after passing through the third and fourth PCIe switch chips, can also be selected as either AB, AC, or AD, again resulting in three selectable communication links. The third PCIe-x4 data link, after passing through the fifth and sixth PCIe switch chips, can also be selected as either AB, AC, or AD, again resulting in three selectable communication links. In total, the rear-mount card has nine PCIe-x4 communication links.

[0045] Figure 3 This is a block diagram illustrating the connection between the front expansion card's PCIe switch chip and the quadrature connectors SW1 to SW3, describing the connection relationship between the front expansion card's PCIe switch chip and the quadrature connectors SW1 to SW3. The B port of the first front expansion card's PCIe switch chip is connected to the PCIe-TX<3..0> connector of SW1, the C port is connected to the PCIe-TX<3..0> connector of SW2, and the D port is connected to the PCIe-TX<3..0> connector of SW3. The B port of the second front expansion card's PCIe switch chip is connected to the PCIe-RX<3..0> connector of SW1, the C port is connected to the PCIe-RX<3..0> connector of SW2, and the D port is connected to the PCIe-RX<3..0> connector of SW3.

[0046] Figure 4 This diagram shows the conduction path of the PCIe switch chips when the card is installed in slot SW1. In slot SW1, PCIe switch chips 1 through 6 are all configured with an AB conduction path.

[0047] Figure 5 This diagram shows the conduction path of the PCIe switch chips when the back-mounted card is in slot SW2. In slot SW2, all PCIe switch chips (numbers 1-6) are configured for AC conduction.

[0048] Figure 6 This diagram shows the conduction path of the PCIe switch chips when the card is installed in slot SW3. In slot SW3, PCIe switch chips 1 through 6 are all configured for AD (Advanced Driver Assist) conduction.

[0049] Figure 7This diagram shows the conduction path of the PCIe switch chips in slots L1, L2, and L3 of the front-mounted card. It illustrates the conduction links of the PCIe switch chips when the front-mounted card is in slots L1, L2, and L3. In slots L1, L2, and L3, the first and second PCIe switch chips are both configured with an AB conduction path.

[0050] Figure 8 This diagram shows the conduction path of the PCIe switch chips in slots L4, L5, and L6 of the front-mounted card. When the card is in slots L4, L5, and L6, the first and second PCIe switch chips are both configured for AC conduction.

[0051] Figure 9 This diagram shows the conduction path of the PCIe switch chips in slots L7, L8, and L9 of the front-mounted card. It illustrates the conduction links of the PCIe switch chips when the front-mounted card is in slots L7, L8, and L9. In slots L7, L8, and L9, the first and second PCIe switch chips are both configured as AD (Advanced Driver Assist) chips.

[0052] The present invention relates to a PCIe communication link under an orthogonal architecture, according to Figures 1-3 Connect according to the connection relationship, and according to different slots... Figures 4-9 By configuring the PCIe switch chip to establish the PCIe communication link, three rear expansion cards can be used to establish a PCIe communication link to nine front expansion cards.

[0053] The following explains in detail the process of establishing PCIe communication links between 3 rear expansion cards and 9 front expansion cards.

[0054] The rear expansion card located in slot SW1 has its PCIe communication link connected to the front expansion cards located in slots L1, L2, and L3. The specific PCIe communication link is as follows: the first PCIe-X4 communication link of the COME module passes through the first and second PCIe switch chips (internal channels AB) of the rear expansion card, and then connects to the L1 connector. The L1 connector connects to the SW1 connector inside the chassis. The SW1 connector then passes through the first and second PCIe switch chips (internal channels AB) of the front expansion cards. This entire link establishes a communication link between the rear expansion card in slot SW1 and the front expansion card in slot L1. The second PCIe-X4 communication link of the COME module passes through the third and fourth PCIe switch chips (internal channels AB) of the rear expansion card, and then connects to the L2 connector. The L2 connector connects to the SW1 connector inside the chassis. The SW1 connector then passes through the first and second PCIe switch chips (internal channels AB) of the front expansion card. This entire link establishes a communication link between the rear expansion card in slot SW1 and the front expansion card in slot L2. The third PCIe-X4 communication link of the COME module passes through the fifth and sixth PCIe switch chips (internal channels AB) of the rear expansion card, and then connects to the L3 connector. The L3 connector connects to the SW1 connector inside the chassis. The SW1 connector then passes through the first and second PCIe switch chips (internal channels AB) of the front expansion card. This entire link establishes a communication link between the rear expansion card in slot SW1 and the front expansion cards in slots L1, L2, and L3. The entire process establishes PCIe communication links between the rear expansion card in slot SW1 and the front expansion cards in slots L1, L2, and L3.

[0055] The rear expansion card located in slot SW2 has its PCIe communication links simultaneously connected to the front expansion cards located in slots L4, L5, and L6. The specific PCIe communication links are as follows: The first PCIe communication link of the COME module passes through the first and second PCIe switch chips (internal channels are AC) of the rear expansion card, and then connects to the L4 connector. The L4 connector connects to the SW2 connector inside the chassis. The SW2 connector then passes through the first and second PCIe switch chips (internal channels are AC) of the front expansion cards. This entire link establishes a communication link between the rear expansion card in slot SW2 and the front expansion card in slot L4. The second PCIe communication link of the COME module passes through the third and fourth PCIe switch chips (internal channels are AC) of the rear expansion card, and then connects to the L5 connector. The L5 connector connects to the SW2 connector inside the chassis. The SW2 connector then passes through the first and second PCIe switch chips (internal channels are AC) of the front expansion cards. This entire link establishes a communication link between the rear expansion card in slot SW2 and the front expansion card in slot L5. The third PCIe communication link of the COME module passes through the 5th and 6th PCIe switch chips (internal channel AC) of the rear expansion card, and then connects to the L6 connector. The L6 connector connects to the SW2 connector inside the chassis. The SW2 connector passes through the 1st and 2nd PCIe switch chips (internal channel AC) of the front expansion card. This entire link establishes a communication link between the rear expansion card in slot SW2 and the front expansion card in slot L6. The above process establishes PCIe communication links between the rear expansion card in slot SW2 and the front expansion cards in slots L4, L5, and L6.

[0056] The rear expansion card located in slot SW3 has its PCIe communication links connected to the front expansion cards located in slots L7, L8, and L9. The specific PCIe communication links are as follows: The first PCIe communication link of the COME module passes through the first and second PCIe switch chips (internal channels of the switches are AD) on the rear expansion card, and then connects to the L7 connector. The L7 connector connects to the SW3 connector inside the chassis. The SW3 connector then passes through the first and second PCIe switch chips (internal channels of the switches are AD) on the front expansion cards. This entire link establishes a communication link between the rear expansion card in slot SW3 and the front expansion card in slot L7. The second PCIe communication link of the COME module passes through the third and fourth PCIe switch chips (internal channels of the switches are AD) on the rear expansion card, and then connects to the L8 connector. The L8 connector connects to the SW3 connector inside the chassis. The SW3 connector then passes through the first and second PCIe switch chips (internal channels of the switches are AD) on the front expansion cards. This entire link establishes a communication link between the rear expansion card in slot SW3 and the front expansion card in slot L8. The third PCIe communication link of the COME module passes through the 5th and 6th PCIe switch chips (internal channels of the switches are AD) on the rear expansion card. After passing through the PCIe switch chips, it connects to the L9 connector. The L9 connector is connected to the SW3 connector inside the chassis. The SW3 connector passes through the 1st and 2nd PCIe switch chips (internal channels of the switches are AD). The entire link establishes the communication link between the rear expansion card in the SW3 slot and the front expansion card in the L9 slot. The above process establishes the PCIe communication links between the rear expansion card in the SW3 slot and the front expansion cards in the L7, L8, and L9 slots.

[0057] The above description is merely a specific embodiment of the present invention. Designers can optimize or improve the invention based on the above examples without deviating from the technical solution.

Claims

1. A method for implementing an orthogonal architecture PCIe communication link, based on a PSE packet switching device, comprising 3 rear insertion cards and 9 front insertion cards, characterized in that, Step 1: The rear-mounted card uses a COME module and employs three PCIe-x4 data links, including three PCIe-TX<3..0> and three PCIe-RX<3..0>. Step 2: The rear insertion card uses 6 PCIe switch chips, of which 3 are connected to PCIe-TX<3..0> and 3 are connected to PCIe-RX<3..0>; Step 3: The six PCIe switch chips of the rear insert card are respectively connected to the L1 to L9 orthogonal connectors, corresponding to the front insert cards of the L1 to L9 slots of the PSE packet switching equipment. The rear insert card has nine PCIe-X4 communication links. Step 4: The front insert card uses two PCIe switch chips, which are respectively connected to the orthogonal connectors SW1 to SW3, corresponding to the rear insert cards in slots SW1 to SW3 of the PSE packet switching equipment; Step 5: For the front insert cards in slots L1 to L9, select one PCIE-X4 communication link from the rear insert cards in slots SW1 to SW3, and set a PCIE switch chip to establish a PCIE communication link between the rear insert cards in slots SW1 to SW3 and the front insert cards in slots L1 to L9. Through the above steps, the PCIe communication link from 3 rear expansion cards to 9 front expansion cards under the orthogonal architecture was established; The PCIe switch chip is model PI3PCIE3413; The six PCIe switch chips of the rear-mount card described in step 3 are respectively connected to the L1 to L9 quadrature connectors, specifically: the B port of the first PCIe switch chip is connected to the PCIe-TX<3..0> of the L1 connector, the C port is connected to the PCIe-TX<3..0> of the L4 connector, and the D port is connected to the PCIe-TX<3..0> of the L7 connector; the B port of the second PCIe switch chip is connected to the PCIe-RX<3..0> of the L1 connector, the C port is connected to the PCIe-RX<3..0> of the L4 connector, and the D port is connected to the PCIe-RX<3..0> of the L7 connector; the B port of the third PCIe switch chip is connected to the PCIe-TX<3..0> of the L2 connector, the C port is connected to the PCIe-TX<3..0> of the L5 connector, and the D port is connected to... The L8 connector's PCIe-TX<3..0> is connected to the L2 connector's PCIe-RX<3..0>, the C port is connected to the L5 connector's PCIe-RX<3..0>, and the D port is connected to the L8 connector's PCIe-RX<3..0>. The 5th PCIe switch chip's B port is connected to the L3 connector's PCIe-TX<3..0>, the C port is connected to the L6 connector's PCIe-TX<3..0>, and the D port is connected to the L9 connector's PCIe-TX<3..0>. The 6th PCIe switch chip's B port is connected to the L3 connector's PCIe-RX<3..0>, the C port is connected to the L6 connector's PCIe-RX<3..0>, and the D port is connected to the L9 connector's PCIe-RX<3..0>. The front-mount card described in step 4 uses two PCIe switch chips, which are connected to the orthogonal connectors SW1 to SW3 respectively. Specifically, the B port of the first PCIe switch chip of the front-mount card is connected to the PCIe-TX<3..0> of the SW1 connector, the C port is connected to the PCIe-TX<3..0> of the SW2 connector, and the D port is connected to the PCIe-TX<3..0> of the SW3 connector; the B port of the second PCIe switch chip of the front-mount card is connected to the PCIe-RX<3..0> of the SW1 connector, the C port is connected to the PCIe-RX<3..0> of the SW2 connector, and the D port is connected to the PCIe-RX<3..0> of the SW3 connector.

2. The method for implementing an orthogonal architecture PCIe communication link according to claim 1, characterized in that, The rear-mount card described in step 2 uses 6 PCIe switch chips, with 3 connected to PCIe-TX<3..0> and 3 connected to PCIe-RX<3..0>. Specifically, of the three PCIe-X4 data links of the COME module, the PCIe-TX<3..0> of the first PCIe-X4 data link is connected to port A of the first PCIe switch chip, and the PCIe-RX<3..0> of the first PCIe-X4 data link is connected to port A of the second PCIe switch chip; the second P... The PCIE-TX<3..0> CIE-X4 data link is connected to port A of the third PCIE switch chip; the PCIE-RX<3..0> of the second PCIE-X4 data link is connected to port A of the fourth PCIE switch chip; the PCIE-TX<3..0> of the third PCIE-X4 data link is connected to port A of the fifth PCIE switch chip; and the PCIE-RX<3..0> of the third PCIE-X4 data link is connected to port A of the sixth PCIE switch chip.

3. The method for implementing an orthogonal architecture PCIe communication link according to claim 1, characterized in that, The rear-mount card described in step 3 has nine PCIe-X4 communication links, namely: the first PCIe-X4 data link, after passing through the first and second PCIe switch chips, has three PCIe-X4 communication links: AB, AC, and AD; the second PCIe-X4 data link, after passing through the third and fourth PCIe switch chips, has three PCIe-X4 communication links: AB, AC, and AD; and the third PCIe-X4 data link, after passing through the fifth and sixth PCIe switch chips, has three PCIe-X4 communication links: AB, AC, and AD.

4. The method for implementing an orthogonal architecture PCIe communication link according to claim 1, characterized in that, For the front-mounted cards in slots L1 to L9 mentioned in step 5, select one PCIe-x4 communication link for the rear-mounted cards in slots SW1 to SW3, and configure the PCIe switch chip as follows: Step 5-1: The two PCIe switch chips of the front insert card in slot L1 select the AB communication path. At the same time, the first and second PCIe switch chips of the rear insert card in slot SW1 select the AB communication path to establish the PCIe communication link between the rear insert card in slot SW1 and the front insert card in slot L1. Step 5-2: The two PCIe switch chips of the front insert card in slot L2 are selected to select the AB communication path. At the same time, the third and fourth PCIe switch chips of the rear insert card in slot SW1 are used to select the AB communication path for establishing the PCIe communication link between the rear insert card in slot SW1 and the front insert card in slot L2. Step 5-3: The two PCIe switch chips of the front insert card in slot L3 are selected to select the AB communication path. At the same time, the 5th and 6th PCIe switch chips of the rear insert card in slot SW1 are used to select the AB communication path for establishing the PCIe communication link between the rear insert card in slot SW1 and the front insert card in slot L3. Step 5-4: The two PCIe switch chips of the front insert card in slot L4 select the AC communication path, and the first and second PCIe switch chips of the rear insert card in slot SW2 select the AC communication path for establishing the PCIe communication link between the rear insert card in slot SW2 and the front insert card in slot L4. Step 5-5: The two PCIe switch chips of the front insert card in slot L5 select the AC communication path, and the third and fourth PCIe switch chips of the rear insert card in slot SW2 select the AC communication path for establishing the PCIe communication link between the rear insert card in slot SW2 and the front insert card in slot L5. Steps 5-6: The two PCIe switch chips of the front insert card in slot L6 select the AC communication path, and the 5th and 6th PCIe switch chips of the rear insert card in slot SW2 select the AC communication path for establishing the PCIe communication link between the rear insert card in slot SW2 and the front insert card in slot L6. Steps 5-7: The two PCIe switch chips of the front insert card in slot L7 select the AD communication path, and the first and second PCIe switch chips of the rear insert card in slot SW3 select the AD communication path for establishing the PCIe communication link between the rear insert card in slot SW3 and the front insert card in slot L7. Steps 5-8: The two PCIe switch chips of the front insert card in slot L8 select the AD communication path, and the third and fourth PCIe switch chips of the rear insert card in slot SW3 select the AD communication path for establishing the PCIe communication link between the rear insert card in slot SW3 and the front insert card in slot L8. Steps 5-9: The two PCIe switch chips of the front insert card in slot L9 select the AD communication path. At the same time, the 5th and 6th PCIe switch chips of the rear insert card in slot SW3 select the AD communication path to establish the PCIe communication link between the rear insert card in slot SW3 and the front insert card in slot L9.

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