An internal power supply generation circuit, a memory chip, and an electronic device

Abstract

The application relates to the chip circuit technical field, and particularly discloses an internal power supply generation circuit, a storage chip and electronic equipment, wherein the internal power supply generation circuit comprises a switching module, a switching module, a negative feedback module, a first branch current module, a second branch current module, a third branch current module, a clamping module, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first resistor, a second resistor and a power supply output end; the fourth PMOS tube of the internal power supply generation circuit is directly connected to a power supply voltage, so that the internal power supply generation circuit does not need to rely on a current mirror to generate an output voltage, the size of an output current of the power supply output end is determined by a subsequent load and an output voltage connected to the power supply output end, unnecessary current generation is avoided, and the problem of excessive static current of the internal power supply generation circuit is effectively solved.

Description

Technical Field

[0001] This application relates to the field of chip circuit technology, and more specifically, to an internal power generation circuit, a memory chip, and an electronic device. Background Technology

[0002] As attached Figure 1 The diagram shows an existing internal power generation circuit. The internal power generation circuit generates an output voltage based on a current mirror. Under high voltage (when the supply voltage is high), the drain-source voltages of transistors P1 and P2 in the current mirror will differ significantly, resulting in a mismatch. This causes transistor P2 to output an excessive current, which in turn generates unnecessary current, leading to a problem of excessive static current in the internal power generation circuit.

[0003] There is currently no effective technical solution to the above problems. Summary of the Invention

[0004] The purpose of this application is to provide an internal power generation circuit, a memory chip, and an electronic device to avoid unnecessary current generation and solve the problem of excessive static current in the internal power generation circuit.

[0005] In a first aspect, this application provides an internal power generation circuit, which includes: a switching module, a negative feedback module, a first branch current module, a second branch current module, a third branch current module, a clamping module, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first resistor, a second resistor, and a power output terminal. One end of the first branch current module is connected to the power supply voltage, and the other end is connected to the gate of the first PMOS transistor and the source of the second PMOS transistor. The drain of the second PMOS transistor is grounded. The source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the gate of the third PMOS transistor, the gate of the second PMOS transistor and one end of the switching module, and the other end of the switching module is grounded through the first resistor; The source of the third PMOS transistor is connected to the power supply voltage through the second branch current module, the drain of the third PMOS transistor is connected to one end of the clamping module and the first end of the negative feedback module, and the other end of the clamping module is grounded. The second terminal of the negative feedback module is connected to the power supply voltage through the third branch current module and is connected to the gate of the fourth PMOS transistor. The third terminal of the negative feedback module is grounded through the second resistor. The source of the fourth PMOS transistor is connected to the power supply voltage, the drain of the fourth PMOS transistor is connected to the power output terminal and the fourth terminal of the negative feedback module, and the fourth terminal of the feedback module is grounded.

[0006] The internal power generation circuit of this application adjusts the output voltage of the power output terminal based on a clamping module and a negative feedback module, so that the output voltage can match the target output voltage or the supply voltage. In both cases, the output voltage of the power output terminal is modulated by changing the conduction capability by adjusting the gate voltage of the fourth PMOS transistor. The fourth PMOS transistor is directly connected to the supply voltage, so that the internal power generation circuit of this application does not need to rely on a current mirror to generate the output voltage. The output current of the power output terminal is determined by the connected downstream load and the output voltage, avoiding unnecessary current generation and effectively solving the problem of excessive static current in the internal power generation circuit.

[0007] The internal power generation circuit includes a clamping module comprising a first capacitor and a diode connected in parallel.

[0008] This diode is a Zener diode, which has a voltage stabilizing function and can stabilize the voltage output from its cathode within a certain voltage range. This allows the input voltage at the first terminal of the negative feedback module to be clamped to the magnitude of the target output voltage when the supply voltage is greater than the target output voltage. In this example, the first capacitor is used to reduce the ripple of the voltage output from the diode cathode, so as to make the voltage more stable.

[0009] The internal power generation circuit, wherein the negative feedback module includes a first NMOS transistor and a second NMOS transistor; The gate of the first NMOS transistor is the first terminal of the negative feedback module, the drain of the first NMOS transistor is the second terminal of the negative feedback module, the source of the first NMOS transistor is connected to the source of the second NMOS transistor and is the third terminal of the negative feedback module, the drain of the second NMOS transistor is connected to the power supply voltage, and the gate of the second NMOS transistor is the fourth terminal of the negative feedback module.

[0010] In this example, when the supply voltage is greater than the target output voltage, the clamping module clamps the gate voltage of the first NMOS transistor to the target output voltage. At this time, the fourth PMOS transistor, together with the first and second NMOS transistors of the negative feedback module, forms a negative feedback loop. When the output voltage at the power supply output terminal deviates, the first and second NMOS transistors can adjust the gate voltage of the fourth PMOS transistor according to the magnitude of the output voltage deviation, thereby changing the conduction capability of the fourth PMOS transistor and thus stabilizing the output voltage at the power supply output terminal to the target output voltage again.

[0011] The internal power generation circuit further includes a step-down module, which includes a fourth NMOS transistor and a fourth resistor. The drain of the fourth NMOS transistor is connected to the gate of the first NMOS transistor, the source of the fourth NMOS transistor is grounded through the fourth resistor, and the gate of the fourth NMOS transistor is grounded.

[0012] The internal power generation circuit further includes a charging module, which includes a third NMOS transistor and a third resistor. The drain of the third NMOS transistor is connected to the power supply voltage, the source of the third NMOS transistor is connected to the gate of the third PMOS transistor through the third resistor, and the gate of the third NMOS transistor is connected to the gate of the third PMOS transistor.

[0013] The internal power generation circuit includes a switching module comprising multiple enable switches connected in parallel.

[0014] The internal power generation circuit includes three enable switches, each controlled by a complementary PWM logic input signal and a running signal.

[0015] The internal power generation circuit further includes a fifth resistor, and the fourth terminal of the negative feedback module is grounded through the fifth resistor.

[0016] Secondly, this application also provides a memory chip, including an internal power generation circuit as provided in the first aspect.

[0017] Thirdly, this application also provides an electronic device, including an internal power generation circuit as provided in the first aspect or a memory chip as provided in the second aspect.

[0018] As can be seen from the above, this application provides an internal power generation circuit, a memory chip, and an electronic device. The internal power generation circuit adjusts the output voltage of the power output terminal based on a clamping module and a negative feedback module, so that the output voltage can match the target output voltage or the supply voltage. In both cases, the output voltage of the power output terminal is modulated by changing the conduction capability by adjusting the gate voltage of the fourth PMOS transistor. The fourth PMOS transistor is directly connected to the supply voltage, so that the internal power generation circuit of this application does not need to rely on a current mirror to generate the output voltage. The output current of the power output terminal is determined by the connected downstream load and the output voltage, avoiding unnecessary current generation and effectively solving the problem of excessive static current in the internal power generation circuit. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the existing internal power generation circuit.

[0020] Figure 2 This is a schematic diagram of the internal power generation circuit provided in an embodiment of this application.

[0021] Figure 3 A more detailed structural schematic diagram of the internal power generation circuit provided in the embodiments of this application.

[0022] Figure 4 Another schematic diagram of the internal power generation circuit provided in the embodiments of this application.

[0023] Reference numerals: 1. Switching module; 2. Negative feedback module; 3. First branch current module; 4. Second branch current module; 5. Third branch current module; 6. Clamping module; VCC, power supply voltage; HPM1, first PMOS transistor; HPM2, second PMOS transistor; HPM3, third PMOS transistor; HPM4, fourth PMOS transistor; R1, first resistor; R2, second resistor; VOUT, power output terminal; C1, first capacitor; D1, diode; HNM1, first NMOS transistor; HNM2, second NMOS transistor; NM3, third NMOS transistor; R3, third resistor; NM4, fourth NMOS transistor; R4, fourth resistor; R5, fifth resistor. Detailed Implementation

[0024] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0025] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0026] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0027] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0028] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0029] like Figure 1 The internal power generation circuit shown in the diagram has resistors R10 and R20, N1 and N2 as N-type transistors, and P1 and P2 as P-type transistors. The circuit starts operating when any of the corresponding enable switches (the three NMOS transistors connected in parallel below) are turned on. The current in the branch containing transistor P1 flows through the gate-source terminals of transistor N2 and resistor R20. Therefore, the output current of transistor P1 satisfies: I P1 =(VGS N2 / R20)-(VGS P2 / R10), where I P1 VGS is the output current of transistor P1. N2 VGS is the gate-source voltage of transistor N2. P2 R20 and R10 represent the gate-source voltage of transistor P2, respectively. In this circuit, resistor R20 is a pull-up resistor, its purpose being to pull the gate voltages of transistors P2 and P1 back to the supply voltage when the circuit is turned off, thus completely turning off transistors P1 and P2. Normally, the output current cutoff of transistor P2 depends on the mirror ratio of the current mirror, but when the supply voltage is high, transistor P1 satisfies VDS. P1 =VGS P1 Among them, VDS P1 This is the drain-source voltage of transistor P2, and transistor P2 satisfies VDS. P2 =VCC-VOUT (VOUT is generally limited to 5V depending on the usage requirements), which causes a large difference in VDS (drain-source voltage) between transistor P1 and transistor P2. This results in a large difference in the matching accuracy of the current mirror, which in turn causes a larger current to be reflected by transistor P2, resulting in unnecessary current generation.

[0030] Firstly, please refer to Figures 2-4Some embodiments of this application provide an internal power generation circuit, which includes: a switching module 1, a negative feedback module 2, a first branch current module 3, a second branch current module 4, a third branch current module 5, a clamping module 6, a first PMOS transistor HPM1, a second PMOS transistor HPM2, a third PMOS transistor HPM3, a fourth PMOS transistor HPM4, a first resistor R1, a second resistor R2, and a power output terminal VOUT. One end of the first branch current module 3 is connected to the power supply voltage VCC, and the other end is connected to the gate of the first PMOS transistor HPM1 and the source of the second PMOS transistor HPM2. The drain of the second PMOS transistor HPM2 is grounded. The source of the first PMOS transistor HPM1 is connected to the power supply voltage VCC. The drain of the first PMOS transistor HPM1 is connected to the gate of the third PMOS transistor HPM3, the gate of the second PMOS transistor HPM2, and one end of the switching module 1. The other end of the switching module 1 is grounded through the first resistor R1. The source of the third PMOS transistor HPM3 is connected to the power supply voltage VCC through the second branch current module 4. The drain of the third PMOS transistor HPM3 is connected to one end of the clamping module 6 and the first end of the negative feedback module 2. The other end of the clamping module 6 is grounded. The second terminal of the negative feedback module 2 is connected to the power supply voltage VCC through the third branch current module 5 and is connected to the gate of the fourth PMOS transistor HPM4. The third terminal of the negative feedback module 2 is grounded through the second resistor R2. The source of the fourth PMOS transistor HPM4 is connected to the power supply voltage VCC, and the drain of the fourth PMOS transistor HPM4 is connected to the power output terminal VOUT and the fourth terminal of the negative feedback module 2. The fourth terminal of the feedback module is grounded.

[0031] Specifically, the switch module 1 is the switch control terminal of the internal power generation circuit in this embodiment of the application, used to control the power output terminal VOUT of the internal power generation circuit to generate an output voltage for power output, and the switch is controlled by a corresponding enable signal; wherein, the first branch current module 3, the second branch current module 4 and the third branch current module 5 are used to generate corresponding branch currents based on the supply voltage VCC when the switch module 1 is turned on to drive the internal power generation circuit to operate so that the power output terminal VOUT outputs a voltage.

[0032] More specifically, the clamping module 6 is used to regulate the input voltage of the first terminal of the negative feedback module 2. When the supply voltage VCC is greater than the target output voltage, the input voltage of the first terminal of the feedback module is clamped to the target output voltage. When the supply voltage VCC is less than or equal to the target output voltage, the first terminal of the feedback module is provided with an input voltage of the same magnitude as the supply voltage VCC based on the drain of the third PMOS transistor HPM3. The target output voltage is the output voltage that the power supply output terminal VOUT is expected to output, which can be determined by configuring the device specifications of the clamping module 6.

[0033] It should be noted that, in order to ensure that the power output terminal VOUT of the internal power generation circuit of this application embodiment can smoothly output the target output voltage during use, the magnitude of the power supply voltage VCC is preferably greater than or equal to the target output voltage.

[0034] More specifically, the internal power generation circuit of this application embodiment can be applied to various chips or electronic devices that need to generate an appropriate output voltage internally to power the devices. When an output voltage needs to be generated, the enable signal controls the switch module 1 to turn on. The first branch current module 3 generates a branch current based on the supply voltage VCC and a bias voltage generated by the first resistor R1, causing the first PMOS transistor HPM1, the second PMOS transistor HPM2, and the third PMOS transistor HPM3 to turn on. The bias voltage generated by the first resistor R1 causes the gate voltage of the third PMOS transistor HPM3 to drop and turn on, thereby pulling up the input voltage of the first terminal of the negative feedback module 2. When the supply voltage VCC is greater than the target output voltage, clamping is performed. Module 6 clamps the input voltage at the first terminal of the negative feedback module 2 to the target output voltage, so that the feedback module adjusts the voltage at the second terminal according to the voltage received at the fourth terminal and the input voltage received at the third terminal, which is equal to the target output voltage, thereby changing the conduction capability of the fourth PMOS transistor HPM4 to clamp and stabilize the voltage at the power output terminal VOUT to the target output voltage. When the supply voltage VCC is less than or equal to the target output voltage, the input voltage at the first terminal of the negative feedback module 2 is pulled down to be lower than the target output voltage, which in turn pulls the gate voltage of the fourth PMOS transistor HPM4 down further and turns it on completely, so that the output voltage at the power output terminal VOUT is equal to the supply voltage VCC.

[0035] The internal power generation circuit of this embodiment adjusts the output voltage of the power output terminal VOUT based on the clamping module 6 and the negative feedback module 2, so that the output voltage can match the target output voltage or the supply voltage VCC. In both cases, the output voltage of the power output terminal VOUT is modulated by changing the conduction capability by adjusting the gate voltage of the fourth PMOS transistor HPM4. The fourth PMOS transistor HPM4 is directly connected to the supply voltage VCC, so that the internal power generation circuit of this embodiment does not need to rely on the current mirror to generate the output voltage. The output current of the power output terminal VOUT is determined by the connected downstream load and the output voltage, avoiding unnecessary current generation and effectively solving the problem of excessive static current in the internal power generation circuit.

[0036] In some preferred embodiments, the clamping module 6 includes a first capacitor C1 and a diode D1 connected in parallel.

[0037] Specifically, such as Figure 3 As shown, one end of the first capacitor C1 and the cathode of the diode D1 are both connected to the first end of the negative feedback module 2, and the other end of the first capacitor C1 and the anode of the diode D1 are both grounded.

[0038] More specifically, the diode D1 is a Zener diode, which has a voltage stabilizing function and can stabilize the voltage output from its cathode within a certain voltage range. This allows the input voltage at the first terminal of the negative feedback module 2 to be clamped to the magnitude of the target output voltage when the supply voltage VCC is greater than the target output voltage. In this embodiment, the first capacitor C1 is used to reduce the ripple of the voltage output from the cathode of the diode D1, so as to make the voltage more stable.

[0039] It should be noted that the clamping capability of the clamping module 6 is determined by the specifications of the diode D1. Therefore, the internal power generation circuit of this application embodiment can be configured with diodes D1 of different specifications according to the needs to design a suitable target output voltage.

[0040] In some preferred embodiments, the target output voltage is 1.8V, 3.3V, 5V or 12V. In this embodiment, 5V is preferred. Other types of voltage values ​​can be connected to the corresponding voltage modulation circuit at the power output terminal VOUT to modulate the output voltage based on 5V. That is, when the supply voltage VCC is greater than the target output voltage, the clamping module 6 can clamp the input voltage of the first terminal of the negative feedback module 2 to 5V, thereby causing the power output terminal VOUT to generate an output voltage of 5V.

[0041] In some preferred embodiments, the negative feedback module 2 includes a first NMOS transistor HNM1 and a second NMOS transistor HNM2; The gate of the first NMOS transistor HNM1 is the first terminal of the negative feedback module 2, the drain of the first NMOS transistor HNM1 is the second terminal of the negative feedback module 2, the source of the first NMOS transistor HNM1 is connected to the source of the second NMOS transistor HNM2 and is the third terminal of the negative feedback module 2, the drain of the second NMOS transistor HNM2 is connected to the power supply voltage VCC, and the gate of the second NMOS transistor HNM2 is the fourth terminal of the negative feedback module 2.

[0042] Specifically, when the supply voltage VCC is greater than the target output voltage, the clamping module 6 clamps the gate voltage of the first NMOS transistor HNM1 to the target output voltage. At this time, the fourth PMOS transistor HPM4, together with the first NMOS transistor HNM1 and the second NMOS transistor HNM2 of the negative feedback module 2, forms a negative feedback loop. This allows the first NMOS transistor HNM1 and the second NMOS transistor HNM2 to adjust the gate voltage of the fourth PMOS transistor HPM4 according to the magnitude of the output voltage shift, thereby changing the conduction capability of the fourth PMOS transistor HPM4. This, in turn, stabilizes the output voltage of the power supply terminal VOUT back to the target output voltage. This adjustment process does not require the participation of a current mirror circuit and can directly change the output voltage of the power supply output terminal VOUT, so that the magnitude of the output current of the power supply output terminal VOUT is determined by the connected downstream load. If the output voltage of the power supply output terminal VOUT increases, the gate voltage of the second NMOS transistor HNM2 increases, thereby enhancing its conduction capability. This increases the conduction current of the second NMOS transistor HNM2, which in turn increases the bias voltage of the second resistor R2. Consequently, the gate voltage of the fourth PMOS transistor HPM4 decreases, thereby suppressing the conduction capability of the fourth PMOS transistor HPM4 and causing its drain output voltage to decrease. This allows the output voltage of the power supply output terminal VOUT to stabilize again at the target output voltage.

[0043] In some preferred embodiments, the internal power generation circuit further includes a buck module, which includes a fourth NMOS transistor NM4 and a fourth resistor R4; The drain of the fourth NMOS transistor NM4 is connected to the gate of the first NMOS transistor HNM1, the source of the fourth NMOS transistor NM4 is grounded through the fourth resistor R4, and the gate of the fourth NMOS transistor NM4 is grounded.

[0044] Specifically, after the switching module 1 is turned off, the fourth NMOS of the buck module drains the current applied to the first terminal of the negative feedback module 2 by the clamping module 6 based on the leakage current, thereby causing the negative feedback module 2 to stop working. That is, in the embodiment where the negative feedback module 2 includes the first NMOS transistor HNM1, the buck module can drain the voltage of the gate of the first NMOS transistor HNM1 to a low level after the switching module 1 is turned off, thereby turning off the first NMOS transistor HNM1.

[0045] In some preferred embodiments, the internal power generation circuit further includes a charging module, which includes a third NMOS transistor NM3 and a third resistor R3; The drain of the third NMOS transistor NM3 is connected to the power supply voltage VCC. The source of the third NMOS transistor NM3 is connected to the gate of the third PMOS transistor HPM3 through the third resistor R3. The gate of the third NMOS transistor NM3 is connected to the gate of the third PMOS transistor HPM3.

[0046] Specifically, after the switching module 1 is turned off, the leakage current generated by the third NMOS transistor NM3 of the charging module based on the supply voltage VCC will leak to the gate of the third PMOS transistor HPM3, causing the gate voltage of the third PMOS transistor HPM3 to rise to the supply voltage VCC, thereby turning off the third PMOS transistor HPM3, thus turning off the clamping module 6 and the second PMOS transistor HPM2.

[0047] More specifically, after the switching module 1 is turned off, the gate voltage of the fourth PMOS transistor HPM4 will also be pulled up to the supply voltage VCC by the third branch current module 5 and then turned off.

[0048] Therefore, in the embodiment that includes a buck module and a charging module, when the switching module 1 is turned off, the first PMOS transistor HPM1, the second PMOS transistor HPM2, the third PMOS transistor HPM3, the fourth PMOS transistor HPM4 in the internal power generation circuit of this application embodiment and the first NMOS transistor HNM1 in the negative feedback module 2 will all be turned off, thereby making the entire circuit completely shut down without any floating point, ensuring that there is no power consumption and safe use after the circuit is turned off.

[0049] In some preferred embodiments, the switch module 1 includes a plurality of enable switches connected in parallel.

[0050] Specifically, in this embodiment, any enable switch can turn on the switch module 1, thereby enabling the internal power generation circuit of this application embodiment to generate an output voltage; setting multiple enable switches connected in parallel enables the internal power generation circuit of this application embodiment to be applicable to various application scenarios.

[0051] In some preferred embodiments, there are three enable switches, each controlled based on two complementary PWM logic input signals and a running signal.

[0052] Specifically, in the embodiments of this application, the enable switch is preferably an NMOS transistor whose drain and source are respectively connected to the gate of the third PMOS transistor HPM3 and the first resistor R1. The gates of these NMOS transistors are connected to the corresponding enable signals, that is, to the two PWM logic input signals and the running signal respectively.

[0053] It should be noted that the PWM logic input signals are only in a complementary state when working normally; when off, they are all in a low-level state.

[0054] More specifically, the operating signal is an enable signal used to determine whether the two complementary PWM logic input signals are operating normally. It is enabled as long as either of the two PWM logic input signals is high, so that the corresponding NMOS transistor remains in the conducting state. It will only switch to the off state when both PWM logic input signals are low for a duration greater than a preset time (e.g., 1ms) to turn off the switch module 1. This implementation allows the internal power generation circuit of this application embodiment to be used with a chip or electronic device that has PWM signal modulation function, and can trigger the switch module 1 to shut down only when the PWM signal is completely turned off. The operating signal can be generated based on the combined circuit design of the aforementioned two PWM logic input signals, logic gate circuits, and delay circuits.

[0055] In some preferred embodiments, the internal power generation circuit further includes a fifth resistor R5, and the fourth terminal of the negative feedback module is grounded through the fifth resistor R5.

[0056] Specifically, the fifth resistor R5 is connected to the power output terminal VOUT as a pull-down resistor. It is configured in the internal power generation circuit of this application embodiment based on the usage requirements of the target output voltage, thereby achieving the purpose of the control circuit.

[0057] More specifically, when switch module 1 is turned off, as can be seen from the foregoing, the fourth PMOS transistor HPM4 is turned off, and in this case, the fifth resistor R5 will not generate additional power consumption.

[0058] In some other embodiments, the internal power generation circuit of this application embodiment may also use a second capacitor (not shown in the figure) instead of the fifth resistor R5.

[0059] In some preferred embodiments, the first branch current module 3, the second branch current module 4, and the third branch current module 5 are all composed of resistors and several PMOS transistors. The PMOS transistors are connected in parallel with the resistors, the gate and drain of each PMOS transistor are connected, and when there are multiple PMOS transistors, they are connected in series. The upper-level PMOS transistor is connected in series with the source of the lower-level PMOS transistor based on the drain.

[0060] Specifically, the first branch current module 3 includes a PMOS transistor and a resistor. One end of the resistor is connected to the supply voltage VCC. The source of the PMOS transistor is connected to the supply voltage VCC, and the drain is connected to its gate and the other end of the resistor. The other end of the resistor is connected to the gate of the first PMOS transistor HPM1.

[0061] More specifically, the second branch current module 4 includes two PMOS transistors and a resistor. One end of the resistor is connected to the supply voltage VCC. The source of the first PMOS transistor is connected to the supply voltage VCC, and its drain and gate are connected to the source of the second PMOS transistor. The drain of the second PMOS transistor, its gate, and the other end of the resistor are connected. The other end of the resistor is connected to the source of the third PMOS transistor HPM3.

[0062] More specifically, the third branch current module 5 includes three PMOS transistors and a resistor. The connection between the two is similar to that of the second branch current module 4, so it will not be described again here. The other end of the resistor is connected to the gate of the fourth PMOS transistor HPM4.

[0063] Secondly, embodiments of this application also provide a memory chip, including the internal power generation circuit as provided in the first aspect.

[0064] Thirdly, embodiments of this application also provide an electronic device, including a power generation circuit as provided in the first aspect or a memory chip as provided in the second aspect.

[0065] In summary, this application provides an internal power generation circuit, a memory chip, and an electronic device. The internal power generation circuit adjusts the output voltage of the power output terminal VOUT based on the clamping module 6 and the negative feedback module 2, so that the output voltage can match the target output voltage or the supply voltage VCC. In both cases, the output voltage of the power output terminal VOUT is modulated by changing the conduction capability by adjusting the gate voltage of the fourth PMOS transistor HPM4. The fourth PMOS transistor HPM4 is directly connected to the supply voltage VCC, so that the internal power generation circuit of this application does not need to rely on a current mirror to generate the output voltage. The output current of the power output terminal VOUT is determined by the connected downstream load and the output voltage, avoiding unnecessary current generation and effectively solving the problem of excessive static current in the internal power generation circuit.

[0066] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0067] The above descriptions are merely some embodiments of the present invention. Those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. An internal power generation circuit, characterized in that, The internal power generation circuit includes: a switching module, a negative feedback module, a first branch current module, a second branch current module, a third branch current module, a clamping module, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first resistor, a second resistor, and a power output terminal. One end of the first branch current module is connected to the power supply voltage, and the other end is connected to the gate of the first PMOS transistor and the source of the second PMOS transistor. The drain of the second PMOS transistor is grounded. The source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the gate of the third PMOS transistor, the gate of the second PMOS transistor and one end of the switching module, and the other end of the switching module is grounded through the first resistor; The source of the third PMOS transistor is connected to the power supply voltage through the second branch current module, the drain of the third PMOS transistor is connected to one end of the clamping module and the first end of the negative feedback module, and the other end of the clamping module is grounded. The second terminal of the negative feedback module is connected to the power supply voltage through the third branch current module and is connected to the gate of the fourth PMOS transistor. The third terminal of the negative feedback module is grounded through the second resistor. The source of the fourth PMOS transistor is connected to the power supply voltage, the drain of the fourth PMOS transistor is connected to the power output terminal and the fourth terminal of the negative feedback module, and the fourth terminal of the feedback module is grounded. The negative feedback module includes a first NMOS transistor and a second NMOS transistor; The gate of the first NMOS transistor is the first terminal of the negative feedback module, the drain of the first NMOS transistor is the second terminal of the negative feedback module, the source of the first NMOS transistor is connected to the source of the second NMOS transistor and is the third terminal of the negative feedback module, the drain of the second NMOS transistor is connected to the power supply voltage, and the gate of the second NMOS transistor is the fourth terminal of the negative feedback module.

2. The internal power generation circuit according to claim 1, characterized in that, The clamping module includes a first capacitor and a diode connected in parallel.

3. The internal power generation circuit according to claim 1, characterized in that, The internal power generation circuit also includes a step-down module, which includes a fourth NMOS transistor and a fourth resistor; The drain of the fourth NMOS transistor is connected to the gate of the first NMOS transistor, the source of the fourth NMOS transistor is grounded through the fourth resistor, and the gate of the fourth NMOS transistor is grounded.

4. The internal power generation circuit according to any one of claims 1-3, characterized in that, The internal power generation circuit also includes a charging module, which includes a third NMOS transistor and a third resistor; The drain of the third NMOS transistor is connected to the power supply voltage, the source of the third NMOS transistor is connected to the gate of the third PMOS transistor through the third resistor, and the gate of the third NMOS transistor is connected to the gate of the third PMOS transistor.

5. The internal power generation circuit according to claim 1, characterized in that, The switching module includes multiple enable switches connected in parallel.

6. The internal power generation circuit according to claim 5, characterized in that, There are three enable switches, each controlled based on two complementary PWM logic input signals and a running signal.

7. The internal power generation circuit according to claim 1, characterized in that, The internal power generation circuit also includes a fifth resistor, and the fourth terminal of the negative feedback module is grounded through the fifth resistor.

8. A memory chip, characterized in that, Includes the internal power generation circuit as described in any one of claims 1-7.

9. An electronic device, characterized in that, It includes the internal power generation circuit as described in any one of claims 1-7 or the memory chip as described in claim 8.

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