Interrupt processing method and device, computer device, storage medium and computer program product

Abstract

The application relates to an interrupt processing method and device, computer equipment, a storage medium and a computer program product. The method comprises the following steps: obtaining interrupt information corresponding to a target interrupt through a target analysis unit; the target interrupt is generated by a target core, and the target core and the target analysis unit correspond to a same component aggregation layer; analyzing the interrupt information through the target analysis unit to determine an interrupt category corresponding to the target interrupt; in the case that the interrupt category is a software generated interrupt, generating an interrupt data packet corresponding to the target interrupt through the target analysis unit; transmitting the interrupt data packet to a processing core corresponding to the target interrupt; and the processing core is used for processing the target interrupt based on the interrupt data packet. The method can improve the efficiency of interrupt processing.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an interrupt handling method, apparatus, computer equipment, storage medium, and computer program product. Background Technology

[0002] A GIC (Generic Interrupt Controller) is a hardware component used to manage and distribute interrupt requests. In ARM (Advanced RISC Machine) server chips, the GIC is responsible for coordinating interrupt requests from various devices and passing the interrupt requests to the corresponding processor cores, thereby ensuring the orderly processing of interrupts and enabling the system to effectively respond to external events and device-triggered interrupts, thus maintaining the stability and performance of the entire system.

[0003] In traditional technology, interrupt requests are first sent to the GIC, which then transmits them to the responding processor core. The processor core then processes the interrupt request, resulting in low efficiency in interrupt handling. Summary of the Invention

[0004] Therefore, it is necessary to provide an interrupt handling method, apparatus, computer device, computer-readable storage medium, and computer program product that can improve the efficiency of interrupt handling in order to address the above-mentioned technical problems.

[0005] Firstly, this application provides an interruption handling method. The method includes:

[0006] The interrupt information corresponding to the target interrupt is obtained through the target parsing unit; the target interrupt is generated by the target core, and the target core and the target parsing unit correspond to the same component aggregation layer.

[0007] The interrupt information is parsed by the target parsing unit to determine the interrupt category corresponding to the target interrupt;

[0008] When the interrupt type is a software-generated interrupt, the interrupt data packet corresponding to the target interrupt is generated by the target parsing unit;

[0009] The interrupt data packet is transmitted to the processing core corresponding to the target interrupt; the processing core is used to process the target interrupt based on the interrupt data packet.

[0010] In one embodiment, the step of parsing the interrupt information through the target parsing unit to determine the interrupt category corresponding to the target interrupt includes:

[0011] The interrupt identifier is obtained from the interrupt information by the target parsing unit;

[0012] If the interrupt identifier is located within the identifier range corresponding to the software-generated interrupt, the target parsing unit determines the target interrupt as a software-generated interrupt.

[0013] In one embodiment, generating the interrupt data packet corresponding to the target interrupt through the target parsing unit includes:

[0014] The interruption information is parsed by the target parsing unit to obtain the affinity information and attribution information corresponding to the processing core;

[0015] The affinity information and the attribution information are stored in the target register by the target parsing unit.

[0016] The target parsing unit generates an interrupt data packet corresponding to the target interrupt based on the target register and the interrupt identifier in the interrupt information.

[0017] In one embodiment, transmitting the interrupt data packet to the processing core corresponding to the target interrupt includes:

[0018] Obtain the ownership information of the processing core from the target register; the target register is a register that stores the affinity information and ownership information corresponding to the processing core.

[0019] If the attribution information is a target chip, the processing core system identifier corresponding to the processing core is determined based on the affinity information in the target register; the target chip is the chip where the target core is located.

[0020] Based on the processing core system identifier, the interrupt data packet is transmitted to the processing core.

[0021] In one embodiment, the interrupt handling method further includes:

[0022] When the attribution information is a remote chip, the interrupt data packet is transmitted to the cross-chip transmission interface corresponding to the target chip; the cross-chip transmission interface is used to transmit the interrupt data packet to the processing core.

[0023] In one embodiment, the interrupt handling method further includes:

[0024] When the interrupt type is a non-software-generated interrupt, the interrupt information is sent to the target reassigner through the target parsing unit; the target reassigner and the target parsing unit correspond to the same component aggregation layer;

[0025] The interrupt information is sent to the target allocator through the target redistributor; the target allocator is used to generate and distribute the interrupt data packets corresponding to the interrupt information.

[0026] Secondly, this application also provides an interrupt handling apparatus. The apparatus includes:

[0027] The acquisition module is used to acquire interrupt information corresponding to the target interrupt through the target parsing unit; the target interrupt is generated by the target core, and the target core and the target parsing unit correspond to the same component aggregation layer;

[0028] The judgment module is used to parse the interrupt information through the target parsing unit to determine the interrupt category corresponding to the target interrupt;

[0029] The generation module is used to generate an interrupt data packet corresponding to the target interrupt through the target parsing unit when the interrupt type is a software interrupt.

[0030] A processing module is used to transmit the interrupt data packet to the processing core corresponding to the target interrupt; the processing core is used to process the target interrupt based on the interrupt data packet.

[0031] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the methods described in the first aspect.

[0032] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any one of the first aspects.

[0033] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in any of the first aspects.

[0034] The aforementioned interrupt handling method, apparatus, computer equipment, storage medium, and computer program product obtain interrupt information corresponding to the target interrupt through a target parsing unit. The target interrupt is generated by the target core, and the target core and the target parsing unit correspond to the same component aggregation layer. The target parsing unit parses the interrupt information to determine the interrupt category corresponding to the target interrupt. When the interrupt category is a software-generated interrupt, the target parsing unit generates an interrupt data packet corresponding to the target interrupt. The interrupt data packet is then transmitted to the processing core corresponding to the target interrupt. The processing core processes the target interrupt based on the interrupt data packet. When the target interrupt is generated by the target core, the target parsing unit, which corresponds to the same composite aggregation layer as the target core, determines the interrupt category of the target interrupt based on the interrupt information corresponding to the target interrupt. When the interrupt category is a software-generated interrupt, the target parsing unit generates an interrupt data packet corresponding to the target interrupt based on the interrupt information and transmits the interrupt data packet to the processing core corresponding to the target interrupt. Compared to sending the interrupt information of the target interrupt to the GIC, where the GIC generates the interrupt data packet, and then transmitting the interrupt data packet to the processing core, this shortens the information routing path, thereby shortening the interrupt handling time and improving the efficiency of interrupt handling. Attached Figure Description

[0035] Figure 1 This is a network topology diagram of an ARM server chip in one embodiment;

[0036] Figure 2 This is a flowchart illustrating an interrupt handling method in one embodiment;

[0037] Figure 3 This is a flowchart illustrating the interrupt packet determination step in one embodiment.

[0038] Figure 4 This is a schematic diagram of the core attribute identifier in another embodiment;

[0039] Figure 5 This is a schematic diagram of the target register in another embodiment;

[0040] Figure 6 This is a flowchart illustrating the interruption of data packet transmission in one embodiment;

[0041] Figure 7 This is a schematic diagram of the routing path for a conventional interrupt handling method in one embodiment;

[0042] Figure 8 This is a schematic diagram of the routing path for an interrupt handling method in one embodiment;

[0043] Figure 9 This is a structural block diagram of an interrupt handling method apparatus in one embodiment;

[0044] Figure 10 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0046] In one embodiment, an interrupt handling method is provided, which can be applied to chips using the ARM architecture. This embodiment takes the application of the method to an ARM server chip as an example for illustration. An ARM server chip refers to a chip that uses the ARM architecture and is used in server and data center environments. ARM server chips typically include multiple processor cores to provide parallel performance for multi-core processing.

[0047] like Figure 1 The network topology shown is the CPU CMN Mesh (CPU Coherent Mesh Network Mesh) of an ARM server chip. The CPU CMN Mesh includes multiple XPs (Crosspoints). Crosspoints can be connected to one or two RN-Fs (Fully coherent requesting nodes) through CAL (Component Aggregation Layer). Each RN-F can be connected to one CPU core. Crosspoints can also be connected to RN-Is (I / O coherent requesting nodes), which can be connected to GICs. Crosspoints can also be connected to CCGs (CXL Control Interface).

[0048] In this embodiment, each RNF is connected to a CPU core, a target resolution unit, and a GICR (GICRedistributor). RN-I is connected to GICD (GIC Distributor), which means that the GICR is separated from the overall GIC and placed closer to the CPU core, thus shortening the distance between the GICR and the CPU core.

[0049] In one embodiment, such as Figure 2 As shown, an interrupt handling method is provided, which includes steps 202 to 208, wherein:

[0050] Step 202: Obtain the interrupt information corresponding to the target interrupt through the target parsing unit; the target interrupt is generated by the target core, and the target core and the target parsing unit correspond to the same component aggregation layer.

[0051] In this context, a parsing unit refers to a hardware module with MPIDR (Multiprocessor Affinity Register) parsing and interrupt dispatching functions. Each parsing unit corresponds one-to-one with a core; that is, each core corresponds to one parsing unit. A target parsing unit refers to the parsing unit corresponding to the target core that generates the target interrupt. An interrupt is an asynchronous event, typically triggered by hardware devices, external input, or other specific conditions. A target interrupt refers to an interrupt generated by the target core. Interrupt information refers to information characterizing the target interrupt, including but not limited to the interrupt number and the processing core attribute identifier. A core refers to the CPU (Central Processing Unit) core. ARM server chips have multiple cores. The target core refers to the core that generates the target interrupt; the target core can be any core in the ARM server chip. The Component Aggregation Layer (CAL) is a structure that integrates the core, GICR, and parsing unit into a common hierarchical structure.

[0052] For example, the target core in the ARM server chip generates a target interrupt and transmits the interrupt information corresponding to the target interrupt to the target parsing unit of the same component aggregation layer. The target parsing unit then obtains the interrupt information corresponding to the target interrupt.

[0053] Step 204: The interrupt information is parsed by the target parsing unit to determine the interrupt category corresponding to the target interrupt.

[0054] Interrupt category refers to the type of the target interrupt, which can be one of SGI (Software Generated Interrupt) or PTI (Packet Timer Interrupt).

[0055] For example, the target parsing unit parses the interrupt information to determine the interrupt category corresponding to the target interrupt.

[0056] Step 206: In the case of software-generated interrupt, the interrupt data packet corresponding to the target interrupt is generated by the target parsing unit.

[0057] Software-generated interrupts refer to interrupts directly generated by the software program within the kernel. Software-generated interrupts are commonly used to implement system event notifications, inter-process communication, or synchronization mechanisms. Data packets are data units transmitted through communication links in a computer network. Interrupt data packets are data units containing relevant interrupt information transmitted in ARM server chips. Interrupt data packets include, but are not limited to, data content, headers, trailers, and data packet identifiers. The data content includes the interrupt identifier and relevant information from the processing kernel.

[0058] For example, when the target parsing unit determines that the interrupt type of the target interrupt is a software-generated interrupt, the target parsing unit generates an interrupt data packet corresponding to the target interrupt based on the interrupt information.

[0059] Step 208: Transmit the interrupt data packet to the processing core corresponding to the target interrupt; the processing core is used to process the target interrupt based on the interrupt data packet.

[0060] The processing core refers to the core that processes the target interrupt. The processing core can be located on the same ARM server chip as the target core, or it can be located on a different ARM server chip.

[0061] For example, the target parsing unit determines the processing core system identifier of the processing core based on the interrupt information, and transmits the interrupt data packet to the processing core corresponding to the target interrupt based on the processing core system identifier. The processing core processes the target interrupt based on the interrupt data packet.

[0062] In the above interrupt handling method, when a target interrupt is generated by the target core, the target parsing unit of the same composite aggregation layer corresponding to the target core determines the interrupt category of the target interrupt based on the interrupt information corresponding to the target interrupt. When the interrupt category is a software interrupt, the target parsing unit generates an interrupt data packet corresponding to the target interrupt based on the interrupt information corresponding to the target interrupt and transmits the interrupt data packet to the processing core corresponding to the target interrupt. Compared with sending the interrupt information of the target interrupt to the GIC, having the GIC generate the interrupt data packet, and then transmitting the interrupt data packet to the processing core, the information routing path is shortened, thereby shortening the interrupt handling time and improving the efficiency of interrupt handling.

[0063] In one embodiment, the interrupt information is parsed by the target parsing unit to determine the interrupt category corresponding to the target interrupt, including:

[0064] The interrupt identifier is obtained from the interrupt information by the target parsing unit; if the interrupt identifier is located in the identifier range corresponding to the software interrupt, the target interrupt is determined to be a software interrupt by the target parsing unit.

[0065] The interrupt identifier is an integer that uniquely identifies the interrupt source. It can be understood as the interrupt number being the interrupt identifier; for example, the interrupt identifier might be 3 or 12. The identifier range refers to the range of interrupt identifiers corresponding to software-generated interrupts. For example, interrupt identifiers between 0 and 15 correspond to interrupts of the data packet timer type, while interrupt identifiers between 16 and 31 correspond to interrupts of the software-generated type. Therefore, the identifier range is [16, 31]. The identifier range may differ between different ARM server chips.

[0066] For example, the target parsing unit obtains the interrupt identifier from the interrupt information, determines whether the interrupt identifier is located in the identifier range, and if the interrupt identifier is located in the identifier range, then the interrupt type of the target interrupt is determined to be a software-generated interrupt.

[0067] In this embodiment, the interrupt type of the target interrupt is determined based on the interrupt identifier in the interrupt information, providing accurate basic information for the subsequent processing of the target interrupt.

[0068] In one embodiment, such as Figure 3 As shown, the interrupt data packet corresponding to the target interrupt is generated by the target parsing unit, including:

[0069] Step 302: The interruption information is parsed by the target parsing unit to obtain the affinity information and belonging information corresponding to the processing core.

[0070] Among them, the processing core attribute identifier refers to the identifier compiled according to the attribute hierarchy and used to represent the processing core. For example, it adopts an identifier such as... Figure 4The method shown determines the core attribute identifier, which contains the core's affinity information. Aff0 represents the core's level 0 affinity; Aff0 can represent the lowest level of affinity and is typically used to represent the processor core's organization at the smallest scale, such as distinguishing different cores on the same chip. Aff1 represents the core's level 1 affinity; Aff1 can represent a lower level of affinity and is typically used to represent the processor core's organization at a relatively small scale, such as the specific socket or location of the core. Aff2 represents the core's level 2 affinity; Aff2 can represent an intermediate level of affinity and is typically used to represent the processor core's organization at a medium scale, such as the board or module where the core resides. Aff3 represents the core's level 3 affinity; Aff3 can represent a higher level of affinity and is typically used to represent the processor core's organization at a larger scale, such as the node or cluster where the processor resides. Affinity information refers to the location, organization, or association with a specific task, resource, or memory region of the core. Attribution information refers to the information about the chip where the processing core is located. Attribution information can be identified by characters. For example, an attribution information of 0 indicates that the processor core is located on the chip where the target core is located, and an attribution information of 1 indicates that the processor core and the target core are located on different chips.

[0071] For example, the target parsing unit obtains the processing core attribute identifier from the interruption information, analyzes the processing core attribute identifier, and obtains the affinity information and attribution information corresponding to the processing core.

[0072] In one embodiment, the target parsing unit obtains the processing core attribute identifier from the interruption information, analyzes the processing core attribute identifier, and obtains the affinity information and attribution information corresponding to the processing core. The affinity information includes zero-level affinity information, first-level affinity information, second-level affinity information, and third-level affinity information.

[0073] Step 304: The affinity information and attribution information are saved in the target register by the target parsing unit.

[0074] The target register refers to the MPIDR (Multiprocessor Affinity Register) register, for example, such as... Figure 5 The target register shown consists of 64 bits. Bits 0 to 7 store level 0 affinity information, bits 8 to 15 store level 1 affinity information, bits 16 to 23 store level 2 affinity information, bit 24 stores the affinity level used, bits 25 to 29 are reserved, bit 30 stores home information, bits 32 to 39 store level 3 affinity information, and bits 40 to 60 are reserved.

[0075] For example, the target parsing unit stores affinity information and attribution information in the target register.

[0076] In one embodiment, the target parsing unit stores the zero-level affinity information, the first-level affinity information, the second-level affinity information, the third-level affinity information, and the attribution information in the target register.

[0077] Step 306: The target parsing unit generates an interrupt data packet corresponding to the target interrupt based on the interrupt identifier in the target register and the interrupt information.

[0078] For example, the ARM server chip packages the affinity information, attribution information and interrupt identifier in the target register through the target parsing unit to obtain the interrupt data packet corresponding to the target interrupt.

[0079] In this embodiment, the target parsing unit parses the interrupt information to obtain the affinity information and attribution information corresponding to the processing core. The affinity information and attribution information are stored in the target register, providing basic information for the transmission of subsequent interrupt data packets. The target parsing unit generates an interrupt data packet corresponding to the target interrupt based on the interrupt identifier in the target register and the interrupt information. The interrupt data packet includes all the information for processing the target interrupt, providing basic information for the processing of subsequent interrupt data packets.

[0080] In one embodiment, such as Figure 6 As shown, transmitting the interrupt data packet to the processing core corresponding to the target interrupt includes:

[0081] Step 602: Obtain the ownership information of the processing core from the target register; the target register is a register that stores the affinity information and ownership information corresponding to the processing core.

[0082] For example, the ARM server chip obtains the ownership information of the processing core from the target register.

[0083] Step 604: If the attribution information is the target chip, determine the processing core system identifier corresponding to the processing core based on the affinity information in the target register; the target chip is the chip where the target core is located.

[0084] Among them, the processing core system identifier refers to the identifier of the processing core in the CPU coherence grid network, and the processing core system identifier can represent the position of the processing core in the CPU coherence grid network.

[0085] For example, based on the attribution information, when it is determined that both the processing core and the target core are located on the target chip, the ARM server chip determines the processing core system identifier corresponding to the processing core according to the affinity information in the target register.

[0086] Step 606: Based on the processing core system identifier, transmit the interrupt data packet to the processing core.

[0087] For example, the ARM server chip generates a target routing path based on the processing core system identifier and the target core system identifier, and transmits the interrupt data packet to the processing core through the target routing path.

[0088] In this embodiment, the interrupt data packet is sent directly from the target core to the processing core. Compared to sending the interrupt information of the target interrupt to the GIC, where the GIC generates the interrupt data packet and then transmits it to the processing core, this shortens the information routing path, thereby reducing the interrupt processing time and improving the efficiency of interrupt processing.

[0089] In one embodiment, the interrupt handling method further includes:

[0090] When the attribution information is a remote chip, the interrupt data packet is transmitted to the cross-chip transmission interface corresponding to the target chip; the cross-chip transmission interface is used to transmit the interrupt data packet to the processing core.

[0091] In this context, "remote chip" refers to a chip other than the target chip. The cross-chip transfer interface (CCG, ComputeExpress Link Gateway) is an interface that converts and transmits interrupt data packets.

[0092] For example, based on the attribution information, when the ARM server chip determines that the processing core is located on a remote chip, it obtains the address of the cross-chip transmission interface in the target chip, sends the interrupt data packet to the cross-chip transmission interface based on the address of the cross-chip transmission interface, and transmits the interrupt data packet to the processing core in the remote chip through the cross-chip transmission interface.

[0093] In this embodiment, when it is determined that the processing core is located on a remote chip, the interrupt data packet is transmitted to the cross-chip transmission interface corresponding to the target chip. The interrupt data packet is then transmitted to the processing core in the remote chip through the cross-chip transmission interface. Compared with sending the interrupt information of the target interrupt to the GIC, having the GIC generate the interrupt data packet, and then transmitting the interrupt data packet to the cross-chip transmission interface, the routing path of the information is shortened, thereby shortening the interrupt processing time and improving the efficiency of interrupt processing.

[0094] In one embodiment, the interrupt handling method further includes:

[0095] When the interrupt type is a non-software generated interrupt, the interrupt information is sent to the target redistributor through the target parsing unit; the target redistributor and the target parsing unit correspond to the same component aggregation layer; the interrupt information is sent to the target distributor through the target redistributor; the target distributor is used to generate and distribute the interrupt data packets corresponding to the interrupt information.

[0096] Non-software-generated interrupts refer to interrupt types other than software-generated interrupts, such as data packet timer interrupts. The redistributor refers to the Generic Interrupt Controller Redistributor (GICR), and the target redistributor refers to the redistributor located in the same component aggregation layer as the target parsing unit. The distributor refers to the Generic Interrupt Controller Distributor (GICD), and the target distributor refers to the distributor located on the target chip.

[0097] For example, when the target parsing unit determines that the interrupt type of the target interrupt is a non-software generated interrupt, it sends the interrupt information to the target redistributor in the same component aggregation layer as the target parsing unit. The target redistributor then sends the interrupt information to the target distributor, which generates the interrupt data packet corresponding to the target interrupt and distributes the interrupt data packet to the processing core.

[0098] In this embodiment, when the interrupt type of the target interrupt is a non-software generated interrupt, the interrupt information is sent to the target allocator through the target redistributor. The target allocator then distributes the target interrupt, ensuring the orderly processing of interrupts. This enables the system to effectively respond to external events and device-triggered interrupts, thereby maintaining the stability and performance of the entire system.

[0099] In one exemplary embodiment, the interrupt handling process includes:

[0100] The target core in the ARM server chip generates a target interrupt and transmits the interrupt information corresponding to the target interrupt to the target parsing unit of the same component aggregation layer. The target parsing unit then obtains the interrupt information corresponding to the target interrupt.

[0101] The target parsing unit retrieves the interrupt identifier from the interrupt information and determines whether the interrupt identifier is within the identifier range. If the interrupt identifier is within the identifier range, the interrupt type of the target interrupt is determined to be a software-generated interrupt. When the target interrupt type is determined to be a software-generated interrupt, the target parsing unit retrieves the processing core attribute identifier from the interrupt information, analyzes the processing core attribute identifier to obtain the affinity information and attribution information corresponding to the processing core, saves the affinity information and attribution information in the target register, and packages the affinity information, attribution information, and interrupt identifier in the target register to obtain the interrupt data packet corresponding to the target interrupt.

[0102] The ARM server chip obtains the ownership information of the processing core from the target register. When it is determined that both the processing core and the target core are located on the target chip, it determines the processing core system identifier corresponding to the processing core based on the affinity information in the target register. Based on the processing core system identifier and the target core system identifier, a target routing path is generated, and the interrupt data packet is transmitted to the processing core through the target routing path. When it is determined that the processing core is located on a remote chip, it obtains the address of the cross-chip transmission interface in the target chip. Based on the address of the cross-chip transmission interface, the interrupt data packet is sent to the cross-chip transmission interface, and the interrupt data packet is transmitted to the processing core in the remote chip through the cross-chip transmission interface. For example, to transmit the target interrupt from the target core at the (0,1) intersection to the processing core at the (3,1) intersection, the routing path using the traditional interrupt handling method is as follows: Figure 7 As shown, the routing path using the interrupt handling method in this embodiment is as follows: Figure 8 As shown, the interrupt handling method in this embodiment shortens the information routing path, thereby shortening the interrupt handling time and improving the efficiency of interrupt handling.

[0103] Once the target parsing unit determines that the interrupt type of the target interrupt is a non-software generated interrupt, it sends the interrupt information to the target redistributor in the same component aggregation layer as the target parsing unit. The target redistributor then sends the interrupt information to the target distributor, which generates the interrupt data packet corresponding to the target interrupt and distributes the interrupt data packet to the processing core.

[0104] In the above interrupt handling method, when a target interrupt is generated by the target core, the target parsing unit of the same composite aggregation layer corresponding to the target core determines the interrupt category of the target interrupt based on the interrupt information corresponding to the target interrupt. When the interrupt category is a software interrupt, the target parsing unit generates an interrupt data packet corresponding to the target interrupt based on the interrupt information corresponding to the target interrupt and transmits the interrupt data packet to the processing core corresponding to the target interrupt. Compared with sending the interrupt information of the target interrupt to the GIC, having the GIC generate the interrupt data packet, and then transmitting the interrupt data packet to the processing core, the information routing path is shortened, thereby shortening the interrupt handling time and improving the efficiency of interrupt handling.

[0105] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0106] Based on the same inventive concept, this application also provides an interrupt handling device for implementing the interrupt handling method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more interrupt handling device embodiments provided below can be found in the limitations of the interrupt handling method described above, and will not be repeated here.

[0107] In one embodiment, such as Figure 9 As shown, an interrupt handling device is provided, including: an acquisition module 902, a judgment module 904, a generation module 906, and a processing module 908, wherein:

[0108] The acquisition module 902 is used to acquire the interrupt information corresponding to the target interrupt through the target parsing unit; the target interrupt is generated by the target core, and the target core and the target parsing unit correspond to the same component aggregation layer;

[0109] The judgment module 904 is used to parse the interrupt information through the target parsing unit and determine the interrupt category corresponding to the target interrupt;

[0110] The generation module 906 is used to generate an interrupt data packet corresponding to the target interrupt through the target parsing unit when the interrupt type is software-generated interrupt.

[0111] The processing module 908 is used to transmit the interrupt data packet to the processing core corresponding to the target interrupt; the processing core is used to process the target interrupt based on the interrupt data packet.

[0112] In one embodiment, the determination module 904 is further configured to: obtain an interrupt identifier from the interrupt information through the target parsing unit; and determine the target interrupt as a software-generated interrupt through the target parsing unit when the interrupt identifier is located in the identifier range corresponding to the software-generated interrupt.

[0113] In one embodiment, the generation module 906 is further configured to: parse the interrupt information through the target parsing unit to obtain the affinity information and attribution information corresponding to the processing core; save the affinity information and attribution information in the target register through the target parsing unit; and generate an interrupt data packet corresponding to the target interrupt based on the interrupt identifier in the target register and the interrupt information through the target parsing unit.

[0114] In one embodiment, the processing module 908 is further configured to: obtain the ownership information of the processing core from the target register; the target register is a register that stores the affinity information and ownership information corresponding to the processing core; if the ownership information is a target chip, determine the processing core system identifier corresponding to the processing core based on the affinity information in the target register; the target chip is the chip where the target core is located; and transmit the interrupt data packet to the processing core based on the processing core system identifier.

[0115] In one embodiment, the processing module 908 is further configured to: transmit the interrupt data packet to the cross-chip transmission interface corresponding to the target chip when the attribution information is a remote chip; the cross-chip transmission interface is configured to transmit the interrupt data packet to the processing core.

[0116] In one embodiment, the processing module 908 is further configured to: send the interrupt information to the target redistributor through the target parsing unit when the interrupt type is a non-software generated interrupt; the target redistributor and the target parsing unit correspond to the same component aggregation layer; send the interrupt information to the target distributor through the target redistributor; the target distributor is used to generate and distribute the interrupt data packet corresponding to the interrupt information.

[0117] Each module in the aforementioned interrupt handling device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0118] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows:Figure 10 As shown, the computer device includes a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements an interrupt handling method. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0119] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0120] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0121] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0122] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0123] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0124] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0125] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0126] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An interrupt handling method, characterized in that, The method is applied to an ARM server chip, where the CPU consistency mesh network includes multiple intersections. Each intersection connects one or two fully consistent request nodes via a component aggregation layer. Each fully consistent request node connects to a core, a resolution unit, and a GIC reallocator, including: The interrupt information corresponding to the target interrupt is obtained through the target parsing unit; the target interrupt is generated by the target core, and the target core and the target parsing unit correspond to the same component aggregation layer. The interrupt information is parsed by the target parsing unit to determine the interrupt category corresponding to the target interrupt; When the interrupt type is a software-generated interrupt, the interrupt information is parsed by the target parsing unit to obtain the affinity information and attribution information corresponding to the processing core. The affinity information refers to the location and organizational structure of the core, and the attribution information refers to the information of the chip where the processing core is located. The affinity information and the attribution information are stored in the target register by the target parsing unit. Based on the interrupt identifier in the target register and the interrupt information, the target parsing unit generates an interrupt data packet corresponding to the target interrupt. When the interrupt type is a non-software-generated interrupt, the interrupt information is sent to the target redistributor through the target parsing unit; the target redistributor and the target parsing unit correspond to the same component aggregation layer; the interrupt information is sent to the target distributor through the target redistributor; the target distributor is used to generate and distribute the interrupt data packet corresponding to the interrupt information; The interrupt data packet is transmitted to the processing core corresponding to the target interrupt; the processing core is used to process the target interrupt based on the interrupt data packet.

2. The method according to claim 1, characterized in that, The step of parsing the interrupt information through the target parsing unit to determine the interrupt category corresponding to the target interrupt includes: The interrupt identifier is obtained from the interrupt information by the target parsing unit; If the interrupt identifier is located within the identifier range corresponding to the software-generated interrupt, the target parsing unit determines the target interrupt as a software-generated interrupt.

3. The method according to claim 1, characterized in that, The software interruption mentioned refers to an interruption directly generated by the software program within the core.

4. The method according to claim 1, characterized in that, The step of transmitting the interrupt data packet to the processing core corresponding to the target interrupt includes: Obtain the ownership information of the processing core from the target register; the target register is a register that stores the affinity information and ownership information corresponding to the processing core. If the attribution information is a target chip, the processing core system identifier corresponding to the processing core is determined based on the affinity information in the target register; the target chip is the chip where the target core is located. Based on the processing core system identifier, the interrupt data packet is transmitted to the processing core.

5. The method according to claim 4, characterized in that, The method further includes: When the attribution information is a remote chip, the interrupt data packet is transmitted to the cross-chip transmission interface corresponding to the target chip; the cross-chip transmission interface is used to transmit the interrupt data packet to the processing core.

6. The method according to claim 4, characterized in that, The step of transmitting the interrupt data packet to the processing core based on the processing core system identifier includes: Based on the processing core system identifier and the target core system identifier, a target routing path is generated, and the interrupted data packet is transmitted to the processing core through the target routing path.

7. An interrupt handling device, characterized in that, The device is applied to an ARM server chip, whose CPU consistency mesh network includes multiple intersections. Each intersection connects one or two fully consistent request nodes via a component aggregation layer. Each fully consistent request node connects to a core, a resolution unit, and a GIC reallocator, including: The acquisition module is used to acquire interrupt information corresponding to the target interrupt through the target parsing unit; the target interrupt is generated by the target core, and the target core and the target parsing unit correspond to the same component aggregation layer; The judgment module is used to parse the interrupt information through the target parsing unit to determine the interrupt category corresponding to the target interrupt; A generation module is used to, when the interrupt type is a software-generated interrupt, parse the interrupt information through the target parsing unit to obtain affinity information and attribution information corresponding to the processing core; the affinity information refers to the location and organizational structure of the core, and the attribution information refers to the information of the chip where the processing core is located; the target parsing unit stores the affinity information and the attribution information in a target register; the target parsing unit generates an interrupt data packet corresponding to the target interrupt based on the interrupt identifier in the target register and the interrupt information; when the interrupt type is a non-software-generated interrupt, the target parsing unit sends the interrupt information to a target redistributor; the target redistributor and the target parsing unit correspond to the same component aggregation layer; the target redistributor sends the interrupt information to a target distributor; the target distributor is used to generate and distribute the interrupt data packet corresponding to the interrupt information; A processing module is used to transmit the interrupt data packet to the processing core corresponding to the target interrupt; the processing core is used to process the target interrupt based on the interrupt data packet.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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