Read and write address translation of reserved memory pages using a multi-page translation unit

Abstract

This disclosure relates to read and write address translations of reserved memory pages using a multi-page translation unit. In some implementations, a memory device can receive a write command that includes data to be written to a plurality of memory pages of a translation unit (TU) of the memory device. The plurality of memory pages of the TU can span a plurality of memory planes of the memory device. The memory device can identify the plurality of memory pages of the TU to which the data is to be written based on one or more bad blocks of the memory device and a determination as to whether one or more memory pages of the memory device are to be reserved. The memory device can write the data to the plurality of memory pages of the TU.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, memory device operations, and, for example, to read and write address translation of reserved memory pages using a multi-page translation unit. Background Technology

[0002] Memory devices are widely used to store information in various electronic devices. A memory device comprises memory cells. A memory cell is an electronic circuit that can be programmed into one of two or more data states. For example, a memory cell can be programmed to represent a single binary value, typically represented by a binary "1" or a binary "0". As another example, a memory cell can be programmed to represent a small number of data states (e.g., 0.5, 1.5, etc.). To store information, an electronic device can write to or program a set of memory cells. To access the stored information, the electronic device can read from or sense the stored states from the set of memory cells.

[0003] Various types of memory devices exist, including Random Access Memory (RAM), Read-Only Memory (ROM), Dynamic RAM (DRAM), Static RAM (SRAM), Synchronous Dynamic RAM (SDRAM), Ferroelectric RAM (FeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Holographic RAM (HRAM), Flash Memory (e.g., NAND and NOR memory), and so on. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., flash memory) can store data for a long time, even without an external power supply. Volatile memory (e.g., DRAM) may lose stored data over time unless the volatile memory is refreshed by power. Summary of the Invention

[0004] One aspect of this disclosure provides a memory device including: one or more components configured to: identify a translation unit (TU) associated with a read command, wherein the TU includes a plurality of memory pages spanning a plurality of memory planes of the memory device; identify an initial memory page among the plurality of memory pages of the TU based on a logical-to-physical mapping table; identify one or more additional memory pages among the plurality of memory pages of the TU based on the initial memory page and based on at least one of: an indication of one or more bad blocks of the memory device, or an index value of the initial memory page or an index value of a memory plane containing the initial memory page among the plurality of memory planes; and read data from the initial memory page and the one or more additional memory pages contained in the TU.

[0005] Another aspect of this disclosure provides a memory device including: one or more components configured to: identify a translation unit (TU) associated with a read command, wherein the TU includes a plurality of memory pages spanning a plurality of memory planes of the memory device; identify an initial memory page among the plurality of memory pages of the TU based on a logical-to-physical mapping table, wherein the initial memory page is contained in a first memory plane among the plurality of memory planes; identify one or more additional memory pages contained in the plurality of memory pages of the TU based on the initial memory page and based on an indication of one or more bad blocks of the memory device, wherein the one or more additional memory pages are contained in one or more additional memory planes among the plurality of memory planes; and read data from the initial memory page and the one or more additional memory pages contained in the TU.

[0006] Another aspect of this disclosure provides a memory device including: one or more components configured to: identify a translation unit (TU) associated with a read command, wherein the TU includes a plurality of memory pages spanning a plurality of memory planes of the memory device; identify an initial memory page among the plurality of memory pages of the TU based on a logical-to-physical mapping table, wherein the initial memory page is contained in a first memory plane among the plurality of memory planes; determine a plane index value of the first memory plane; identify one or more additional memory pages contained in the plurality of memory pages of the TU based on the initial memory page and based on the plane index value, wherein the one or more additional memory pages are contained in one or more additional memory planes among the plurality of memory planes; and read data from the initial memory page and the one or more additional memory pages contained in the TU.

[0007] Another aspect of this disclosure provides a method comprising: receiving, via a memory device, a write command comprising data to be written to a plurality of memory pages of a translation unit (TU) of the memory device, wherein the plurality of memory pages of the TU span a plurality of memory planes of the memory device; identifying, via the memory device, the plurality of memory pages of the TU to which the data is to be written based on: one or more bad blocks of the memory device, and a determination regarding whether one or more memory pages of the memory device will be retained; and writing the data to the plurality of memory pages of the TU via the memory device.

[0008] Another aspect of this disclosure provides an apparatus comprising: means for storing an indication of a set of reserved memory pages of the apparatus based on an indication of a set of bad blocks contained in the apparatus and a conversion unit (TU) size, wherein the TU size indicates the number of memory pages contained in a TU of the apparatus, wherein the TU comprises a plurality of memory pages spanning a plurality of memory planes of the apparatus; and means for preventing user data from being written to the set of reserved memory pages. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating an example system capable of read and write address translation using reserved memory pages with multiple page translation units.

[0010] Figure 2 It is a diagram of instance components contained in a memory device.

[0011] Figure 3 This is a diagram illustrating an example memory architecture that can be used by a memory device.

[0012] Figure 4 This is a diagram illustrating an example of memory address translation.

[0013] Figure 5 This is a diagram illustrating an example of a multi-planar page of a memory device.

[0014] Figure 6 This is a diagram illustrating an example of a multiplanar page stripe in a memory device.

[0015] Figure 7 This is a diagram illustrating an example of a multi-planar block stripe in a memory device.

[0016] Figure 8 This is a diagram illustrating instances of reserving and deserving memory pages for multi-page translation units.

[0017] Figure 9 This is a diagram illustrating an example of write address translation using reserved memory pages with a multi-page translation unit.

[0018] Figure 10 This is a diagram illustrating an example of read address translation using reserved memory pages with a multi-page translation unit.

[0019] Figure 11 This is a diagram of another example of write address translation using reserved memory pages with a multi-page translation unit.

[0020] Figure 12-15 This is a diagram illustrating examples of write address translation and read address translation performed using the techniques described in this article.

[0021] Figure 16-20This is a flowchart of an example method for read address translation and write address translation using reserved memory pages in a multi-page translation unit. Detailed Implementation

[0022] As the storage capacity of non-volatile memory devices such as solid-state drives (SSDs) increases, these devices require more and more volatile memory, such as DRAM, to enable fast execution of various memory operations, such as logic-to-physical (L2P) address translation. For example, one or more L2P address tables can be stored in and accessed from DRAM to achieve faster memory translation than accessing those L2P address tables from non-volatile memory (e.g., NAND memory). Larger capacity SSDs have more physical addresses to store data, thus requiring larger L2P tables to store a greater number of logical-to-physical address mappings. The increased demand for DRAM as SSD storage capacity increases leads to larger SSD physical sizes (e.g., due to larger capacity non-volatile memory and correspondingly larger capacity volatile memory), consumes additional power to maintain and operate the DRAM (e.g., for refresh operations), and increases manufacturing costs. Reducing the required size of DRAM (e.g., for a given SSD capacity) will reduce the physical footprint of the SSD, reduce SSD power consumption, and lower the manufacturing and operating costs of the SSD.

[0023] One technique for reducing DRAM size is to use L2P table swapping, where only a portion of the L2P table is stored in DRAM, while the rest is stored in NAND memory. However, this technique requires additional memory operations (compared to storing the entire L2P table in DRAM) to write portions of the L2P table from DRAM to NAND and read portions of the L2P table from NAND to DRAM. This increases the latency of L2P address translation and corresponding read / write operations, consumes memory devices more quickly, and leads to write amplification issues, especially in SSDs operating in write-intensive environments.

[0024] Another technique for reducing DRAM size is to use a large Translation Unit (TU) size. A TU is a logical memory cell that can correspond to a single logical block address (LBA) indicated in a host command or to multiple LBAs. L2P table entries can map a single logical TU to a single physical memory page (or a portion of a single physical memory page). Therefore, the maximum size of a TU can be limited by the page size of the memory device. For example, if a TU is 4 kilobytes in size, and each L2P table entry contains a mapping from a single TU to a single physical address, then each L2P table entry maps to 4 kilobytes of user data. If the page size is 16 kilobytes, then the TU size can be increased to 16 kilobytes, resulting in a number of L2P table entries in the DRAM that is one-quarter the size of a 4 kilobyte TU. However, this can still result in a DRAM size larger than expected.

[0025] Increasing the TU size to a size larger than the page size of the memory device results in a smaller DRAM size required to store the L2P table. However, this presents several challenges. For example, increasing the TU size to a size larger than the page size will cause L2P table entries to map a single TU to multiple pages (referred to as a "multi-page TU"). If the L2P table indicates every single one of the multiple pages, this does not help reduce the size of the L2P table. Instead, the size of the L2P table can be reduced by indicating only the single page contained in the multi-page TU. However, the memory device will need to determine the additional pages contained in the multi-page TU, which is a challenge because pages are not always contiguous. For example, pages in a multi-page TU may be contained in different memory planes, different page stripes, and / or different block stripes (e.g., for good memory utilization). Furthermore, some pages may be defective (e.g., they may be contained in defective blocks or planes), which will alter the L2P mapping.

[0026] Some implementations described herein achieve read and write address translation for multi-page TUs. In some implementations, the memory device can dynamically retain and / or unretain memory pages to exclude or include those memory pages from the multi-page TU accordingly. Retained memory pages are sometimes referred to as "virtually discarded" memory pages, and retained memory pages (or memory pages marked as retained) may be called "virtually discarded" memory pages. Similarly, unretained memory pages are sometimes referred to as "virtually restored" memory pages, and unretained memory pages (or memory pages marked as unretained) may be called "virtually restored" memory pages. The memory device can retain or unretain memory pages to improve speed and reduce the processing power required for read and write address translation. Therefore, the memory device can efficiently utilize multi-page TUs, resulting in smaller L2P tables and smaller DRAM, which reduces the physical footprint of the memory device, reduces the power consumption of the memory device required for DRAM operation and maintenance, and lowers the manufacturing and operating costs of the memory device.

[0027] Figure 1 This is a diagram illustrating an example system 100 capable of read and write address translation using reserved memory pages of a multi-page translation unit. System 100 may include one or more means, devices, and / or components for performing the operations described herein. For example, system 100 may include a host device 110 and a memory device 120. Memory device 120 may include a controller 130 and a memory 140. Host device 110 may communicate with memory device 120 (e.g., controller 130 of memory device 120) via host interface 150. Controller 130 and memory 140 may communicate via memory interface 160.

[0028] System 100 can be any electronic device configured to store data in memory. For example, system 100 can be a computer, mobile phone, wired or wireless communication device, network device, server, device in a data center, device in a cloud computing environment, vehicle (e.g., car or airplane), and / or Internet of Things (IoT) device. Host device 110 may include one or more processors configured to execute instructions and store data in memory 140. For example, host device 110 may include a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and / or another type of processing component.

[0029] Memory device 120 can be any electronic device or apparatus configured to store data in memory. In some embodiments, memory device 120 can be an electronic device configured to persistently store data in non-volatile memory. For example, memory device 120 can be a hard disk drive, solid-state drive (SSD), flash memory device (e.g., NAND flash memory device or NOR flash memory device), universal serial bus (USB) flash drive, memory card (e.g., Secure Digital (SD) card), secondary storage device, non-volatile memory high speed (NVMe) device, and / or embedded multimedia card (eMMC) device. In this case, memory 140 may include non-volatile memory configured to retain stored data after power loss of memory device 120. For example, memory 140 may include NAND memory or NOR memory. In some implementations, memory 140 may include volatile memory that requires power to maintain stored data and loses stored data after power is lost from memory device 120, such as one or more latches and / or random access memory (RAM), such as dynamic RAM (DRAM) and / or static RAM (SRAM). For example, the volatile memory may cache data read from or written to non-volatile memory, and / or cache instructions executed by controller 130.

[0030] Controller 130 can be any device configured to communicate with a host device (e.g., via host interface 150) and memory 140 (e.g., via memory interface 160). Alternatively or additionally, controller 130 can be configured to control the operation of memory device 120 and / or memory 140. For example, controller 130 may include a memory controller, system controller, ASIC, FPGA, processor, microcontroller, and / or one or more processing components. In some embodiments, controller 130 may be a high-level controller that can communicate directly with host device 110 and can instruct one or more low-level controllers regarding memory operations to be performed in conjunction with memory 140. In some embodiments, controller 130 may be a low-level controller that can receive instructions regarding memory operations from a high-level controller that directly interfaces with host device 110. As an example, the high-level controller may be an SSD controller, and the low-level controller may be a non-volatile memory controller (e.g., a NAND controller) or a volatile memory controller (e.g., a DRAM controller). In some implementations, a set of operations described herein as being performed by controller 130 may be performed by a single controller (e.g., the entire set of operations may be performed by a single high-level controller or a single low-level controller). Alternatively, a set of operations described herein as being performed by controller 130 may be performed by more than one controller (e.g., a first subset of the operations may be performed by a high-level controller, and a second subset of the operations may be performed by a low-level controller).

[0031] Host interface 150 enables communication between host device 110 and storage device 120. Host interface 150 may include, for example, a Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect High Speed ​​(PCIe) interface, NVMe interface, USB interface, Universal Flash Storage (UFS) interface and / or an Embedded Multimedia Card (eMMC) interface.

[0032] Memory interface 160 enables communication between memory device 120 and memory 140. Memory interface 160 may include a non-volatile memory interface (e.g., for communicating with non-volatile memory), such as a NAND interface or a NOR interface. Alternatively, memory interface 160 may include a volatile memory interface (e.g., for communicating with volatile memory), such as a Double Data Rate (DDR) interface.

[0033] In some embodiments, memory device 120 and / or controller 130 may be configured to identify a translation unit (TU) associated with a read command, wherein the TU comprises multiple memory pages spanning multiple memory planes of the memory device; identify an initial memory page among the multiple memory pages of the TU based on a logical-to-physical mapping table; identify one or more additional memory pages among the multiple memory pages of the TU based on the initial memory page and based on at least one of the following: an indication of one or more bad blocks of the memory device, or an index value for identifying the initial memory page or identifying a memory plane containing the initial memory page among the multiple memory planes; and read data from the initial memory page contained in the TU and the one or more additional memory pages.

[0034] In some embodiments, memory device 120 and / or controller 130 may be configured to identify a TU associated with a read command, wherein the TU comprises multiple memory pages spanning multiple memory planes of the memory device; identify an initial memory page among the multiple memory pages of the TU based on a logical-to-physical mapping table, wherein the initial memory page is contained in a first memory plane among the multiple memory planes; identify one or more additional memory pages contained among the multiple memory pages of the TU based on the initial memory page and based on an indication of one or more bad blocks of the memory device, wherein the one or more additional memory pages are contained in one or more additional memory planes among the multiple memory planes; and read data from the initial memory page and the one or more additional memory pages contained in the TU.

[0035] In some embodiments, memory device 120 and / or controller 130 may be configured to identify a TU associated with a read command, wherein the TU comprises multiple memory pages spanning multiple memory planes of the memory device; identify an initial memory page among the multiple memory pages of the TU based on a logical-to-physical mapping table, wherein the initial memory page is contained in a first memory plane among the multiple memory planes; determine a plane index value for the first memory plane; identify one or more additional memory pages contained among the multiple memory pages of the TU based on the initial memory page and based on the plane index value, wherein the one or more additional memory pages are contained in one or more additional memory planes among the multiple memory planes; and read data from the initial memory page and the one or more additional memory pages contained in the TU.

[0036] In some embodiments, memory device 120 and / or controller 130 may be configured to receive a write command containing data to be written to a plurality of memory pages of a TU of the memory device, wherein the plurality of memory pages of the TU span a plurality of memory planes of the memory device; identify the plurality of memory pages of the TU to which data is to be written based on: one or more bad blocks of the memory device, and a determination of whether one or more memory pages of the memory device will be retained; and write the data to the plurality of memory pages of the TU.

[0037] In some embodiments, memory device 120 and / or controller 130 may be configured to store an indication of a set of reserved memory pages of the memory device based on an indication of a set of bad blocks contained in the memory device and a TU size, wherein the TU size indicates the number of memory pages contained in a TU of the memory device, wherein the TU contains multiple memory pages spanning multiple memory planes of the memory device; and to prevent user data from being written to said set of reserved memory pages.

[0038] As pointed out above, Figure 1 Provided as an example. Other examples are available in the section about Figure 1 The situations described are different.

[0039] Figure 2 This is a diagram of an instance component contained in memory device 120. (As described above...) Figure 1 As described, memory device 120 may include controller 130 and memory 140. For example... Figure 2As shown, memory 140 may include one or more non-volatile memory arrays 205, such as one or more NAND memory arrays and / or one or more NOR memory arrays. Alternatively, memory 140 may include one or more volatile memory arrays 210, such as one or more SRAM arrays and / or one or more DRAM arrays. Controller 130 may use non-volatile memory interface 215 to transmit signals to and receive signals from non-volatile memory array 205. Controller 130 may use volatile memory interface 220 to transmit signals to and receive signals from volatile memory array 210.

[0040] Controller 130 can control the operation of memory 140, for example, by executing one or more instructions. For example, memory device 120 can store one or more instructions as firmware in memory 140, and controller 130 can execute said one or more instructions. Alternatively, controller 130 can receive one or more instructions from host device 110 via host interface 150, and can execute said one or more instructions. In some embodiments, a non-transitory computer-readable medium (e.g., volatile memory and / or non-volatile memory) can store a set of instructions (e.g., one or more instructions or codes) for controller 130 to execute. Controller 130 can execute said set of instructions to perform one or more operations or methods described herein. In some embodiments, execution of said set of instructions by controller 130 causes controller 130 and / or memory device 120 to perform one or more operations or methods described herein. In some embodiments, a hard-wired circuitry system is used instead of said one or more instructions or in combination with them to perform one or more operations or methods described herein. Alternatively, one or more components of the controller 130 and / or memory device 120 may be configured to perform one or more operations or methods described herein. Instructions are sometimes referred to as “commands”.

[0041] For example, controller 130 may transmit signals to and / or receive signals from memory 140 based on one or more instructions to transfer data (e.g., write or program) to all or part of memory 140 (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes of memory 140), transfer data from it (e.g., read) and / or erase it. Alternatively or additionally, controller 130 may be configured to control access to memory 140 and / or provide a translation layer (e.g., for mapping logical addresses of the memory array to physical addresses) between host device 110 and memory 140. In some embodiments, controller 130 may translate host interface commands (e.g., commands received from host device 110) into memory interface commands (e.g., commands for performing operations on the memory array).

[0042] like Figure 2As shown, controller 130 may include memory management component 225, address translation component 230, page reservation component 235, and / or command execution component 240. In some embodiments, one or more of these components are implemented as one or more instructions (e.g., firmware) executed by controller 130. Alternatively, one or more of these components may be implemented as application-specific integrated circuits (ASICs) different from controller 130.

[0043] Memory management component 225 can be configured to manage the performance of memory device 120. For example, memory management component 225 can perform wear leveling, bad block management, block discarding, read interference management, and / or other memory management operations. In some embodiments, memory device 120 may (e.g., in memory 140) store one or more memory management tables. Memory management tables may store information that can be used or updated by memory management component 225, such as information about memory block usage period, memory block erase count, one or more bad blocks, and / or error information associated with memory partitions (e.g., memory cells, memory rows, memory blocks, etc.).

[0044] Address translation component 230 may be configured to perform read address translation and / or write address translation of memory device 120. For example, address translation component 230 may perform read address translation of a multi-page TU based on a received read command. Address translation component 230 may identify the multi-page TU associated with the read command and may identify multiple memory pages contained in the multi-page TU, such as the initial memory page of the multi-page TU and one or more additional memory pages of the multi-page TU. For example, address translation component 230 may use a logic-to-physical mapping table to identify the initial memory page of the multi-page TU and may use one or more techniques described herein to identify one or more additional memory pages of the multi-page TU. In some embodiments, address translation component 230 may prevent data from being read from reserved memory pages.

[0045] Alternatively or concurrently, address translation component 230 may perform write address translation for a multi-page TU based on a received write command. Address translation component 230 may use one or more techniques described herein to identify multiple memory pages to be included in the multi-page TU and to which data will be written. For example, address translation component 230 may identify multiple memory pages based on one or more bad blocks and / or a determination of whether one or more memory pages will be retained. In some embodiments, address translation component 230 may use one or more techniques described herein to select memory pages to be included in the multi-page TU. Address translation component 230 may store an indication of the initial page of the multi-page TU in a logical-to-physical mapping table such that the initial page can be identified during read address translation.

[0046] Page reservation component 235 may reserve and unreserve memory pages using one or more techniques described herein. In some embodiments, page reservation component 235 may use one or more techniques described herein to determine whether to reserve and / or unreserve memory pages (and / or determine which memory pages to reserve and / or unreserve). For example, page reservation component 235 may reserve one or more memory pages based on bad block configuration. When a memory page is reserved, storage of user data in said memory page is prohibited by memory device 120. In other words, memory device 120 may be configured to prevent user data from being stored in reserved memory pages. In some embodiments, page reservation component 235 may unreserve one or more memory pages when bad block configuration changes (e.g., based on the detection of a new bad block). When a memory page is unreserved, storage of user data in said memory page is permitted by memory device 120. In other words, memory device 120 may be configured to store user data in unreserved memory pages. In some embodiments, page reservation component 235 may store an indication of one or more reserved memory pages (e.g., based on bad block configuration and / or TU size).

[0047] Command execution component 240 can be configured to execute one or more memory commands, such as read commands or write commands (sometimes referred to as programming commands). For example, command execution component 240 can execute a read command to read data from a multi-page unit (e.g., from the initial page of the multi-page unit and one or more additional pages of the multi-page unit). Command execution component 240 can read data from multiple pages (e.g., unreserved pages) in the multi-page unit identified during read address translation. As another example, command execution component 240 can execute a write command to write data to a multi-page unit (e.g., to the initial page of the multi-page unit and one or more additional pages of the multi-page unit). Command execution component 240 can write data to multiple pages (e.g., unreserved pages) in the multi-page unit identified during write address translation. In some embodiments, command execution component 240 can write non-user data (e.g., dummy data or parity data) to reserved pages.

[0048] Figure 2 The one or more devices or components shown may be configured to perform the operations described elsewhere herein, such as in combination with Figure 3-20 One or more operations and / or methods are described. For example, controller 130, memory management component 225, address translation component 230, page reservation component 235, and / or command execution component 240 may be configured to perform one or more operations and / or methods for memory device 120.

[0049] Figure 2 The number and arrangement of components shown are provided as examples. In fact, compared to... Figure 2The components shown may include additional components, fewer components, different components, or components arranged in different ways. Furthermore, Figure 2 The two or more components shown can be implemented within a single component, or Figure 2 The single component shown can be implemented as multiple distributed components. Alternatively, Figure 2 The set of components shown (e.g., one or more components) can be performed as described by Figure 2 The other set of components shown performs one or more operations.

[0050] Figure 3 This is a diagram illustrating an example memory architecture 300 that can be used by memory device 120. Memory device 120 can use memory architecture 300 to store data. As shown, memory architecture 300 may include a die 310, which may include multiple planes 320. A plane 320 may include multiple blocks 330. A block 330 may include multiple pages 340. Although... Figure 3 A specific number of planes 320 per die 310, a specific number of blocks 330 per plane 320, and a specific number of pages 340 per block 330 are shown, but these numbers may differ from those shown. In some embodiments, the memory architecture 300 is a NAND memory architecture.

[0051] A die 310 is a structure made of a semiconductor material such as silicon. In some embodiments, a die 310 is the smallest unit in the memory that can independently execute commands. The memory device 120 may include one or more dies 310. In some embodiments, the memory device 120 may include multiple dies 310. In this case, the multiple dies 310 can each perform corresponding memory operations (e.g., read operations, write operations, or erase operations) in parallel. For example, the controller 130 of the memory device 120 may be configured to perform memory operations on multiple dies 310 simultaneously for parallel control.

[0052] Each die 310 of the memory device 120 includes one or more planes 320. A plane 320 is sometimes referred to as a memory plane. In some embodiments, the same and simultaneous (sometimes limited) operations can be performed on multiple planes 320. For example, multi-plane commands (e.g., multi-plane read commands or multi-plane write commands) can be executed simultaneously on multiple planes 320, while single-plane commands (e.g., single-plane read commands or single-plane write commands) can be executed on a single plane 320. A logic cell of the memory device 120 may contain one or more planes 320 of the die 310. In some embodiments, a logic cell may contain all planes 320 of the die 310 and may be equivalent to the die 310. Alternatively, a logic cell may contain less than all planes 320 of the die 310. A logic cell may be identified by a Logic Unit Number (LUN). Depending on the context, the term "LUN" may refer to a logic cell or an identifier (e.g., a number) of said logic cell.

[0053] Each plane 320 contains multiple blocks 330. A block 330 is sometimes referred to as a memory block. Each block 330 contains multiple pages 340. A page 340 is sometimes referred to as a memory page. A block 330 is the smallest unit of memory that can be erased. In other words, a single page 340 of a block 330 cannot be erased without erasing every other page 340 of the block 330. A page 340 is the smallest unit of memory that can be written to (i.e., the smallest unit of memory that can be programmed with data). The terms "programming" memory and "writing to" memory are used interchangeably. A page 340 may contain multiple memory cells accessible via the same access line (sometimes called a word line). In some embodiments, a block 330 may be divided into multiple sub-blocks. A sub-block is a portion of a block 330 and may contain a subset of the pages 340 of the block and / or a subset of the memory cells of the block 330.

[0054] In some implementations, read and write operations are performed on a specific page 340, while an erase operation is performed on block 330 (e.g., all pages 340 in block 330). In some implementations, to prevent memory consumption, all pages 340 of block 330 can be programmed before block 330 is erased, enabling new programming operations to be performed on pages 340 of block 330. After pages 340 are programmed with data (hereinafter referred to as "old data"), the data can be erased, but the data cannot be overwritten with new data before erasure. An erase operation would erase all pages 340 in block 330, and erasing the entire block 330 whenever new data is to replace old data would rapidly consume memory cells in block 330. Therefore, instead of performing an erase operation, new data can be stored in new pages (e.g., empty pages), as indicated by reference numeral 350, and old pages storing old data can be marked as invalid, as indicated by reference numeral 360. Next, the memory device 120 can direct the data-associated operation to the new page (e.g., in an address table) and can track invalid pages, preventing programming operations from being performed on invalid pages before the erase operation.

[0055] When block 330 meets the erase condition, memory device 120 may select block 330 for erasure, copy the valid data of block 330 (e.g., copy to a new block 330 or copy to the same block 330 after erasure), and erase block 330. For example, the erase condition may be that all pages 340 of block 330 or a threshold number or percentage of pages 340 of block 330 are not available for further programming (e.g., invalid or already storing valid data). As another example, the erase condition may be that the number or percentage of free pages 340 of block 330 (e.g., pages 340 available for writing) is less than or equal to a threshold. The process of selecting block 330 that meets the erase condition, copying the valid pages 340 of said block 330 to a new block 330 (or copying to the same block 330 after erasure), and erasing block 330 is sometimes referred to as garbage collection and is used to free up memory space in memory device 120.

[0056] As pointed out above, Figure 3 Provided as an example. Other examples are available in the section about Figure 3 The situations described are different.

[0057] Figure 4 This is a diagram illustrating example 400 of memory address translation. (See diagram for example.) Figure 4 As shown, memory device 120 may store one or more address translation tables. Address translation tables, sometimes called logical-to-physical (L2P) mapping tables, L2P address tables, or L2P tables, are used to translate logical memory addresses into physical memory addresses.

[0058] For example, memory device 120 may receive memory commands (e.g., from host device 110), which may indicate logical memory addresses, such as logical block addresses (LBAs), sometimes referred to as host addresses. Memory device 120 may use one or more address translation tables to identify physical memory addresses (sometimes referred to as physical addresses) corresponding to logical memory addresses. For example, a read command may indicate an LBA from which data will be read, or a write command may indicate an LBA to which data will be written (or to overwrite data previously written to said LBA). Memory device 120 may use L2P tables (or multiple L2P tables) to translate said LBAs (or multiple LBAs) into physical addresses associated with memory device 120. Physical addresses may indicate physical locations in non-volatile memory, such as portions of a die, plane, block, page, and / or page containing data.

[0059] In some implementations, the memory device 120 may use logical addresses called translation units (TUs), which may correspond to one or more LBAs. For example... Figure 4 As shown, entries in the L2P table can indicate a mapping between a TU (e.g., indicated by a TU index value) and the physical address where data associated with the TU is stored. Figure 4 In the TU, the physical address indicates the die, plane, block, and page.

[0060] Some embodiments described herein use multi-page TUs, where each TU contains multiple pages (e.g., spanning multiple planes of memory device 120) to reduce the size of the L2P table and thus reduce the amount of DRAM required to support L2P translation operations. To reduce the size of the L2P table, each L2P entry may map a TU (e.g., a multi-page TU) to an initial page contained within the TU, and may not indicate one or more additional pages contained within the TU (e.g., to conserve memory resources). Therefore, memory device 120 may need to identify the one or more additional pages in the multi-page TU during read address translation and / or write address translation. Some embodiments described herein enable memory device 120 to identify the one or more additional pages in the multi-page TU that are not explicitly included in L2P entries. In some cases, identifying the one or more additional pages is complex and may consume additional processing and / or memory resources. Some embodiments described herein achieve efficient read address translation and / or efficient write address translation while conserving processing and / or memory resources.

[0061] As pointed out above, Figure 4 Provided as an example. Other examples are available in the section about Figure 4 The situations described are different.

[0062] Figure 5This is a diagram illustrating an example multi-plane page 500 of a memory device. The example multi-plane page 500 comprises a three-level cell (TLC). In a TLC, a memory cell (e.g., a three-level memory cell) stores three data bits. The first bit is stored in the first page associated with the memory cell, shown as the lower page (LP), the second bit is stored in the second page associated with the memory cell, shown as the upper page (UP), and the third bit is stored in the third page associated with the memory cell, shown as the extra page (XP). Based on the page size associated with the memory device, each page is associated with multiple memory cells in the plane. For example, a 4-kilobyte page would contain 4,096 memory cells in a plane (e.g., where 1 kilobyte equals 1,024 bits). In the case of TLC, the same 4,096 memory cells are used for the lower page, upper page, and extra page, where each page of memory cells can store one information bit. Therefore, 4,096 TLC memory cells can store 12,288 bits (4,096 × 3 = 12,288).

[0063] Therefore, in Figure 5 In one example, a multi-plane page 500 spanning multiple planes of memory device 120 contains each page type of a TLC (e.g., three page types, shown as LP, UP, and XP). For example, a multi-plane page 500 spanning all planes of memory device 120 contains each page type of a TLC, where memory device 120 contains six planes (shown as planes 0 to 5). More generally, a multi-plane page may span multiple planes (e.g., all planes) of memory device 120 containing each page type of a memory cell. For example, for a single-level cell (SLC) storing one bit per memory cell, the corresponding multi-plane page will span multiple planes (e.g., all planes) of memory device 120 containing each page type of the SLC (e.g., a single page type, such as LP). As another example, for a double-level cell (DLC) or multi-level cell (MLC) storing two bits per memory cell, the corresponding multi-plane page will span multiple planes (e.g., all planes) of memory device 120 containing each page type of the DLC or MLC (e.g., two page types, such as LP and UP). As another example, for a four-level cell (QLC) that stores four bits per memory cell, the corresponding multi-plane page will span multiple planes (e.g., all planes) of memory device 120 to contain each page type of the QLC (e.g., four page types, such as LP, UP, XP and top page (TP)).

[0064] like Figure 5As shown, and by reference numeral 505, in some cases, the plane may contain one or more defective blocks. A defective block is a block that cannot be used for memory operations (e.g., read or write operations) due to an error or functional failure. For example, a defective block may be a memory block that cannot reliably store and / or retrieve data (e.g., due to physical damage, damage, manufacturing defects, errors, degradation, component malfunction, etc.). Defective blocks may be detected during manufacturing as part of a testing process (e.g., where the defective block is due to a manufacturing defect), and / or during the lifetime of the memory device (e.g., during operation of the memory device, for example, due to degradation over time). In some cases, the plane may contain one or more defective blocks and one or more good blocks.

[0065] like Figure 5 The diagram further illustrates that the block in plane 3 containing the multi-plane page 500 shown is a defective block. Therefore, the lower page, upper page, and additional pages shown cannot be used to store data in plane 3. Thus, a first multi-page TU containing four pages (as an example) and used to store data in the multi-plane page 500 shown may contain the lower page in plane 0, the lower page in plane 1, the lower page in plane 2, and the lower page in plane 4 (e.g., not the lower page in plane 3), as indicated by reference numeral 510. Similarly, as indicated by reference numeral 515, a second multi-page TU containing four pages and used to store data in the multi-plane page 500 shown may contain the lower page in plane 5, the upper page in plane 0, the upper page in plane 1, and the upper page in plane 2.

[0066] As indicated by reference numeral 520 in the figure, the initial page of the third multi-page TU is not the upper page of plane 3 (which is contained in the bad block). The initial page of the third multi-page TU, which contains four pages and is used to store data in the multi-plane page 500 shown, can be the upper page in plane 4. The multi-page TU may also contain the upper page in plane 5, the additional page in plane 0, and the additional page in plane 1.

[0067] As indicated by reference numeral 525, in order to be able to use the remaining three pages of the shown multi-plane page 500 (an additional page for plane 2, an additional page for plane 4, and an additional page for plane 5), the memory device 120 must allow for cross-plane pages, wherein a plurality of pages TU contains pages in a plurality of multi-plane pages (in Figure 5 In this example, three pages come from the shown multiplane page 500, and one page comes from the next sequential multiplane page. For example, a fourth multiplane TU containing four pages may include an additional page in plane 2, an additional page in plane 4 (skipping plane 3), an additional page in plane 5, and a lower page in the next sequential multiplane page logically following the shown multiplane page 500.

[0068] When the L2P table only indicates the initial page of a multi-page TU, allowing multiple page TUs to contain pages from different multi-plane pages complicates read and write address translation. These complexities include determining which additional pages are contained in the multi-plane TU (and which multi-plane pages those additional pages belong to), considering bad blocks, and other complexities. However, not allowing multiple page TUs to contain pages from multiple multi-plane pages leads to wasted resources. For example, in... Figure 5 In this example, three good pages will remain unused (the additional pages in planes 2, 4, and 5). This could result in an unacceptable amount of unused resources within memory device 120. Some embodiments described herein enable memory device 120 to handle the complexity associated with multi-plane pages in an efficient manner. Furthermore, some embodiments described herein can selectively enable or disable multi-plane pages based on one or more conditions, thereby achieving a balance between such complexity and potential waste of memory resources. Additional details are described elsewhere in this document.

[0069] As pointed out above, Figure 5 Provided as an example. Other examples are available in the section about Figure 5 The situations described are different.

[0070] Figure 6 This is a diagram illustrating an example 600 of a multiplanar page stripe of a memory device. Figure 6 The example multi-planar page stripe region shown (shown as page stripe region X and page stripe region Y) contains a TLC. Other example multi-planar page stripe regions may contain SLC, DLC (sometimes called MLC), QLC, five-level cell (PLC), etc.

[0071] like Figure 6 As shown, the multiplanar page stripe spans multiple dies and contains multiplanar pages, such as all dies of memory device 120 (e.g., where in Figure 6 In one example, memory device 120 includes four dies. For instance, page stripe X is shown as a first multi-plane page containing a first die (shown as die 0, which contains six planes, shown as P0 to P5), a second multi-plane page containing a second die (shown as die 1), a third multi-plane page containing a third die (shown as die 2), and a fourth multi-plane page containing a fourth die (shown as die 3). In some cases, a multi-page TU may span the multi-plane pages contained within the multi-plane page stripe, as shown by reference numerals 605 and 610.

[0072] In some cases, as indicated by reference numeral 615, to fully utilize pages, memory device 120 may allow multi-planar page bands to span, wherein a plurality of pages TU contain pages in a plurality of multi-planar page bands (in Figure 6In this example, one page comes from page strip zone X, and three pages come from page strip zone Y. In other cases, one or more pages at the end of each multi-plane page strip zone may be unused, for example... Figure 6 The final page of the page stripe X in the L2P table. However, this complicates read and write address translation when only the initial page of the multi-page TU is indicated in the L2P table. These complexities include determining which additional pages are contained in the multi-plane TU (and which multi-plane page stripes those additional pages belong to) and taking into account bad blocks, among other complexities.

[0073] Some embodiments described herein prevent multi-page TUs from containing pages from different multi-plane page stripes, thereby reducing the complexity of read and write address translation (and thus saving processing and memory resources). For example, memory device 120 may reserve one or more unused pages at the ends of a multi-plane page stripe, preventing user data from being stored in those pages, rather than allowing data to be stored across those pages using the multi-plane page stripe, thus reducing complexity. If the bad block configuration of memory device 120 changes at a later time (e.g., due to degradation during the lifetime of the memory device), then memory device 120 may unreserve one or more reserved pages, allowing user data to be stored in those pages without having to cross the multi-plane page stripe, thereby improving memory resource utilization. Additional details are described elsewhere in this document.

[0074] As pointed out above, Figure 6 Provided as an example. Other examples are available in the section about Figure 6 The situations described are different.

[0075] Figure 7 This is a diagram illustrating an example 700 of a multi-planar block stripe of a memory device. Figure 7 The illustrated multi-plane block stripe (shown as block stripe A and block stripe B) contains a TLC. Other examples of multi-plane block stripes may contain SLCs, DLCs (sometimes called MLCs), QLCs, PLCs, etc. Furthermore, in some embodiments, a multi-plane block stripe may contain multi-plane page stripes with different types of memory cells, such as a first page stripe with an SLC, a second page stripe with a TLC, and so on.

[0076] like Figure 7 As shown, a multi-planar block band region contains multiple multi-planar page band regions. For example, block band region A is shown as containing page band regions C to F, and block band region B is shown as containing page band regions G to Z.

[0077] In some cases, as indicated by reference numeral 705, to fully utilize pages, memory device 120 may allow multi-plane block stripes to be spanned, wherein a plurality of pages TU contain pages in a plurality of multi-plane block stripes (in Figure 7In this example, one page comes from block band A, and three pages come from block band B. In other cases, one or more pages at the end of each multiplane block band may be unused, for example... Figure 7 The final page of block stripe A in the L2P table. However, this complicates read and write address translation when only the initial page of the multi-page TU is indicated in the L2P table. These complexities include determining which pages are contained in the multi-plane TU (and which multi-plane block stripes those additional pages belong to) and taking into account bad blocks, among other complexities.

[0078] Some embodiments described herein prevent multi-page TUs from containing pages in different multi-plane block stripes, thereby reducing the complexity of read and write address translation (and thus saving processing and memory resources). For example, memory device 120 may reserve one or more unused pages at the ends of a multi-plane block stripe, preventing user data from being stored in those pages, rather than allowing data to be stored across those pages using the multi-plane block stripe, thus reducing complexity. If the poor block configuration of memory device 120 changes at a later time (e.g., due to degradation during the lifetime of the memory device), then memory device 120 may unreserve one or more reserved pages, allowing user data to be stored in those pages without having to cross the multi-plane block stripe, thereby improving memory resource utilization. Additional details are described elsewhere in this document.

[0079] As pointed out above, Figure 7 Provided as an example. Other examples are available in the section about Figure 7 The situations described are different.

[0080] Figure 8 This is a diagram of example 800 showing the retention and deretention of memory pages in multi-page translation units. Combined with... Figure 8 The described operations can be performed by memory device 120 and / or one or more components of memory device 120, such as controller 130 and / or one or more components of controller 130. In example 800, a multi-plane page spanning six planes (planes 0 to 5) contains a TLC, and a multi-page TU contains four pages. As described elsewhere herein, a multi-page TU may contain multiple memory pages spanning multiple memory planes of memory device 120.

[0081] As indicated by reference numeral 805, at the first moment, the multi-plane page does not contain any bad blocks. In this case, as shown, the memory device 120 can write data to the first multi-page TU, shown as TU1, in the lower pages of planes 0 to 3. The memory device 120 can store an indication of the initial page of the first multi-page TU in the L2P table, for example by storing an indication that the logical address of TU1 corresponds to the physical address corresponding to the lower page of plane 0 of the multi-plane page shown (e.g., and an indication of the die and / or block containing the multi-plane page). To conserve memory resources, the memory device 120 can prevent the storage of indications for the second, third, and fourth pages of the first multi-page TU (e.g., the lower pages of planes 1 to 3) in the L2P table.

[0082] As further illustrated, memory device 120 may write data to a second multi-page TU, shown as TU2, in the lower pages of planes 4 and 5 and the upper pages of planes 0 and 1. Memory device 120 may store an indication of the initial page of the second multi-page TU in an L2P table, for example by storing an indication that the logical address of TU2 corresponds to the physical address corresponding to the lower page of plane 4 of the multi-plane page (e.g., and an indication of the die and / or block containing the multi-plane page). To conserve memory resources, memory device 120 may prevent the storage of indications for the second, third, and fourth pages of the second multi-page TU (e.g., the lower pages of plane 5 and the upper pages of planes 0 and 1) in the L2P table.

[0083] As further shown, memory device 120 can write data to a third multi-page TU, shown as TU3, in the upper pages of planes 2 to 5. Memory device 120 can store an indication of the initial page of the third multi-page TU in an L2P table, and memory device 120 can prevent the storage of indications of the second, third, and fourth pages of the third multi-page TU in the L2P table, in a manner similar to that described above.

[0084] As further shown, memory device 120 can write data to a fourth multi-page TU, shown as TU4, in additional pages of planes 0 to 3. Memory device 120 can store an indication of the initial page of the fourth multi-page TU in an L2P table, and memory device 120 can prevent the storage of indications of the second, third, and fourth pages of the fourth multi-page TU in the L2P table, in a manner similar to that described above.

[0085] Based on writing data from the first multi-page TU to the fourth multi-page TU to the illustrated multi-plane page, memory device 120 may (under some conditions, described in more detail elsewhere herein) reserve one or more pages. For example, because memory device 120 cannot write the complete multi-page TU (e.g., all four pages containing the multi-page TU) to the multi-plane page, memory device 120 may reserve the last two pages of the multi-plane page, as indicated by reference numeral 810. Alternatively or additionally, memory device 120 may reserve one or more pages to improve read address translation, as described in more detail elsewhere herein.

[0086] When a page is reserved, memory device 120 is prohibited from storing or writing user data to that page. In other words, memory device 120 can be configured to prevent user data from being stored or written to a reserved page. This reduces the complexity associated with read address translation, where memory device 120 does not need to identify pages spanning multiple multiplane pages, multiple multiplane page bands, and / or multiple multiplane block bands within a multi-page TU. In some embodiments, memory device 120 may write non-user data to the reserved memory page, such as dummy data (e.g., all 0s or all 1s) or parity data. For example, memory device 120 may write parity data associated with one or more TUs contained in the same multiplane page as the reserved page. In this way, useful information can be stored in the reserved page (e.g., instead of dummy data), thereby improving memory utilization and / or reliability.

[0087] In some implementations, the number of pages reserved in a multi-plane page by the memory device 120 may depend on the cell type of the multi-plane page (e.g., SLC, DLC, TLC, QLC, etc.), the TU size of the multi-page TU (e.g., the number of memory pages contained in the multi-page TU), and / or the bad block configuration associated with the multi-plane page (e.g., the number and / or location of bad blocks in the multi-plane page). As an example, for Figure 8 The TLC multi-plane page shown has a total of 18 pages (6 LP, 6 UP, and 6 XP). For a TU size of four pages (e.g., four pages per multi-page TU) with no bad blocks, the memory device 120 reserves two pages (18 modulo 4 = 2). As another example, for a TU size of three pages with no bad blocks or for a TU size of two pages with no bad blocks, the memory device 120 will not reserve any pages (18 modulo 3 = 0, 18 modulo 2 = 0). As another example, for a TU size of five pages with no bad blocks, the memory device 120 will reserve three pages (18 modulo 5 = 3).

[0088] As indicated by reference numeral 815, at a later time, the bad block configuration of the multi-plane page changes, and the multi-plane page contains bad blocks. The bad block configuration can change, for example, when new bad blocks are detected during the lifetime and / or operation of the memory device 120, for example due to degradation, malfunction, damage, or error. As shown, blocks in plane 1 and plane 3, each containing the illustrated multi-plane page, are identified as bad blocks. Therefore, the illustrated lower page, upper page, and additional page cannot be used to store data in plane 1 or plane 3. Based on the detection of a new bad block configuration (e.g., new bad blocks), the memory device 120 can mark one or more reserved memory pages (e.g., all or a subset of reserved memory pages) as unreserved memory pages. This allows the memory device 120 to write user data to the unreserved memory pages previously marked as reserved memory pages.

[0089] For example, as shown in conjunction with reference numeral 815, memory device 120 (e.g., after erasing multi-plane pages and / or identifying bad blocks) may write data to a first multi-page TU (e.g., TU1) in the lower pages of planes 0, 2, 4, and 5. Similarly, memory device 120 may write data to a second multi-page TU (e.g., TU2) in the upper pages of planes 0, 2, 4, and 5. Finally, memory device 120 may write data to a third multi-page TU (e.g., TU3) in additional pages of planes 0, 2, 4, and 5. In this case, as shown by reference numeral 820, memory device 120 unreserves previously reserved pages, allowing user data (e.g., of the multi-page TU) to be written to those pages. When a page is unreserved, memory device 120 is permitted to store or write user data to said page. In other words, memory device 120 can be configured to store or write user data to unreserved memory pages. This improves the memory resource utilization of memory device 120.

[0090] As pointed out above, Figure 8 Provided as an example. Other examples are available in the section about Figure 8 The situations described are different.

[0091] Figure 9 This is a diagram of example 900 of write address translation using reserved memory pages with a multi-page translation unit. Combined with... Figure 9 The described operations may be performed by memory device 120 and / or one or more components of memory device 120, such as controller 130 and / or one or more components of controller 130.

[0092] As indicated by reference numeral 905, memory device 120 (e.g., controller 130) may receive write commands for multi-page TUs. For example, memory device 120 may receive a write command containing data of multiple memory pages to be written to a TU of memory device 120. As described elsewhere herein, the multiple memory pages of a TU (e.g., a multi-page TU) may span multiple memory planes of memory device 120. In some embodiments, memory device 120 may receive write commands from host device 110. The write command may include, for example, one or more LBAs. The one or more LBAs may correspond to one or more TUs. For example, a TU may correspond to a single LBA or multiple LBAs.

[0093] As indicated by reference numeral 910, memory device 120 (e.g., controller 130) can identify multiple memory pages of the TU to which data is to be written based on one or more bad blocks of memory device 120 and / or a determination regarding whether one or more memory pages of memory device 120 will be retained. In some embodiments, a write cursor can indicate the next page of memory device 120 to be written (e.g., using a page index, multi-plane page stripe index, block index, plane index, and / or die index). The write cursor can skip bad pages. A bad page is a page contained within a bad block. Figure 9 In the example, the page shown in plane 2 (shown as P2) of bare die 1 is a defective page, the page shown in plane 3 (shown as P3) of bare die 3 is a defective page, and the page shown in plane 5 (shown as P5) of bare die 6 is a defective page.

[0094] When writing data to a multi-page TU, memory device 120 writes to the initial page of the multi-page TU (e.g., as indicated by a write cursor), and then to one or more additional pages sequentially following the initial page, but memory device 120 skips (e.g., does not write data to) any bad pages. The number of pages written by memory device 120 depends on the TU size of the multi-page TU. For example, for a TU size of four pages, memory device 120 writes to four pages (the initial page and three additional pages).

[0095] The memory device 120 may use a page write sequence to sequentially write to pages. The page write sequence may include writing all pages across all planes within the die to a specific page type (e.g., one of LP, UP, XP, TP, etc.) (e.g., in order from the lowest indexed plane to the highest indexed plane), then writing across all planes within the die to the next page type (e.g., in the page type order of LP, UP, XP, TP, etc.), and so on. Continuing the page write sequence, after writing to all page types within the specific die, the memory device 120 writes to the next die in the same manner (e.g., writing to all planes and the specific page type before moving to the next page type).

[0096] In some implementations, each page within a multi-plane page stripe is identified using a page index value. The memory device 120 can write pages sequentially into the multi-plane page stripe based on the page index values, starting with the lowest page index value and ending with the highest page index value. Each page within the multi-plane page stripe can be identified using a different page index value. Example page index values ​​are... Figure 9 As shown in the image.

[0097] For example, for the multi-plane page stripe 915 of the SLC, the memory device 120 will follow a page write sequence, first writing to the lower page (LP) of plane 0 of die 0 (shown as having page index value 0), then writing to the lower page of plane 1 of die 0 (shown as having page index value 1), and so on, until all lower pages of die 0 have been written (e.g., from plane 0 to plane 5, shown as having page index values ​​0 to 5). Then, the memory device 120 will sequentially write across the planes of die 1 to each lower page of each plane of die 1 (with page index values ​​6 to 11), except for the lower page of plane 2 of die 1 (shown as having page index value 8), which is a bad page. Then, memory device 120 sequentially writes across planes to each lower page of each plane of die 2, and then sequentially across planes to each lower page of each plane of die 3 (except for the lower page of plane 3, which is shown as having page index value 21), die 4 and die 5 (not shown, but they do not contain any bad pages), die 6 (except for the lower page of plane 5, which is shown as having page index value 41) and die 7, and so on.

[0098] In some implementations, the memory device 120 is configured to prevent multi-plane page stripe crossings and / or multi-plane block stripe crossings to reduce complexity. In other words, the memory device 120 may prevent a multi-page TU from containing pages in multiple multi-plane page stripes and / or may prevent a multi-page TU from containing pages in multiple multi-plane block stripes. In some implementations, to prevent multi-plane page stripe crossings, the memory device 120 may reserve one or more pages at the end of a multi-plane page stripe to prevent user data from being stored in those pages. The “end” of a multi-plane page stripe refers to the last page to be written in the multi-plane page stripe. In some implementations, to prevent multi-plane block stripe crossings, the memory device 120 may reserve one or more pages at the end of a multi-plane block stripe to prevent user data from being stored in those pages. The “end” of a multi-plane block stripe refers to the last page to be written in the multi-plane block stripe. Therefore, in some implementations, all memory pages contained in a multi-page TU are contained in a single multi-plane page stripe and a single multi-plane block stripe. Although different multi-page TUs may be contained in different multi-plane page bands and / or different multi-plane block bands, each individual multi-page TU must be contained in a specific multi-plane page band and a specific multi-plane block band.

[0099] In some implementations, the number of pages retained by memory device 120 at the end of a multi-plane page stripe may depend on the cell type of the memory cells contained in the multi-plane page stripe (e.g., SLC, DLC, TLC, QLC, etc.), the TU size of the multi-page TU, and / or the configuration of bad blocks associated with the multi-plane page stripe (e.g., the number and / or location of bad blocks in the multi-plane page stripe). Because memory device 120 can retain pages that cannot form a complete multi-page TU, the number of pages retained by memory device 120 at the end of the multi-plane page stripe may be less than the number of pages contained in the multi-page TU.

[0100] As an example, for Figure 9 The SLC multiplane page stripe 915 shown has a total of 48 pages (one LP for each of the six planes in each of the eight dies). However, three of those pages are contained in bad blocks, leaving a total of 45 good pages. For a TU size of four pages, the memory device 120 reserves one page at the end of the SLC multiplane page stripe 915 because the memory device 120 can construct 11 complete TUs, filling a total of 44 pages, leaving one page (45 modulo 4 = 1). Therefore, if the memory device 120 is configured to prevent multiplane page stripe crossings, then the memory device 120 reserves one page at the end of the SLC multiplane page stripe 915 (with page index value 47).

[0101] As another example, for the multi-plane page stripe 920 of DLC (or MLC), the memory device 120 will follow a page write sequence, first writing to all lower pages (shown as having page index values ​​0 to 5) across all planes of die 0, then writing to all upper pages (shown as having page index values ​​6 to 11) across all planes of die 0, for die 1 (skipping bad pages in plane 2 of die 1, which are shown as having page index values ​​14 and 20), then for die 2, then for die 3 (skipping bad pages in plane 3 of die 3, which are shown as having page index values ​​39 and 45), then for die 4, then for die 5, then for die 6 (skipping bad pages in plane 5 of die 6, which are shown as having page index values ​​77 and 83), and then repeating the sequence for die 7. Unlike the SLC multi-plane page stripe 915 described above, the memory device 120 will write to the LP contained in plane 5 of die 7 for the DLC multi-plane page stripe 920. The memory device 120 will not retain this page in the DLC multiplane page stripe 920 because the memory device 120 will continue to write to the upper pages of the die 7, such that the lower pages of plane 5 of the die 7 and the upper pages of planes 0, 1, and 2 of the die 7 will form a TU with four pages. However, the memory device 120 will retain the last two pages of the DLC multiplane page stripe 920 (e.g., the upper pages in plane 4 and plane 5 of the die 7, with page index values ​​94 and 95).

[0102] for Figure 9 The DLC multiplanar page stripe 920 shown has a total of 96 pages (48 LPs and 48 UPs). However, 6 of those pages are contained in bad blocks, leaving 90 good pages. For a TU size of four pages, the memory device 120 reserves the two pages at the end of the DLC multiplanar page stripe 920 because the memory device 120 can construct 22 complete TUs, filling a total of 88 pages, leaving two pages remaining (90 modulo 4 = 2). Therefore, if the memory device 120 is configured to prevent multiplanar page stripe crossings, then the memory device 120 reserves the two pages at the end of the DLC multiplanar page stripe 920.

[0103] As another example, for the multi-plane page stripe 925 of the TLC, the memory device 120 will follow the page write sequence, first writing to all lower pages (with page index values ​​0 to 5) across all planes of die 0, then writing to all upper pages (with page index values ​​6 to 11) across all planes of die 0, and then writing to all additional pages (with page index values ​​12 to 17) across all planes of die 0. Then, the memory device 120 will follow the sequence for die 1 (skipping bad pages in plane 2 of die 1, shown as having page index values ​​20, 26, and 32), then for die 2, then for die 3 (skipping bad pages in plane 3 of die 3, shown as having page index values ​​57, 63, and 69), then for die 4, then for die 5, then for die 6 (skipping bad pages in plane 5 of die 6, shown as having page index values ​​113, 119, and 125), and then for die 7.

[0104] for Figure 9 The TLC multi-plane page stripe 925 shown has a total of 144 pages (48 LPs, 48 ​​UPs, and 48 XPs). However, nine of those pages are contained in bad blocks, leaving a total of 135 good pages. For a TU size of four pages, the memory device 120 reserves the three pages at the end of the TLC multi-plane page stripe 925 because the memory device 120 can construct 33 complete TUs, filling a total of 132 pages, leaving three pages remaining (135 modulo 4 = 3). Therefore, if the memory device 120 is configured to prevent multi-plane page stripe crossings, then the memory device 120 reserves the three pages at the end of the TLC multi-plane page stripe 925 (e.g., extra pages in plane 3 of die 7, extra pages in plane 4 of die 7, and extra pages in plane 5 of die 7, which have page index values ​​141, 142, and 143).

[0105] Therefore, when writing data to a multi-page TU, the memory device 120 can identify pages contained in the multi-page TU based on one or more bad blocks and / or a determination of whether one or more pages (and which memory pages) will be retained. For example, the memory device 120 can skip bad pages (e.g., prevent writing to those pages and / or exclude those pages from the multi-page TU) and can skip retained pages (e.g., by identifying retained pages, such as one or more pages at the end of a multi-plane page stripe that cannot form a complete multi-page TU).

[0106] After identifying the pages of a multi-page unit (and excluding bad and reserved pages from the multi-page TU), the memory device 120 may write data contained in a write command to the identified pages. In some embodiments, the memory device 120 may store an indication of the initial page of the multi-page TU in an L2P table, such as the first sequential page in the multi-page TU (e.g., and an indication of the die and / or block containing the multi-plane page). To conserve memory resources, the memory device 120 may prevent the storage of indications of any additional pages of the multi-page TU in the L2P table.

[0107] In some embodiments, memory device 120 may (e.g., in memory 140) store a data structure indicating one or more bad blocks (e.g., a set of bad blocks), sometimes referred to as a bad block data structure. The bad block data structure may indicate one or more bad blocks (e.g., using block identifiers) and / or one or more bad pages (e.g., using page identifiers, such as page index values). Memory device 120 may use the bad block data structure (e.g., a bad block table) to determine whether any memory pages will be retained and / or to identify memory pages to be retained. In some embodiments, memory device 120 may also (e.g., in memory 140) store a retention configuration indicating one or more memory pages to be retained (e.g., a set of retained memory pages), which may be based on the one or more bad blocks, TU size, and / or cell type (as described above). Memory device 120 may use the bad block table and / or retention configuration when identifying pages to be included in a multi-page TU (e.g., to identify bad pages to be skipped or retained pages).

[0108] If the memory device 120 detects a new bad block (e.g., based on a detected error or another condition associated with the block), the memory device 120 may store an indication of the new bad block in a bad block data structure. The memory device 120 may then modify the retention configuration based on the updated bad block table (and / or TU size and / or cell type). In some cases, detecting a new bad block may result in a number of retained pages exceeding the number before the bad block was detected. In other cases, detecting a new bad block may result in a number of retained pages falling short of the number before the bad block was detected. In either case, the memory device 120 may update the retention configuration to indicate the retained pages.

[0109] As pointed out above, Figure 9 Provided as an example. Other examples are available in the section about Figure 9 The situations described are different.

[0110] Figure 10 This is a diagram of example 1000 of read address translation using reserved memory pages with a multi-page translation unit. Combined with... Figure 10The described operations may be performed by memory device 120 and / or one or more components of memory device 120, such as controller 130 and / or one or more components of controller 130.

[0111] As indicated by reference numeral 1005, memory device 120 (e.g., controller 130) may receive read commands for multiple page TUs. In some embodiments, memory device 120 may receive read commands from host device 110. A read command may include, for example, one or more LBAs. The one or more LBAs may correspond to one or more TUs. For example, a TU may correspond to a single LBA or multiple LBAs.

[0112] As indicated by reference numeral 1010, memory device 120 can identify the initial page of a multi-page TU based on an L2P mapping table. In some embodiments, entries in the L2P mapping table (sometimes referred to as L2P entries or L2P table entries) may indicate a TU (e.g., using a TU index value), such as a multi-page TU, and may indicate the initial page associated with said TU (e.g., using a page identifier, such as a page index value). To conserve memory resources, an L2P entry may indicate only a single page associated with a multi-page TU, rather than indicating multiple pages or all pages associated with a multi-page TU. In some embodiments, said single page is the initial page, such as the first sequential page of the multi-page TU (e.g., according to the page write sequence, as described above). Figure 9 (The sequence described).

[0113] In some implementations, a page identifier included in an L2P entry can uniquely identify a page of memory device 120 (e.g., across the entire memory device 120, encompassing all dies, blocks, planes, and / or other memory cells). Alternatively, a page identifier (e.g., a page index value) can identify a page within a memory cell, such as a page within a multi-plane page stripe. For example, a page can be identified using a die identifier that identifies the die containing the page, a plane identifier that identifies the plane containing the page, a block identifier that identifies the block containing the page, a multi-plane page stripe identifier that identifies the multi-plane page stripe, and / or a page identifier that identifies the page (e.g., within a die, plane, block, and / or multi-plane page stripe). Memory device 120 can identify the initial page of the TU by performing a lookup of the TU (e.g., using the TU index value, which may be determined based on LBA and / or other information indicated in a read command), and then identifying the page indicated in the L2P entry (e.g., via the page index value).

[0114] As indicated by reference numeral 1015, memory device 120 may identify one or more additional pages of a multi-page TU based on an initial page and indications of one or more defective blocks of memory device 120 (which may indicate one or more reserved memory pages of memory device 120). For example, a multi-page TU may contain an initial page and one or more additional pages. In some embodiments, the initial page is indicated in an L2P table (as described above), while the one or more additional pages are not indicated in an L2P table. For example, if a multi-page TU contains four pages, then one of the four pages (e.g., the initial page) may be indicated in an L2P table, while the remaining three of the four pages (e.g., the additional pages) may not be indicated in an L2P table. Therefore, memory device 120 may need to determine the one or more additional pages based on the initial page and one or more techniques described herein.

[0115] As described elsewhere herein, multiple pages of a TU (e.g., a multi-page TU) may span multiple planes of the memory device 120. For example, the initial page of a multi-page TU may be contained in a first plane (sometimes referred to as the initial plane) among the multiple planes, and the one or more additional pages may be contained in one or more additional planes among the multiple planes. In some cases (e.g., depending on the number of planes in the memory device 120, bad block configuration, and / or reserved configuration), each page of a multi-page TU is contained in a different plane. However, in some cases, two or more pages of a multi-page TU may be contained in the same plane (e.g., but different pages or page types of the plane).

[0116] In some implementations, to identify the one or more additional pages of a multi-page TU, the memory device 120 may perform a bad block determination (sometimes called a bad block search). The memory device 120 may perform a bad block determination to determine whether any page in a sequence of pages following the initial page of the multi-page TU is contained in a bad block. The number of sequential pages may be based on the TU size (and may be additional pages in the TU besides the initial page). For example, for a TU size of four pages, there is one initial page and three additional pages. Therefore, the memory device 120 may determine whether any of the three pages sequentially following the initial page are contained in a bad block. When reading data from the TU, the memory device 120 may skip all pages contained in the bad block (based on the bad block determination).

[0117] To perform bad block determination, memory device 120 may read a bad block data structure. As described elsewhere herein, the bad block data structure may indicate one or more bad blocks (e.g., using block identifiers) and / or one or more bad pages (e.g., using page identifiers, such as page index values). In some embodiments, the bad block data structure may indicate page index values ​​of bad pages for different types of multi-plane page stripes (e.g., SLC, DLC, TLC, etc.). Figure 10 In the example, the bad block data structure can indicate that the pages with index values ​​8, 21, and 41 in SLC multiplane page strip 915 are bad pages, the pages with index values ​​14, 20, 39, 45, 77, and 83 in DLC multiplane page strip 920 are bad pages, and the pages with index values ​​20, 36, 32, 57, 63, 69, 113 and 119, 125 in TLC multiplane page strip 925 are bad pages.

[0118] However, in some implementations, for multi-plane page stripes with memory cells storing two or more bits per memory cell (e.g., for DLC, TLC, etc.), it is not explicitly stored that all these page index values ​​are represented. The bad block data structure may store only a single page index value per bad block (e.g., an indication of only the initial page for each plane containing the bad block). For example, instead of storing an indication that pages with page index values ​​14 and 20 are bad pages, the bad block data structure may store only an explicit indication of page index value 14, and the memory device 120 may use an offset value equal to the number of die planes to identify additional bad pages. Figure 10 In this example, each die has six planes. Therefore, for the DLC multi-plane page stripe 920, the memory device uses the indication of page index 14 to determine that the page with page index 20 (14+6=20) is also a bad page. Similarly, for the TLC multi-plane page stripe 925, the memory device uses the indication of page index 20 to determine that the page with page index 26 (20+6=26) and the page with page index 32 (20+6+6=32) are also bad pages. In this way, the amount of memory required for the bad block data structure can be reduced.

[0119] Based on the read bad block data structure, memory device 120 can determine a set of page index values, sometimes referred to as bad page index values, for a set of bad pages in a multi-plane page band region indicating the location of the initial page. Memory device 120 can use the first page index value of the initial page that identifies the multi-plane page TU being read to identify a second page index value contained within the set of bad page index values. For example, memory device 120 can identify the second page index value as the page index value closest to the first page index value (of the initial page) among all bad page index values ​​greater than the first page index value (associated with the same multi-plane page band region as the first page index value). In other words, memory device 120 can identify the lowest bad page index value greater than the first page index value of the initial page (e.g., because memory device 120 needs to determine whether any subsequent pages of the initial page are bad pages within the TU size).

[0120] After identifying a second page index value from the set of bad page index values, the memory device 120 may determine whether the second page index value is within an offset threshold of the first page index value. The offset threshold may be based on the TU size (e.g., equal to the number of extra pages, the TU size minus one, or in some cases equal to the TU size). The memory device 120 may identify the one or more extra pages of the TU based on whether the second page index value is within the offset threshold of the first page index value. If the second page index value is within the offset threshold of the first page index value, then the page with the second page index value may be skipped (e.g., not read, because the page is not included in the multi-page TU). In this case, the initial page and the one or more extra pages are non-sequential and have at least one non-contiguous page index value.

[0121] If the second page index value is not within the offset threshold of the first page index value, then the page with the second page index value can be read (e.g., because the page is contained in a multi-page TU). In this case, the initial page and the one or more additional pages are sequential and have consecutive page index values.

[0122] As an example, memory device 120 may receive a read command indicating a multi-page TU, wherein the initial page within the SLC multi-plane page stripe 915 has a page index value of 0. As described elsewhere herein, memory device 120 may determine the initial page index value of 0 based on the L2P entries of the multi-page TU. Memory device 120 may determine that pages 8, 21, and 41 are bad pages within the SLC multi-plane page stripe 915, such as... Figure 10 As shown in the diagram. The lowest page index value among the bad page index values ​​8, 21, and 41 that is greater than the initial page index value 0 is 8. In this example, the TU size is four, and the number of extra pages is three (e.g., one less than the TU size). The memory device 120 can determine that the second page index value (8) is not within the offset threshold (3) of the initial page index value (0). Therefore, the memory device 120 can read from the three sequential pages following page 0. In this example, the pages of the multi-page TU are sequential, and the memory device 120 can read the multi-page TU from consecutive pages 0, 1, 2, and 3.

[0123] As another example, memory device 120 can receive a read command indicating multiple pages TU, wherein the initial page has a page index value 38 within the SLC multi-plane page stripe 915. Similarly, memory device 120 can determine that pages 8, 21, and 41 are bad pages within the SLC multi-plane page stripe 915, such as... Figure 10As shown in the diagram. The lowest page index value among the bad page index values ​​8, 21, and 41 that is greater than the initial page index value 38 is 41. In this example, the TU size is four, and the number of extra pages is three (e.g., one less than the TU size). The memory device 120 can determine that the second page index value (41) is within an offset threshold (3) of the initial page index value (38) (e.g., 38 + 3 = 41). Therefore, the memory device 120 can skip page 41 when reading a multi-page TU and can read the next page after page 41 (unless said page is also a bad page). For example, the memory device 120 can read from non-contiguous pages 38, 39, 40, and 42 (e.g., reading a multi-page TU with four pages, where page 41 is a bad page), which are also non-sequential.

[0124] If no bad page has an index value greater than the initial page index value, then the memory device 120 can read from the three sequential pages following the initial page index value. For example, for the initial page index value 43 in the SLC multiplane page stripe 915 (where the highest bad page index is 41), the memory device 120 can read multipage TUs from pages 43, 44, 45, and 46, which are sequential and have consecutive page index values. Using this technique, the memory device 120 will not attempt to read user data from reserved pages because writing data to multipage TUs (as described above)... Figure 9 When described, memory device 120 will not (in the L2P table) store page index values ​​that would result in reads via reserved pages.

[0125] After identifying pages of a multi-page TU (e.g., the initial page and one or more additional pages), the memory device 120 can read data from the identified pages. In some embodiments, the memory device 120 can provide the read data to the host device 110.

[0126] As pointed out above, Figure 10 Provided as an example. Other examples are available in the section about Figure 10 The situations described are different.

[0127] Figure 11 This is a diagram of example 1100 of write address translation using reserved memory pages with a multi-page translation unit. (Combined with...) Figure 11 The described operations may be performed by memory device 120 and / or one or more components of memory device 120, such as controller 130 and / or one or more components of controller 130.

[0128] As indicated by reference numeral 1105 in the accompanying drawings, the memory device 120 (e.g., controller 130) can receive write commands for multiple page TUs, as described above. Figure 9As described by reference numeral 905. As shown by reference numeral 1110, memory device 120 (e.g., controller 130) can identify multiple memory pages of the TU to which data will be written based on one or more bad blocks of memory device 120 and / or a determination of whether one or more memory pages of memory device 120 will be reserved.

[0129] exist Figure 9 In Example 900, memory device 120 reserves one or more pages at the end of each multiplane page stripe, which cannot form a complete TU (with a TU size configured from memory device 120). This technique maximizes page utilization while prohibiting multiplane page stripe crossings, but may complicate bad block identification, thus consuming processing resources during read address translation, as described above. Figure 10 As described. Combined with Figure 11-15 The described technique reduces the complexity and processing resources required for read address translation.

[0130] In some implementations, when writing data to a multi-page TU, the memory device 120 can identify a multi-plane page (sometimes referred to as the initial multi-plane page) containing the initial memory page of the multi-page TU. For example, the memory device 120 can locate a write cursor that indicates the initial memory page and / or the multi-plane page containing the initial memory page. The memory device 120 can determine whether the multi-plane page contains any bad blocks (e.g., bad pages), and can also determine whether the next sequential multi-plane page following the said multi-plane page contains any bad blocks. The next sequential multi-plane page is the next multi-plane page to be written in the same multi-plane page stripe (e.g., the next die). For example, if the initial page of SLC multi-plane page stripe 1115 has page index 0, then the initial multi-plane page contains pages 0 to 5 on die 0, and the next sequential multi-plane page contains pages 6 to 10 on die 1.

[0131] If the initial multiplane page does not contain any bad blocks (e.g., determined according to a bad block data structure) and the next sequential multiplane page does not contain any bad blocks (e.g., determined according to a bad block data structure), then memory device 120 may prevent the retention of any memory page of the initial multiplane page and may prevent the retention of any memory page of the next sequential multiplane page. This helps improve resource utilization. For example, in SLC multiplane page stripe 1115, memory device 120 does not retain any pages of die 0 and does not retain any pages of die 1. In some embodiments, if the initial multiplane page (e.g., the initial page containing the TU to be written) does not contain any bad blocks, then the initial page may be selected to have an even page index value (e.g., 0, 2, 4, etc.) or a page index value that otherwise satisfies a certain condition. Alternatively, if the initial multiplane page does not contain any bad blocks, then the initial page may be selected such that the plane index value of the plane containing the initial page is even (e.g., 0, 2, 4, etc.) or otherwise satisfies a certain condition. This simplifies read address translation, as described in more detail elsewhere in this article.

[0132] When memory device 120 does not retain any pages in a contiguous multiplane page, memory device 120 may select sequential pages (one or two of those multiplane pages) for writing to the multipage TU. For example, memory device 120 may select a set of sequential memory pages that are all contained within an initial multiplane page, such as pages 0 through 3 (e.g., when the initial page is page 0). As another example, memory device 120 may select a first set of sequential memory pages contained within the initial multiplane page and a second set of sequential memory pages contained within the next sequential multiplane page, such as pages 4 through 7 (e.g., when the initial page is page 4). In some embodiments, this span of multiplane pages only occurs when the number of each die plane is not a power of two (e.g., not 2). n In cases such as 2, 4, 8, 16, etc., for example in Figure 11 In other words, for some combination of TU size and per die plane, the span of multiplane pages may not be necessary to construct a complete TU having the TU size when there are no bad blocks in the multiplane pages.

[0133] If the initial multiplane page contains a bad block (e.g., determined according to a bad block data structure) or the next sequential multiplane page contains a bad block (e.g., determined according to a bad block data structure), then the memory device 120 may reserve at least one memory page of the initial multiplane page. For example, if the initial multiplane page contains a bad block, then the memory device 120 may reserve at least one memory page such that the page index value of the initial page and / or the plane index value of the memory plane containing the initial memory page is odd (e.g., 1, 3, 5, etc.) or otherwise satisfies a certain condition. For example, in SLC multiplane page stripe 1115, if the initial page is in die 3 having a bad page (page 21) in plane 3, then the memory device 120 reserves page 18 (in plane 0 of die 3). This makes page 19 (odd-numbered page) in plane 1 (odd-numbered plane) the initial page of the multiplane page TU. Using even-numbered page indices and / or plane indices for the initial page when there are no bad blocks in the initial multi-page plane, and using odd-numbered page indices and / or plane indices for the initial page when there are at least one bad block in the initial multi-page plane, simplifies read address translation, as described in more detail elsewhere in this document.

[0134] As another example, if the next sequential multiplane page contains a bad block, then the memory device 120 may reserve at least one memory page at the end of the initial multiplane page, for example, when the remaining number of unwritten pages in the initial multiplane page is less than the TU size. For example, in SLC multiplane page stripe 1115, if the initial page is page 12 (in plane 0 of die 2, which does not have a bad block), then the memory device 120 may write a multi-page TU to pages 12 through 15. To avoid crossing to the next sequential multiplane page (of die 3) containing a bad block, the memory device 120 may reserve pages 16 and 17 at the end of the multiplane page of die 2, because the memory device 120 cannot form a complete TU with four pages within the multiplane page of die 2. This simplifies read address translation because, in conjunction with the above... Figure 10 The bad blocks described need to be removed.

[0135] When the memory device 120 reserves a page, the memory device 120 does not write user data to the page, and the page is not included in the multi-page TU. (Except in combination) Figure 11 In addition to the techniques described, memory device 120 may reserve one or more pages at the end of a multi-page stripe (e.g., when a complete TU cannot be formed), as described above. Figure 9 As described herein. Furthermore, the memory device 120 can cancel reserved pages, and / or can reserve different pages after a new bad block is detected, as described elsewhere herein. Additionally, for DLC multiplane page stripe 1120 and / or for TLC multiplane page stripe 1125, the memory device 120 can combine... Figure 11Pages are reserved in a similar manner as described. Use Figure 11 Additional details of the technology are provided below. Figure 12-15 describe.

[0136] As pointed out above, Figure 11 Provided as an example. Other examples are available in the section about Figure 11 The situations described are different.

[0137] Figure 12 It uses the above text in combination Figure 11 The described technique involves write address translation and read address translation, as illustrated in Figure 1200. Combined with... Figure 12 The described operations may be performed by memory device 120 and / or one or more components of memory device 120, such as controller 130 and / or one or more components of controller 130.

[0138] As indicated by reference numeral 1205, the memory device 120 (e.g., controller 130) can receive write commands for multiple pages TU, as described above. Figure 9 As described by reference numeral 905. As shown by reference numeral 1210, memory device 120 (e.g., controller 130) can determine that the initial multiplane page (e.g., the initial page containing data to be written) and the next sequential multiplane page (as described elsewhere herein) do not contain any bad blocks. For example, memory device 120 may make this determination when identifying the pages of the multiplane TU to which data will be written.

[0139] As indicated by reference numeral 1215 in the attached figure, Figure 12 In this context, the initial multiplane page is a TLC multiplane page containing six planes (planes 0 to 5) on die 0, and the next sequential multiplane page is a TLC multiplane page containing six planes (planes 0 to 5) on die 1. As shown in the figure, there are no bad blocks (or bad pages) in these multiplane pages. Therefore, the memory device 120 can prevent any memory page from being retained as the initial multiplane page, and can also prevent any memory page from being retained as the next sequential multiplane page, as described above. Figure 11 As described. Furthermore, memory device 120 can enable multi-plane page spanning. This helps improve resource utilization. For example, all pages of the initial multi-plane page and the next sequential multi-plane page are written to multi-page TUs, such as the first multi-page TU in planes 0 to 3 of die 0, the second multi-page TU in planes 4 and 5 of die 0, and the UP of planes 0 and 1 of die 0, etc.

[0140] As indicated by reference numeral 1220, the memory device 120 (e.g., controller 130) can receive read commands for multiple pages TU, as described above. Figure 10As described by reference numeral 1005. As shown by reference numeral 1225, memory device 120 (e.g., controller 130) can identify the initial page of a multi-page TU based on an L2P mapping table, as described elsewhere herein.

[0141] As indicated by reference numeral 1230, the memory device 120 (e.g., controller 130) can identify one or more additional pages of the multi-page TU based on an index value associated with the initial page. The index value can be, for example, a plane index value (e.g., identifying the plane containing the initial page) or a page index value (e.g., identifying the initial page, as described above). Figure 9-11 (Described page index value). The memory device 120 may use an L2P mapping table to determine the index value. For example, an L2P entry may indicate a TU (e.g., a multi-page TU), and may also indicate the plane index value and / or page index value associated with the initial page of the TU.

[0142] Memory device 120 may use an index value to identify one or more additional pages of a multi-page TU. For example, if the index value meets a certain condition (e.g., a first condition), then memory device 120 may identify sequential (or consecutive) pages (e.g., the initial page and the one or more additional pages) as pages of a multi-page TU. As an example, if the index value (e.g., a plane index value or a page index value) is even, then memory device 120 may identify sequential pages (e.g., the initial page and the one or more additional pages) as pages of a multi-page TU. Alternatively or additionally, if the index value meets the first condition (e.g., it is even), then memory device 120 may prevent the above combination from being performed when identifying the one or more additional memory pages. Figure 10 The bad blocks described were identified. This saves processing resources and simplifies read address translation.

[0143] After identifying pages of a multi-page TU (e.g., the initial page and one or more additional pages), the memory device 120 can read data from the identified pages. In some embodiments, the memory device 120 can provide the read data to the host device 110.

[0144] As pointed out above, Figure 12 Provided as an example. Other examples are available in the section about Figure 12 The situations described are different.

[0145] Figure 13 It uses the above text in combination Figure 11 The described technique involves write address translation and read address translation, as illustrated in Figure 1300. Combined with... Figure 13 The described operations may be performed by memory device 120 and / or one or more components of memory device 120, such as controller 130 and / or one or more components of controller 130.

[0146] As indicated by reference numeral 1305, the memory device 120 (e.g., controller 130) can receive write commands for multiple pages TU, as described above. Figure 9 As described by reference numeral 905. As indicated by reference numeral 1310, memory device 120 (e.g., controller 130) can determine that an initial multi-plane page (e.g., containing the initial page to be written) contains bad blocks (e.g., at least one bad block). For example, memory device 120 can make this determination when identifying a page of a multi-page TU to which data is to be written, as described above. Figure 9 and 11 As described.

[0147] As indicated by reference numeral 1315 in the attached figure, Figure 13 In this context, the initial multiplane page is a TLC multiplane page comprising six planes (planes 0 to 5). As shown, plane 2 contains bad blocks from the pages of the multiplane page (e.g., pages with corresponding page indices 2, 8, and 14). Therefore, memory device 120 can reserve one or more memory pages of the initial multiplane page, as described above. Figure 11 As described. In some embodiments, memory device 120 may reserve one or more memory pages such that the index value associated with the initial memory page to be written (e.g., the page index value of the initial memory page or the plane index value of the memory plane containing the initial memory page) satisfies a certain condition (e.g., a second condition) so that it has an odd value. Alternatively or additionally, memory device 120 may disable multi-plane page traversal, which reduces the complexity associated with read address translation.

[0148] For example, in Figure 13 In the diagram, memory device 120 reserves the first page of a multi-plane page, shown as having page index value 0 and contained in a plane with plane index value 0. This prevents the initial page of the TU from being associated with an even-numbered page index value and / or an even-numbered plane index value. Memory device 120 may use a page with page index value 1 (and contained in a plane with plane index value 1) as the initial page, which has an odd value. During read address translation, this can be signaled to indicate the need to perform bad block determination to identify the one or more additional pages. Because page 2 is a bad page, the first multi-page TU of the illustrated multi-plane page contains pages 1, 3, 4, and 5.

[0149] When writing the second multi-page TU to the illustrated multi-plane page, memory device 120 reserves page 6 (an even-numbered page) instead of using page 6 as the initial page of the second multi-page TU, and memory device 120 uses page 7 (an odd-numbered page) as the initial page of the second multi-page TU, similarly signaling that bad block determination will be performed during read address translation. Similarly, when writing the third multi-page TU to the illustrated multi-plane page, memory device 120 reserves page 12 instead of using page 12 as the initial page of the third multi-page TU, and memory device 120 uses page 13 (an odd-numbered page) as the initial page of the third multi-page TU, similarly signaling that bad block determination will be performed during read address translation.

[0150] As indicated by reference numeral 1320, the memory device 120 (e.g., controller 130) can receive read commands for multiple pages TU, as described above. Figure 10 As described by reference numeral 1005. As shown by reference numeral 1325, memory device 120 (e.g., controller 130) can identify the initial page of a multi-page TU based on an L2P mapping table, as described elsewhere herein.

[0151] As indicated by reference numeral 1330, memory device 120 (e.g., controller 130) can identify one or more additional pages of a multi-page TU based on an index value associated with the initial page (e.g., a plane index value or a page index value, as described elsewhere herein).

[0152] Memory device 120 can use an index value to identify one or more additional pages of a multi-page TU. For example, if the index value meets a second condition (e.g., it is odd), then memory device 120 can perform bad block determination, as described above. Figure 9 As described, the memory device 120 can select an index value associated with the initial page during write address translation (e.g., by reserving or preventing the reservation of one or more pages) to signal whether bad block determination needs to be performed during read address translation. For example, if the memory device 120 selects an even index value (e.g., 0), this indicates that there are no bad blocks in the multi-plane pages containing the initial page, and the memory device 120 can abandon bad block determination after the initial page is identified during read address translation (e.g., and can read from consecutive pages in the multi-page TU). However, if the memory device 120 selects an odd index value, this indicates that at least one bad block exists in the multi-plane pages containing the initial page, and the memory device 120 must perform bad block determination after the initial page is identified during read address translation (e.g., to identify which pages to skip during read address translation of the multi-page TU). This saves processing resources compared to performing bad block determination during each read address translation.

[0153] After identifying pages of a multi-page TU (e.g., the initial page and one or more additional pages), the memory device 120 can read data from the identified pages. In some embodiments, the memory device 120 can provide the read data to the host device 110.

[0154] As pointed out above, Figure 13 Provided as an example. Other examples are available in the section about Figure 13 The situations described are different.

[0155] Figure 14 It uses the above text in combination Figure 11 The described technique involves write address translation and read address translation, as illustrated in Figure 1400. Combined with... Figure 14 The described operations may be performed by memory device 120 and / or one or more components of memory device 120, such as controller 130 and / or one or more components of controller 130.

[0156] As indicated by reference numeral 1405, the memory device 120 (e.g., controller 130) can receive write commands for multiple page TUs, as described above. Figure 9 As described by reference numeral 905. As shown by reference numeral 1410, memory device 120 (e.g., controller 130) can determine that an initial multi-plane page (e.g., containing the initial page to be written) contains bad blocks (e.g., at least one bad block). For example, memory device 120 can make this determination when identifying the page of the multi-page TU to which data is to be written, as described above. Figure 9 and 11 As described.

[0157] As indicated by reference numeral 1415 in the attached figure, Figure 14 In this context, the initial multiplane page is a TLC multiplane page containing six planes (planes 0 to 5). As shown, planes 1 and 4 each contain bad blocks in pages of the multiplane page shown (e.g., pages with corresponding page indices 1, 4, 7, 10, 13, and 16). Therefore, memory device 120 can reserve one or more memory pages of the initial multiplane page, as described above. Figure 11 As described. In some embodiments, memory device 120 may reserve one or more memory pages such that the index value associated with the initial memory page to be written (e.g., the page index value of the initial memory page or the plane index value of the memory plane containing the initial memory page) satisfies a certain condition (e.g., a second condition) so that it has an odd value. Alternatively or additionally, memory device 120 may disable multi-plane page traversal, which reduces the complexity associated with read address translation.

[0158] For example, in Figure 14In the diagram, memory device 120 reserves the first page of the multi-plane page, shown as having page index value 0 and contained in a plane with plane index value 0. This prevents the initial page of the TU from being associated with an even-numbered page index value and / or an even-numbered plane index value. Memory device 120 may skip bad pages with page index value 1. Memory device 120 may also reserve pages with page index value 2 (and contained in a plane with plane index value 2) to prevent the initial page of the TU from being associated with an even-numbered page index value and / or an even-numbered plane index value. Memory device 120 may use a page with page index value 3 (and contained in a plane with plane index value 3) as the initial page, which has an odd value. During read address translation, this can be signaled to indicate the need to perform bad block determination to identify the one or more additional pages. Because pages 1 and 4 are bad pages, the first multi-page TU of the illustrated multi-plane page contains pages 3, 5, 6, and 8.

[0159] When writing the second multi-page TU to the illustrated multi-plane page, memory device 120 uses the next available page, shown as page 9, as the initial page of the second multi-page TU (instead of reserving the page), because 9 is an odd number. This signals the need to perform a bad block determination during read address translation. The second multi-page TU of the illustrated multi-plane page comprises pages 9, 11, 12, and 14. Memory device 120 then reserves pages 15 and 17 because the multi-plane page spans deprecation, and these two pages cannot form a complete TU (with a size of four pages).

[0160] As indicated by reference numeral 1420, the memory device 120 (e.g., controller 130) can receive read commands for multiple pages TU, as described above. Figure 10 As described by reference numeral 1005. As shown by reference numeral 1425, memory device 120 (e.g., controller 130) can identify the initial page of a multi-page TU based on an L2P mapping table, as described elsewhere herein. As shown by reference numeral 1430, memory device 120 (e.g., controller 130) can identify one or more additional pages of a multi-page TU based on an index value associated with the initial page (e.g., a plane index value or a page index value, as described elsewhere herein). Because the index value associated with the initial page is odd, memory device 120 can perform bad block determination to identify the one or more additional pages, as described above in conjunction with... Figure 9 and Figure 13 As described.

[0161] After identifying pages of a multi-page TU (e.g., the initial page and one or more additional pages), the memory device 120 can read data from the identified pages. In some embodiments, the memory device 120 can provide the read data to the host device 110.

[0162] As pointed out above, Figure 14Provided as an example. Other examples are available in the section about Figure 14 The situations described are different.

[0163] Figure 15 It uses the above text in combination Figure 11 The described technique involves write address translation and read address translation, as illustrated in Figure 1500. Combined with... Figure 15 The described operations may be performed by memory device 120 and / or one or more components of memory device 120, such as controller 130 and / or one or more components of controller 130.

[0164] As indicated by reference numeral 1505, the memory device 120 (e.g., controller 130) can receive write commands for multiple page TUs, as described above. Figure 9 As described by reference numeral 905. As indicated by reference numeral 1510, memory device 120 (e.g., controller 130) can determine that an initial multi-plane page (e.g., containing the initial page to be written) contains bad blocks (e.g., at least one bad block). For example, memory device 120 can make this determination when identifying a page of a multi-page TU to which data is to be written, as described above. Figure 9 and 11 As described.

[0165] As indicated by reference numeral 1515 in the attached figure, Figure 15 In this context, the initial multiplane page is a TLC multiplane page containing six planes (planes 0 to 5). As shown, planes 0, 1, and 2 each contain a bad block in a page of the illustrated multiplane page (e.g., a page with corresponding page indices 0, 1, 2, 6, 7, 8, 12, 13, and 14). Therefore, memory device 120 can reserve one or more memory pages of the initial multiplane page, as described elsewhere herein.

[0166] For example, in Figure 15 In this example, memory device 120 uses page 3 (of plane 3) as the initial page because the index values ​​(e.g., page index value and plane index value) are odd. During read address translation, this can be signaled to indicate the need to perform bad block determination to identify the one or more additional pages. Because pages 6, 7, and 8 are bad pages, the first multi-page TU of the illustrated multi-plane page includes pages 3, 4, 5, and 9.

[0167] When writing the second multi-page TU to the illustrated multi-plane page, memory device 120 reserves page 10 because page 10 is an even-numbered page. Then, memory device 120 uses page 11 as the initial page of the second multi-page TU because 11 is an odd number, which signals the need to perform bad block determination during read address translation. The second multi-page TU of the illustrated multi-plane page contains pages 11, 15, 16, and 17. In this case, memory device 120 does not need to reserve any pages at the end of the multi-plane page.

[0168] As indicated by reference numeral 1520, the memory device 120 (e.g., controller 130) can receive read commands for multiple pages TU, as described above. Figure 10 As described by reference numeral 1005. As shown by reference numeral 1525, memory device 120 (e.g., controller 130) can identify the initial page of a multi-page TU based on an L2P mapping table, as described elsewhere herein. As shown by reference numeral 1530, memory device 120 (e.g., controller 130) can identify one or more additional pages of a multi-page TU based on an index value associated with the initial page (e.g., a plane index value or a page index value, as described elsewhere herein). Because the index value associated with the initial page is odd, memory device 120 can perform bad block determination to identify the one or more additional pages, as described above in conjunction with... Figure 9 and Figure 13 As described.

[0169] After identifying pages of a multi-page TU (e.g., the initial page and one or more additional pages), the memory device 120 can read data from the identified pages. In some embodiments, the memory device 120 can provide the read data to the host device 110.

[0170] As pointed out above, Figure 15 Provided as an example. Other examples are available in the section about Figure 15 The situations described are different.

[0171] Figure 16This is a flowchart of an example method 1600 associated with read and write address translation using reserved memory pages with a multi-page translation unit. In some embodiments, a memory device (e.g., memory device 120) is executable or configurable to perform method 1600. In some embodiments, another device or set of devices, separate from or including the memory device (e.g., system 100), is executable or configurable to perform method 1600. Alternatively or additionally, one or more components of the memory device (e.g., controller 130, memory management component 225, address translation component 230, page reservation component 235, and / or command execution component 240) are executable or configurable to perform method 1600. Thus, the components for performing method 1600 may include the memory device and / or one or more components of the memory device. Alternatively or additionally, a non-transitory computer-readable medium may store one or more instructions that, when executed by the memory device (e.g., controller 130 of memory device 120), cause the memory device to perform method 1600.

[0172] like Figure 16 As shown, method 1600 may include identifying a TU associated with a read command, wherein the TU comprises multiple memory pages spanning multiple memory planes of a memory device (box 1610). Figure 16 As further shown, method 1600 may include identifying an initial memory page (box 1620) among the plurality of memory pages of the TU based on a logical-to-physical mapping table. Figure 16 As further shown, method 1600 may include identifying one or more additional memory pages of the plurality of memory pages of the TU based on an initial memory page and based on at least one of the following: an indication of one or more bad blocks of the memory device, or identifying the initial memory page or identifying an index value of a memory plane containing the initial memory page among the plurality of memory planes (box 1630). Figure 16 As further shown in the diagram, method 1600 may include reading data from an initial memory page contained in the TU and the one or more additional memory pages (block 1640).

[0173] Method 1600 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods or operations described elsewhere in this document.

[0174] In the first aspect, all memory pages contained in the TU are contained in a single multiplane page stripe and a single multiplane block stripe.

[0175] In the second aspect, either alone or in combination with the first aspect, at least one memory page of the TU is contained in a first multiplane page, and at least one other memory page of the TU is contained in a second multiplane page.

[0176] In a third aspect, either alone or in combination with one or more of the first and second aspects, all memory pages contained in the TU are de-reserved memory pages, and the multi-plane page strip containing the TU contains one or more reserved memory pages that will not be written to user data.

[0177] In the fourth aspect, either alone or in combination with one or more of the first to third aspects, the one or more reserved memory pages are reserved memory pages located at the end of a multi-planar page strip and fewer in number than the number of memory pages contained in the TU.

[0178] In the fifth aspect, either alone or in combination with one or more of the first to fourth aspects, the number of reserved memory pages located at the end of the multiplanar page strip is based on the number of bits stored in each memory cell contained in the multiplanar page strip.

[0179] In a sixth aspect, either alone or in combination with one or more of the first to fifth aspects, method 1600 includes detecting a new defective block in the memory device and, based on the detection of the new defective block, marking one of the one or more reserved memory pages as a dereserved memory page, wherein marking the memory page as a dereserved memory page enables the memory device to write user data to the memory page.

[0180] although Figure 16 An example box of method 1600 is shown, but in some implementations, compared to Figure 16 The boxes depicted herein may include additional boxes, fewer boxes, different boxes, or boxes arranged in a different manner. Alternatively, two or more boxes in method 1600 may be executed simultaneously. Method 1600 is an example of a method that can be performed by one or more of the means described herein. The one or more means may perform or be configured to perform one or more other methods based on the operations described herein.

[0181] Figure 17This is a flowchart of an example method 1700 associated with read and write address translation using reserved memory pages with a multi-page translation unit. In some embodiments, a memory device (e.g., memory device 120) is executable or configurable to perform method 1700. In some embodiments, another device or set of devices, separate from or including the memory device (e.g., system 100), is executable or configurable to perform method 1700. Alternatively or additionally, one or more components of the memory device (e.g., controller 130, memory management component 225, address translation component 230, page reservation component 235, and / or command execution component 240) are executable or configurable to perform method 1700. Thus, the components for performing method 1700 may include the memory device and / or one or more components of the memory device. Alternatively or additionally, a non-transitory computer-readable medium may store one or more instructions that, when executed by the memory device (e.g., controller 130 of memory device 120), cause the memory device to perform method 1700.

[0182] like Figure 17 As shown, method 1700 may include identifying a TU associated with a read command, wherein the TU comprises multiple memory pages spanning multiple memory planes of the memory device (box 1710). Figure 17 As further shown, method 1700 may include identifying an initial memory page among the plurality of memory pages based on a logical-to-physical mapping table, wherein the initial memory page is contained in a first memory plane among the plurality of memory planes (box 1720). Figure 17 As further shown, method 1700 may include an indication based on an initial memory page and one or more faulty blocks of the memory device, identifying one or more additional memory pages contained in the plurality of memory pages of the TU, wherein the one or more additional memory pages are contained in one or more additional memory planes among the plurality of memory planes (box 1730). Figure 17 As further shown in the diagram, method 1700 may include reading data from an initial memory page contained in the TU and the one or more additional memory pages (box 1740).

[0183] Method 1700 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods or operations described elsewhere in this document.

[0184] In a first aspect, method 1700 includes: identifying a first page index value that identifies an initial memory page; determining a set of page index values ​​indicating a set of bad pages of the memory device based on indications of one or more bad blocks of the memory device; identifying a second page index value that is closest to the first page index value among all page index values ​​greater than the first page index value included in the set of page index values; determining whether the second page index value is within an offset threshold of the first page index value; and identifying the one or more additional memory pages of the TU based on whether the second page index value is within the offset threshold of the first page index value.

[0185] In the second aspect, either alone or in combination with the first aspect, method 1700 includes identifying the one or more additional memory pages of the TU as one or more sequential memory pages based on determining that the second page index value is not within an offset threshold of the first page index value, wherein the initial memory page and the one or more sequential memory pages have consecutive page index values.

[0186] In a third aspect, either alone or in combination with one or more of the first and second aspects, method 1700 includes identifying the one or more additional memory pages of the TU as one or more non-sequential memory pages based on determining a second page index value within an offset threshold of a first page index value, wherein the initial memory page and the one or more non-sequential memory pages have at least one non-contiguous page index value.

[0187] In the fourth aspect, either alone or in combination with one or more of the first to third aspects, the offset threshold is based on the number of memory pages contained in the TU.

[0188] In a fifth aspect, either alone or in combination with one or more of the first to fourth aspects, the indication of the one or more bad blocks of the memory device includes a data structure that stores an indication of a set of page index values ​​corresponding to a set of pages contained in the one or more bad blocks.

[0189] In the sixth aspect, either alone or in combination with one or more of the first to fifth aspects, for each memory cell storing two or more bits, the data structure stores only an indication of the initial page of each plane for each plane containing bad blocks.

[0190] although Figure 17 An example box of method 1700 is shown, but in some implementations, compared to Figure 17 The boxes depicted herein may include additional boxes, fewer boxes, different boxes, or boxes arranged in a different manner. Alternatively, two or more boxes in method 1700 may be executed simultaneously. Method 1700 is an example of a method that can be performed by one or more of the means described herein. The one or more means may perform or be configured to perform one or more other methods based on the operations described herein.

[0191] Figure 18 This is a flowchart of an example method 1800 associated with read and write address translation using reserved memory pages with a multi-page translation unit. In some embodiments, a memory device (e.g., memory device 120) is executable or configurable to perform method 1800. In some embodiments, another device or set of devices, separate from or including the memory device (e.g., system 100), is executable or configurable to perform method 1800. Alternatively or additionally, one or more components of the memory device (e.g., controller 130, memory management component 225, address translation component 230, page reservation component 235, and / or command execution component 240) are executable or configurable to perform method 1800. Thus, the components for performing method 1800 may include the memory device and / or one or more components of the memory device. Alternatively or additionally, a non-transitory computer-readable medium may store one or more instructions that, when executed by the memory device (e.g., controller 130 of memory device 120), cause the memory device to perform method 1800.

[0192] like Figure 18 As shown, method 1800 may include identifying a TU associated with a read command, wherein the TU comprises multiple memory pages spanning multiple memory planes of the memory device (box 1810). Figure 18 As further shown, method 1800 may include identifying an initial memory page among the plurality of memory pages based on a logical-to-physical mapping table, wherein the initial memory page is contained in a first memory plane among the plurality of memory planes (box 1820). Figure 18 As further shown, method 1800 may include determining a plane index value for the first memory plane (box 1830). Figure 18 As further shown, method 1800 may include identifying one or more additional memory pages contained in the plurality of memory pages of the TU based on an initial memory page and based on a plane index value, wherein the one or more additional memory pages are contained in one or more additional memory planes among the plurality of memory planes (box 1840). Figure 18 As further shown in the diagram, method 1800 may include reading data from an initial memory page contained in the TU and the one or more additional memory pages (block 1850).

[0193] Method 1800 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods or operations described elsewhere in this document.

[0194] In a first aspect, method 1800 includes determining that a plane index value satisfies a first condition, and based on determining that the plane index value satisfies the first condition, identifying the one or more additional memory pages of the TU as one or more sequential memory pages, wherein the initial memory page and the one or more sequential memory pages are sequential.

[0195] In a second aspect, either alone or in combination with the first aspect, method 1800 includes preventing the execution of a bad block search when the one or more additional memory pages of the TU are identified based on determining that the plane index value satisfies the first condition.

[0196] In a third aspect, either alone or in combination with one or more of the first and second aspects, the first condition is that the plane index value is even.

[0197] In a fourth aspect, either alone or in combination with one or more of the first to third aspects, method 1800 includes determining that a plane index value satisfies a second condition, performing a bad block search based on the determination that the plane index value satisfies the second condition, and identifying the one or more additional memory pages of the TU based on the performance of the bad block search.

[0198] In the fifth aspect, either alone or in combination with one or more of the first to fourth aspects, the second condition is that the plane index value is odd.

[0199] In a sixth aspect, either alone or in combination with one or more of the first to fifth aspects, method 1800 includes: as part of executing a write command to write user data to the TU, performing a bad block search of a multiplane page containing at least a portion of the TU and a next-order multiplane page; determining, based on the bad block search, whether the multiplane page contains any bad blocks and whether the next-order multiplane page contains any bad blocks; selecting a first memory plane in which the user data will be written in the initial memory page based on the determination that the multiplane page contains any bad blocks and based on the determination that the next-order multiplane page contains any bad blocks; and storing an indication of the initial memory page in a logical-to-physical mapping table.

[0200] In a seventh aspect, either alone or in combination with one or more of the first to sixth aspects, method 1800 includes selecting an even-numbered memory plane as the first memory plane based on determining that the multiplane page does not contain any bad blocks and based on determining that the next sequential multiplane page does not contain any bad blocks.

[0201] In an eighth aspect, either alone or in combination with one or more of the first to seventh aspects, method 1800 includes preventing any memory pages in the reserved multiplane page and the next sequential multiplane page from being retained based on determining that the multiplane page does not contain any bad blocks and based on determining that the next sequential multiplane page does not contain any bad blocks.

[0202] In the ninth aspect, either alone or in combination with one or more of the first to eighth aspects, method 1800 includes selecting an odd-numbered memory plane as the first memory plane based on determining that a multi-plane page contains a bad block or based on determining that the next sequential multi-plane page contains a bad block.

[0203] In a tenth aspect, either alone or in combination with one or more of the first to ninth aspects, method 1800 includes reserving one or more memory pages from the multiplane page or the next-order multiplane page based on determining that the multiplane page contains a bad block or based on determining that the next-order multiplane page contains a bad block.

[0204] although Figure 18 An example box of method 1800 is shown, but in some implementations, compared to Figure 18 The boxes depicted herein may include additional boxes, fewer boxes, different boxes, or boxes arranged in a different manner. Alternatively, two or more boxes in method 1800 may be executed simultaneously. Method 1800 is an example of a method that can be performed by one or more of the means described herein. The one or more means may perform or be configured to perform one or more other methods based on the operations described herein.

[0205] Figure 19 This is a flowchart of an example method 1900 associated with read and write address translation using reserved memory pages with a multi-page translation unit. In some embodiments, a memory device (e.g., memory device 120) is executable or configurable to perform method 1900. In some embodiments, another device or set of devices, separate from or including the memory device (e.g., system 100), is executable or configurable to perform method 1900. Alternatively or additionally, one or more components of the memory device (e.g., controller 130, memory management component 225, address translation component 230, page reservation component 235, and / or command execution component 240) are executable or configurable to perform method 1900. Thus, the components for performing method 1900 may include the memory device and / or one or more components of the memory device. Alternatively or additionally, a non-transitory computer-readable medium may store one or more instructions that, when executed by the memory device (e.g., controller 130 of memory device 120), cause the memory device to perform method 1900.

[0206] like Figure 19 As shown, method 1900 may include receiving a write command containing data of a plurality of memory pages to be written to a TU of the memory device, wherein the plurality of memory pages of the TU span multiple memory planes of the memory device (box 1910). Figure 19As further shown, method 1900 may include identifying the plurality of memory pages of the TU to which data is to be written based on: one or more bad blocks of the memory device, and a determination of whether to retain one or more memory pages of the memory device (box 1920). Figure 19 As further shown in the diagram, method 1900 may include writing data to the plurality of memory pages of the TU (box 1930).

[0207] Method 1900 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods or operations described elsewhere in this document.

[0208] In the first aspect, a data structure indicating the one or more bad blocks is stored in the memory of the memory device, and a configuration of the one or more memory pages to be reserved is stored in the memory of the memory device based on the one or more bad blocks.

[0209] In the second aspect, either alone or in combination with the first aspect, method 1900 includes detecting a new defective block, storing an indication of the new defective block in a data structure, and modifying the configuration of the one or more memory pages to be retained based on the detection of the new defective block.

[0210] In a third aspect, either alone or in combination with one or more of the first and second aspects, method 1900 includes: identifying a multiplane page of an initial memory page among the plurality of memory pages containing TU; determining that the multiplane page does not contain any bad block among the one or more bad blocks; determining that a next sequential multiplane page following the multiplane page does not contain any bad block among the one or more bad blocks; based on determining that the multiplane page does not contain any bad block and based on determining that the next sequential multiplane page does not contain any bad block, preventing the retention of any memory page in the multiplane page and preventing the retention of any memory page in the next sequential multiplane page; and based on determining that the multiplane page does not contain any bad block and based on determining that the next sequential multiplane page does not contain any bad block, selecting sequential memory pages as the plurality of memory pages, wherein the sequential memory pages comprise one of a set of sequential memory pages all contained in the multiplane page or one of a first set of sequential memory pages contained in the multiplane page and a second set of sequential memory pages contained in the next sequential multiplane page.

[0211] In a fourth aspect, either alone or in combination with one or more of the first to third aspects, the memory device is permitted to write to a first set of sequential memory pages contained in multi-plane pages and a second set of sequential memory pages contained in the next sequential multi-plane pages only if the number of planes contained in the die of the memory device to be written is not a power of two.

[0212] In a fifth aspect, either alone or in combination with one or more of the first to fourth aspects, method 1900 includes: identifying a multiplane page of an initial memory page among the plurality of memory pages containing TU; determining that the multiplane page contains a bad block among the one or more bad blocks or that a next sequential multiplane page following the multiplane page contains a bad block among the one or more bad blocks; reserving at least one memory page among the multiplane pages based on determining that the multiplane page contains a bad block or that the next sequential multiplane page contains a bad block; and selecting a set of memory pages contained in the multiplane pages as the plurality of memory pages based on reserving at least one memory page among the multiplane pages, wherein the set of memory pages does not contain the at least one memory page that was reserved.

[0213] In a sixth aspect, either alone or in combination with one or more of the first to fifth aspects, the at least one memory page is reserved such that the index value of the initial memory page or the memory plane containing the initial memory page satisfies a certain condition, or the at least one memory page is reserved at the end of the multi-plane page when the number of unwritten memory pages at the end of the multi-plane page is less than the number of memory pages per TU.

[0214] although Figure 19 An example block of method 1900 is shown, but in some implementations, compared to Figure 19 The boxes depicted herein may include additional boxes, fewer boxes, different boxes, or boxes arranged in a different manner. Alternatively, two or more boxes in method 1900 may be executed simultaneously. Method 1900 is an example of a method that can be performed by one or more of the means described herein. The one or more means may perform or be configured to perform one or more other methods based on the operations described herein.

[0215] Figure 20This is a flowchart of an example method 2000 associated with read and write address translation using reserved memory pages with a multi-page translation unit. In some embodiments, a memory device (e.g., memory device 120) is executable or configurable to perform method 2000. In some embodiments, another device or set of devices, separate from or including the memory device (e.g., system 100), is executable or configurable to perform method 2000. Alternatively or additionally, one or more components of the memory device (e.g., controller 130, memory management component 225, address translation component 230, page reservation component 235, and / or command execution component 240) are executable or configurable to perform method 2000. Thus, the components for performing method 2000 may include the memory device and / or one or more components of the memory device. Alternatively or additionally, a non-transitory computer-readable medium may store one or more instructions that, when executed by the memory device (e.g., controller 130 of memory device 120), cause the memory device to perform method 2000.

[0216] like Figure 20 As shown, method 2000 may include storing an indication of a set of reserved memory pages of the device based on an indication of a set of defective blocks contained in the device and a TU size, wherein the TU size indicates the number of memory pages contained in a TU of the device, wherein the TU contains multiple memory pages spanning multiple memory planes of the device (box 2010). Figure 20 As further shown in the diagram, method 2000 may include preventing user data from being written to the set of reserved memory pages (box 2020).

[0217] Method 2000 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods or operations described elsewhere in this document.

[0218] In the first aspect, method 2000 includes writing non-user data to the set of reserved memory pages.

[0219] In the second aspect, either alone or in combination with the first aspect, non-user data includes dummy data or parity data.

[0220] although Figure 20 An example block of method 2000 is shown, but in some implementations, compared to Figure 20The boxes depicted herein may include additional boxes, fewer boxes, different boxes, or boxes arranged in a different manner. Alternatively, two or more boxes in method 2000 may be executed simultaneously. Method 2000 is an example of a method that can be performed by one or more of the means described herein. The one or more means may perform or be configured to perform one or more other methods based on the operations described herein.

[0221] In some embodiments, a memory device includes one or more components configured to: identify a TU associated with a read command, wherein the TU includes a plurality of memory pages spanning a plurality of memory planes of the memory device; identify an initial memory page among the plurality of memory pages of the TU based on a logical-to-physical mapping table; identify one or more additional memory pages among the plurality of memory pages of the TU based on the initial memory page and based on at least one of: an indication of one or more bad blocks of the memory device, or an index value of the initial memory page or an index value of a memory plane containing the initial memory page among the plurality of memory planes; and read data from the initial memory page and the one or more additional memory pages contained in the TU.

[0222] In some embodiments, a memory device includes one or more components configured to: identify a TU associated with a read command, wherein the TU includes a plurality of memory pages spanning a plurality of memory planes of the memory device; identify an initial memory page among the plurality of memory pages of the TU based on a logical-to-physical mapping table, wherein the initial memory page is contained in a first memory plane among the plurality of memory planes; identify one or more additional memory pages contained in the plurality of memory pages of the TU based on the initial memory page and based on an indication of one or more bad blocks of the memory device, wherein the one or more additional memory pages are contained in one or more additional memory planes among the plurality of memory planes; and read data from the initial memory page and the one or more additional memory pages contained in the TU.

[0223] In some embodiments, a memory device includes one or more components configured to: identify a TU associated with a read command, wherein the TU includes a plurality of memory pages spanning a plurality of memory planes of the memory device; identify an initial memory page among the plurality of memory pages of the TU based on a logical-to-physical mapping table, wherein the initial memory page is contained in a first memory plane among the plurality of memory planes; determine a plane index value for the first memory plane; identify one or more additional memory pages contained in the plurality of memory pages of the TU based on the initial memory page and based on the plane index value, wherein the one or more additional memory pages are contained in one or more additional memory planes among the plurality of memory planes; and read data from the initial memory page and the one or more additional memory pages contained in the TU.

[0224] In some embodiments, a method includes: receiving, via a memory device, a write command containing data to be written to a plurality of memory pages of a Unit (TU) of the memory device, wherein the plurality of memory pages of the TU span multiple memory planes of the memory device; identifying, via the memory device, the plurality of memory pages of the TU to which the data is to be written based on: one or more bad blocks of the memory device, and a determination regarding whether one or more memory pages of the memory device will be retained; and writing the data to the plurality of memory pages of the TU via the memory device.

[0225] In some embodiments, a device includes: means for storing an indication of a set of reserved memory pages of the device based on an indication of a set of bad blocks contained in the device and a TU size, wherein the TU size indicates the number of memory pages contained in a TU of the device, wherein the TU contains a plurality of memory pages spanning a plurality of memory planes of the device; and means for preventing user data from being written to the set of reserved memory pages.

[0226] The foregoing disclosure provides illustrations and descriptions, but is not intended to be exhaustive or to limit the implementation schemes to the precise forms disclosed. Modifications and variations can be made based on the foregoing disclosure, or from the practice of the implementation schemes described herein.

[0227] As used in this article, “meeting the threshold” can refer to a value that is greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, etc., depending on the context.

[0228] Even if a specific combination of features is recited in the claims and / or disclosed in the specification, such combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features can be combined in ways not specifically recited in the claims and / or not disclosed in the specification. For example, this disclosure includes each dependent claim in the claim set, as well as each other individual claim in the claim set and each combination of multiple claims. As used herein, the phrase “at least one of” in the list of items refers to any combination of these items containing a single member. As an example, “at least one of a, b, or c” is intended to cover a, b, c, a+b, a+c, b+c, and a+b+c, and any combination of multiples of the same element (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c, or any other order of a, b, and c).

[0229] Unless explicitly stated otherwise, no element, action, or instruction used herein should be considered critical or necessary. Furthermore, as used herein, “a” (articles “a” and “an”) is intended to include one or more items and is interchangeable with “one or more”. Similarly, as used herein, “the” (article “the”) is intended to include one or more items referenced in conjunction with “the” and is interchangeable with “the one or more”. If only one item is expected, then the phrase “only one,” “single,” or similar language is used. Furthermore, as used herein, terms such as “has / have / having” are expected to be open-ended terms and do not limit the elements they modify (e.g., an element “having” A may also have B). Additionally, unless explicitly stated otherwise, the phrase “based on” means “at least partially based on.” As used herein, the term “multiple” can be replaced with “a plurality of” or vice versa. Furthermore, as used herein, unless otherwise explicitly stated (e.g., if and only one of which is used), the term “or” is intended to be inclusive when used in series and is interchangeable with “and / or”.

Claims

1. A memory device, comprising: One or more components configured as follows: Identify the conversion unit TU associated with the read command. The TU comprises multiple memory pages spanning multiple memory planes of the memory device; Based on the logical-to-physical mapping table, the initial memory page among the plurality of memory pages of the TU is identified, wherein the initial memory page is contained in a first memory plane among the plurality of memory planes; Based on the initial memory page and based on the indication of one or more faulty blocks of the memory device, identify one or more additional memory pages contained within the plurality of memory pages of the TU, wherein the one or more additional memory pages are contained in one or more additional memory planes among the plurality of memory planes, and In order to identify the one or more additional memory pages of the TU, the one or more components are configured to: The first page index value is identified, which identifies the initial memory page; Based on the indication of one or more bad blocks in the memory device, a set of page index values ​​indicating a set of bad pages in the memory device are determined; Identify the second page index value that is closest to the first page index value among all page index values ​​greater than the first page index value contained in the set of page index values; Determine whether the index value of the second page is within the offset threshold of the index value of the first page; and The one or more additional memory pages of the TU are identified based on whether the second page index value is within the offset threshold of the first page index value; as well as Data is read from the initial memory page and the one or more additional memory pages contained in the TU.

2. The memory device of claim 1, wherein all memory pages in the TU are contained in a single multiplanar page stripe and a single multiplanar block stripe.

3. The memory device of claim 1, wherein at least one memory page of the TU is contained in a first multiplane page, and at least one other memory page of the TU is contained in a second multiplane page.

4. The memory device of claim 1, wherein all memory pages in the TU are de-reserved memory pages, and The multi-planar page stripe containing the TU includes one or more reserved memory pages that will not be written to user data.

5. The memory device of claim 4, wherein the one or more reserved memory pages are reserved memory pages located at the end of the multiplanar page strip region and are fewer in number than the number of memory pages contained in the TU.

6. The memory device of claim 5, wherein the number of reserved memory pages located at the end of the multiplanar page strip is based on the number of bits stored in each memory cell contained in the multiplanar page strip.

7. The memory device of claim 4, wherein the one or more components are further configured to: Detecting new defective blocks in the memory device; and Based on the detection of the new defective block, one of the one or more reserved memory pages is marked as a dereserved memory page. The memory page is marked as a de-reserved memory page, which enables the memory device to write user data to the memory page.

8. The memory device of claim 1, wherein, in order to identify the one or more additional memory pages of the TU, the one or more components are configured to: Based on the determination that the second page index value is not within the offset threshold of the first page index value, the one or more additional memory pages of the TU are identified as one or more sequential memory pages. The initial memory page and the one or more sequential memory pages have consecutive page index values.

9. The memory device of claim 1, wherein, in order to identify the one or more additional memory pages of the TU, the one or more components are configured to: Based on the determination that the second page index value is within the offset threshold of the first page index value, the one or more additional memory pages of the TU are identified as one or more non-sequential memory pages. The initial memory page and the one or more non-sequential memory pages have at least one non-contiguous page index value.

10. The memory device of claim 1, wherein the offset threshold is based on the number of memory pages contained in the TU.

11. The memory device of claim 1, wherein the indication of the one or more bad blocks of the memory device comprises a data structure that stores an indication corresponding to a set of page index values ​​contained in a set of pages in the one or more bad blocks.

12. The memory device of claim 11, wherein for each memory cell storing two or more bits, the data structure stores only an indication of the initial page of each plane containing the bad block.

13. A memory device, comprising: One or more components configured as follows: Identify a translation unit (TU) associated with a read command, wherein the TU comprises multiple memory pages spanning multiple memory planes of the memory device; Based on the logical-to-physical mapping table, the initial memory page among the plurality of memory pages of the TU is identified, wherein the initial memory page is contained in a first memory plane among the plurality of memory planes; Determine the plane index value of the first memory plane; Based on the initial memory page and the plane index value, identify one or more additional memory pages contained in the plurality of memory pages of the TU. The one or more additional memory pages are contained in one or more additional memory planes among the plurality of memory planes; and In order to identify the one or more additional memory pages of the TU, the one or more components are configured to: The plane index value is determined to satisfy the first condition; as well as Based on the determination that the plane index value satisfies the first condition, the one or more additional memory pages of the TU are identified as one or more sequential memory pages, wherein the initial memory page and the one or more sequential memory pages are sequential; as well as Data is read from the initial memory page and the one or more additional memory pages contained in the TU.

14. The memory device of claim 13, wherein the one or more components are further configured to: Based on the determination that the plane index value satisfies the first condition, bad block search is prevented when identifying the one or more additional memory pages of the TU.

15. The memory device of claim 13, wherein the first condition is that the plane index value is an even number.

16. The memory device of claim 13, wherein all memory pages in the TU are contained in a single multiplanar page stripe and a single multiplanar block stripe.

17. The memory device of claim 13, wherein all memory pages contained in the TU are de-reserved memory pages, and the multi-plane page strip containing the TU contains one or more reserved memory pages that will not be written to user data.

18. A memory device, comprising: One or more components configured as follows: Identify a translation unit (TU) associated with a read command, wherein the TU comprises multiple memory pages spanning multiple memory planes of the memory device; Based on the logical-to-physical mapping table, the initial memory page among the plurality of memory pages of the TU is identified, wherein the initial memory page is contained in a first memory plane among the plurality of memory planes; Determine the plane index value of the first memory plane; Based on the initial memory page and the plane index value, identify one or more additional memory pages contained in the plurality of memory pages of the TU. The one or more additional memory pages are contained in one or more additional memory planes among the plurality of memory planes; and In order to identify the one or more additional memory pages of the TU, the one or more components are configured to: The plane index value is determined to satisfy the first condition; Based on determining that the plane index value satisfies the first condition, a bad block search is performed; and Based on performing the bad block search, identify the one or more additional memory pages of the TU; as well as Data is read from the initial memory page and the one or more additional memory pages contained in the TU.

19. The memory device of claim 18, wherein the first condition is that the plane index value is odd.

20. The memory device of claim 18, wherein all memory pages in the TU are contained in a single multiplanar page stripe and a single multiplanar block stripe.

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