Pixel circuit, driving method thereof, and display device

Abstract

This disclosure provides a pixel circuit and its driving method, as well as a display device. The pixel circuit of this disclosure includes: a first storage capacitor, a second storage capacitor, a driving transistor, a threshold compensation sub-circuit, a data writing sub-circuit, a test sub-circuit, and a light-emitting device; the control electrode of the driving transistor is connected to a first node, the first electrode is connected to a first power supply signal line, and the second electrode is connected to a second node; the threshold compensation sub-circuit is configured to write a threshold voltage to the second node in response to a first control signal on the first control signal line to compensate for the threshold voltage of the driving transistor; the data writing sub-circuit is configured to write a data signal from a data signal line to a third node in response to a second control signal on the second control signal line; the test sub-circuit is configured to control the connection and disconnection between the first power supply signal line and the sensing signal line in response to a test control signal on the test control signal line to detect whether the driving transistor is functioning properly.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a pixel circuit and its driving method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are light-emitting devices that use organic solid-state semiconductors as light-emitting materials. Due to their advantages such as simple fabrication process, low cost, low power consumption, high brightness, and wide operating temperature range, they have broad application prospects. Summary of the Invention

[0003] This disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a pixel circuit and its driving method, as well as a display device.

[0004] In a first aspect, embodiments of this disclosure provide a pixel circuit, wherein the pixel circuit includes: a first storage capacitor, a second storage capacitor, a driving transistor, a threshold compensation sub-circuit, a data writing sub-circuit, a test sub-circuit, and a light-emitting device;

[0005] One end of the first storage capacitor is connected to the first node, and the other end is connected to the second node;

[0006] One end of the second storage capacitor is connected to the second node, and the other end is connected to the third node;

[0007] The control electrode of the driving transistor is connected to the first node, the first electrode is connected to the first power signal line, and the second electrode is connected to the second node.

[0008] The threshold compensation sub-circuit is configured to write a threshold voltage into a second node in response to a first control signal on a first control signal line to compensate for the threshold voltage of the driving transistor.

[0009] The data writing sub-circuit is configured to write the data signal of the data signal line to the third node in response to the second control signal line;

[0010] The test sub-circuit is configured to control the connection and disconnection between the first power supply signal line and the sensing signal line in response to the test control signal of the test control signal line, so as to detect whether the driving transistor is normal.

[0011] The first electrode of the light-emitting device is connected to the second node, and the second electrode is connected to the second power signal line.

[0012] In some embodiments, the threshold compensation sub-circuit and the data writing sub-circuit are multiplexed into the test sub-circuit;

[0013] The first control signal line and the second control signal line are multiplexed into the test control signal line;

[0014] The data signal lines are multiplexed into the sensing signal lines.

[0015] In some embodiments, the pixel circuit further includes: a first reset sub-circuit;

[0016] The first reset sub-circuit is configured to write the initialization signal of the initialization signal line to the third node in response to the first control signal line.

[0017] In some embodiments, the first reset sub-circuit includes a first transistor; the threshold compensation sub-circuit includes a second transistor.

[0018] The control electrode of the first transistor is connected to the first control signal line, the first electrode is connected to the initialization signal line, and the second electrode is connected to the first electrode of the second transistor.

[0019] The control electrode of the second transistor is connected to the first control signal line, the first electrode is connected to the second electrode of the first transistor, and the second electrode is connected to the third node.

[0020] In some embodiments, the pixel circuit further includes: a second reset sub-circuit;

[0021] The second reset sub-circuit is configured to write the reset signal of the reset signal line to the first node in response to the third control signal of the third control signal line.

[0022] In some embodiments, the second reset sub-circuit includes: a fourth transistor;

[0023] The control electrode of the fourth transistor is connected to the third control signal line, the first electrode is connected to the reset signal line, and the second electrode is connected to the first node.

[0024] In some embodiments, the pixel circuit further includes: a first light emission control sub-circuit and a second light emission control sub-circuit;

[0025] The first light-emitting control sub-circuit is configured to control the on / off connection between the first power supply signal line and the first terminal of the driving transistor in response to a first light-emitting control signal of the first light-emitting control signal line;

[0026] The second light-emitting control sub-circuit is configured to control the on / off connection between the second terminal of the driving transistor and the first terminal of the light-emitting device in response to the second light-emitting control signal of the second light-emitting control signal line.

[0027] In some embodiments, the first light-emitting control sub-circuit includes a sixth transistor; the second light-emitting control sub-circuit includes a seventh transistor;

[0028] The control electrode of the sixth transistor is connected to the first light-emitting control signal line, the first electrode is connected to the first power signal line, and the second electrode is connected to the first electrode of the driving transistor.

[0029] The control electrode of the seventh transistor is connected to the second light-emitting control signal line, the first electrode is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting device.

[0030] In some embodiments, the first light emission control sub-circuit and the second light emission control sub-circuit are multiplexed as the test sub-circuit;

[0031] The first light emission control signal line and the second light emission control signal line are multiplexed into the test control signal line.

[0032] In some embodiments, the pixel circuit further includes: a test reset sub-circuit;

[0033] The test reset sub-circuit is configured to write the test reset signal of the test reset signal line into the first node in response to the test reset control signal of the test reset control signal line.

[0034] In some embodiments, the second reset sub-circuit is multiplexed as the test reset sub-circuit; the third control signal line is multiplexed as the test reset control signal line; and the reset signal line is multiplexed as the test reset signal line.

[0035] In some embodiments, the data writing sub-circuit includes: a fifth transistor;

[0036] The control electrode of the fifth transistor is connected to the second control signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the third node.

[0037] Secondly, embodiments of this disclosure provide a display device, wherein the display device includes the pixel circuit as described above.

[0038] Thirdly, embodiments of this disclosure provide a method for driving a pixel circuit, used to drive the pixel circuit as described above, wherein the method for driving the pixel circuit includes:

[0039] During the threshold compensation phase, in response to the first control signal of the first control signal line, the threshold voltage is written to the second node;

[0040] During the data writing phase, in response to the second control signal of the second control signal line, the data signal of the data signal line is written to the third node;

[0041] During the testing phase, in response to the test control signal of the test control signal line, the connection and disconnection between the first power signal line and the sensing signal line are controlled to detect whether the driving transistor is normal. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present disclosure.

[0043] Figure 2 for Figure 1 The diagram shows the timing of the pixel circuit driving the light-emitting device.

[0044] Figure 3 for Figure 1 The voltage values ​​of each node in the pixel circuit shown are displayed during the process of driving the light-emitting device.

[0045] Figure 4 for Figure 1 The timing diagram of the pixel circuit during the detection process is shown.

[0046] Figure 5 This is a schematic flowchart of a pixel circuit driving method provided in an embodiment of the present disclosure. Detailed Implementation

[0047] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0049] The transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors are symmetrical, there is no distinction between them. In the embodiments of this disclosure, to distinguish the source and drain of the transistor, one of the terminals is called the first terminal, and the other is called the second terminal. Furthermore, transistors can be classified into N-type and P-type according to their characteristics. The following embodiments use N-type transistors for explanation. When an N-type transistor is used, the first terminal is the source of the N-type transistor, and the second terminal is the drain of the N-type transistor. When the gate input is high, the source and drain are turned on. It is conceivable that using a P-type transistor is something that those skilled in the art can easily conceive of without creative effort, and therefore it is also within the protection scope of the embodiments of this disclosure. The first power signal line can be a high-level power signal line, and the second power signal line can be a low-level power signal line.

[0050] In the embodiments of the present invention, the light-emitting device is a current-driven light-emitting device. Further, it can be a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), or an organic light-emitting diode (OLED). In this disclosure, an OLED is used as an example for illustration, where the first electrode and the second electrode are the anode and cathode of the OLED, respectively.

[0051] Currently, OLED light-emitting devices are generally driven to emit light through pixel circuits to achieve display functions. Pixel circuits include devices such as driving transistors and storage capacitors (for details, please refer to the 7T1C, 8T1C, 8T2C circuits in related technologies, which will not be listed or described in detail here). Since the threshold voltage Vth of the driving transistor changes with time, it is necessary to compensate for the threshold voltage Vth of the driving transistor in the pixel circuit.

[0052] As display product sizes increase and form factors change (from landscape to portrait), the scanning time per line decreases. Related pixel circuits perform data writing and threshold voltage compensation simultaneously within the same timeframe, resulting in the threshold voltage compensation time being shorter than the scanning time per line. This leads to insufficient threshold voltage compensation time at high frequencies and high resolutions, impacting image quality. A solution is to separate threshold compensation and data writing, performing them in separate time periods without interference. This allows the threshold voltage compensation time to exceed the scanning time per line, resulting in a longer compensation period and improved display quality.

[0053] However, current pixel circuits do not have detection capabilities. During array test (AT), it is impossible to determine whether the driving transistors are functioning properly. This results in defective array substrates being sent to the next process, wasting resources and affecting production efficiency.

[0054] To at least solve one of the aforementioned technical problems, this disclosure provides a pixel circuit and its driving method, as well as a display device. The pixel circuit and its driving method, as well as the display device provided in this disclosure will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0055] In a first aspect, embodiments of this disclosure provide a pixel circuit. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present disclosure, such as... Figure 1 As shown, the pixel circuit includes: a first storage capacitor C1, a second storage capacitor C2, a driving transistor T3, a threshold compensation sub-circuit 101, a data writing sub-circuit 102, a test sub-circuit 103, and a light-emitting device OLED; one end of the first storage capacitor C1 is connected to a first node N1, and the other end is connected to a second node N2; one end of the second storage capacitor C2 is connected to the second node N2, and the other end is connected to a third node N3; the gate of the driving transistor T3 is connected to the first node N1, the source is connected to the first power supply signal line VDD, and the drain is connected to the second node N2; the threshold compensation sub-circuit 102 is configured to respond to a first control signal line Gate1. The threshold voltage Vth is written to the second node N2 in response to the control signal of the second control signal line Gate2 to compensate for the threshold voltage Vth of the driving transistor T3; the data writing sub-circuit 102 is configured to write the data signal of the data signal line Vdata to the third node N3 in response to the second control signal line Gate2; the test sub-circuit 103 is configured to control the on / off connection between the first power signal line VDD and the sensing signal line Sensor in response to the test control signal line Gate2 to detect whether the driving transistor T3 is normal; the anode of the light-emitting device OLED is connected to the second node N2, and the cathode is connected to the second power signal line VSS.

[0056] The first storage capacitor C1 and the second storage capacitor C2 are connected in series. They can not only store the voltage signals of the corresponding nodes, but also act as voltage dividers to ensure that the preset voltage signal is input to the corresponding nodes.

[0057] The driving transistor T3 can convert the driving voltage signal provided by the first power signal line VDD into a driving current signal, and input the driving current to the anode of the light-emitting device OLED to drive the light-emitting device OLED to emit light and realize the display function.

[0058] The threshold compensation sub-circuit 101 can write the threshold voltage Vth into the second node N2 to compensate the threshold voltage of the driving transistor T3, so as to prevent the threshold voltage of the driving transistor T3 from shifting over time, thus ensuring the display effect of the display screen.

[0059] The data writing sub-circuit 102 can write the data signal into the third node N3, and under the voltage division effect of the first storage capacitor C1 and the second storage capacitor C2, the data signal is input to the gate of the driving transistor T3. By adjusting the voltage value of the data signal, the opening degree of the driving transistor T3 can be adjusted to control the magnitude of the driving current passing through it, thereby adjusting the brightness of the light-emitting device OLED.

[0060] The test sub-circuit 103 can control the connection and disconnection between the first power signal line VDD and the sensing signal line Sensor. By detecting the current in the sensing signal line Sensor, it can determine whether the driving transistor T3 is normal, thus preventing defective array substrates from flowing to the next process.

[0061] In the pixel circuit provided in this embodiment, since the threshold compensation sub-circuit 101 and the data writing sub-circuit 102 are controlled by the voltage signals provided by the first control signal line Gate1 and the second control signal line Gate2, respectively, they will not interfere with each other. They can work in different time periods, and the threshold compensation process is not limited by the data writing process time. The threshold voltage compensation time can be longer than the scan time of one line, thus improving the display effect of the screen. At the same time, the test sub-circuit 103 can control the continuity between the first power signal line VDD and the sensing signal line Sensor, and detect whether there is a sensing current in the sensing signal line Sensor to determine whether the driving transistor T3 in the pixel circuit is normal. This can prevent defective array substrates from flowing to the next process, thus avoiding resource waste and improving production efficiency.

[0062] In some embodiments, such as Figure 1 As shown, the threshold compensation sub-circuit 101 and the data writing sub-circuit 102 are multiplexed into the test sub-circuit 103; the first control signal line Gate1 and the second control signal line Gate2 are multiplexed into the test control signal line Gate; and the data signal line Dat is multiplexed into the sensing signal line Sensor.

[0063] In practical applications, the driving and detection processes of the pixel circuit are performed in separate time periods. During the driving process, the threshold compensation sub-circuit 101 compensates for the threshold voltage of the driving transistor T3, and the data writing sub-circuit 102 writes data signals to the third node N3. During the detection process, the threshold compensation sub-circuit 101 and the data writing sub-circuit 102 can be multiplexed into a detection sub-circuit 103, which controls the connection and disconnection between the first power supply signal line VDD and the sensing signal line Sensor, and detects whether there is a sensing current in the sensing signal line Sensor (data signal line Vdata) to determine whether the driving transistor T3 in the pixel circuit is functioning properly. In this way, the driving and detection processes of the pixel circuit can be implemented simultaneously without adding additional circuit structures, thereby simplifying the circuit structure and saving manufacturing costs.

[0064] like Figure 1 As shown, the pixel circuit further includes: a first reset sub-circuit 104; the first reset sub-circuit 104 is configured to write the initialization signal of the initialization signal line Int to the third node N3 in response to a first control signal on the first control signal line Gate1. The first reset sub-circuit 104 includes: a first transistor T1; the threshold compensation sub-circuit 101 includes: a second transistor T2; the gate of the first transistor T1 is connected to the first control signal line Gate1, the source is connected to the initialization signal line Vint, and the drain is connected to the source of the second transistor T2; the gate of the second transistor T2 is connected to the first control signal line Gate1, the source is connected to the drain of the first transistor T1, and the drain is connected to the third node N3.

[0065] The pixel circuit also includes a second reset circuit 105; the second reset circuit 105 is configured to write a reset signal of the reset signal line Vref to the first node N1 in response to a third control signal on the third control signal line Gate3. The second reset circuit includes a fourth transistor T4; the gate of the fourth transistor T4 is connected to the third control signal line Gate3, the source is connected to the reset signal line Vref, and the drain is connected to the first node N1.

[0066] The pixel circuit further includes: a first light-emitting control sub-circuit 106 and a second light-emitting control sub-circuit 107; the first light-emitting control sub-circuit 106 is configured to control the switching between the first power supply signal line VDD and the source of the driving transistor T3 in response to a first light-emitting control signal on the first light-emitting control signal line EM1; the second light-emitting control sub-circuit 107 is configured to control the switching between the drain of the driving transistor T3 and the anode of the light-emitting device OLED in response to a second light-emitting control signal on the second light-emitting control signal line EM2. The first light-emitting control sub-circuit 106 includes: a sixth transistor T6; the second light-emitting control sub-circuit 107 includes: a seventh transistor T7; the gate of the sixth transistor T6 is connected to the first light-emitting control signal line EM1, the source is connected to the first power supply signal line VDD, and the drain is connected to the source of the driving transistor T3; the gate of the seventh transistor T7 is connected to the second light-emitting control signal line EM2, the source is connected to the drain of the driving transistor T3, and the drain is connected to the anode of the light-emitting device OLED. The first light-emitting control sub-circuit 106 and the second light-emitting control sub-circuit 107 are multiplexed into a test sub-circuit 104; the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are multiplexed into a test control signal line Gate.

[0067] The pixel circuit also includes: a test reset sub-circuit 108; the test reset sub-circuit 108 is configured to write the test reset signal of the test reset signal line Vref' into the first node N1 in response to the test reset control signal of the test reset control signal line Gate'. The second reset sub-circuit 105 is multiplexed as the test reset sub-circuit 108; the third control signal line Gate3 is multiplexed as the test reset control signal line Gate'; and the reset signal line Vref is multiplexed as the test reset signal line Vref'.

[0068] The data writing sub-circuit 102 includes: a fifth transistor T5; the gate of the fifth transistor T5 is connected to the second control signal line Gate2, the source is connected to the data signal line Vdata, and the drain is connected to the third node N3.

[0069] Figure 2 for Figure 1 The diagram shown illustrates the timing of the pixel circuit driving the light-emitting device. Figure 3 for Figure 1 The pixel circuit shown illustrates the voltage values ​​at each node during the driving of the light-emitting device. Figure 4 for Figure 1 The timing diagram of the pixel circuit during the detection process is shown below. Figure 2 , Figure 3 and Figure 4 The operation of the pixel circuit provided in the embodiments of this disclosure will be described in further detail.

[0070] It should be noted that each transistor in the pixel circuit provided in this embodiment is an N-type transistor, which can be an oxide thin-film transistor or a low-temperature polycrystalline silicon thin-film transistor, and is not specifically limited.

[0071] The process of driving light-emitting devices can be divided into four stages: the first stage, the second stage, the third stage, and the fourth stage.

[0072] Phase 1 (Initialization Phase): The first control signal in Gate1 and the third control signal in Gate3 are both at high potentials. The second control signal in Gate2, the first light emission control signal in EM1, and the second light emission control signal in EM2 are all at low potentials. Transistors T1, T2, and T4 are turned on, while transistors T5, T6, and T7 are turned off. The reset signal is written to node N1 via transistor T4, where the reset signal is at a high potential, causing the driving transistor T3 to turn on. The initialization signal is written to node N3 via transistors T1 and T2. The initialization signal resets the anode of the OLED device; at this time, the OLED device does not emit light.

[0073] Second stage (threshold compensation stage): The first control signal of the first control signal line Gate1, the third control signal of the third control signal line Gate3, and the first light-emitting control signal of the first light-emitting control signal line EM1 are at high potentials; the second control signal of the second control signal line Gate2 and the second light-emitting control signal of the second light-emitting control signal line EM2 are at low potentials. The first transistor T1, the second transistor T2, the driving transistor T3, and the fourth transistor T4 are turned on, while the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off. The potential of the first node N1 remains unchanged at the reset signal, and the potential of the third node N3 remains unchanged at the initialization signal. Since the reset signal is at a high potential, the driving transistor T3 is turned on. The potential of the second node N2 gradually rises due to the leakage of the first power supply signal through the driving transistor T3, and finally stabilizes at Vref-Vth, at which point the driving transistor T3 is turned off. At this time, the potential difference across the first storage capacitor C1 is Vth.

[0074] The third stage (data writing stage): The second control signal of the second control signal line Gate2 and the third control signal of the third control signal line Gate3 are at high potentials. The fourth transistor T4 and the fifth transistor T5 are turned on, and the remaining transistors are turned off. At this time, the data signal on the data signal line Vdata is the data voltage corresponding to the grayscale of the light-emitting device OLED. The third node N3 writes the data signal because the fifth transistor T5 is turned on. The first node N1 holds the reset signal because the fourth transistor T4 is turned on. The potential of the second node N2 changes from the initialization signal to the data signal because the potential of the third node N3 changes. The voltage jump variable of the first storage capacitor C1 and the second storage capacitor C2 is C1 / (C1+C2)*(Vdata-Vint). Therefore, the final potential of the second node N2 is Vref-Vth+C1 / (C1+C2)*(Vdata-Vint). The potential difference across the second storage capacitor C1 is Vth-C1 / (C1+C2)*(Vdata-Vint).

[0075] Fourth stage (light emission stage): The first control signal of the first control signal line Gate1, the second control signal of the second control signal line Gate2, and the third control signal of the third control signal line Gate3 are all at low potentials. The first light emission control signal of the first light emission control signal line EM1 and the second light emission control signal of the second light emission control signal line EM2 are at high potentials. Only the driving transistor T3, the first light emission control transistor T6, and the second light emission control transistor T7 are turned on, while the other transistors are turned off. At the previous moment, the potential of the first node N1 was Vref, and the potential of the third node N3 was Vref-Vth+C1 / (C1+C2)*(Vdata-Vint). Therefore, for the driving transistor T3, Vgs=Vth-C1 / (C1+C2)*(Vdata-Vint), and the driving current of the OLED device is I=1 / 2*K*[C1 / (C1+C2)*(Vdata-Vint)]. 2 As can be seen from the above process of driving the light-emitting device, the driving current formula for the OLED light-emitting device does not include the first power supply voltage VDD, resulting in a smaller voltage drop, which can further improve the display effect of the display image.

[0076] The detection process can be divided into two stages, namely the first stage and the second stage.

[0077] In the first stage (reset stage), the third control signal of the third control signal line Gate3 is at a high level, which can input the reset signal of the reset signal line Vref to the first node N1 to reset the gate of the driving transistor T3, thereby avoiding the influence of other voltage signals on the potential of the first node N1 and improving the detection accuracy.

[0078] In the second stage (detection stage), the first control signal of the first control signal line Gate1, the second control signal of the second control signal line Gate2, the first light emission control signal of the first light emission control signal line EM1, and the second light emission control signal of the second light emission control signal line EM2 are at high potentials. The second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned on. The first node N1 retains the reset signal from the previous moment, and the driving transistor T3 is turned on. In this way, a current loop can be formed between the first power supply signal line VDD and the data signal line Vdata (sensing signal line Sensor). The functionality of the driving transistor T3 can be determined by detecting whether there is current in the data signal line Vdata.

[0079] Secondly, this disclosure provides a display device that includes the pixel circuit described in any of the above embodiments. The display device can be any product or component with display functionality, such as a television, mobile phone, monitor, laptop computer, digital photo frame, or navigator. Its implementation principle is similar to that of the pixel circuit described above and will not be repeated here.

[0080] Thirdly, embodiments of this disclosure provide a method for driving a pixel circuit, which can drive the pixel circuit provided in any of the above embodiments. Figure 5 This is a flowchart illustrating a pixel circuit driving method provided in an embodiment of the present disclosure, as shown below. Figure 5 As shown, the driving method of the pixel circuit includes the following steps S501 to S503.

[0081] S501, in the threshold compensation stage, in response to the first control signal of the first control signal line, writes the threshold voltage to the second node.

[0082] During the threshold compensation phase: the first control signal of the first control signal line Gate1, the third control signal of the third control signal line Gate3, and the first light-emitting control signal of the first light-emitting control signal line EM1 are at high potentials; the second control signal of the second control signal line Gate2 and the second light-emitting control signal of the second light-emitting control signal line EM2 are at low potentials; the first transistor T1, the second transistor T2, the driving transistor T3, and the fourth transistor T4 are turned on; and the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off. The potential of the first node N1 remains unchanged at the reset signal level, and the potential of the third node N3 remains unchanged at the initialization signal level. Because the reset signal is at a high potential, the driving transistor T3 is turned on. The potential of the second node N2 gradually rises due to the leakage current from the first power supply signal through the driving transistor T3, eventually stabilizing at Vref-Vth, at which point the driving transistor T3 is turned off. At this time, the potential difference across the first storage capacitor C1 is Vth.

[0083] S502, in the data writing phase, responds to the second control signal of the second control signal line and writes the data signal of the data signal line to the third node.

[0084] During the data writing phase: the second control signal of the second control signal line Gate2 and the third control signal of the third control signal line Gate3 are at high potentials, the fourth transistor T4 and the fifth transistor T5 are turned on, and the remaining transistors are turned off. At this time, the data signal on the data signal line Vdata is the data voltage corresponding to the grayscale of the light-emitting device OLED. The third node N3 writes the data signal because the fifth transistor T5 is turned on. The first node N1 holds the reset signal because the fourth transistor T4 is turned on. The potential of the second node N2 changes from the initialization signal to the data signal due to the third node N3. The voltage jump of the first storage capacitor C1 and the second storage capacitor C2 is C1 / (C1+C2)*(Vdata-Vint), so the final potential of the second node N2 is Vref-Vth+C1 / (C1+C2)*(Vdata-Vint). The potential difference across the second storage capacitor C1 is Vth-C1 / (C1+C2)*(Vdata-Vint).

[0085] S503, during the testing phase, responds to the test control signal of the test control signal line to control the connection and disconnection between the first power signal line and the sensing signal line in order to detect whether the driving transistor is normal.

[0086] During the testing phase, the first control signal of the first control signal line Gate1, the second control signal of the second control signal line Gate2, the first light emission control signal of the first light emission control signal line EM1, and the second light emission control signal of the second light emission control signal line EM2 are all at high potentials. The second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned on. The first node N1 retains the reset signal from the previous moment, and the driving transistor T3 is turned on. In this way, a current loop can be formed between the first power supply signal line VDD and the data signal line Vdata (sensing signal line Sensor). The functionality of the driving transistor T3 can be determined by detecting whether there is current in the data signal line Vdata.

[0087] It should be noted that the driving method of the pixel circuit also includes a light emission stage and an initialization stage, which can be referred to the description of the working process of the pixel circuit in the above embodiments, and will not be described in detail here.

[0088] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A pixel circuit, wherein, The pixel circuit includes: a first storage capacitor, a second storage capacitor, a driving transistor, a threshold compensation sub-circuit, a data writing sub-circuit, a test sub-circuit, and a light-emitting device; One end of the first storage capacitor is connected to the first node, and the other end is connected to the second node; One end of the second storage capacitor is connected to the second node, and the other end is connected to the third node; The control electrode of the driving transistor is connected to the first node, the first electrode is connected to the first power signal line, and the second electrode is connected to the second node. The threshold compensation sub-circuit is configured to write a threshold voltage into a second node in response to a first control signal on a first control signal line to compensate for the threshold voltage of the driving transistor. The data writing sub-circuit is configured to write the data signal of the data signal line to the third node in response to the second control signal line; The test sub-circuit is configured to control the connection and disconnection between the first power supply signal line and the sensing signal line in response to the test control signal of the test control signal line, so as to detect whether the driving transistor is normal. The first electrode of the light-emitting device is connected to the second node, and the second electrode is connected to the second power signal line. The threshold compensation sub-circuit and the data writing sub-circuit are multiplexed into the test sub-circuit; The first control signal line and the second control signal line are multiplexed into the test control signal line; The data signal lines are multiplexed into the sensing signal lines.

2. The pixel circuit according to claim 1, wherein, The pixel circuit further includes: a first reset sub-circuit; The first reset sub-circuit is configured to write the initialization signal of the initialization signal line to the third node in response to the first control signal line.

3. The pixel circuit according to claim 2, wherein, The first reset sub-circuit includes a first transistor; the threshold compensation sub-circuit includes a second transistor. The control electrode of the first transistor is connected to the first control signal line, the first electrode is connected to the initialization signal line, and the second electrode is connected to the first electrode of the second transistor. The control electrode of the second transistor is connected to the first control signal line, the first electrode is connected to the second electrode of the first transistor, and the second electrode is connected to the third node.

4. The pixel circuit according to claim 3, wherein, The pixel circuit further includes: a second reset sub-circuit; The second reset sub-circuit is configured to write the reset signal of the reset signal line to the first node in response to the third control signal of the third control signal line.

5. The pixel circuit according to claim 4, wherein, The second reset circuit includes: a fourth transistor; The control electrode of the fourth transistor is connected to the third control signal line, the first electrode is connected to the reset signal line, and the second electrode is connected to the first node.

6. The pixel circuit according to claim 4, wherein, The pixel circuit further includes: a first light-emitting control sub-circuit and a second light-emitting control sub-circuit; The first light-emitting control sub-circuit is configured to control the on / off connection between the first power supply signal line and the first terminal of the driving transistor in response to a first light-emitting control signal of the first light-emitting control signal line; The second light-emitting control sub-circuit is configured to control the on / off connection between the second terminal of the driving transistor and the first terminal of the light-emitting device in response to the second light-emitting control signal of the second light-emitting control signal line.

7. The pixel circuit according to claim 6, wherein, The first light-emitting control sub-circuit includes a sixth transistor; the second light-emitting control sub-circuit includes a seventh transistor. The control electrode of the sixth transistor is connected to the first light-emitting control signal line, the first electrode is connected to the first power signal line, and the second electrode is connected to the first electrode of the driving transistor. The control electrode of the seventh transistor is connected to the second light-emitting control signal line, the first electrode is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting device.

8. The pixel circuit according to claim 6, wherein, The first light-emitting control sub-circuit and the second light-emitting control sub-circuit are multiplexed into the test sub-circuit; The first light emission control signal line and the second light emission control signal line are multiplexed into the test control signal line.

9. The pixel circuit according to claim 8, further comprising: Test the reset circuit; The test reset sub-circuit is configured to write the test reset signal of the test reset signal line into the first node in response to the test reset control signal of the test reset control signal line.

10. The pixel circuit according to claim 9, wherein, The second reset sub-circuit is multiplexed as the test reset sub-circuit; the third control signal line is multiplexed as the test reset control signal line; and the reset signal line is multiplexed as the test reset signal line.

11. The pixel circuit according to claim 1, wherein, The data writing sub-circuit includes: a fifth transistor; The control electrode of the fifth transistor is connected to the second control signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the third node.

12. A display device, wherein, The display device includes the pixel circuitry as described in any one of claims 1 to 11.

13. A method for driving a pixel circuit, used to drive the pixel circuit as described in any one of claims 1 to 11, wherein, The driving method for the pixel circuit includes: During the threshold compensation phase, in response to the first control signal of the first control signal line, the threshold voltage is written to the second node; During the data writing phase, in response to the second control signal of the second control signal line, the data signal of the data signal line is written to the third node; During the testing phase, in response to the test control signal of the test control signal line, the connection and disconnection between the first power signal line and the sensing signal line are controlled to detect whether the driving transistor is normal.

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