Semiconductor structure preparation method, semiconductor structure and semiconductor device

Abstract

The present application provides a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor device, the method comprising: providing a substrate, and etching the substrate to form an active structure; the active structure comprises a first end and a second end, the first end of the active structure being farther away from the substrate than the second end of the active structure; forming a first material layer on a first region of the substrate; forming a first dummy gate structure across the active structure on the first material layer; flipping the semiconductor structure, and removing the substrate to expose the second end of the active structure and the first material layer; using the first material layer as an etching mask, etching the semiconductor structure until a preset height is reached; depositing semiconductor material on the semiconductor structure to form a second dummy gate structure; etching the second dummy gate structure until the active structure of the source and drain regions is exposed to form a third dummy gate structure; removing the first dummy gate structure and the third dummy gate structure to form a first gate structure and a second gate structure, respectively.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor device. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] When a stacked transistor is prepared using a traditional sequential method, it is difficult to self-align the gate structure between the upper and lower transistors and the preparation process is complicated. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor device to achieve self-alignment of gate structures between upper and lower transistors.

[0005] The method comprises: providing a substrate, and etching the substrate to form an active structure; wherein the active structure comprises a first end and a second end, and the first end of the active structure is farther from the substrate than the second end of the active structure; forming a first material layer on a first region of the substrate, and the first region is located at gate regions on both sides of the active structure; forming a first dummy gate structure across the active structure on the first material layer; flipping the semiconductor structure, and removing the substrate to expose the second end of the active structure and the first material layer; using the first material layer as an etching mask, etching the semiconductor structure until a preset height is reached; depositing semiconductor material on the semiconductor structure to form a second dummy gate structure; the height of the second dummy gate structure in the gate region is higher than the height of the second dummy gate structure in the source and drain region; etching the second dummy gate structure until the active structure in the source and drain region is exposed to form a third dummy gate structure; removing the first dummy gate structure and the third dummy gate structure to form a first gate structure and a second gate structure, respectively.

[0006] In some possible embodiments, the semiconductor structure is etched using the first material layer as an etching mask until a preset height is reached, including: using the first material layer as an etching mask to selectively etch the second end of the active structure in the gate region, the second end of the active structure in the source and drain region, and a shallow trench isolation structure surrounding the active structure, until the height difference between the active structure and the first dummy gate structure reaches a preset height, thereby forming a first groove in the gate region.

[0007] In some possible embodiments, semiconductor material is deposited on the semiconductor structure to form a second dummy gate structure, including: depositing semiconductor material on the source and drain regions and the gate region having the first groove by an isotropic deposition method until the first groove is filled; etching the second dummy gate structure until the active structure of the source and drain regions is exposed to form a third dummy gate structure, including: etching the second dummy gate structure by an anisotropic etching method until the active structure of the source and drain regions is exposed, and forming a third dummy gate structure in the gate region.

[0008] In some possible embodiments, the first dummy gate structure and the third dummy gate structure are removed to form a first gate structure and a second gate structure, respectively, including: removing the first dummy gate structure and the third dummy gate structure; depositing a first metal material at the removed first dummy gate structure to form a first gate structure; the height of the first gate structure wraps around a first portion of the active structure; the first end is located at the first portion; and depositing a second metal material on the first gate structure until it covers the removed third dummy gate structure to form a second gate structure.

[0009] In some possible embodiments, a first material layer is formed on a first area of ​​a substrate, including: depositing a hard mask material on the etched substrate until a second groove formed by an active structure is filled, and removing the hard mask material on the active structure using an etch-back process to form a second material layer; the active structure protrudes from the second material layer; and removing the second material layer located on the source and drain areas to form a first material layer on the first area of ​​the substrate.

[0010] In some possible embodiments, before depositing a hard mask material on the etched substrate until the second groove formed by the active structure is filled, the method also includes: depositing a first oxide material on the etched substrate to form an oxide layer; flipping the semiconductor structure and removing the substrate to expose the second end of the active structure and the first material layer located in the gate area, including: removing the substrate using a planarization process until the second end of the active structure and the oxide layer are exposed; removing the oxide layer in the gate area to expose the first material layer in the gate area.

[0011] In some possible embodiments, after forming a first dummy gate structure across the active structure on the first material layer, the method further includes: depositing a second oxide material in the source and drain region to form a shallow trench isolation structure, the shallow trench isolation structure covering the second portion of the active structure and exposing the first portion of the active structure; forming a first source and drain structure, a first source and drain metal, and a first interlayer dielectric layer in the source and drain region based on the first portion; etching the second dummy gate structure until the active structure in the source and drain region is exposed to form a third dummy gate structure, the method further includes: thinning the shallow trench isolation structure in the source and drain region to expose the second portion of the active structure; forming a second source and drain structure, a second source and drain metal, and a second interlayer dielectric layer in the source and drain region based on the second portion of the active structure.

[0012] In some possible embodiments, the substrate includes: a first substrate layer, a second substrate layer and a buried oxide layer which are stacked, and the buried oxide layer is located between the first substrate layer and the second substrate layer; etching the substrate to form an active structure includes: etching the first substrate layer, the buried oxide layer, and a first portion of the second substrate layer, retaining a second portion of the second substrate layer to form an active structure; wherein the first substrate layer forms a first portion of the active structure, and the first portion of the second substrate layer forms a second portion of the active structure.

[0013] In a second aspect, an embodiment of the present application provides a semiconductor structure, which can be prepared using a preparation method as in any embodiment of the first aspect. The semiconductor structure includes: a first transistor; a second transistor, wherein the first transistor and the second transistor are arranged opposite to each other; wherein the first active structure of the first transistor and the second active structure of the second transistor form an active structure, and the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

[0014] In some possible implementations, an isolation layer is formed between the first active structure and the second active structure, and the isolation layer is used to electrically isolate the first active structure from the second active structure; the isolation layer is generated by a buried oxide layer in the substrate.

[0015] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the above embodiment.

[0016] In an embodiment of the present application, during the preparation of the first transistor of the lower layer, a first material layer is set in the gate region so that after flipping the wafer, the gate region of the second transistor can be determined based on the position of the first material layer, thereby achieving self-alignment of the gate structures of the upper and lower transistors.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 A schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of a first structure of a semiconductor structure in an embodiment of the present application;

[0021] Figures 3 to 21 A schematic diagram of a preparation process of a semiconductor structure in an embodiment of the present application;

[0022] Fig. 22 A second structural schematic diagram of a semiconductor structure in an embodiment of the present application;

[0023] Fig.23 A third structural schematic diagram of a semiconductor structure in an embodiment of the present application;

[0024] Fig.24 A fourth structural schematic diagram of a semiconductor structure in an embodiment of the present application;

[0025] Figures 25 to 30 A schematic diagram of another preparation process of a semiconductor structure in an embodiment of the present application;

[0026] Figure 31 to Figure 34 It is a schematic diagram of another preparation process of the semiconductor structure in the embodiment of the present application.

[0027] The above figures: 10, semiconductor structure; 11, first transistor; 12, second transistor; 13, active structure; 131, first active structure; 132, second active structure; 21, substrate; 211, fin structure; 2111, first part of fin structure; 2112, second part of fin structure; 22, oxide layer; 23, silicon nitride material layer; 24, first pseudo-gate structure; 25, first material layer; 26, shallow trench isolation structure; 27, first spacer; 28, first source-drain structure; 29, first interlayer dielectric layer; 30, first A source-drain metal; 31. a first metal interconnection layer; 32. a first insulating layer; 33. a carrier; 34. a first groove; 35. a second dummy gate structure; 36. a third dummy gate structure; 37. a second spacer; 38. a second source-drain structure; 39. a second interlayer dielectric layer; 40. a metal gate structure; 401. a metal gate dielectric layer; 402. a metal gate electrode layer; 41. a first gate structure; 42. a second insulating layer; 43. a second gate structure; 44. a second source-drain metal; 45. a second metal interconnection layer; 46. a buried oxide layer; 47. a nanosheet structure. DETAILED DESCRIPTION

[0028] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0029] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0030] In one embodiment, there are two schemes for manufacturing a stacked transistor, the first is a monolithic scheme, and the second is a sequential scheme.

[0031] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layers of transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0032] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding the wafer on top of the already manufactured lower transistor, and the two transistors are stacked vertically. However, the temperature needs to be strictly controlled during the thermal process of processing the upper transistor to avoid affecting the lower transistor and the interconnection lines. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance.

[0033] The current challenges of the above solution are: because the manufacturing process is fixed, there is difficulty in aligning the upper and lower layer transistors.

[0034] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a semiconductor structure to achieve self-alignment of the gate structure between upper and lower transistors.

[0035] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memory and processor.

[0036] In one embodiment, the semiconductor structure may include at least two transistors, for example, a first transistor and a second transistor. The first transistor and the second transistor are arranged back to back. The first active structure in the first transistor and the second active structure in the second transistor are formed by the same process, and in this case, it can be understood that the first transistor and the second transistor are self-aligned.

[0037] In the embodiment of the present application, the first transistor and the second transistor in the semiconductor structure may be transistors of the same type, such as any one of the following: a fin field effect transistor, a gate-all-around transistor, and a planar transistor.

[0038] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application, see Figure 1 As shown, the method for preparing the semiconductor structure may include:

[0039] S101, providing a substrate, and etching the substrate to form an active structure.

[0040] The active structure includes a first end and a second end, and the first end of the active structure is farther away from the substrate than the second end of the active structure.

[0041] It should be noted that when the transistor in the semiconductor structure is a fin field effect transistor, the active structure is a fin structure; when the transistor in the semiconductor structure is a full-surround gate transistor, the active structure is a nanosheet structure; when the transistor in the semiconductor structure is a planar transistor, the active structure is a block structure.

[0042] In one embodiment, the substrate may be a silicon (Si) substrate or a silicon-on-insulator (SOI) substrate. Of course, the substrate may also be a substrate made of other semiconductor materials, which is not specifically limited in the embodiment of the present application.

[0043] It is understandable that when the type of semiconductor structure is different, the arrangement of the substrate is also different accordingly. For example, when the semiconductor structure is a fin field effect transistor or a planar transistor, the semiconductor substrate can be a single-layer structure, that is, a substrate made of one semiconductor material; when the semiconductor structure is a full-surround gate transistor, the semiconductor substrate can be a stacked structure, that is, a stacked layer obtained by stacking Si material and silicon germanium (SiGe) material.

[0044] In some embodiments, when the semiconductor structure is a fin field effect transistor, the above S101 may include: etching the substrate to form a plurality of fin structures.

[0045] In some other embodiments, when the semiconductor structure is a full-surround gate transistor, the above S101 may include: etching the substrate to form a columnar structure, wherein the substrate may be formed of alternately deposited silicon layers and silicon germanium layers.

[0046] In some other embodiments, when the semiconductor structure is a planar transistor, the above S101 may include: etching the substrate to form a block structure.

[0047] In the embodiment of the present application, since the semiconductor structure includes two transistors, and the first active structure of the first transistor and the second active structure of the second transistor are formed by the same etching process, a larger etching depth can be used when etching the semiconductor substrate. For example, the height of the fin-shaped structure (which may also be a columnar structure or a block structure) obtained by etching can be greater than 100 nm. It should be noted that the height of the fin-shaped structure can be set according to actual conditions, and the embodiment of the present application does not specifically limit this.

[0048] In one embodiment, the substrate may be an SOI substrate, including: a first substrate layer, a second substrate layer and a buried oxide layer which are stacked, wherein the buried oxide layer is located between the first substrate layer and the second substrate layer. The above S101 may include: etching a first portion of the first substrate layer, the buried oxide layer and the second substrate layer, and retaining a second portion of the second substrate layer to form an active structure.

[0049] The first substrate layer forms a first part of the active structure (i.e., the first active structure of the first transistor), and the first part of the second substrate layer forms a second part of the active structure (i.e., the second active structure of the second transistor). The first part of the active structure is farther from the substrate than the second part of the active structure, the first end of the active structure is located at the end of the first part, and the second end of the active structure is located at the end of the second part.

[0050] In one embodiment, the SOI substrate including the buried oxide layer can be formed by a variety of preparation processes, which are not specifically limited in the present embodiment. For example, a SOI substrate with a buried oxide layer is obtained by sequentially performing the preparation of a buried oxide layer, hydrogen ion implantation, bonding and splitting processes on a single crystal silicon wafer; or, by implanting oxygen ions to a certain depth below the surface of the silicon wafer. After high temperature annealing after ion implantation, a layer of buried silicon dioxide (buried oxide layer) is formed in the silicon wafer.

[0051] S102, forming a first material layer on a first region of the substrate.

[0052] The first region is located at the gate region on both sides of the active structure.

[0053] It is understandable that after etching the substrate to form the active structure, a first material layer can be formed based on the etched substrate, wherein the first material layer is located in the first region, that is, the first material layer is located in the gate region of the semiconductor structure, and the first material layer does not cover the active structure but is located on both sides of the active structure.

[0054] It should be noted that the semiconductor structure includes a gate structure that spans the active structure, and the location of the gate structure can be divided into a gate region of the semiconductor structure. The semiconductor structure also includes a source-drain structure located on both sides of the gate structure, and the location of the source-drain structure can be divided into a source-drain region of the semiconductor structure. The gate region and the source-drain region can be arranged at intervals.

[0055] In some embodiments, the above S102 may include: depositing a hard mask material on the etched substrate until the second groove formed by the active structure is filled, and removing the hard mask material on the active structure by an etching back process to form a second material layer; removing the second material layer located on the source and drain areas to form a first material layer on the first area of ​​the substrate.

[0056] The active structure protrudes from the second material layer, which can also be understood as the second material layer surrounding the circumference of the second end of the active structure but not covering the active structure.

[0057] It can be understood that after the second material layer located on the source and drain regions is removed, the gate region on the semiconductor structure still retains the second material layer, and the retained second material layer is the first material layer.

[0058] In one embodiment, the first material layer can be used as a hard mask in a subsequent etching process. The hard mask material forming the first material layer can be a material with high corrosion resistance and hardness, such as silicon nitride (SiN), silicon dioxide (SiO2), etc.

[0059] In other embodiments, the above S102 may include: depositing a first oxide material on the etched substrate to form an oxide layer; depositing a hard mask material on the oxide layer until the second groove formed by the active structure is filled, and using a back etching process to remove the hard mask material on the active structure to form the above-mentioned second material layer.

[0060] It is understandable that before forming the first material layer, a first oxide material can be deposited to form an oxide layer. The oxide layer can protect the active structure. On the one hand, it prevents the first material layer from directly contacting the substrate and generating a large stress. For example, when the active structure is a fin-shaped structure, the oxide layer can prevent the stress between the first material layer and the substrate from causing the fin-shaped structure to collapse. On the other hand, the oxide layer can also protect the surface of the active structure (such as the interface state, etc.).

[0061] Among them, the first oxide material can be silicon dioxide (SiO2), silicon oxycarbide (SiCO), etc., and this embodiment of the present application does not make any specific limitation on this.

[0062] S103 , forming a first dummy gate structure crossing the active structure on the first material layer.

[0063] It can be understood that, by depositing semiconductor material on the first material layer, a first dummy gate structure can be formed, wherein the first dummy gate structure spans across the active structure and wraps the active structure.

[0064] In some embodiments, the semiconductor material forming the first dummy gate structure may be polysilicon.

[0065] In some embodiments, after forming the first dummy gate structure, spacers may be formed on both sides of the first dummy gate structure.

[0066] In some embodiments, after the above S103, it may include: depositing a second oxide material in the source and drain region to form a shallow trench isolation structure, the shallow trench isolation structure covers the second part of the active structure and exposes the first part of the active structure; in the source and drain region, based on the first part, forming a first source and drain structure, a first source and drain metal and a first interlayer dielectric layer.

[0067] It is understandable that after the dummy gate structure is formed, a second oxide material may be deposited in the source and drain regions to form a shallow trench isolation (STI) structure, the height of which is sufficient to ensure that the STI structure covers the second portion of the active structure and exposes the first portion of the active structure.

[0068] It is understandable that in order to perform subsequent preparation of semiconductor structures on the active structure, such as preparing the first source-drain structure, the shallow trench isolation structure can be etched to expose the first part of the active structure for subsequent preparation processes.

[0069] In the embodiment of the present application, the second oxide material forming the shallow trench isolation structure may be any one of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO), etc.

[0070] It should be noted that the etching process mentioned in the embodiments of the present application may include any one of the following: dry etching, wet etching, reactive ion etching and chemical oxide removal process, which is not limited in the embodiments of the present application.

[0071] In some embodiments, after exposing the first portion of the active structure, ion implantation may be performed at a connection between the first portion of the active structure and the second portion of the active structure to form an electrical isolation layer, which is used to electrically isolate the first portion of the active structure (the first active structure) from the second portion of the active structure (the second active structure).

[0072] The ions implanted include P-type ions, N-type ions or oxygen ions. The P-type ions may be one of the following: boron (B), gallium (Ga), aluminum (Al). The N-type ions may be one of the following: phosphorus (P), arsenic (As), antimony (Sb).

[0073] It should be noted that when there is a buried oxide layer in the substrate, the buried oxide layer can form a natural electrical isolation between the first part and the second part, thereby eliminating the need for ion implantation at the connection between the first part and the second part.

[0074] It can be understood that after exposing the first portion of the active structure, a first source-drain structure, a first source-drain metal and a first interlayer dielectric layer may be formed in the source-drain region based on the first portion of the active structure.

[0075] The first interlayer dielectric layer may wrap the first active structure, the first source-drain structure and the first source-drain metal.

[0076] It should be noted that the first source-drain structure, the first source-drain metal and the first interlayer dielectric layer can all be formed through standard steps of a semiconductor manufacturing process, and the embodiments of the present application do not specifically limit this.

[0077] Exemplarily, a source-drain groove may be formed in the first portion of the exposed active structure. A source-drain epitaxial growth may be performed at the source-drain groove to obtain a first source-drain structure. A metal material may be deposited above the first source-drain structure to obtain a first source-drain metal. A semiconductor material may be deposited above the first active structure to obtain a first interlayer dielectric layer.

[0078] Exemplarily, a portion of the first active structure is removed by etching to provide a source-drain groove of the first semiconductor structure. A strained material such as silicon germanium or silicon carbide is formed in the source-drain groove by selective epitaxial growth to fill the source-drain groove of the first semiconductor structure, and then a first source-drain structure is formed on the strained material by a heavy doping process.

[0079] It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and / or the first drain electrode structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, the source-drain groove, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source electrode and / or drain electrode".

[0080] In some embodiments, after the above S103, the above method further includes: completing the post-process structure through standard steps of the semiconductor manufacturing process, and bonding the formed semiconductor structure to the carrier wafer.

[0081] It is understandable that after forming the first interlayer dielectric layer, a back-end process (such as deposition of dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.) can be performed on the first interlayer dielectric layer and the first dummy gate structure to form a first metal interconnect layer of the first transistor. An insulating material (such as silicon oxide) is deposited on the first metal interconnect layer to form a first insulating layer, and the first insulating layer is bonded to the carrier wafer.

[0082] In the embodiment of the present application, the first semiconductor structure is bonded to the carrier wafer, which can provide physical support for the flipped semiconductor structure after flipping the wafer, and effectively prevent the first semiconductor structure from being broken by external force during the preparation of the second transistor.

[0083] S104, flipping the semiconductor structure and removing the substrate to expose the second end of the active structure and the first material layer.

[0084] It is understandable that the semiconductor structure formed in S103 can be flipped so that the substrate of the semiconductor structure is placed upward, and then the substrate is removed by etching. After the substrate is removed, the second end of the active structure and the first material layer formed in S102 can be exposed.

[0085] The first material layer is located on both sides of the active structure of the gate region.

[0086] In some implementations, when an oxide layer is formed on the substrate, the above S104 may include: removing the substrate using a planarization process until the second end of the active structure and the oxide layer are exposed; and removing the oxide layer in the gate region to expose the first material layer in the gate region.

[0087] It can be understood that by performing a chemical-mechanical planarization (CMP) process on the substrate, the second end and the oxide layer of the active structure can be exposed, and then the oxide layer of the gate region is etched to expose the first material layer.

[0088] S105, using the first material layer as an etching mask, etching the semiconductor structure until a preset height is reached.

[0089] It can be understood that using the first material layer as an etching mask can protect the first dummy gate structure at the bottom of the first material layer from being etched, and the remaining structures not covered by the first material layer will be etched to a preset height.

[0090] Here, the preset height is less than the height of the second portion of the active structure. The preset height is correlated with the width of the active region to ensure that a groove with a preset aspect ratio is formed in the gate region and the height of the second portion of the active structure is sufficient for the back transistor.

[0091] For example, when preparing a fin transistor with a width of 10 nm, the preset height is 5-10 nm.

[0092] In one embodiment, the above S105 may include: using the first material layer as an etching mask, selectively etching the second end of the active structure in the gate area, the second end of the active structure in the source and drain area, and the shallow trench isolation structure surrounding the active structure, until the height difference between the active structure and the first dummy gate structure reaches a preset height, thereby forming a first groove in the gate area.

[0093] It can be understood that by selectively etching the second end of the active structure in the gate region, the height of the first dummy gate structure in the gate region can be kept unchanged, and the active structure in the gate region is etched down by a preset height, thereby forming a first groove in the gate region. The position of the first groove corresponds to the position of the active structure. By selectively etching the second end of the active structure in the source and drain region and the shallow trench isolation structure surrounding the active structure, the structure in the source and drain region can be etched down by a preset height as a whole, and the height of the source and drain region is the same as the height of the bottom of the first groove.

[0094] It should be noted that, in the semiconductor structure formed in S105 , the height of the first dummy gate structure in the gate region is higher than the heights of other structures.

[0095] In some embodiments, after the above S105, the step may further include: removing the first material layer.

[0096] It is understandable that the first material layer is used to locate the gate region and as an etching mask in the etching process. After etching is completed in S105, the height of the first dummy gate structure in the gate region is higher than the height of the source and drain region, and the gate region can be preliminarily located. At this time, the first material layer can be removed.

[0097] S106, depositing a semiconductor material on the semiconductor structure to form a second dummy gate structure.

[0098] Wherein, the height of the second dummy gate structure in the gate region is higher than the height of the second dummy gate structure in the source and drain regions.

[0099] It can be understood that the height of the first dummy gate in the gate region of the semiconductor structure formed in S105 is higher than the height at other positions. The height of the second dummy gate structure formed by depositing semiconductor material on the semiconductor must be higher in the gate region than in the source and drain regions.

[0100] Here, the semiconductor material of the second dummy gate structure may be the same as the material of the first dummy gate structure, for example, polysilicon, silicon nitride or amorphous carbon.

[0101] In some embodiments, the above S106 may include: depositing semiconductor material on the source and drain regions and the gate region having the first groove by an isotropic deposition method until the first groove is filled; etching polysilicon by an anisotropic etching method until the active structure of the source and drain regions is exposed, and forming a third dummy gate structure in the gate region.

[0102] It is understandable that, since the deposition of semiconductor material adopts an isotropic process, polysilicon will also be deposited on the sidewall of the first groove formed in the gate region, so the deposition rate at the first groove will be higher than the deposition rate at the source and drain regions. Therefore, after the first groove is filled, the height of the second dummy gate structure at the first groove is higher than the height of the source and drain regions, that is, the second dummy gate structure in the gate region is higher than the second dummy gate structure in the source and drain regions.

[0103] Furthermore, based on the feature that the second dummy gate structure in the gate region is higher than the second dummy gate structure in the source and drain regions, the gate region and the source and drain regions can be distinguished, and the position of the gate region can be obtained in a self-aligned manner, thereby forming a self-aligned dummy gate structure in subsequent steps.

[0104] S107 , etching the second dummy gate structure until the active structure of the source and drain regions is exposed to form a third dummy gate structure.

[0105] It can be understood that, since the height of the second dummy gate structure in the gate region is higher than that in the source and drain regions, the second dummy gate structure formed by etching S106 will first expose the active structure in the source and drain regions. When the active structure in the source and drain regions is exposed, etching can be stopped, and the second dummy gate structure in the gate region is retained, that is, a third dummy gate structure is formed.

[0106] In some embodiments, the above S107 may include: etching the second dummy gate structure in an anisotropic etching manner until the active structure of the source and drain regions is exposed, and forming a third dummy gate structure in the gate region.

[0107] It can be understood that by etching the second dummy gate structure using an anisotropic etching process, the height difference of the second dummy gate structure in the gate region and the source and drain region will not change, thereby removing the second dummy gate structure in the source and drain region and retaining the crystalline silicon structure (third dummy gate structure) in the gate region, thereby forming a self-aligned dummy gate structure of the semiconductor structure, that is, the first dummy gate structure and the third dummy gate structure are self-aligned.

[0108] In some embodiments, after the above S107, it may include: in the source and drain regions, thinning the shallow trench isolation structure to expose the second portion of the active structure; in the source and drain regions, forming a second source and drain structure, a second source and drain metal, and a second interlayer dielectric layer based on the second portion of the active structure.

[0109] Here, the process of forming the second source-drain structure, the second source-drain metal and the second interlayer dielectric layer can refer to the process of forming the first source-drain structure, the first source-drain metal and the first interlayer dielectric layer, and for the sake of brevity of the specification, it will not be repeated here.

[0110] S108 , removing the first dummy gate structure and the third dummy gate structure to form a first gate structure and a second gate structure respectively.

[0111] It can be understood that after forming the self-aligned first dummy gate structure and the third dummy gate structure, the first dummy gate structure and the third dummy gate structure can be removed, and metal materials can be deposited to form the first gate structure and the second gate structure respectively.

[0112] It should be noted that the first gate structure and the second gate structure can be formed through standard steps of a semiconductor manufacturing process, and the embodiments of the present application do not specifically limit this.

[0113] In the embodiment of the present application, the metal material of the first gate structure and the second gate structure can be any one of the following: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN). The materials of the first gate structure and the second gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

[0114] In the embodiment of the present application, the materials of the first gate structure and the second gate structure can be made of the same or different metal materials according to actual conditions, and the embodiment of the present application does not specifically limit this.

[0115] In some embodiments, the above S108 may include: removing the first dummy gate structure and the third dummy gate structure, depositing a first metal material at the removed first dummy gate structure to form a first gate structure; the height of the first gate structure wraps the first part of the active structure; depositing a second metal material on the first gate structure until it covers the removed third dummy gate structure to form a second gate structure.

[0116] The first end of the active structure is located at the first portion, and the first portion of the active structure is used to form a first transistor.

[0117] It can be understood that a first metal material is deposited at the first dummy gate structure to form a first gate structure, and the first gate structure wraps the first part of the active structure, exposing the second part of the active structure, so that a first transistor can be formed based on the first part of the active structure. A second metal material is deposited on the first gate structure until the second metal material covers the removed third gate structure to form a second gate structure, so that the second gate structure wraps the second part of the active structure, so that a second transistor can be formed based on the second part of the active structure. In the above process, the first dummy gate structure and the third dummy gate structure are self-aligned, so that the first gate structure and the second gate structure are self-aligned.

[0118] Here, the first metal material is different from the second metal material.

[0119] In one embodiment, the above S108 may include: removing the first dummy gate structure and the third dummy gate structure to form a metal gate; selectively etching the upper half of the metal gate and retaining the lower half of the metal gate to form a first gate structure. Depositing an insulating medium on the first gate structure to form an insulating layer. The insulating layer is used to isolate the first gate structure of the first transistor from the second gate structure of the second transistor. Depositing a metal material on the insulating layer to form a second gate structure.

[0120] The metal gate may include: a gate dielectric layer and a gate electrode layer.

[0121] In one embodiment, etching the upper metal gate may include: etching the gate electrode layer of the upper portion, the gate dielectric layer and the gate electrode layer of the lower portion forming a first gate structure, and the gate dielectric layer of the upper portion and the metal material deposited on the upper portion forming a second gate structure.

[0122] In one embodiment, etching the upper metal gate may further include etching the upper gate dielectric layer and the upper gate electrode layer. When a metal material is deposited on the insulating layer, a second gate structure is directly formed.

[0123] In some embodiments, after the above S108, the above method further includes: completing a post-process structure through standard steps of a semiconductor manufacturing process to form a semiconductor structure in the embodiment of the present application.

[0124] It can be understood that after forming the first gate structure and the second gate structure, a post-process (such as deposition of dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.) can be performed on the second source and drain metal and the second gate structure to form a second metal interconnect layer of the second transistor.

[0125] In an embodiment of the present application, a substrate is provided and an active structure is formed on the substrate, so that the active structure of two transistors can be formed through one process; a first transistor is formed by using the first part of the active structure, and a second transistor is formed by using the second part of the active structure after flipping the wafer, so that the upper and lower layers of transistors are self-aligned.

[0126] In addition, during the preparation of the first transistor in the lower layer, a first material layer is provided in the gate region so that after flipping the wafer, the gate region of the second transistor can be determined based on the position of the first material layer, thereby achieving self-alignment of the gate structures of the upper and lower transistors.

[0127] Below, the active structure in the semiconductor structure is a fin-shaped structure as an example to illustrate the method for preparing the semiconductor structure provided in the embodiment of the present application. Figure 2 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application. Figure 2 (a) is a top view of a semiconductor structure. It should be noted that, for ease of understanding, only the fin structure, the gate structure, and the source-drain structure are shown in the top view; Figure 2 (b) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the gate structure (i.e., the AA' direction); Figure 2 (c) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the source-drain structure (i.e., BB' direction); Figure 2 (d) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction (ie, CC' direction) of the fin structure.

[0128] See also Figure 2 As shown, the semiconductor structure 10 includes a first transistor 11 and a second transistor 12, and the active structure in the semiconductor structure 10 is a plurality of fin structures. The fin structure is divided into two parts, namely, the first part and the second part, the first part is used as the first active structure in the first transistor 11, and the second part is used as the second active structure in the second transistor 12. The first gate structure 41 in the first transistor 11 and the second gate structure 43 in the second transistor 12 are self-aligned.

[0129] Here, self-alignment refers to that during the manufacturing process, the first gate structure 41 and the second gate structure 43 are aligned.

[0130] In combination with the above preparation method, Figure 2 The preparation process of the semiconductor structure shown is described. Figures 3 to 21 is a schematic diagram of a preparation process of a semiconductor structure in an embodiment of the present application, wherein: Figure 3 (a) to Fig.21(a) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., AA' direction). Figure 3 (b) to Fig.21 (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., BB' direction); Figure 3 (c) to Fig.21 (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction (ie, CC' direction) of the fin structure.

[0131] In one example, a process for preparing the semiconductor structure 10 may include the following steps:

[0132] Step 1: Patterning and etching are performed on the silicon substrate 21 through standard steps of semiconductor manufacturing process to form a fin structure 211, and the fin structure 211 is obtained as shown in FIG. Figure 3 The structure shown.

[0133] It should be noted that the height of the fin structure 211 may be greater than 100 nm.

[0134] Step 2: In Figure 3 An oxide material is deposited on the structure shown in the figure to form an oxide layer 22 of the fin structure; silicon nitride is then deposited on the oxide layer 22, and the silicon nitride is etched back to form a silicon nitride material layer, so as to obtain Figure 4 The structure shown.

[0135] Step 3: Open the Figure 4 The gate region of the structure shown in FIG. 1 is formed by depositing polysilicon as a first dummy gate structure 24 on the gate region to obtain a gate region as shown in FIG. Figure 5 The structure shown.

[0136] Here, the first dummy gate structure 24 spans across the plurality of fin structures 211 in the AA′ direction and is arranged at intervals in the CC′ direction.

[0137] Step 4: Remove the silicon nitride material layer 23 in the area not covered by the dummy gate to obtain Figure 6 The structure shown.

[0138] It can be understood that the silicon nitride material layer that is not removed forms the first material layer 25 , and the first material layer 25 covers the first region.

[0139] Here, the first region is located at the gate region on both sides of the fin structure 211 .

[0140] Step 5: Figure 6In the structure shown in the figure, an oxide material is deposited in the source and drain regions to form a first shallow trench isolation layer; the first shallow trench isolation layer is etched to form a second shallow trench isolation layer (i.e., shallow trench isolation structure 26). The height of the upper surface of the shallow trench isolation structure 26 is lower than the first portion 2111 (top) of the fin structure 211, and the structure shown in the figure is obtained. Figure 7 The structure shown.

[0141] Step 6: Figure 7 In the gate region of the structure shown in the figure, the first spacer 27 of the first transistor 11 is formed by the standard steps of the semiconductor manufacturing process; Figure 7 The source and drain regions of the structure shown in FIG. 1 are formed by completing the first source and drain structure 28 and the first interlayer dielectric layer 29 of the first transistor 11 through standard steps of semiconductor manufacturing process to obtain the structure shown in FIG. Figure 8 The structure shown.

[0142] Step 7: Figure 8 The source-drain region in the structure shown in the figure is completed with the first source-drain metal 30 of the first transistor 11, and the back-end interconnection process of the first transistor 11 is completed on the source-drain region and the gate region to form a first metal interconnection layer 31. The first metal interconnection layer 31 is connected to the first source-drain metal 30, and the structure shown in the figure is as follows: Fig. 9 The structure shown.

[0143] Step 8: Fig. 9 An insulating oxide is deposited on the structure shown in FIG. 1 to form a first insulating layer 32; a carrier 33 is bonded to the first transistor 11 above the first insulating layer 32, and then the carrier 33 is flipped to obtain a structure as shown in FIG. Fig.10 The structure shown.

[0144] Step 9: Thin the wafer and use a chemical mechanical planarization process to selectively stop above the oxide layer 22, thereby exposing the end of the second portion 2112 of the fin structure 211, and obtaining Fig.11 The structure shown.

[0145] Step 10: Use a selective etching process to etch the oxide layer 22 and the fin structure 211, at least etching away a preset height, to obtain Fig.12 The structure shown.

[0146] Here, the first material layer 25 in the first region can be used as an etching mask to protect the first dummy gate structure 24 at the bottom of the first material layer 25 from being etched. Thus, in the AA' direction, a plurality of first grooves 34 are formed in the gate region. The groove depth of the first groove 34 is equal to the preset height.

[0147] Step 11: Fig.12 Polysilicon is deposited isotropically on the structure shown in FIG. Fig.13 The structure shown.

[0148] It should be noted that, since the deposition method is isotropic deposition, deposition will also occur on the sidewall of the first groove 34 in the gate region, so the first groove 34 (such as Fig.13 The deposition thickness of the source and drain regions (as shown by the solid arrows in Fig.13 In the cross section of the fin structure ( Fig.13 When observed in (c) above, the polysilicon in the gate region is higher than the polysilicon in the source and drain regions.

[0149] Further, polysilicon is deposited continuously until the first groove 34 in the gate region is filled and leveled, thereby obtaining Fig.14 The structure shown.

[0150] It should be noted that, when the first groove 34 in the gate region is filled, a second dummy gate structure 35 is formed. Fig.14 When observing (c) in FIG. 1 , the height of the second pseudo gate structure 35 in the gate region (eg Fig.14 ) is higher than the height of the second dummy gate structure 35 in the source and drain regions (as shown by the solid arrow in Fig.14 ).

[0151] Step 12: Etching using anisotropic etching Fig.14 The second pseudo gate structure 35 in the structure shown in FIG. 1 is formed until the polysilicon in the source and drain regions is completely removed, leaving only the polysilicon in the gate region, to obtain a structure as shown in FIG. Fig.15 The structure shown.

[0152] It should be noted that, due to the anisotropic etching method, the height difference of the polysilicon in the gate region and the source and drain regions does not change. When the polysilicon in the source and drain regions is completely etched, the polysilicon in the gate region still exists. The polysilicon in the gate region can form a third dummy gate structure 36 .

[0153] It should be noted that the third dummy gate structure 36 is located in the gate region, so as to achieve self-alignment with the first dummy gate structure 24 .

[0154] Step 13: Removal Fig.15 The first material layer 25 on the structure shown in FIG. 1 is selectively etched to form the shallow trench isolation structure 26, thereby exposing the second portion 2112 of the fin structure 211, and obtaining the structure shown in FIG. Fig.16 The structure shown.

[0155] It should be noted that the exposed second portion 2112 of the fin structure 211 is prepared by the same process as the first portion 2111 of the fin structure 211. Therefore, the fin structures 211 of the first transistor 11 and the second transistor 12 are of the same origin, so that during the preparation of the second transistor 12, the active structure is self-aligned without the need for additional photolithography.

[0156] In one embodiment, the first material layer 25 may be removed before the eleventh step.

[0157] Step 14: Fig.16 In the gate region of the structure shown in the figure, the second spacer 37 of the second transistor 12 is formed by the standard steps of the semiconductor manufacturing process; Fig.15 The source-drain region of the structure shown in FIG. 1 is formed by completing the second source-drain structure 38 and the second interlayer dielectric layer 39 of the second transistor 12 through standard steps of semiconductor manufacturing process to obtain the structure shown in FIG. Fig.17 The structure shown.

[0158] Step 15: Remove the first dummy gate structure 24 and the third dummy gate structure 36, and deposit metal material at the positions of the first dummy gate structure 24 and the third dummy gate structure 36 to form a metal gate structure 40, so as to obtain Fig.18 The structure shown.

[0159] It should be noted that the metal gate structure 40 may include a metal gate dielectric layer 401 and a metal gate electrode layer 402 .

[0160] Step 16: Selective Etching Fig.18 The metal gate structure 40 in the structure shown in FIG. 1 is removed to remove the metal gate structure 40 in the second transistor 12 region to obtain Fig.19 The structure shown.

[0161] It should be noted that, in this step, only the metal gate electrode layer 402 in the metal gate structure 40 may be etched.

[0162] In some embodiments, the metal gate dielectric layer 401 and the metal gate electrode layer 402 in the metal gate structure 40 may be etched.

[0163] It should be noted that the retained metal gate structure 40 in the region of the first transistor 11 can form a first gate structure 41 .

[0164] Step 17: Deposit an insulating material on the first gate structure 41 to form a second insulating layer 42, and obtain Fig. 20 The structure shown.

[0165] Step 18: Deposit a metal material on the second insulating layer 42 to form a second gate structure 43 of the second transistor 12, thereby obtaining Fig.21 The structure shown.

[0166] Here, the first gate structure 41 of the first transistor 11 and the second gate structure 43 of the second transistor 12 may be self-aligned.

[0167] It should be noted that the second insulating layer 42 is used to electrically isolate the first gate structure 41 from the second gate structure 43 .

[0168] Step 19: Fig.21 The source-drain region in the structure shown in FIG. 1 is used to complete the second source-drain metal 44 of the second transistor 12, and the back-end interconnection process of the second transistor 12 is completed on the source-drain region and the gate region to form a second metal interconnection layer 45. The second metal interconnection layer 45 is connected to the second source-drain metal 44 to obtain the following structure: Figure 2 The structure shown.

[0169] At this point, the first transistor and the second transistor are fabricated, and the first gate structure 41 is aligned with the second gate structure 43 .

[0170] In one example, Fig. 22 Schematic diagram of the second structure of the semiconductor structure in the embodiment of the present application. Fig. 22 (a) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., AA' direction). Fig. 22 (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., BB' direction); Fig. 22 (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction (ie, CC' direction) of the fin structure.

[0171] The second semiconductor structure is different from the first semiconductor structure in that the substrate 21 in the second semiconductor structure 10 may include: a first substrate layer, a second substrate layer and a buried oxide layer 46 which are stacked. The buried oxide layer 46 is located between the first substrate layer and the second substrate layer. For example, it is a silicon-on-insulator (SOI) substrate.

[0172] In the second semiconductor structure, the first substrate layer can be used to form a first part 2111 of the fin structure, and the second part of the second substrate layer can be used to form a second part 2112 of the fin structure, so that electrical isolation can be achieved by utilizing the buried oxide layer 46 between the first part 2111 of the fin structure and the second part 2112 of the fin structure.

[0173] In one example, Fig.23 This is a schematic diagram of the third structure of the semiconductor structure in the embodiment of the present application. Fig.24This is a schematic diagram of the fourth structure of the semiconductor structure in the embodiment of the present application. Fig.23 (a) in 24 to (a) in 25 are cross-sectional views of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., the AA' direction). Fig.23 (b) in 24 to (b) in 24 are cross-sectional views of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., the BB' direction); Fig.23 (c) in 24 to (c) in 24 are cross-sectional views of the semiconductor structure along the cross-sectional direction of the active structure (ie, CC' direction).

[0174] like Fig.23 and Fig.24 As shown, the first transistor 11 and the second transistor 12 are arranged opposite to each other. The first active structure 131 of the first transistor 11 and the second active structure 132 of the second transistor 12 form an active structure 13, and the first gate structure 41 of the first transistor 11 and the second gate structure 43 of the second transistor 12 are self-aligned. Fig.23 The active structure in can be a nanosheet structure, Fig.24 The active structure in can be a block structure.

[0175] It should be noted that Figure 22 to Figure 24 The semiconductor structures shown can all be used Figure 1 The steps in one or more corresponding embodiments are used for preparation, which will not be described in detail for the sake of brevity of the specification.

[0176] Combine the following Figure 1 The steps in one or more embodiments corresponding to Fig.23 The preparation process of the semiconductor structure shown is briefly described. Figures 25 to 30 is a schematic diagram of another preparation process of a semiconductor structure in an embodiment of the present application, wherein: Fig.25 (a) to Fig.30 (a) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., AA' direction). Fig.25 (b) to Fig.30 (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., BB' direction); Fig.25 (c) to Fig.30 (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the nanosheet structure (ie, CC' direction).

[0177] In one example, another process for preparing the semiconductor structure 10 may include the following steps:

[0178] Step 1: Graphically and etch the silicon substrate 21 through the standard steps of the semiconductor manufacturing process to form a nanosheet structure 47; deposit silicon nitride on the substrate 21 formed with the nanosheet structure 47, and etch back the silicon nitride to form a silicon nitride material layer; deposit polysilicon on the gate region of the semiconductor structure 10 as a first pseudo-gate structure 24; remove the silicon nitride material layer in the area not covered by the first pseudo-gate structure 24 (source and drain area) to form a first material layer 25; deposit oxide material in the source and drain area to form a first shallow trench isolation layer; etch the first shallow trench isolation layer to form a second shallow trench isolation layer (i.e., shallow trench isolation structure 26). The height of the upper surface of the shallow trench isolation structure 26 is lower than the first part of the nanosheet structure 47 (which is subsequently formed). Fig.23 The first active structure 131 in FIG. 1 is obtained as follows: Fig.25 The structure shown.

[0179] Step 2: In Fig.25 In the gate region of the structure shown, the first spacer 27 of the first transistor 11 is formed by the standard steps of the semiconductor manufacturing process; in the source and drain region, the first source and drain structure 28 and the first interlayer dielectric layer 29 of the first transistor 11 are completed by the standard steps of the semiconductor manufacturing process. Subsequently, the first source and drain metal 30 of the first transistor 11 is completed in the source and drain region, and the back-end interconnection process of the first transistor 11 is completed on the source and drain region and the gate region to form a first metal interconnection layer 31. The first metal interconnection layer 31 is connected to the first source and drain metal 30 to obtain the following. Fig.26 The structure shown.

[0180] Step 3: In Fig.26 An insulating oxide is deposited on the structure shown in the figure to form a first insulating layer 32; a carrier 33 is bonded to the first transistor 11 above the first insulating layer 32. The wafer is then flipped over, the wafer is thinned, and a chemical mechanical planarization process is used to stop above the first material layer 25, thereby exposing the end of the second portion of the nanosheet structure 47, and obtaining the following: Fig. 27 The structure shown.

[0181] Step 4: Use a selective etching process to etch the nanosheet structure 47 not covered by the first material layer 25, at least etching away a preset height, to obtain Fig.28 The structure shown.

[0182] Here, the first material layer 25 in the first region can be used as an etching mask to protect the first dummy gate structure 24 at the bottom of the first material layer 25 from being etched. Thus, in the AA' direction, a first groove 34 is formed in the gate region. The groove depth of the first groove 34 is equal to the preset height.

[0183] Step 5: Remove the first material layer 25, and deposit polysilicon by isotropic deposition to obtain Fig.29 The structure shown.

[0184] It should be noted that, since the deposition method is isotropic deposition, deposition will also be performed on the sidewalls of the first groove 34 in the gate region, so the deposition thickness in the first groove 34 will be higher than that in the source and drain regions. When observing the cross section of the fin structure, the polysilicon in the gate region will be higher than that in the source and drain regions. Further, the polysilicon is deposited until the first groove 34 in the gate region is filled and leveled, and the following is obtained: Fig.29 The structure shown.

[0185] It should be noted that, when the first groove 34 in the gate region is filled, a second dummy gate structure 35 is formed. Fig.29 When observed in (c) in FIG. 1 , the height of the second dummy gate structure 35 in the gate region is higher than the height of the second dummy gate structure 35 in the source and drain regions.

[0186] Step 6: Etching using anisotropic etching Fig.29 The second dummy gate structure 35 in the structure shown in FIG. 1 is formed until the polysilicon in the source and drain regions is completely removed, leaving only the polysilicon in the gate region, to form a third dummy gate structure 36, and the structure shown in FIG. Fig.30 The structure shown.

[0187] It should be noted that, due to the anisotropic etching method, the height difference of the polysilicon in the gate region and the source and drain regions does not change. When the polysilicon in the source and drain regions is completely etched, the polysilicon in the gate region still exists. The polysilicon in the gate region can form a third dummy gate structure 36 .

[0188] It should be noted that the third dummy gate structure 36 is located in the gate region, so as to achieve self-alignment with the first dummy gate structure 24 .

[0189] Step 7: Fig.30 In the gate region of the structure shown in the figure, the second spacer 37 of the second transistor 12 is formed by the standard steps of the semiconductor manufacturing process; Fig.15 The source / drain region in the structure shown is formed by a standard step of semiconductor manufacturing process based on the second part of the nanosheet structure 47 (subsequently formed Fig.23 The second active structure 132 in the second transistor 12 is formed by forming a second source-drain structure 38 and a second interlayer dielectric layer 39. Subsequently, the first dummy gate structure 24 and the third dummy gate structure 36 are removed, and a first gate structure and a second gate structure are formed at the positions of the first dummy gate structure 24 and the third dummy gate structure 36. Subsequently, a second source-drain metal 44 of the second transistor 12 is formed in the source-drain region, and a back-end interconnection process of the second transistor 12 is completed on the source-drain region and the gate region to form a second metal interconnection layer 45. The second metal interconnection layer 45 is connected to the second source-drain metal 44 to obtain a structure as shown in FIG. Fig.23 The structure shown.

[0190] At this point, the first transistor and the second transistor are fabricated, and the first gate structure 41 is aligned with the second gate structure 43 .

[0191] In some possible embodiments, when the active structure is a nanosheet structure, the semiconductor material forming the nanosheet structure and the semiconductor material forming the first pseudo-gate structure may be materials that have high etching selectivity to each other, so that there is no need to form a first material layer during the preparation of the semiconductor structure. It only takes a selective etching process to etch the nanosheet structure after flipping the wafer, but not the first pseudo-gate structure, so that a first groove is formed at the nanosheet structure, thereby forming a second pseudo-gate structure that is self-aligned with the first pseudo-gate structure.

[0192] In this process, there is no need to form a first material layer as a hard mask, thereby reducing the complexity of the preparation process of the semiconductor structure.

[0193] In one embodiment, the nanosheet structure may be formed of a first semiconductor material (e.g., silicon (Si), silicon carbide (SiC), etc.) or a second semiconductor material (e.g., silicon germanium (SiGe), etc.). The first semiconductor material and the second semiconductor material may be materials having high etching selectivity to each other. The first semiconductor material or the second semiconductor material may also be a material having high etching selectivity to the material forming the first gate structure.

[0194] For example, when the semiconductor material in the nanosheet structure that is in contact with the substrate is silicon germanium, and the material of the first gate structure is polysilicon, there is a high etching selectivity between silicon germanium and polysilicon.

[0195] Figure 31 to Figure 34 Schematic diagram of another preparation process of the semiconductor structure in the embodiment of the present application. Fig.31 (a) to Fig.34 (a) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., AA' direction). Fig.31 (b) to Fig.34 (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., BB' direction); Fig.31 (c) to Fig.34 (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the nanosheet structure (ie, CC' direction).

[0196] In one example, another manufacturing process of the semiconductor structure 10 may include the following steps:

[0197] Step 1: Patterning and etching the silicon substrate 21 through standard steps of semiconductor manufacturing process to form a nanosheet structure 47; depositing polysilicon on the gate region of the semiconductor structure 10 as the first pseudo-gate structure 24; depositing oxide material in the source and drain regions to form a first shallow trench isolation layer; etching the first shallow trench isolation layer to form a second shallow trench isolation layer (i.e., shallow trench isolation structure 26). The height of the upper surface of the shallow trench isolation structure 26 is lower than the first part of the nanosheet structure 47 (which is subsequently formed). Fig.23 The first active structure 131 in FIG. 1 is obtained as follows: Fig.31 The structure shown.

[0198] Step 2: In Fig.31 In the gate region of the structure shown, the first spacer 27 of the first transistor 11 is formed by the standard steps of the semiconductor manufacturing process; in the source and drain region, the first source and drain structure 28 and the first interlayer dielectric layer 29 of the first transistor 11 are completed by the standard steps of the semiconductor manufacturing process. Subsequently, the first source and drain metal 30 of the first transistor 11 is completed in the source and drain region, and the back-end interconnection process of the first transistor 11 is completed on the source and drain region and the gate region to form a first metal interconnection layer 31. The first metal interconnection layer 31 is connected to the first source and drain metal 30 to obtain the following. Fig.32 The structure shown.

[0199] Step 3: In Fig.32 An insulating oxide is deposited on the structure shown in the figure to form a first insulating layer 32; a carrier 33 is bonded to the first transistor 11 above the first insulating layer 32. The wafer is then flipped, the wafer is thinned, and the substrate 21 is removed, thereby exposing the end of the second portion of the nanosheet structure 47, and obtaining the following: Fig.33 The structure shown.

[0200] Step 4: Use a selective etching process to etch the nanosheet structure 47, at least etching away a preset height, to obtain Fig.34 The structure shown.

[0201] Here, the nanosheet structure 47 and the first dummy gate structure 24 have high etching selectivity, so that the first dummy gate structure 24 is not etched. Thus, in the AA' direction, a first groove 34 is formed in the gate region. The groove depth of the first groove 34 is equal to a preset height.

[0202] Step 5: Deposit polysilicon by isotropic deposition to obtain Fig.29 The structure shown.

[0203] Understandably, the next steps are Figure 29 to Figure 30 The corresponding steps are the same until the Fig.23 For the sake of brevity of the description, it will not be described in detail here.

[0204] Thus, when the active structure is a nanosheet structure, the first transistor and the second transistor can be prepared without forming the first material layer 25, thereby effectively reducing the number of preparation steps and the complexity of preparation.

[0205] In one or more of the above-mentioned embodiments of preparing semiconductor structures, not only can the process flow of stacking transistors be greatly simplified, but also the consistency of the active structure and gate structure of the upper and lower transistors can be taken into account. In particular, the gate structure and active structure of the upper and lower transistors are self-aligned and stacked, which on the one hand solves the long-standing problems such as complex processes and alignment difficulties existing in the existing mainstream technical solutions for stacking transistors, and realizes the promotion of the industrialization of transistor stacking technology. On the other hand, through the self-aligned "back-to-back" active structure and gate structure, the upper and lower transistors can have independent signal and power supply networks, and are connected through local interconnection, which greatly releases metal wiring resources without changing the extremely miniaturized 4T track unit design.

[0206] Finally, the solution of realizing upper and lower transistors by flipping the wafer is compatible with the existing mainstream device architecture, and can realize the front and back stacking of planar transistors, FinFET, GAA Nanosheet and even vertical transistors (VTFET), without the need for special process development for specific device architectures. It is highly flexible and has strong extensibility from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, is highly practical, and has broad prospects for development.

[0207] The present application embodiment provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can be found in the above Figure 2 , Figure 22 to Figure 24 The semiconductor structure shown will not be described in detail here.

[0208] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be found in the above Figure 2 , Figure 22 to Figure 24 The semiconductor structure shown will not be described in detail here.

[0209] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0210] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: A substrate is provided, wherein the substrate comprises a first portion and a second portion along a thickness direction, and the substrate is etched to form a second groove and an active structure separated by the second groove in the first portion of the substrate; the active structure comprises a fin structure, a stacked nanosheet structure or a block structure; The gate region spans across the active structure, the source-drain region spans across the active structure, and the gate region and the source-drain region are different; the active structure includes a first end and a second end, and the first end of the active structure is farther away from the second portion of the substrate than the second end of the active structure; forming a first material layer on a first region of the substrate, wherein the first region is located at gate regions on both sides of the active structure; On the first material layer, forming a first dummy gate structure crossing the active structure; Flipping the wafer and removing the second portion of the substrate to expose the second end of the active structure and the first material layer; Using the first material layer as an etching mask, selectively etching the second end of the active structure until a preset height is reached; Depositing a semiconductor material to form a second dummy gate structure; wherein the height of the second dummy gate structure in the gate region is higher than the height of the second dummy gate structure in the source and drain regions; Etching the second dummy gate structure until the active structure of the source and drain regions is exposed, wherein the etched second dummy gate structure forms a third dummy gate structure in the gate region; The first dummy gate structure and the third dummy gate structure are removed to expose the active structure; the active structure includes a first part and a second part, the first end is located at the first part of the active structure, and the second end is located at the second part of the active structure; a first metal material is deposited at the removed first dummy gate structure to form a first gate structure; the first gate structure wraps the first part of the active structure; a second metal material is deposited on the first gate structure until it covers the removed third dummy gate structure to form a second gate structure; the second gate structure wraps the second part of the active structure.

2. The preparation method according to claim 1, characterized in that: After forming a first dummy gate structure across the active structure on the first material layer, the method further includes: forming a shallow trench isolation structure in the source-drain region, wherein the shallow trench isolation structure is located on both sides of the active structure, and the active structure protrudes from the shallow trench isolation structure; The step of using the first material layer as an etching mask to selectively etch the second end of the active structure until a preset height is reached includes: Using the first material layer as an etching mask, the second end of the active structure in the gate area, the second end of the active structure in the source and drain area and the shallow trench isolation structure are selectively etched until the height difference between the active structure and the first dummy gate structure reaches a preset height, and a first groove is formed in the gate area, the first groove is formed after the second end of the active structure in the gate area is etched, and the depth of the first groove is equal to the preset height.

3. The preparation method according to claim 2, characterized in that: The step of depositing a semiconductor material to form a second dummy gate structure includes: Semiconductor material is deposited on the source / drain region and the gate region having the first groove by an isotropic deposition method until the first groove is filled, wherein the deposited semiconductor material forms the second dummy gate structure.

4. The preparation method according to claim 2, characterized in that: The forming of a first material layer on the first region of the substrate comprises: Depositing a hard mask material on the etched substrate until the second groove is filled, and removing the hard mask material on the active structure by an etch-back process to form a second material layer; the active structure protrudes from the second material layer; The second material layer located on the source / drain region is removed, and the first material layer is formed on the second material layer on the first region of the substrate.

5. The preparation method according to claim 4, characterized in that: The active structure is a fin-shaped structure; The method further comprises depositing a hard mask material on the etched substrate until the second groove is filled: Depositing a first oxide material on the top, sidewalls and bottom of the second groove of the fin structure to form an oxide layer; The flipping and removing the second portion of the substrate to expose the second end of the active structure and the first material layer comprises: removing the second portion of the substrate by a planarization process until the second end of the active structure and the oxide layer are exposed; The oxide layer in the gate region is removed to expose the first material layer in the gate region.

6. The preparation method according to claim 4, characterized in that: After forming a first dummy gate structure across the active structure on the first material layer, the method further includes: Depositing a second oxide material in the source / drain region to form a shallow trench isolation structure, wherein the shallow trench isolation structure covers the second portion of the active structure and exposes the first portion of the active structure; In the source-drain region, based on the first part of the active structure, a first source-drain structure, a first source-drain metal and a first interlayer dielectric layer are formed; After etching the second dummy gate structure until the active structure of the source and drain regions is exposed, the method further includes: In the source and drain region, thinning the shallow trench isolation structure to expose a second portion of the active structure; In the source / drain region, based on the second portion of the active structure, a second source / drain structure, a second source / drain metal and a second interlayer dielectric layer are formed.

7. The preparation method according to claim 1, characterized in that: The substrate comprises: a first substrate layer, a second substrate layer and a buried oxide layer which are stacked, and the buried oxide layer is located between the first substrate layer and the second substrate layer.

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