A TMBS device and preparation method thereof

Abstract

The invention discloses a TMBS device and a preparation method thereof in the field of semiconductor technology. The TMBS device comprises: an N+ type silicon substrate; an N-type silicon epitaxial, arranged above the N+ type silicon substrate, a plurality of etched holes are arranged on the upper part of the N-type silicon epitaxial, the etched holes are composed of a shallow groove area located at the upper part and a deep hole area located at the lower part, the inner diameter of the deep hole area gradually decreases from top to bottom, silicon oxide is arranged on the inner wall of the etched hole, and the etched hole is filled with conductive polysilicon; a barrier alloy is arranged above the N-type silicon epitaxial; a front metal is arranged above the barrier alloy and the etched hole. The deep hole area at the lower part of the etched hole of the TMBS device forms an oblique sidewall shape, the charge coupling efficiency is enhanced, the electric field force is equally divided, and a higher avalanche breakdown voltage value is provided; and all the etched holes are placed in the N-type silicon epitaxial layer, so as to avoid excessive electric field strength in the Schottky contact area, concentrate the electric field lines at the bottom of the circular hole edge, and significantly reduce the leakage current under the same reverse bias voltage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a TMBS device and a preparation method thereof. Background Art

[0002] Power semiconductor devices determine the working efficiency, energy consumption, chip size and manufacturing cost in power electronics technology. The pn junction has a long reverse recovery time due to minority carrier storage, making it difficult to be used as a device in high-frequency applications. Schottky diodes have extremely fast switching speeds because metal and n-type semiconductors form electrical contact, and electrons control current transmission as majority carriers. Under reverse bias, there is no minority carrier storage. However, since the forward conduction voltage drop depends on the metal-semiconductor interface barrier height, drift region resistance, and the ohmic voltage drop of the substrate and ohmic contact, the avalanche breakdown voltage is directly related to the drift region resistance and has a 2.5-power functional relationship, making it difficult to improve the withstand voltage of Schottky diodes. TMBS is called a trench MOS Schottky diode. By introducing a trench structure, the maximum electric field strength originally belonging to the Schottky contact area is divided equally, thereby improving the withstand voltage, or using metals with lower work functions to reduce the overall on-state voltage drop and reduce power consumption during device use.

[0003] Conventional TMBS devices usually adopt a design of right-angled long strip trenches. By optimizing the trench size and increasing the trench spacing to increase the active area, the forward conduction voltage drop of the chip can be reduced to a certain extent; or the trench depth and the thickness of the oxide layer between the trenches can be changed to continuously optimize the distribution of the potential lines and divide the electric field force equally. However, the sidewalls of the trench are vertical structures. Although the bottom of the trench has been improved to a rounded corner, it is still easy to form a design similar to a spherical junction, resulting in concentrated electric field distribution at the corners of the trench edge, which is easy to break down prematurely and cause chip damage. These unfavorable factors have restricted the application of TMBS devices in the field of power semiconductor devices. Summary of the invention

[0004] The present application provides a TMBS device and a preparation method thereof, thereby solving the problem of concentrated electric field distribution at the corners of the groove edges of conventional TMBS devices in the prior art and susceptibility to premature breakdown, thereby achieving the effect of increasing the avalanche breakdown voltage and reducing the leakage current.

[0005] The embodiment of the present application provides a TMBS device, including:

[0006] N+ type silicon substrate;

[0007] An N-type silicon epitaxial layer is arranged above the N+ type silicon substrate, a plurality of etched holes are arranged on the upper part of the N-type silicon epitaxial layer, the etched holes are composed of a shallow groove area located at the upper part and a deep hole area located at the lower part, the inner diameter of the deep hole area gradually decreases from top to bottom, the inner wall of the etched hole is provided with silicon oxide, and the etched hole is filled with conductive polysilicon;

[0008] A barrier alloy disposed above the N-type silicon epitaxy;

[0009] A front metal is disposed above the barrier alloy and the etched hole;

[0010] The back metal is arranged below the N+ type silicon substrate.

[0011] The beneficial effects of the above embodiments are: the TMBS device reduces the area occupied by the original long strip groove without changing the chip size through the porous distribution structure, greatly increases the barrier alloy area of ​​the Schottky contact, and effectively reduces the on-state voltage drop; the deep hole area at the bottom of the etched hole of the TMBS device forms an oblique sidewall shape through the RIE etching process, and the overall inclination angle is 100-120°, which is changed from a right angle to an obtuse angle structure. Compared with the square column design at the bottom of the traditional groove, the charge coupling efficiency is enhanced, the electric field force is divided equally, and a higher avalanche breakdown voltage value is provided; the etched holes of the TMBS device are all placed in the N-type silicon epitaxial layer to avoid excessive electric field intensity in the surface Schottky contact area, and the electric field lines are concentrated at the bottom of the edges of the two layers of circular holes, further dividing the electric field force, effectively reducing the Schottky barrier lowering effect caused by the image force, and the leakage current is significantly reduced under the same reverse bias voltage. The static parameters of the TMBS device are comprehensively improved, and there is less power consumption and higher chip reliability in the field of high-frequency power devices.

[0012] Based on the above embodiments, the present application can be further improved as follows:

[0013] In one embodiment of the present application, the etched holes are evenly spaced and staggered on the N-type silicon epitaxy. The effective spacing of the Schottky barrier alloy region is adjusted so that the TMBS device has a larger active area and can reduce the on-state voltage drop.

[0014] In one embodiment of the present application, the inner diameter of the shallow groove area is larger than the maximum inner diameter of the deep hole area. The etched hole is designed with double grooves to form a step structure, which divides the maximum electric field strength twice, reduces the Schottky barrier lowering effect caused by the image force under reverse bias, and thus reduces leakage current.

[0015] In one embodiment of the present application, the shallow groove area has a depth of 0.5-0.7 μm, and the deep hole area has a depth of 1.5-4 μm, so as to transfer the maximum electric field strength from the Schottky metal contact surface to the bottom of the deep hole edge, thereby achieving the effect of improving the withstand voltage.

[0016] In one of the embodiments of the present application, the thickness of the silicon oxide in the etched hole is 100-400 nm.

[0017] In one of the embodiments of the present application, the polysilicon is phosphorus-diffused polysilicon.

[0018] In one embodiment of the present application, the barrier alloy is a Ni / Pt alloy. Using Ni / Pt alloy to form Schottky contact, controlling the metal content ratio to control the metal work function, the forward conduction voltage drop of TMBS decreases as the Ni content increases, and the leakage current increases due to the decrease in barrier height; when the Pt content increases, the barrier height increases, the leakage current decreases, and the on-state voltage drop increases; using Ni / Pt alloy is convenient for selecting the appropriate effect according to the chip usage scenario.

[0019] The present application also provides a method for preparing a TMBS device, comprising the following steps:

[0020] S1: growing the N-type silicon epitaxial layer on the N+ type silicon substrate;

[0021] S2: etching a plurality of circular hole windows of the shallow groove area arranged and distributed on the N-type silicon epitaxial layer, etching the deep hole area in the circular hole windows, wherein the inner diameter of the deep hole area gradually decreases from top to bottom;

[0022] S3: annealing and growing a silicon oxide layer on the N-type silicon epitaxy;

[0023] S4: depositing polysilicon on the silicon oxide layer by LPCVD, diffusing phosphorus into the polysilicon, and performing annealing;

[0024] S5: removing the excess polysilicon;

[0025] S6: depositing silicon oxide as an oxide layer on the silicon oxide and polysilicon;

[0026] S7: etching away the silicon oxide to expose the N-type silicon epitaxial layer, and at the same time, over-etching the polysilicon to be flush with the upper surface of the N-type silicon epitaxial layer;

[0027] S8: sputtering alloy on the N-type silicon epitaxy to form a Schottky contact and generate a barrier alloy;

[0028] S9: evaporating a front metal on the barrier alloy, silicon oxide, and polysilicon;

[0029] S10: Sputtering back metal on the lower surface of the N+ type silicon substrate.

[0030] In one of the embodiments of the present application, in the step S2, the circular hole windows are arranged in a staggered distribution, and adjacent windows form a diamond structure.

[0031] In one embodiment of the present application, the inner diameter of the shallow groove region is greater than the maximum inner diameter of the deep hole region, the depth of the shallow groove region is 0.5-0.7 μm, and the depth of the deep hole region is 1.5-4 μm.

[0032] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0033] 1. The TMBS device reduces the area occupied by the original long strip trench without changing the chip size through a porous distribution structure, greatly increases the barrier alloy area of ​​the Schottky contact, and effectively reduces the on-state voltage drop;

[0034] 2. The deep hole area at the bottom of the etched hole of the TMBS device is formed into an angled sidewall shape through the RIE etching process, and the overall inclination angle is 100-120°. Compared with the square column design at the bottom of the traditional trench, the charge coupling efficiency is enhanced, the electric field force is equally divided, and a higher avalanche breakdown voltage value is provided;

[0035] 3. All the etched holes of the TMBS device are placed in the N-type silicon epitaxial layer to avoid excessive electric field strength in the Schottky contact area, concentrate the electric field lines at the bottom of the circular hole edge, further divide the electric field force, and effectively reduce the Schottky barrier lowering effect caused by the image force. Under the same reverse bias voltage, the leakage current is significantly reduced;

[0036] 4. The static parameters of the TMBS device are comprehensively improved, resulting in lower power consumption and higher chip reliability in the field of high-frequency power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0038] Figure 1 Schematic diagram of the structure of the TMBS device in the embodiment;

[0039] Figure 2 The process diagram of the TMBS device preparation method in the embodiment is shown in FIG. Figure 1 ;

[0040] Figure 3 The process diagram of the TMBS device preparation method in the embodiment is shown in FIG. Figure 2 ;

[0041] Figure 4 The process diagram of the TMBS device preparation method in the embodiment is shown in FIG. Figure 3 ;

[0042] Figure 5 The process diagram of the TMBS device preparation method in the embodiment is shown in FIG. Figure 4 ;

[0043] Figure 6 The process diagram of the TMBS device preparation method in the embodiment is shown in FIG. Figure 5 ;

[0044] Figure 7 The process diagram of the TMBS device preparation method in the embodiment is shown in FIG. Figure 6 ;

[0045] Figure 8 The process diagram of the TMBS device preparation method in the embodiment is shown in FIG. Figure 7 .

[0046] Among them, 1. N+ type silicon substrate, 2. N- type silicon epitaxy, 3. silicon oxide, 4. polysilicon, 5. barrier alloy, 6. front metal, 7. back metal. DETAILED DESCRIPTION

[0047] The present invention is further explained below in conjunction with specific implementation methods. It should be understood that these implementation methods are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

[0048] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0049] In the description of the present invention, it should be noted that the terms "above", "below", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the inventive product is usually placed when in use. These are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on the present invention.

[0050] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0051] In the description of the present invention, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in the present invention and the features of different embodiments or examples without contradiction.

[0052] The embodiments of the present application provide a TMBS device and a method for preparing the same, thereby solving the problem of concentrated electric field distribution at the corners of the groove edges of conventional TMBS devices in the prior art and causing premature breakdown, thereby achieving the effect of increasing the avalanche breakdown voltage and reducing the leakage current.

[0053] The technical solution in the embodiment of the present application is to solve the above problems, and the overall idea is as follows:

[0054] Embodiment 1:

[0055] like Figure 1 As shown, a TMBS device comprises:

[0056] N+ type silicon substrate 1;

[0057] The N-type silicon epitaxy 2 is arranged above the N+ type silicon substrate 1. A plurality of etching holes are arranged on the upper part of the N-type silicon epitaxy 2. The etching holes are evenly spaced and staggered on the N-type silicon epitaxy 2. The etching holes are composed of a shallow groove area located at the upper part and a deep hole area located at the lower part. The inner diameter of the shallow groove area is larger than the maximum inner diameter of the deep hole area. The inner diameter of the deep hole area gradually decreases from top to bottom. Silicon oxide 3 is arranged on the inner wall of the etching hole. The etching hole is filled with conductive polysilicon 4.

[0058] A barrier alloy 5 is disposed above the N-type silicon epitaxy 2;

[0059] The front metal 6 is disposed above the barrier alloy 5 and the etched hole;

[0060] The back metal 7 is disposed below the N+ type silicon substrate 1 .

[0061] Based on the above embodiments, the present application can be further improved as follows:

[0062] Furthermore, the shallow groove area has a depth of 0.5-0.7 μm, and the deep hole area has a depth of 1.5-4 μm, so as to transfer the maximum electric field strength from the Schottky metal contact surface to the bottom of the deep hole edge, thereby achieving the effect of improving the withstand voltage.

[0063] Furthermore, the thickness of the silicon oxide 3 in the etched hole is 100-400 nm.

[0064] Furthermore, the filling medium inside the etched hole is polysilicon 4, which is then expanded with phosphorus to make the polysilicon 4 conductive. The doping material here can be changed to other pentavalent ions such as As to provide higher conductivity; or metals such as Al and Cu can be filled while filling the polysilicon 4 to make the whole directly conductive.

[0065] Further, the barrier alloy 5 is a Ni / Pt alloy. The Ni / Pt alloy is used to form a Schottky contact, and the metal work function is controlled by controlling the metal content ratio. When the Ni content is increased, the forward conduction voltage drop of the TMBS decreases. At this time, due to the decrease in the barrier height, the leakage current increases; when the Pt content is increased, the barrier height increases, the leakage current decreases, and the on-state voltage drop increases; the use of Ni / Pt alloy is convenient for selecting the appropriate effect according to the chip usage scenario.

[0066] Embodiment 2:

[0067] A method for preparing the TMBS device as described in Example 1 comprises the following steps:

[0068] S1: growing an N-type silicon epitaxial layer 2 on an N+ type silicon substrate 1;

[0069] S2: On the N-type silicon epitaxial layer 2, a plurality of shallow groove area circular hole windows are etched and arranged, the shallow groove areas are all in the epitaxial layer, and deep hole area columns are etched in the shallow groove circular hole windows, and the inner diameter of the deep hole area gradually decreases from top to bottom, such as Figure 2 As shown; in the conventional practice, the bottom of the groove should be rounded, which means that the bottom is a rounded structure to avoid the spike discharge effect formed by the right angle; this step makes the side wall of the groove have an inclined angle to form an oblique side wall structure; compared with the right-angle side wall, the oblique side wall structure can avoid electric field "crowding", the electric field strength will be reduced, and the overall inclination angle is 100~120 degrees;

[0070] S3: On the N-type silicon epitaxial layer 2, annealing is performed in an oxygen atmosphere, and a dense silicon oxide layer 3 is grown by dry oxygen oxidation, such as Figure 3 As shown;

[0071] S4: depositing polysilicon 4 on the silicon oxide 3 layer by LPCVD. The thickness of polysilicon 4 should be higher than the deep groove columnar region and can evenly fill the two-layer circular hole step groove. Figure 4As shown, phosphorus is diffused and doped into the polysilicon 4, and annealing is performed to repair the lattice damage. At the same time, the P ions change from the original interstitial atoms to substitutional atoms, forming covalent bonds to make the polysilicon 4 conductive;

[0072] S5: On the polysilicon 4, the thin silicon oxide generated by phosphorus diffusion and the surface particles are removed to expose the polysilicon 4 layer, and the excess polysilicon 4 is removed by dry etching. Figure 5 As shown;

[0073] S6: On the silicon oxide 3 and the polysilicon 4, silicon oxide 3 is deposited as an oxide layer by LPCVD, and annealed and reflowed, such as Figure 6 As shown; the purpose of depositing the oxide layer again is to prevent the oxide layer thickness in the terminal area from being too thin, resulting in a high edge potential and avoiding a significant increase in the probability of breakdown occurring at the terminal;

[0074] S7: Etch away the silicon oxide 3 to expose the upper surface of the N-type silicon epitaxial 2. At the same time, over-etch the polysilicon 4 to be level with or lower than the upper surface of the N-type silicon epitaxial 2. Figure 7 As shown;

[0075] S8: Sputtering alloy on the surface (i.e., N-type silicon epitaxial 2, silicon oxide 3, polysilicon 4), annealing under high-purity N2 to form Schottky contact, generating barrier alloy 5, wet etching away the alloy on silicon oxide 3 and polysilicon 4, such as Figure 8 As shown;

[0076] S9: evaporating the front metal 6 on the barrier alloy 5, silicon oxide 3, and polysilicon 4 to corrode the terminal to prevent the edge electric field from being too strong and causing avalanche breakdown in advance, thereby improving product reliability as a conductive layer;

[0077] S10: On the lower surface of the N+ type silicon substrate 1, a grinding wheel is used to thin the silicon wafer, heat dissipation is enhanced, acid treatment is performed to release the mechanical stress generated by thinning, and a back metal 7 is sputtered, such as Figure 1 shown.

[0078] Furthermore, in step S2, the shallow groove circular hole windows are arranged in a staggered distribution, and when viewed from a top view, adjacent windows form a diamond structure.

[0079] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A TMBS device, characterized in that: include: N+ type silicon substrate; An N-type silicon epitaxial layer is arranged above the N+ type silicon substrate, a plurality of etched holes are arranged on the upper part of the N-type silicon epitaxial layer, the etched holes are composed of a shallow groove area located at the upper part and a deep hole area located at the lower part, the inner diameter of the deep hole area gradually decreases from top to bottom, the inner diameter of the shallow groove area is larger than the maximum inner diameter of the deep hole area, the depth of the shallow groove area is 0.5-0.7 μm, the depth of the deep hole area is 1.5-4 μm, the side wall of the deep hole area is beveled, the inclination angle is 100-120°, the etched hole is transformed from a right angle to an obtuse angle structure, the inner wall of the etched hole is provided with silicon oxide, and the etched hole is filled with conductive polysilicon; A barrier alloy disposed above the N-type silicon epitaxy; A front metal is disposed above the barrier alloy and the etched hole; The back metal is arranged below the N+ type silicon substrate.

2. The TMBS device according to claim 1, characterized in that: The etching holes are evenly spaced and staggeredly distributed on the N-type silicon epitaxy.

3. The TMBS device according to claim 1, characterized in that: The thickness of the silicon oxide in the etched hole is 100-400 nm.

4. The TMBS device according to claim 1, characterized in that: The polysilicon is phosphorus-diffused polysilicon.

5. The TMBS device according to claim 1, characterized in that: The barrier alloy is a Ni / Pt alloy.

6. A method for preparing a TMBS device according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1: growing the N-type silicon epitaxial layer on the N+ type silicon substrate; S2: etching a plurality of circular hole windows of the shallow groove area arranged and distributed on the N-type silicon epitaxial layer, etching the deep hole area in the circular hole windows, wherein the inner diameter of the deep hole area gradually decreases from top to bottom; S3: annealing and growing a silicon oxide layer on the N-type silicon epitaxy; S4: depositing polysilicon on the silicon oxide layer by LPCVD, diffusing phosphorus into the polysilicon, and performing annealing; S5: removing the excess polysilicon; S6: depositing silicon oxide as an oxide layer on the silicon oxide and polysilicon; S7: etching away the silicon oxide to expose the N-type silicon epitaxial layer, and at the same time, over-etching the polysilicon to be flush with the upper surface of the N-type silicon epitaxial layer; S8: sputtering alloy on the N-type silicon epitaxy to form a Schottky contact and generate a barrier alloy; S9: evaporating a front metal on the barrier alloy, silicon oxide, and polysilicon; S10: Sputtering back metal on the lower surface of the N+ type silicon substrate.

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