Epitaxial wafer, method of manufacturing the same, and display device

Abstract

An epitaxial wafer, its fabrication method, and a display device are disclosed. The epitaxial wafer comprises: an N-type doped layer, a functional well structure, and a P-type doped structure stacked together. The functional well structure is located between the N-type doped layer and the P-type doped structure. The functional well structure includes a luminescent substructure and a transition substructure, with the transition substructure located between the luminescent substructure and the N-type doped layer. In the luminescent substructure, the functional well structure is a multi-quantum well structure. The barrier layer in the multi-quantum well structure has a weaker blocking effect on holes, which can increase the migration distance of holes, thereby increasing the number of luminescent quantum wells and improving the luminous efficiency of the epitaxial wafer.

Description

Technical Field

[0001] This invention relates to the field of epitaxial structure design, and particularly to an epitaxial wafer, its preparation method, and a display device. Background Technology

[0002] A quantum well LED (MQW LED) is a special type of light-emitting diode. In the epitaxial wafer of a quantum well LED, the light-emitting layer includes a quantum well structure, resulting in a higher radiative recombination rate of electrons and holes and thus higher luminous efficiency.

[0003] Quantum well light-emitting diode epitaxial wafers have advantages such as high luminous efficiency, tunable emission wavelength, and low operating voltage. Therefore, quantum well structures are increasingly being used in display technology to improve the performance of display devices.

[0004] However, the luminous efficiency of existing quantum well LED epitaxial wafers needs to be further improved. Summary of the Invention

[0005] The problem addressed by this invention is how to further improve the luminous efficiency of quantum well light-emitting diode epitaxial wafers.

[0006] To address the aforementioned problems, the present invention provides an epitaxial wafer comprising: an N-type doped layer, a functional well structure, and a P-type doped structure stacked together; the functional well structure being located between the N-type doped layer and the P-type doped structure, and the functional well structure comprising: a luminescent substructure and a transition substructure, the transition substructure being located between the luminescent substructure and the N-type doped layer.

[0007] Accordingly, the present invention also provides an epitaxial wafer, comprising: an N-type doped layer, a functional well structure, and a P-type doped structure stacked sequentially; the functional well structure includes a light-emitting substructure, the light-emitting substructure includes a redundant barrier layer; the redundant barrier layer is located between the N-type doped layer and the P-type doped structure.

[0008] The present invention also provides a display device, characterized in that it includes: an epitaxial wafer, wherein the epitaxial wafer is the epitaxial wafer of the present invention.

[0009] Accordingly, the present invention also provides a method for preparing an epitaxial wafer, comprising: forming an N-type doped layer on a substrate; forming a functional well structure on the N-type doped layer, wherein the step of forming the functional well structure comprises: sequentially forming a transition substructure and a light-emitting substructure on the N-type doped layer; and forming a P-type doped structure on the light-emitting substructure.

[0010] Furthermore, the present invention also provides a method for preparing an epitaxial wafer, comprising: forming an N-type doped layer on a substrate; forming a functional well structure on the N-type doped layer, wherein the step of forming the functional well structure on the N-type doped layer comprises: sequentially forming a redundant barrier layer on the N-type doped layer; and forming a P-type doped structure on the redundant barrier layer.

[0011] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0012] In this invention, the functional well structure located between the N-type doped layer and the P-type doped structure includes a luminescent substructure and a transition substructure, wherein the transition substructure is located between the luminescent substructure and the N-type doped layer. The luminescent substructure is a multi-quantum well structure. The barrier layer in the multi-quantum well structure has a weaker blocking effect on holes, which can increase the migration distance of holes, thereby increasing the number of luminescent quantum wells and improving the luminescence efficiency of the epitaxial wafer.

[0013] In an optional embodiment of the present invention, the light-emitting substructure further includes a redundant barrier layer located between the multi-period light-emitting layer and the P-type doped structure. The redundant barrier layer blocks electrons, preventing a high electron concentration in the multi-quantum-well structure. Electrons in the multi-quantum-well structure migrate to the P-type doped structure and undergo non-radiative recombination with holes in the P-type doped structure, affecting the luminous efficiency of the epitaxial wafer. The transition substructure, located between the light-emitting substructure and the N-type doped layer, effectively controls the electron concentration of the light-emitting layer without the need for an N-type current diffusion layer between the N-type doped layer and the light-emitting substructure. This improves the electron-hole balance in the light-emitting layer, effectively increasing the luminous efficiency of the epitaxial wafer. Furthermore, controlling the electron concentration in the light-emitting layer through the transition substructure eliminates the need for an electron blocking layer between the P-type doped layer and the light-emitting substructure, effectively increasing the hole migration distance and further improving the luminous efficiency of the light-emitting diode.

[0014] In an optional embodiment of the present invention, the P-type doped structure includes a P-type layer and a multi-period doped layer, wherein the multi-period doped layer is located between the P-type layer and the functional well structure; the multi-period doped layer includes multiple doped stacks, wherein the doped stacks include ternary doped layers and binary doped layers, wherein the ternary doped layer is located between the binary doped layer in the same doped stack and the functional well structure. The multi-period doped layer can increase the effective hole concentration, improve hole injection efficiency, and enhance the electron-hole balance in the photonic structure; furthermore, it can lower the annealing temperature of subsequent annealing processes, effectively reducing the impact of the annealing process on the potential well in the functional well structure. Attached Figure Description

[0015] Figure 1 A schematic diagram of a cross-sectional structure of an epitaxial wafer is shown;

[0016] Figure 2 The diagram shows cross-sectional structural schematics of some embodiments of the epitaxial wafer of the present invention;

[0017] Figure 3 This diagram shows a cross-sectional view of the photonic structure in some embodiments of the epitaxial wafer of the present invention.

[0018] Figure 4 This diagram shows a cross-sectional view of the transition substructure in some embodiments of the epitaxial wafer of the present invention.

[0019] Figure 5 This diagram shows a cross-sectional view of the P-type doped structure in some embodiments of the epitaxial wafer of the present invention.

[0020] Figure 6 A cross-sectional schematic diagram of the stress adjustment structure in some embodiments of the epitaxial wafer of the present invention is shown;

[0021] Figure 7 The following are schematic flowcharts illustrating some embodiments of the epitaxial wafer preparation method of the present invention;

[0022] Figure 8 It shows Figure 7 The diagram shows a detailed flowchart of the steps for forming a functional well structure in some embodiments of the epitaxial wafer fabrication method.

[0023] Figure 9 The diagram shows a flowchart of some embodiments of the epitaxial wafer preparation method of the present invention. Detailed Implementation

[0024] As can be seen from the background technology, existing epitaxial wafers have the problem that their luminous efficiency needs to be further improved.

[0025] The hole concentration in an MQW LED plays a decisive role in the brightness of the LED epitaxial wafer. In III-V group (e.g., gallium nitride, GaN) substrates, the hole mobility (approximately 10 cm⁻¹) is... 2 / Vs) is much lower than the electron mobility (approximately 300 cm⁻¹). 2 / Vs), which can easily lead to the following problems:

[0026] (1) In a multiple quantum well (MQW) structure, the concentration of electrons is much higher than that of holes. Some electrons even leak into the P-type semiconductor and recombine with the holes provided by the P-type semiconductor, which leads to a decrease in hole injection efficiency.

[0027] (2) MQW LEDs generally have 7 to 10 quantum wells, of which 3 to 5 quantum wells close to the P-type semiconductor have higher luminous brightness, while 5 to 7 quantum wells close to the N-type semiconductor have lower luminous brightness; the uneven distribution of holes and electrons restricts the further improvement of the luminous brightness of the LED epitaxial wafer.

[0028] (3) GaN materials with P-type dopants (such as Mg) in MQW LEDs are difficult to obtain high hole concentrations, resulting in hole concentrations in MQWs being much lower than electron concentrations, which restricts the improvement of the luminous brightness of the epitaxial wafer of the light-emitting diode.

[0029] refer to Figure 1 The diagram shows a cross-sectional structure of an epitaxial wafer.

[0030] The epitaxial wafer includes an N-type semiconductor 41, a quantum well light-emitting layer 90, and a P-type semiconductor 75 sequentially stacked on a substrate 1.

[0031] In order to diffuse the current, in the P-type semiconductor 75, a P-type current spreading layer 752 is provided on the side of the P-type functional layer 751 that provides holes away from the quantum well light-emitting layer 90; in the N-type semiconductor 41, an N-type current spreading layer 412 is provided on the side of the N-type layer 411 that provides electrons away from the quantum well light-emitting layer 90.

[0032] In addition, to prevent electrons from leaking into the P-type semiconductor 75, a current blocking layer 80 is provided between the P-type semiconductor 75 and the quantum well light-emitting layer 90.

[0033] The current blocking layer 80, while suppressing electron leakage into the P-type semiconductor 75, also suppresses hole injection from the P-type semiconductor 75 into the quantum well light-emitting layer 90, resulting in reduced hole injection efficiency and uneven distribution of holes and electrons in the quantum well light-emitting layer 90.

[0034] To address the aforementioned technical problem, the present invention provides an epitaxial wafer comprising: an N-type doped layer, a functional well structure, and a P-type doped structure stacked together; the functional well structure being located between the N-type doped layer and the P-type doped structure, and the functional well structure comprising: a luminescent substructure and a transition substructure, the transition substructure being located between the luminescent substructure and the N-type doped layer.

[0035] In this invention, the light-emitting substructure comprises a multi-period light-emitting layer that is a multi-quantum-well structure. The barrier layer of the multi-quantum-well structure has a weaker blocking effect on holes, increasing the migration distance of holes and thus increasing the number of light-emitting quantum wells, thereby improving the luminous efficiency of the epitaxial wafer. The transition substructure is located between the light-emitting substructure and the N-type doped layer. This eliminates the need for an N-type current diffusion layer between the N-type doped layer and the light-emitting substructure, effectively controlling the electron concentration in the light-emitting substructure. This improves the electron-hole balance in the light-emitting substructure, thereby effectively improving the luminous efficiency of the epitaxial wafer. Furthermore, controlling the electron concentration in the light-emitting layer through the transition substructure eliminates the need for an electron blocking layer between the P-type doped layer and the light-emitting substructure, effectively increasing the migration distance of holes and thus further improving the luminous efficiency of the epitaxial wafer.

[0036] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] refer to Figure 2 and Figure 3 ,in Figure 2 The diagram shows cross-sectional structural schematics of some embodiments of the epitaxial wafer of the present invention. Figure 3 A cross-sectional schematic diagram of the photonic structure in some embodiments of the epitaxial wafer of the present invention is shown.

[0038] like Figure 2 As shown, the epitaxial wafer includes: an N-type doped layer 40, a functional well structure 60, and a P-type doped structure 70 stacked together; the functional well structure 60 is located between the N-type doped layer 40 and the P-type doped structure 70, and the functional well structure 60 includes: a light-emitting substructure 62 and a transition substructure 61, the transition substructure 61 being located between the light-emitting substructure 62 and the N-type doped layer 40. The following detailed description of the cross-sectional structural schematic diagram of an embodiment of the epitaxial wafer of the present invention is provided in conjunction with the accompanying drawings.

[0039] The N-type doped layer 40 is used to provide electrons; the P-type doped structure 70 is used to provide holes.

[0040] The different charge carriers provided by the N-type doped layer 40 and the P-type doped structure 70 undergo radiative recombination in the luminescent substructure 62 to achieve luminescence.

[0041] Different charge carriers undergo radiative recombination in the luminescent substructure 62 within the functional well structure 60. The transition substructure 61 is located between the luminescent substructure 62 and the N-type doped layer 40. This eliminates the need for an N-type current diffusion layer between the N-type doped layer 40 and the luminescent substructure 62, effectively controlling the electron concentration in the luminescent substructure 62 and improving the electron-hole balance within it. Furthermore, controlling the electron concentration in the luminescent substructure 62 through the transition substructure 61 eliminates the need for an electron blocking layer between the P-type doped structure 70 and the luminescent substructure 62, effectively increasing the hole migration distance and thus significantly improving the luminous efficiency of the epitaxial wafer.

[0042] refer to Figure 3 As with the aforementioned embodiments, the present invention will not repeat the details here. The difference from the aforementioned embodiments is that, in some embodiments of the present invention, the light-emitting substructure 62 includes a multi-period light-emitting layer 621, which is located between the transition substructure 61 and the p-type doped structure 70.

[0043] In some embodiments of the present invention, the light-emitting substructure 62 further includes a redundant barrier layer 622, which is located between the multi-period light-emitting layer 621 and the P-type doped structure 70.

[0044] In the luminescent structure 62, the radiative recombination of different charge carriers specifically occurs in the multi-period luminescent layer 621. The redundant barrier layer 622 located between the multi-period luminescent layer 621 and the P-type doped structure 70 has a weak blocking effect on holes, which can increase the migration distance of holes, thereby effectively improving the luminescence efficiency of the epitaxial wafer.

[0045] In some embodiments, the light-emitting substructure 62 includes a multi-period light-emitting layer 621 and a redundant barrier layer 622 located between the multi-period light-emitting layer 621 and the p-type doped structure 70. The multi-period light-emitting layer 621 and the redundant barrier layer 622 cooperate to form a multi-quantum-well structure.

[0046] In some embodiments of the present invention, the multi-period light-emitting layer 621 is a multi-quantum-well structure; the multi-period light-emitting layer 621 includes: a plurality of light-emitting stacks, each light-emitting stack including: a first barrier layer 62b and a first well layer 62a, wherein the first barrier layer 62b is located between the first well layer 62a and the N-type doped layer in the same light-emitting stack. The first barrier layer 62b is close to the N-type doped layer, and the first well layer 62a is close to the P-type doped layer.

[0047] The multi-period light-emitting layer 621 has a multi-quantum-well structure. The first barrier layer 62b has a weak blocking effect on holes, which can increase the migration distance of holes, thereby increasing the number of light-emitting quantum wells and improving the light-emitting efficiency of the epitaxial wafer.

[0048] like Figure 3 As shown, the multi-period light-emitting layer 621 includes a first light-emitting stack 6211, a second light-emitting stack 6212, a third light-emitting stack 6213, ... and an N1th light-emitting stack 621N1, which are sequentially stacked along the direction from the N-type doped layer 40 to the P-type doped structure 70.

[0049] In some embodiments, the multi-period light-emitting layer 621 has 5 to 10 of the light-emitting stacks. For example... Figure 3 In some of the embodiments shown, N1 ranges from 5 to 10.

[0050] It should be noted that in some embodiments, a transition substructure 61 is provided on the side of the first light-emitting stack 6211 away from the p-type doped layer 70; the first light-emitting stack 6211 is disposed between the transition substructure 61 and the second light-emitting stack 6212.

[0051] In addition, in some embodiments, the redundant barrier layer 622 is disposed on the side of the N1 luminescent stack 621N1 away from the N-type doped layer 40, and the N1 luminescent stack 621N1 is located between the redundant barrier layer 622 and the N1-1 luminescent stack 621N1-1.

[0052] In some embodiments, the functional well structure 60 is a group III-V multiple quantum well structure. Figure 3 In some of the embodiments shown, the epitaxial wafer is used in a display device; the functional well structure 60 is a group III-V multiple quantum well structure.

[0053] In other embodiments of the present invention, the functional well structure may also be a group II-VI multiple quantum well structure.

[0054] In some embodiments, the first well layer 62a is In w Ga 1-w The first barrier layer 62b is an N-type doped GaN layer, where 0.1 ≤ w ≤ 0.4. For example, the first barrier layer 62b contains an N-type dopant, such as Si or Ge.

[0055] In some embodiments, the thickness of the first well layer 62a ranges from 2.0 nm to 4.0 nm, and the thickness of the first barrier layer 62b ranges from 9.0 nm to 14.0 nm.

[0056] In some embodiments of the example, in the multi-period light-emitting layer 621, the thickness of the first barrier layer 62b of different light-emitting stacks is equal, and the thickness of the first well layer 62a of different light-emitting stacks is equal.

[0057] Continue to refer to Figure 3 The redundant barrier layer 622 can block electrons from entering the P-type doped structure, preventing nonradiative recombination of electrons and holes in the P-type doped structure from affecting the luminous efficiency of the epitaxial wafer, thereby increasing the hole concentration in the luminescent substructure 62 and increasing the radiative recombination rate in the luminescent substructure 62.

[0058] The redundant barrier layer 622 is located on the side of the N1 luminescent stack away from the N-type doped layer. As a barrier layer, the redundant barrier layer 622, together with the first well layer 62a and the first barrier layer 62b in the N1 luminescent stack, constitutes the quantum well closest to the P-type doped structure in the luminescent substructure 62. The redundant barrier layer 622 has a weak blocking effect on holes, which can increase the migration distance of holes, thereby increasing the number of luminescent quantum wells and improving the luminescence efficiency of the epitaxial wafer.

[0059] In some embodiments, the redundant barrier layer 622 is an intrinsic layer. The redundant barrier layer 622 is undoped. The redundant barrier layer 622 does not contain any doped atoms. The redundant barrier layer 622 also prevents the diffusion of P-type dopants from the P-type doped structure into the photonic structure 62, effectively improving the stability and performance of the photonic structure 62.

[0060] In some embodiments, the functional well structure 60 is a III-V group multiple quantum well structure; the redundant barrier layer 622 is a III-V group intrinsic layer. Figure 3 In some of the embodiments shown, the functional well structure 60 is a group III-V multiple quantum well structure, and the redundant barrier layer 622 is a group III-V intrinsic layer.

[0061] For example, the first barrier layer 62b is an N-type doped GaN layer, and the redundant barrier layer 622 is an intrinsic GaN layer. The redundant barrier layer 622 is an undoped GaN layer. The material of the redundant barrier layer 622 is undoped GaN.

[0062] In other embodiments of the present invention, the functional well structure may also be a group II-VI multiple quantum well structure; the redundant barrier layer is a group II-VI intrinsic layer. The redundant barrier layer is an intrinsic layer of the material of the first barrier layer. The material of the redundant barrier layer is the same as the material of the undoped first barrier layer.

[0063] In some embodiments, the redundant barrier layer 622 serves as a barrier layer; the thickness of the redundant barrier layer 622 is equal to the thickness of the first barrier layer 62b. For example, the thickness of the redundant barrier layer 622 ranges from 9.0 nm to 14.0 nm.

[0064] refer to Figure 4 The diagram shows a cross-sectional view of the transition substructure in some embodiments of the epitaxial wafer of the present invention.

[0065] For the same parts as the foregoing embodiments, the present invention will not be elaborated herein. The differences from the foregoing embodiments are that, in some embodiments, the transition sub-structure 61 includes: a plurality of transition stacks, and each transition stack includes: a second barrier layer 61b and a second well layer 61a, and the second barrier layer 61b is located between the second well layer 61a of the same transition stack and the N-type doped layer 40. The second barrier layer 61b is close to the N-type doped layer, and the second well layer 61a is close to the P-type doped layer.

[0066] The transition sub-structure 61 is also a multi-quantum well structure. The transition sub-structure 61 including a plurality of such transition stacks can effectively control the electron concentration in the light-emitting sub-structure 62 and improve the balance between electrons and holes in the multi-period light-emitting layer.

[0067] As Figure 4 shown, the transition sub-structure 61 includes: a first transition stack 611, a second transition stack 612, a third transition stack 613,..., and an N2th transition stack 61N2, which are sequentially stacked along the direction from the N-type doped layer to the P-type doped structure.

[0068] In some embodiments, the transition sub-structure 61 has 3 to 5 such transition stacks. As Figure 4 shown in some embodiments, the range of N2 is 3 to 5.

[0069] It should be noted that, in some embodiments, a stress adjustment structure 50 is provided on the side of the first transition stack 611 away from the P-type doped layer; the first transition stack 611 is disposed between the stress adjustment structure 50 and the second transition stack 612.

[0070] In addition, a light-emitting sub-structure 62 is provided on the side of the N2th transition stack 61N2 away from the N-type doped layer, and the N2th transition stack 61N2 is located between the light-emitting sub-structure 62 and the N2-1th transition stack 61N2-1.

[0071] In some embodiments, the functional well structure is a III-V multi-quantum well structure, and the second well layer 61a is an In x Ga 1-x N layer, where 0 < x ≤ 0.3; the second barrier layer 61b is an N-type doped Al y Ga 1-y N layer, where 0 ≤ y ≤ 0.2. For example, the second barrier layer 61b has an N-type dopant, such as Si or Ge.

[0072] In some embodiments, the second barrier layer 61b is an N-type doped Al y Ga 1-yThe N layer has 0 < y ≤ 0.2; wherein, the proportion of the Al component in the second barrier layer 61b on the side far from the N-type doped layer 40 is greater than the proportion of the Al component in the second barrier layer 61b on the side close to the N-type doped layer 40.

[0073] Al has a relatively large bandgap. Al y Ga 1-y The higher the proportion of the Al component in the N layer, Al y Ga 1-y The larger the bandgap of the N layer, the lower the probability of electrons jumping to the conduction band, the better the effect of blocking electron diffusion, and the smaller the electron diffusion speed; the closer to the light-emitting substructure 62, the higher the proportion of the Al component, which can better reduce the electron concentration and speed entering the light-emitting substructure 62, enabling more electrons to undergo radiative recombination with holes in the light-emitting substructure 62 and reducing electron loss.

[0074] Exemplarily, along the direction away from the N-type doped layer 40, the proportion of the Al component in the second barrier layer 61b increases layer by layer. Within the transition substructure 61, in two adjacent transition stacks, the proportion of the Al component in the second barrier layer 61b in the transition stack on the side far from the N-type doped layer 40 is greater than the proportion of the Al component in the second barrier layer 61b in the transition stack on the side close to the N-type doped layer 40; however, the proportion of the Al component in the same second barrier layer 61b is uniform.

[0075] Such as Figure 4 As shown, in the transition substructure 61, the proportion of the Al component in the second barrier layer 61b in the second transition stack 612 is greater than the proportion of the Al component in the second barrier layer 61b in the first transition stack 611; the proportion of the Al component in the second barrier layer 61b in the third transition stack 613 is greater than the proportion of the Al component in the second barrier layer 61b in the second transition stack 611;...; the proportion of the Al component in the second barrier layer 61b in the N2th transition stack 61N2 is greater than the proportion of the Al component in the second barrier layer 61b in the (N2 - 1)th transition stack 61N2 - 1; however, the proportion of the Al component in the second barrier layer 61b in the first transition stack 611, the second barrier layer 61b in the second transition stack 612, the second barrier layer 61b in the third transition stack 613,..., and the second barrier layer 61b in the N2th transition stack 61N2 are each uniform.

[0076] In other embodiments, the proportion of Al component in the second barrier layer gradually increases along the direction away from the N-type doped layer. In the transition substructure, not only is the proportion of Al component in the second barrier layer of the transition stack away from the N-type doped layer greater than that of the transition stack closer to the N-type doped layer in two adjacent transition stacks, but the proportion of Al component within the same second barrier layer is also uneven: the proportion of Al component away from the N-type doped layer is also greater than that closer to the N-type doped layer in the same second barrier layer.

[0077] In some embodiments, the thickness of the second well layer 61a ranges from 2.0 nm to 4.0 nm, and the thickness of the second barrier layer 61b ranges from 7.0 nm to 12.0 nm.

[0078] For example, in some embodiments, the thickness of the second barrier layer 61b of different transition stacks in the transition substructure 61 is equal, and the thickness of the second well layer 61a of different transition stacks is equal.

[0079] refer to Figure 5 The diagram shows a cross-sectional view of the P-type doped structure in some embodiments of the epitaxial wafer of the present invention.

[0080] As with the foregoing embodiments, the present invention will not be repeated here. The difference from the foregoing embodiments is that, in some embodiments, the P-type doped structure 70 includes a P-type layer 71 and a multi-period doped layer 72, the multi-period doped layer 72 being located between the P-type layer 71 and the functional well structure 60.

[0081] The P-type doped structure 70 has a multi-period doped layer 72, which can increase the effective hole concentration in the P-type doped structure 70, thereby increasing the hole concentration in the light-emitting structure 62 and the balance of electrons and holes in the light-emitting structure 62, and improving the brightness of the epitaxial wafer.

[0082] Moreover, the setting of the multi-period doped layer 72 can reduce the annealing temperature of the subsequent annealing process, effectively control the influence of the annealing process on the potential well in the functional well structure, and reduce the damage of the high temperature during the annealing process to the potential well in the first well layer 62a and the first barrier layer 62b of the multi-period light-emitting layer 621 in the light-emitting structure 62.

[0083] In some embodiments, the multi-period doped layer 72 is also a multi-quantum well structure; the multi-period doped layer 72 includes multiple doped stacks, the doped stacks including: a ternary doped layer 72a and a binary doped layer 72b, the ternary doped layer 72a being located between the binary doped layer 72b and the functional well structure 60 in the same doped stack.

[0084] like Figure 5In some embodiments shown, the multi-period doped layer 72 includes a first doped stack 721, a second doped stack 722, a third doped stack 723, ... and an N3 doped stack 72N3, which are sequentially stacked along the direction from the N-type doped layer to the P-type doped structure.

[0085] In some embodiments, the multi-period doped layer 72 has at least five doped stacks. For example... Figure 5 In some of the embodiments shown, N3 is greater than or equal to 5.

[0086] It should be noted that in some embodiments, the first doped stack 721 has a light-emitting substructure 62 on the side facing the N-type doped layer 40; the first doped stack 721 is located between the light-emitting substructure 62 and the second doped stack 722.

[0087] In addition, in some embodiments, a P-type layer 71 is disposed on the side of the N3rd doped stack 72N3 away from the N-type doped layer 40, and the N3rd doped stack 72N3 is located between the P-type layer 71 and the N3-1st doped stack 72N3-1.

[0088] In some embodiments, the concentration range of the P-type dopant in the P-type doped structure 70 is 3 × 10⁻⁶. 18 atoms / cm 3 Up to 5×10 20 atoms / cm 3 The concentration range of the P-type dopant in both the P-type layer 71 and the multi-period doped layer 72 is 3 × 10⁻⁶. 18 atoms / cm 3 Up to 5×10 20 atoms / cm 3 Setting the concentration range of the P-type dopant in the P-type doped structure 70 within the above-mentioned range can effectively increase the hole concentration. Moreover, within this concentration range, the P-type dopant is less likely to aggregate and affect the hole concentration.

[0089] In some embodiments, the concentration of P-type dopant in the multi-period doped layer 72 on the side away from the N-type doped layer 40 is greater than the concentration of P-type dopant in the multi-period doped layer 72 on the side closer to the N-type doped layer 40.

[0090] The non-uniform distribution of P-type dopant in the multi-period doped layer 72: the farther away from the light-emitting structure 62, the higher the concentration of P-type dopant; the closer to the light-emitting structure 62, the lower the concentration of P-type dopant, which can effectively increase the concentration of holes in the P-type doped structure 70.

[0091] In some exemplary embodiments, the concentration of P-type dopant in the multi-period doped layer 72 increases periodically along the direction away from the N-type doped layer 40. Within the multi-period doped layer 72, in two adjacent doped stacks, the concentration of P-type dopant in the doped stack on the side away from the N-type doped layer is greater than the concentration of P-type dopant in the doped stack on the side closer to the N-type doped layer.

[0092] like Figure 5 As shown, in the multi-period doped layer 72, the concentration of P-type dopant in the second doped layer 722 is greater than the concentration of P-type dopant in the first doped layer 721; the concentration of P-type dopant in the third doped layer 722 is greater than the concentration of P-type dopant in the second doped layer 721; ...; the concentration of P-type dopant in the N3rd doped layer 72N3 is greater than the concentration of P-type dopant in the N3-1th doped layer 72N3-1.

[0093] In some embodiments, the concentration of P-type dopant is uniform within the same doped stack. Specifically, the P-type dopant is uniformly distributed in the ternary doped layer 72a and the binary doped layer 72b of the same doped stack; that is, the concentration of P-type dopant is equal everywhere in the ternary doped layer 72a and the binary doped layer 72b of the same doped stack.

[0094] like Figure 5 As shown, the P-type dopant in the first doped stack 721, the second doped stack 722, the third doped stack 723, ..., and the N3rd doped stack 72N3 is uniformly distributed. The P-type dopant concentration is equal everywhere in the ternary doped layers 72a and 72b of the first doped stack 721, the ternary doped layers 72a and 72b of the second doped stack 722, the ternary doped layers 72a and 72b of the third doped stack 723, ..., and the ternary doped layers 72a and 72b of the N3rd doped stack 72N3.

[0095] In other embodiments, within the same doped stack, the concentration of P-type dopant increases layer by layer along the direction away from the N-type doped layer. Within the same doped stack, the concentration of P-type dopant in the binary doped layer is greater than that in the ternary doped layer; however, the distribution of P-type dopant is uniform within each of the binary and ternary doped layers; the concentration of P-type dopant is equal everywhere in the binary doped layer; and the concentration of P-type dopant is equal everywhere in the ternary doped layer.

[0096] For example, in the binary doped layer of the first doped stack, the concentration of P-type dopant is greater than that in the ternary doped layer of the first doped stack, but the concentration of P-type dopant is equal everywhere in the binary doped layer of the first doped stack, and the concentration of P-type dopant is equal everywhere in the ternary doped layer of the first doped stack; in the binary doped layer of the second doped stack, the concentration of P-type dopant is greater than that in the ternary doped layer of the second doped stack, but the concentration of P-type dopant is equal everywhere in the binary doped layer of the second doped stack, and the concentration of P-type dopant is equal everywhere in the ternary doped layer of the second doped stack; The concentration of P-type dopant in the binary doped layer of the three-doped stack is greater than that in the ternary doped layer of the third-doped stack, but the concentration of P-type dopant in the binary doped layer of the third-doped stack is equal everywhere; ...; the concentration of P-type dopant in the binary doped layer of the N3rd-doped stack is greater than that in the ternary doped layer of the N3rd-doped stack, but the concentration of P-type dopant in the binary doped layer of the N3rd-doped stack is equal everywhere; ...

[0097] In other embodiments, within the same doped stack, the concentration of P-type dopant gradually increases along the direction away from the N-type doped layer. Within the same doped stack, the concentration of P-type dopant in the binary doped layer is greater than that in the ternary doped layer; and the distribution of P-type dopant in both the binary and ternary doped layers is non-uniform: in the binary doped layer, the concentration of P-type dopant gradually increases along the direction away from the N-type doped layer; in the ternary doped layer, the concentration of P-type dopant gradually increases along the direction away from the N-type doped layer.

[0098] For example, in the binary doped layer of the first doped stack, the concentration of P-type dopant is greater than that in the ternary doped layer of the first doped stack, and the concentration of P-type dopant in both the binary and ternary doped layers of the first doped stack gradually increases in the direction away from the N-type doped layer; in the binary doped layer of the second doped stack, the concentration of P-type dopant is greater than that in the ternary doped layer of the second doped stack, and the concentration of P-type dopant in both the binary and ternary doped layers of the second doped stack gradually increases in the direction away from the N-type doped layer; ...; in the binary doped layer of the N3rd doped stack, the concentration of P-type dopant is greater than that in the ternary doped layer of the N3rd doped stack, and the concentration of P-type dopant in both the binary and ternary doped layers of the N3rd doped stack gradually increases in the direction away from the N-type doped layer.

[0099] like Figure 5In some embodiments shown, the multi-period doped layer 72 is a group III-V multiple quantum well structure, the ternary doped layer 72a is a p-type doped InGaN layer, and the binary doped layer 72b is a p-type doped GaN layer. For example, both the InGaN layer and the GaN layer have a p-type dopant, such as at least one of Mg and Zn.

[0100] In some embodiments, the Ga content in the multi-period doped layer 72 on the side away from the N-type doped layer 40 is less than the Ga content in the multi-period doped layer 72 on the side closer to the N-type doped layer 40; the In content in the InGaN layer of the multi-period doped layer 72 on the side away from the N-type doped layer 40 is greater than the In content in the InGaN layer of the multi-period doped layer 72 on the side closer to the N-type doped layer 40.

[0101] The Ga and In content of the multi-period doped layer 72 is not uniformly distributed. The further away from the light-emitting structure 62, the higher the In content and the lower the Ga content; the closer to the light-emitting structure 62, the lower the In content and the higher the Ga content, thereby effectively increasing the hole concentration in the P-type doped structure 70.

[0102] In some exemplary embodiments, along the direction away from the N-type doped layer 40, the Ga content in the multi-period doped layer 72 decreases periodically, while the In content increases periodically. Within the multi-period doped layer 72, in two adjacent doped stacks, the Ga content in the doped stack on the side away from the N-type doped layer is less than the Ga content in the doped stack on the side closer to the N-type doped layer, and the In content in the doped stack on the side away from the N-type doped layer is greater than the In content in the doped stack on the side closer to the N-type doped layer.

[0103] like Figure 5 As shown, in the multi-period doped layer 72, the Ga content in the second doped stack 722 is less than the Ga content in the first doped stack 721, and the In content in the second doped stack 722 is greater than the In content in the first doped stack 721; the Ga content in the third doped stack 722 is less than the Ga content in the second doped stack 721, and the In content in the third doped stack 722 is greater than the In content in the second doped stack 721; ...; the Ga content in the N3rd doped stack 72N3 is less than the Ga content in the N3-1st doped stack 72N3-1, and the In content in the N3rd doped stack 72N3 is greater than the In content in the N3-1st doped stack 72N3-1.

[0104] In some embodiments, the Ga component content is uniform within the same doped stack, and the In component content is uniform within the InGaN layer. Specifically, the Ga component content is uniform in both the InGaN and GaN layers of the same doped stack; the In component content is uniform within the InGaN layer of the same doped stack. That is, the Ga component is uniformly distributed in both the InGaN and GaN layers of the same doped stack; and the In component is uniformly distributed within the InGaN layer of the same doped stack.

[0105] like Figure 5 As shown, the Ga composition is uniformly distributed in the InGaN and GaN layers of the first doped stack 721, the InGaN and GaN layers of the second doped stack 722, the InGaN and GaN layers of the third doped stack 723, ..., and the InGaN and GaN layers of the N3rd doped stack 72N3. The In composition is also uniformly distributed in the InGaN layers of the first doped stack 721, the second doped stack 722, the third doped stack 723, ..., and the InGaN layer of the N2nd doped stack 72N2.

[0106] In other embodiments, within the same doped stack, the Ga content decreases layer by layer along the direction away from the N-type doped layer. Specifically, within the same doped stack, the Ga content in the GaN layer is less than the Ga content in the InGaN layer; however, the Ga content in both the GaN and InGaN layers is uniform; that is, the Ga content in both the GaN and InGaN layers is uniformly distributed.

[0107] For example, in the first doped stack, the Ga content in the GaN layer is less than the Ga content in the InGaN layer; in the second doped stack, the Ga content in the GaN layer is less than the Ga content in the InGaN layer; in the third doped stack, the Ga content in the GaN layer is less than the Ga content in the InGaN layer; ...; in the N2nd doped stack, the Ga content in the GaN layer is less than the Ga content in the InGaN layer; however, the Ga content is uniform in both the GaN and InGaN layers of the first doped stack, the GaN and InGaN layers of the second doped stack, the GaN and InGaN layers of the third doped stack, ..., and the GaN and InGaN layers of the N2nd doped stack; that is, the Ga content is uniform in both the GaN and InGaN layers of the first doped stack, the GaN and InGaN layers of the second doped stack, the GaN and InGaN layers of the third doped stack, ..., and the GaN and InGaN layers of the N2nd doped stack.

[0108] In other embodiments, within the same doped stack, the Ga content gradually decreases along the direction away from the N-type doped layer, while the In content gradually increases in the InGaN layer. Specifically, in the InGaN and GaN layers of the same doped stack, the Ga content in the GaN layer is less than that in the InGaN layer; moreover, the Ga content in both the GaN and InGaN layers gradually decreases: along the direction away from the N-type doped layer, the Ga content in both the GaN and InGaN layers gradually decreases. Furthermore, the In content in the InGaN layer gradually increases. Additionally, within the InGaN layer of the same doped stack, the In content is not uniform along the direction away from the N-type doped layer, and the In content gradually increases.

[0109] For example, in the first doped stack, the Ga content in the GaN layer is less than the Ga content in the InGaN layer; in the second doped stack, the Ga content in the GaN layer is less than the Ga content in the InGaN layer; in the third doped stack, the Ga content in the GaN layer is less than the Ga content in the InGaN layer; ...; in the N2nd doped stack, the Ga content in the GaN layer is less than the Ga content in the InGaN layer; the Ga content in the GaN and InGaN layers of the first doped stack, the GaN and InGaN layers of the second doped stack, the GaN and InGaN layers of the third doped stack, ..., the GaN and InGaN layers of the N2nd doped stack are not uniform: the Ga content gradually decreases in the direction away from the N-type doped layer. Furthermore, the In content in the second doped InGaN layer is greater than that in the first doped InGaN layer; the In content in the third doped InGaN layer is greater than that in the first doped InGaN layer; ...; the In content in the N2nd doped InGaN layer is greater than that in the N2-1th doped InGaN layer; moreover, the In content in the first doped InGaN layer, the second doped InGaN layer, the third doped InGaN layer, ..., the N2nd doped InGaN layer is not uniform: the In content gradually increases in the direction away from the N-type doped layer.

[0110] In some embodiments, the thickness of the doped stack ranges from 5 nm to 10 nm.

[0111] In some embodiments of the example, the thickness of different doped layers in the multi-period doped layer 72 is equal. Furthermore, the thickness of the ternary doped layer 72a in the multi-period doped layer 72 is equal, and the thickness of the binary doped layer 72b in the multi-period doped layer 72 is equal.

[0112] Continue to refer to Figure 5 The P-type layer 71 serves as the P-electrode of the epitaxial wafer to achieve electrical connection.

[0113] In some embodiments of the present invention, the functional well structure is a III-V group multiple quantum well structure, and the P-type layer 71 is an InGaN layer doped with a P-type dopant.

[0114] The InGaN material of the P-type layer 71 has a narrow band gap and good conductivity. After doping with P-type dopant, the InGaN layer doped with P-type dopant can further improve the conductivity of the InGaN layer, and also increase the hole concentration in the P-type doped structure 70, thereby increasing the hole concentration that radiatively recombines with electrons in the luminescent structure 62 and improving the luminous brightness of the epitaxial wafer.

[0115] Reference Figure 2 In some embodiments of the present invention, the N-type doped layer 40 of the epitaxial wafer is a single-layer structure or a multi-layer composite structure. For example, the functional well structure is a III-V group multiple quantum well structure, and the N-type doped layer 40 includes at least one of a GaN layer, an AlGaN layer, and an AlInGaN layer.

[0116] The N-type doped layer 40 contains an N-type dopant; in some embodiments, the concentration of the N-type dopant in the N-type doped layer 40 is in the range of 8 × 10⁻⁶. 18 atoms / cm 3 Up to 1×10 21 atoms / cm 3 .

[0117] In some embodiments, the thickness of the N-type doped layer 40 ranges from 2.0 μm to 4.0 μm.

[0118] refer to Figure 6 The diagram shows a cross-sectional view of the stress adjustment structure in some embodiments of the epitaxial wafer of the present invention.

[0119] As with the foregoing embodiments, the present invention will not be repeated here. The difference from the foregoing embodiments is that, in some embodiments, the functional well structure 60 further includes a stress-adjusting structure 50, which is located between the N-type doped layer 40 and the transition substructure 61.

[0120] The stress-adjusting layer 50 can shield the nonradiative recombination caused by extended dislocations on the side of the stress-adjusting layer 50 away from the P-type doped layer 70.

[0121] In some embodiments of the present invention, the stress-adjusting structure 50 is a multi-quantum-well structure; the stress-adjusting structure 50 includes: a plurality of stress-adjusting stacks, the stress-adjusting stacks including a third well layer 501 and a third barrier layer 502, the third barrier layer 502 being located between the third well layer 501 and the N-type doped layer 40 in the same stress-adjusting stack. The third barrier layer 502 is close to the N-type doped layer 40, and the third well layer 501 is close to the P-type doped structure 70.

[0122] During electron injection, the stress-regulating structure of the functional trap structure can also slow down the lateral (direction perpendicular to the electron injection direction) diffusion of electrons, which can avoid electron loss caused by premature lateral diffusion of electrons. This can increase the concentration of electrons that enter the photonic structure and undergo radiative recombination with holes, thereby improving the utilization rate of electrons.

[0123] like Figure 6 As shown, the stress adjustment structure 50 includes a first stress adjustment stack 51, a second stress adjustment stack 52, a third stress adjustment stack 53, ... and an N4th stress adjustment stack 5N4, which are sequentially stacked along the direction from the N-type doped layer to the P-type doped structure.

[0124] In some embodiments of the present invention, the stress-adjusting structure 50 has at least nine stress-adjusting stacks. For example... Figure 6 In some of the embodiments shown, N4 is greater than or equal to 9.

[0125] It should be noted that in some embodiments, an N-type doped layer 40 is disposed on the side of the first stress-adjusting stack 51 away from the P-type doped layer 70; the first stress-adjusting stack 51 is disposed between the N-type doped layer 40 and the second stress-adjusting stack 52.

[0126] In addition, in some embodiments, a transition substructure 61 is provided on the side of the N4th stress-adjusting stack 5N4 away from the N-type doped layer 40, and the N4th stress-adjusting stack 5N4 is located between the transition substructure 61 and the N4-1st stress-adjusting stack 5N4-1.

[0127] In some embodiments of the present invention, the functional well structure is a III-V multi-quantum well structure, and the third well layer 501 is In z Ga 1-z N layer, where 0 < z ≤ 0.1, and the third barrier layer 502 is a GaN layer.

[0128] In some embodiments of the present invention, the thickness range of the third well layer 501 is 1.0 nm to 2.5 nm, and the thickness range of the third barrier layer 502 is 2.0 nm to 4.0 nm.

[0129] In some embodiments of the example, in the stress adjustment structure 50, the thicknesses of the third well layers 501 of different stress adjustment stacks are equal, and the thicknesses of the third barrier layers 502 of different stress adjustment stacks are equal.

[0130] Continuing to refer to Figure 2 , in some embodiments of the present invention, the epitaxial wafer further includes: an undoped layer 30, a buffer layer 20, and a substrate 10; wherein, the substrate 10 is located on a side of the N-type doped layer 40 away from the P-type doping structure 70; the buffer layer 20 is located between the substrate 10 and the N-type doped layer 40. The undoped layer 30 is located between the buffer layer 20 and the N-type doped layer 40.

[0131] The substrate 10 is used to provide mechanical support.

[0132] In some embodiments, the substrate 10 may be a substrate of a single material, or the substrate 10 may also be a composite substrate having multiple materials. For example, the substrate 10 is at least one of a sapphire substrate, a GaN substrate, an AlN substrate, a Si substrate, and a SiC substrate.

[0133] The undoped layer 30 is used for transition to better form the N-type doped layer. The material of the undoped layer 30 corresponds to the material of the N-type doped layer 40.

[0134] In some embodiments, the undoped layer 30 is a single-layer structure or a multi-layer composite structure. For example, the undoped layer 30 is at least one of a GaN layer, an AlGaN layer, and an AlInGaN layer. Specifically, the thickness range of the undoped layer 30 is 2.0 μm to 4.0 μm.

[0135] The buffer layer 20 is used to reduce the dislocation density of subsequent epitaxial functional layers (N-type doped layer 40, functional well structure 60, and P-type doping structure 70) to improve the growth quality of the epitaxial functional layers. The material of the buffer layer 20 corresponds to the material of the N-type doped layer 40.

[0136] In some embodiments, the buffer layer 20 is a single-layer structure or a multi-layer composite structure. For example, the buffer layer 20 is at least one of an AlN layer, a GaN layer, an AlGaN layer, and an AlInGaN layer. Specifically, the thickness of the buffer layer 20 ranges from 15 nm to 50 nm.

[0137] Accordingly, refer to Figure 2 and Figure 3 The present invention also provides an epitaxial wafer, the epitaxial wafer comprising: an N-type doped layer 40, a functional well structure 60 and a P-type doped structure 70 stacked sequentially; the functional well structure 60 includes a light-emitting substructure 62, the light-emitting substructure 62 including a redundant barrier layer 622; the redundant barrier layer 622 is located between the N-type doped layer 40 and the P-type doped structure 70.

[0138] In some embodiments, the N-type doped layer 40, the functional well structure 60, and the P-type doped structure 70 are the same as or similar to those in the aforementioned epitaxial wafer embodiments. Specific technical solutions for the N-type doped layer 40, the functional well structure 60, and the P-type doped structure 70 can be found in the aforementioned epitaxial wafer embodiments.

[0139] The redundant barrier layer 622 blocks electrons, preventing a high electron concentration in the multi-quantum-well structure. Electrons in the multi-quantum-well structure migrate to the P-type doped structure 70 and undergo non-radiative recombination with holes in the P-type doped structure 70, affecting the luminous efficiency of the epitaxial wafer. The transition substructure is located between the light-emitting substructure 62 and the N-type doped layer 40. This eliminates the need for an N-type current diffusion layer between the N-type doped layer 40 and the light-emitting substructure 62, effectively controlling the electron concentration of the light-emitting layer. This improves the electron-hole balance in the light-emitting layer and enhances the luminous efficiency of the epitaxial wafer. Furthermore, controlling the electron concentration in the light-emitting layer through the transition substructure eliminates the need for an electron blocking layer between the P-type doped structure 70 and the light-emitting substructure 62, effectively increasing the hole migration distance and further improving the luminous efficiency of the light-emitting diode.

[0140] In some embodiments, such as Figure 2 and Figure 3 As shown, the light-emitting substructure 62 further includes a multi-period light-emitting layer 621, which is located between the N-type doped layer 40 and the redundant barrier layer 622. The multi-period light-emitting layer 621 is the same as or similar to that in the aforementioned epitaxial wafer embodiment. Specific technical solutions for the multi-period light-emitting layer 621 can be found in the aforementioned epitaxial wafer embodiment.

[0141] In some embodiments, such as Figure 2 and Figure 5As shown, the P-type doped structure 70 includes a P-type layer 71 and a multi-period doped layer 72, wherein the multi-period doped layer 72 is located between the P-type layer 71 and the functional well structure 60. The P-type layer 71 and the multi-period doped layer 72 are the same as or similar to those in the aforementioned epitaxial wafer embodiments. Specific technical solutions for the P-type layer 71 and the multi-period doped layer 72 can be found in the aforementioned epitaxial wafer embodiments.

[0142] In some embodiments, such as Figure 2 and Figure 6 As shown, the functional well structure 60 further includes a stress adjustment structure 50, which is located between the N-type doped layer 40 and the light-emitting structure 60. The stress adjustment structure 50 is the same as or similar to that in the aforementioned epitaxial wafer embodiments. Specific technical solutions for the stress adjustment structure 50 can be found in the aforementioned epitaxial wafer embodiments.

[0143] In some embodiments, such as Figure 2 As shown, the epitaxial wafer further includes: an undoped layer 30, a buffer layer 20, and a substrate 10; the substrate 10 is located on the side of the N-type doped layer 40 away from the P-type doped structure 70; the buffer layer 20 is located between the substrate 10 and the N-type doped layer 40; the undoped layer 30 is located between the buffer layer 20 and the N-type doped layer 40. The undoped layer 30, the buffer layer 20, and the substrate 10 are the same as or similar to those in the aforementioned epitaxial wafer embodiments. Specific technical solutions for the undoped layer 30, the buffer layer 20, and the substrate 10 can be found in the aforementioned epitaxial wafer embodiments.

[0144] In addition, the present invention also provides a display device.

[0145] The display device includes an epitaxial wafer, wherein the epitaxial wafer is the epitaxial wafer of the present invention.

[0146] The epitaxial wafer described herein is the epitaxial wafer of this invention. Specific technical solutions for the epitaxial wafer are described in the aforementioned embodiments, and will not be repeated here.

[0147] In the epitaxial wafer of this invention, the functional well structure located between the N-type doped layer and the P-type doped structure includes a luminescent substructure and a transition substructure, wherein the transition substructure is located between the luminescent substructure and the N-type doped layer. In the luminescent substructure, the multi-period luminescent layer is a multi-quantum well structure. The barrier layers of the quantum wells and the redundant barrier layers have a weak blocking effect on holes, which can increase the migration distance of holes, thereby increasing the number of luminescent quantum wells and improving the luminous efficiency of the epitaxial wafer. The transition substructure, located between the luminescent substructure and the N-type doped layer, effectively controls the electron concentration of the luminescent layer without the need for an N-type current diffusion layer between the N-type doped layer and the luminescent substructure. This improves the electron-hole balance in the luminescent layer and effectively enhances the luminous efficiency of the epitaxial wafer. Furthermore, controlling the electron concentration in the luminescent layer through the transition substructure eliminates the need for an electron blocking layer between the P-type doped layer and the luminescent substructure, effectively increasing the migration distance of holes and further improving the luminous efficiency of the epitaxial wafer.

[0148] The epitaxial wafer of the present invention has higher luminous efficiency and greater luminous brightness, which can effectively improve the display effect of the display device and effectively reduce the energy consumption of the display device.

[0149] In addition, the present invention also provides a method for preparing an epitaxial wafer.

[0150] refer to Figure 7 The diagram shows a flowchart of some embodiments of the epitaxial wafer preparation method of the present invention.

[0151] Reference Figure 1 , showed Figure 7 The diagram shows a cross-sectional structure of the epitaxial wafer formed by some embodiments of the epitaxial wafer preparation method.

[0152] The preparation method includes: performing step S110 to form an N-type doped layer 40 on a substrate; performing step S120 to form a functional well structure 60 on the N-type doped layer 40, wherein the step of forming the functional well structure 60 on the N-type doped layer 40 includes: sequentially forming a transition substructure 61 and a light-emitting substructure 62 on the N-type doped layer 40; and performing step S130 to form a P-type doped structure 70 on the light-emitting substructure 62.

[0153] In some embodiments of the present invention, the preparation method further includes: before performing step S110, performing step S101 to provide a substrate 10; performing step S102 to sequentially form a buffer layer 20 and an undoped layer 30 on the substrate 10; and then sequentially performing steps S110, S120 and S130 to sequentially form the N-type doped layer 40, the functional well structure 60 and the P-type doped structure 70 on the undoped layer 30.

[0154] In some embodiments of the present invention, the steps of performing step S110, forming the N-type doped layer 40 on the substrate, performing step S120, forming the functional well structure 60, and performing step S130, forming the P-type doped structure 70 on the redundant barrier layer 622, are all performed by an epitaxial growth apparatus; the step of performing step S101, providing the substrate 10, includes: after providing the substrate 10, placing the substrate 10 in the epitaxial growth apparatus.

[0155] In some embodiments of the present invention, step S102, which involves sequentially forming a buffer layer 20 and an undoped layer 30 on the substrate 10, includes: growing a buffer layer 20 on the substrate 10; and growing an undoped layer 30 on the buffer layer 20.

[0156] For example, in the step of growing a buffer layer 20 on the substrate 10, the temperature of the epitaxial growth apparatus is set to a range of 500°C to 1000°C, the pressure is set to a range of 50 Torr to 500 Torr, a growth material source is introduced into the epitaxial growth apparatus, and the buffer layer 20 is grown on the substrate 10.

[0157] In some embodiments, in the step of growing the buffer layer 20, at least two types of growth material sources are introduced into the epitaxial growth apparatus to grow the buffer layer 20, which is a single-layer structure or a multi-layer composite structure.

[0158] For example, in the step of growing the buffer layer 20 on the substrate 10, an Al source (e.g., trimethylaluminum) and an N source (e.g., ammonia) are introduced into the epitaxial growth apparatus to grow a buffer layer 20 with AlN as the growth material; for example, in the step of growing the buffer layer 20 on the substrate 10, a Ga source (e.g., trimethylgallium or triethylgallium) and an N source (e.g., ammonia) are introduced into the epitaxial growth apparatus to grow a buffer layer 20 with GaN as the growth material; for example, in the step of growing the buffer layer 20 on the substrate 10... A buffer layer 20 with AlGaN as the growth material source is introduced into the epitaxial growth apparatus, consisting of an Al source (e.g., trimethylaluminum), an In source (e.g., trimethylindium), a Ga source (e.g., trimethylgallium or triethylgallium), and an N source (e.g., ammonia). For example, in the step of growing the buffer layer 20 on the substrate 10, a buffer layer 20 with AlInGaN as the growth material source is introduced into the epitaxial growth apparatus, consisting of an Al source (e.g., trimethylaluminum), an In source (e.g., trimethylindium), a Ga source (e.g., trimethylgallium or triethylgallium), and an N source (e.g., ammonia).

[0159] For example, in the step of growing an undoped layer 30 on the buffer layer 20, the temperature of the epitaxial growth equipment is set to a range of 1000°C to 1200°C, the pressure is set to a range of 50 Torr to 500 Torr, a growth material source is introduced into the epitaxial growth equipment, and an undoped layer 30 is grown on the buffer layer 20.

[0160] In some embodiments, during the growth of the undoped layer 30, at least two types of growth material sources are introduced into the epitaxial growth apparatus to grow the undoped layer 30 of a single-layer structure or a multilayer composite structure.

[0161] For example, in the step of growing an undoped layer 30 on the buffer layer 20, a Ga source (e.g., trimethylgallium) and an N source (e.g., ammonia) are introduced into the epitaxial growth apparatus to grow an undoped layer 30 of GaN material; for example, in the step of growing an undoped layer 30 on the buffer layer 20, an Al source (e.g., trimethylaluminum), a Ga source (e.g., trimethylgallium), and an N source (e.g., ammonia) are introduced into the epitaxial growth apparatus to grow an undoped layer 30 of AlGaN material; for example, in the step of growing an undoped layer 30 on the buffer layer 20, an Al source (e.g., trimethylaluminum), an In source (e.g., trimethylindium), a Ga source (e.g., trimethylgallium), and an N source (e.g., ammonia) are introduced into the epitaxial growth apparatus to grow an undoped layer 30 of AlInGaN material.

[0162] In some embodiments of the present invention, in step S110, which involves forming an N-type doped layer 40 on the substrate 10, the N-type doped layer 40 is grown on the undoped layer 30.

[0163] For example, the temperature range of the epitaxial growth equipment is set to 1000°C to 1100°C, and the pressure range is set to 50 Torr to 300 Torr. A growth material source and an N-type dopant source are introduced into the epitaxial growth equipment. The N-type dopant source can be at least one of a Si source and a Ge source.

[0164] In some embodiments, in the step of forming the N-type doped layer 40, at least two types of growth material sources are introduced into the epitaxial growth apparatus to grow the N-type doped layer 40 of a single-layer structure or a multilayer composite structure.

[0165] For example, in the step of forming the N-type doped layer 40, a Ga source (e.g., trimethylgallium) and an N source (e.g., ammonia) and an N-type doping source are introduced into the epitaxial growth apparatus to form the N-type doped layer 40 with GaN as the growth material; in the step of forming the N-type doped layer 40, an Al source (e.g., trimethylaluminum), a Ga source (e.g., trimethylgallium), and an N source (e.g., ammonia) and an N-type doping source are introduced into the epitaxial growth apparatus to form the N-type doped layer 40 with AlGaN as the growth material; in the step of forming the N-type doped layer 40, an Al source (e.g., trimethylaluminum), an In source (e.g., trimethylindium), a Ga source (e.g., trimethylgallium), and an N source (e.g., ammonia) and an N-type doping source are introduced into the epitaxial growth apparatus to form the N-type doped layer 40 with AlInGaN as the growth material.

[0166] Continue to refer to Figure 7 After forming the N-type doped layer 40, step S120 is performed to form the functional well structure 60. Step S120, which forms the functional well structure 60, includes forming a luminescent substructure 62 and a transition substructure 61.

[0167] Reference Figure 8 , showed Figure 7 The diagram shows a detailed flowchart of the steps for forming a functional well structure in some embodiments of the epitaxial wafer fabrication method.

[0168] In some embodiments of the present invention, the step of forming the light-emitting substructure 62 includes forming a multi-period light-emitting layer 621 on the transition substructure 61. Furthermore, in some embodiments, the step of forming the light-emitting substructure further includes forming a redundant barrier layer on the multi-period light-emitting layer.

[0169] For example, the steps of forming the light-emitting substructure 62 and the transition substructure 61 include: performing step S121 to form the transition substructure 61; and performing step S122 to form the light-emitting substructure 62 on the side of the transition substructure 61 away from the N-type doped layer 40.

[0170] For example, the steps of forming the luminescent substructure 62 and the transition substructure 61 include: growing the transition substructure 61 on the N-type doped layer 40; and growing the luminescent substructure 62 on the transition substructure 61.

[0171] In some embodiments, step S121, forming the transition substructure 61, includes: forming a transition stack, wherein forming the transition stack includes: forming a second barrier layer 61b; forming a second well layer 61a, wherein the second barrier layer 61b is located between the second well layer 61a of the same transition stack and the N-type doped layer 40; in step S121, forming the transition substructure 61, the step of forming the transition stack is performed multiple times to form a plurality of the transition stacks stacked along the line connecting the N-type doped layer 40 and the P-type doped structure 70.

[0172] In some embodiments, the step of forming the transition stack includes: growing a second barrier layer 61b; and growing a second well layer 61a on the second barrier layer 61b. For example, in the step of forming the transition stack, the temperature setting of the epitaxial growth apparatus is set to a range of 750°C to 900°C, and the pressure setting is set to a range of 100 Torr to 500 Torr.

[0173] For example, in the step of growing a second barrier layer 61b on an N-type doped layer 40, an Al source (e.g., trimethylaluminum), a Ga source (e.g., triethylgallium), an N source (e.g., ammonia) and an N-type dopant source are introduced into the epitaxial growth apparatus to grow an Al material that is N-type doped. y Ga 1-y The second barrier layer 61b of N has 0 < y ≤ 0.2; wherein the N-type doped source can be at least one of Si source and Ge source.

[0174] For example, in the step of growing a second barrier layer 61b on an N-type doped layer 40, a Ga source (e.g., triethylgallium), an N source (e.g., ammonia) and an N-type dopant source are introduced into an epitaxial growth apparatus to grow a second barrier layer 61b of N-type doped GaN material; wherein the N-type dopant source can be at least one of a Si source and a Ge source.

[0175] For example, in the step of growing the second well layer 61a on the second barrier layer 61b, an In source (e.g., trimethylindium), a Ga source (e.g., triethylgallium), and an N source (e.g., ammonia) are introduced into the epitaxial growth apparatus, and the material grown on the second barrier layer 61b is In. x Ga 1-x The second well layer 61a of N, where 0 < x ≤ 0.3.

[0176] In some embodiments of the present invention, the step of forming the second barrier layer 61b includes: providing an Al source (e.g., trimethylaluminum), a Ga source (e.g., triethylgallium), and an N source (e.g., ammonia) to form the second barrier layer 61b, wherein the second barrier layer 61b is Al. y Ga 1-yN layers, where 0 < y ≤ 0.2; during the multiple executions of the step of forming the transition stack, the amount of Al source provided in the later step of forming the transition stack and forming the second barrier layer 61b is greater than the amount of Al source provided in the earlier step of forming the transition stack and forming the second barrier layer 61b, thereby making the proportion of Al component in the second barrier layer 61b on the side away from the N-type doped layer 40 greater than the proportion of Al component in the second barrier layer 61b on the side closer to the N-type doped layer 40.

[0177] It should be noted that during the multiple executions of the step of forming the transition layer, the step of forming the transition layer in the later execution of the process of forming the second barrier layer 61b with a larger Al source input and the step of forming the transition layer in the earlier execution of the process of forming the second barrier layer 61b with a smaller Al source input may not be adjacent in the time domain.

[0178] In some exemplary embodiments, during multiple executions of the step of forming the transition layer, the amount of Al source supplied during the formation of the second barrier layer 61b increases sequentially. During two adjacent executions of the step of forming the transition layer, when the step of forming the second barrier layer 61b is executed, the amount of Al source supplied during the later execution of the step of forming the transition layer 61b is greater than the amount of Al source supplied during the previous execution of the step of forming the transition layer 61b; the amount of Al source supplied during the same execution of the step of forming the transition layer 61b remains stable.

[0179] Specifically, such as Figure 4 In some of the embodiments shown, during the multiple executions of the step of forming the transition stack, the Al source injection rate is greater when the second execution of the step of forming the transition stack to grow the second transition stack 612 and the step of forming the second barrier layer 61b is executed than when the first execution of the step of forming the transition stack to grow the first transition stack 611 and the step of forming the second barrier layer 61b is executed; the Al source injection rate is greater when the third execution of the step of forming the transition stack to grow the third transition stack 613 and the step of forming the second barrier layer 61b is executed than when the second execution of the step of forming the transition stack to grow the second transition stack 612 and the step of forming the second barrier layer 61b is executed; ...; the Al source injection rate is greater when the N2nd execution of the step of forming the transition stack to grow the N2nd transition stack 61N2 and the step of forming the second barrier layer 61b is executed than when the N2-1th execution of the step of forming the transition stack to grow the N2-1th transition stack 61N2-1 and the step of forming the second barrier layer 61b is executed.

[0180] However, the Al source injection rates during the following steps remain stable: the first execution of the step to form the transition layer 611 to grow the first transition layer 611, the second execution of the step to form the transition layer 612 to grow the second barrier layer 61b, the third execution of the step to form the transition layer 613 to grow the third barrier layer 61b, ..., the N2-1th execution of the step to form the transition layer 612 to grow the N2-1th transition layer 61N2-1 to grow the N2th barrier layer 61N2-1 to grow the N2th barrier layer 61N2 to grow the N2th barrier layer 61N2 to grow the N2th barrier layer 61N2 to grow the N2th barrier layer 61N2 to grow the N2th barrier layer 61N2. N2 ranges from 3 to 5.

[0181] In other embodiments, during the repeated execution of the step of forming the transition layer, the amount of Al source supplied during the formation of the second barrier layer gradually increases. For example, in the repeated execution of the step of forming the transition layer, when the step of forming the second barrier layer 61b is executed in two adjacent executions, the amount of Al source supplied during the later execution of the step of forming the transition layer 61b is greater than the amount of Al source supplied during the previous execution of the step of forming the transition layer 61b; the amount of Al source supplied during the same execution of the step of forming the transition layer 61b also increases over time.

[0182] In some specific embodiments, during the multiple executions of the step of forming the transition layer, the Al source injection rate is greater when the step of forming the second barrier layer is executed during the second execution of the step of forming the transition layer to grow the second transition layer than when the step of forming the second barrier layer is executed during the first execution of the step of forming the transition layer to grow the first transition layer; the Al source injection rate is greater when the step of forming the second barrier layer is executed during the third execution of the step of forming the transition layer to grow the third transition layer than when the step of forming the second barrier layer is executed during the second execution of the step of forming the transition layer to grow the second transition layer; ...; the Al source injection rate is greater when the step of forming the second barrier layer is executed during the N2nd execution of the step of forming the transition layer to grow the N2nd transition layer than when the step of forming the second barrier layer is executed during the N2-1th execution of the step of forming the transition layer to grow the N2-1th transition layer.

[0183] Furthermore, the Al source injection rate increases over time during the following steps: the first execution of the step to form the transition layer 611 to grow the first transition layer 611, the second execution of the step to form the transition layer 61b, the third execution of the step to form the transition layer 612 to grow the third transition layer 612, the N2-1th execution of the step to form the transition layer 61N2-1 to grow the N2-1th transition layer 61N2-1 to grow the N2nd transition layer 61N2 to grow the second barrier layer 61b, and the N2th execution of the step to form the transition layer 61N2 to grow the N2nd barrier layer 61N2 to grow the second barrier layer 61b.

[0184] Continue to refer to Figure 8 After forming the transition substructure, step S122 is performed to form the light-emitting substructure 62. For example, the light-emitting substructure 62 is formed on the transition substructure 61. The step of performing step S122 to form the light-emitting substructure 62 includes: forming a multi-period light-emitting layer 621 and a redundant barrier layer 622.

[0185] In some embodiments of the present invention, the step of performing step S122, forming a multi-period light-emitting layer 621 and a redundant barrier layer 622, includes: forming a multi-period light-emitting layer 621; and forming the redundant barrier layer 622 on the side of the multi-period light-emitting layer 621 away from the N-type doped layer 40.

[0186] In some embodiments, the step of forming a multi-period light-emitting layer 621 includes: forming a light-emitting stack, wherein the step of forming the light-emitting stack includes: forming a first barrier layer 62b; forming a first well layer 62a, wherein the first barrier layer 62b is located between the first well layer 62a of the same light-emitting stack and the N-type doped layer 40; in the step of forming a multi-period light-emitting layer 621, the step of forming the light-emitting stack is performed multiple times to form a plurality of light-emitting stacks stacked along the line connecting the N-type doped layer 40 and the P-type doped structure 70.

[0187] In some embodiments, the step of forming the light-emitting stack includes: growing a first barrier layer 62b; and growing a first well layer 62a on the first barrier layer 62b. For example, in the step of forming the light-emitting stack, the temperature of the epitaxial growth apparatus is set to a range of 750°C to 900°C, and the pressure is set to a range of 50 Torr to 300 Torr; a Ga source (e.g., triethylgallium), an N source (e.g., ammonia), and an N-type doped source (e.g., at least one of a Si source and a Ge source) are introduced into the epitaxial growth apparatus; a first barrier layer 62a of N-type doped GaN is grown; then, the introduction of the N-type doped source is stopped, while the introduction of the Ga source (e.g., triethylgallium) and the N source (e.g., ammonia) continues, and an In source (e.g., trimethylindium) is introduced into the epitaxial growth apparatus to grow an In material on the first barrier layer 62a. w Ga 1-w The first well layer of N is 62b, where 0.1≤w≤0.4.

[0188] After forming the multi-period light-emitting layer 621, a redundant barrier layer 622 is grown on the multi-period light-emitting layer 621. For example, in the step of forming the redundant barrier layer 622, the temperature of the epitaxial growth apparatus is set to a range of 750°C to 900°C, and the pressure range is set to a range of 50 Torr to 300 Torr. A Ga source (e.g., triethylgallium) and an N source (e.g., ammonia) are introduced into the epitaxial growth apparatus, and a redundant barrier layer 622 of GaN material is grown on the multi-period light-emitting layer 621.

[0189] In some embodiments, the process conditions in the step of growing the redundant barrier layer 622 are the same as those in the step of growing the first barrier layer 62b, and the resulting redundant barrier layer 622 has the same properties as the resulting first barrier layer 62b. The redundant barrier layer 622 can serve as a barrier layer, and together with the first well layer 62a and the first barrier layer 62b in the N1th luminescent stack, it constitutes the quantum well structure closest to the p-type doped structure 70 in the luminescent substructure 62.

[0190] Continue to refer to Figure 8 Combined with reference Figure 6 In some embodiments of the present invention, the step of forming the functional well structure 60 includes: performing step S110, after forming the N-type doped layer 40 on the substrate, performing step S121, before forming the transition substructure 61, and performing step S123, to form the stress-adjusting structure 50.

[0191] For example, the steps of forming the functional well structure 60 include: performing step S110, after forming the N-type doped layer 40 on the substrate, performing step S121, before forming the transition substructure 61, and performing step S123, forming a stress-adjusting structure 50 on the N-type doped layer 40.

[0192] In some embodiments of the present invention, the step of forming the stress-adjusting structure 50 includes: forming a stress-adjusting stack, wherein the step of forming the stress-adjusting stack includes: forming a third well layer 501; forming a third barrier layer 502, wherein the third barrier layer 502 is located between the third well layer 501 and the N-type doped layer 40 in the same stress-adjusting stack; wherein the step of forming the stress-adjusting stack is performed multiple times in the step of forming the stress-adjusting stack, thereby forming a plurality of the stress-adjusting stacks stacked along the line connecting the N-type doped layer 40 and the P-type doped structure 70.

[0193] In some embodiments, the step of forming a stress-regulated stack includes: growing a third barrier layer 502; and growing a third well layer 501 on the third barrier layer 503. For example, in the step of forming the stress-regulated stack, the temperature setting range of the epitaxial growth apparatus is set to 700°C to 900°C, and the pressure range is set to 100 Torr to 300 Torr.

[0194] For example, in the step of growing a third barrier layer 502 on the N-type doped layer 40, a Ga source (e.g., at least one of trimethylgallium and triethylgallium) and an N source (e.g., ammonia) are introduced into the epitaxial growth apparatus to grow a third barrier layer 501 of GaN material on the N-type doped layer 40.

[0195] For example, in the step of growing the third well layer 501 on the third barrier layer 503, after growing the third barrier layer 502 on the N-type doped layer 40, Ga source and N source are continuously introduced into the epitaxial growth apparatus while maintaining the amount of Ga source and N source introduced at a constant level, and an In source (e.g., trimethylindium) is introduced into the epitaxial growth apparatus, and the material grown on the third barrier layer 501 is In. z Ga 1-z The third well layer 502 of N, where 0 < z ≤ 0.1.

[0196] The Ga source introduced into the epitaxial growth apparatus is at least one of trimethylgallium and triethylgallium. After the third barrier layer 502 is grown on the N-type doped layer 40, a Ga source continues to be introduced into the epitaxial growth apparatus to grow In as the growth material. z Ga 1-z The third well layer 502 of N; the Ga source introduced during the growth of the third well layer 501 on the third barrier layer 503 is the same Ga source introduced during the growth of the third barrier layer 502 on the N-type doped layer 40.

[0197] Continue to refer to Figure 7 The preparation method further includes: after forming the functional well structure 60, performing step S130, forming a P-type doped structure 70 on the redundant barrier layer 622.

[0198] In some embodiments of the present invention, the step of forming the P-type doped structure 70 includes: forming a multi-period doped layer 72; and forming a P-type layer 71 on the side of the multi-period doped layer 72 away from the N-type doped layer 40. For example, the multi-period doped layer 72 is grown on the functional well structure 60.

[0199] In some embodiments, the step of forming a multi-period doped layer 72 includes: forming a doped stack, wherein forming a doped stack includes: forming a ternary doped layer 72a; forming a binary doped layer 72b, wherein the ternary doped layer 72a is located between the binary doped layer 72b and the functional well structure 60 in the same doped stack; wherein the step of forming a multi-period doped layer 72 is performed multiple times to form a plurality of doped stacks stacked along the line connecting the N-type doped layer 40 and the P-type doped structure 70.

[0200] For example, such as Figure 5 As shown, in the step of forming a multi-period doped layer 72, the step of forming a doped stack is performed for the first time to form a first doped stack 721, the step of forming a doped stack is performed for the second time to form a second doped stack 722, the step of forming a doped stack is performed for the third time to form a third doped stack 723, ..., the step of forming a doped stack is performed for the N3rd time to form an N3rd doped stack 72N3.

[0201] In some embodiments, the step of forming the multi-period doped layer 72 is performed at least five times. For example... Figure 5 In some of the embodiments shown, N3 is greater than or equal to 5.

[0202] In some embodiments, the step of forming a doped stack includes: providing a P-type dopant source; and, during multiple executions of the step of forming the doped stack, the amount of P-type dopant provided in the step of providing the P-type dopant source in a previous execution of the step of forming the doped stack is less than the amount of P-type dopant provided in the step of providing the P-type dopant source in a subsequent execution of the step of forming the doped stack, thereby making the P-type dopant concentration of the multi-period doped layer 72 on the side away from the N-type doped layer 40 greater than the P-type dopant concentration of the multi-period doped layer 72 on the side closer to the N-type doped layer 40.

[0203] It should be noted that during the multiple executions of the steps for forming the doped stack, the steps of providing the P-type dopant source in the earlier steps of forming the doped stack with a smaller amount of P-type dopant source and the steps of providing the P-type dopant source in the later steps of forming the doped stack with a larger amount of P-type dopant source may not be adjacent in the time domain.

[0204] In some exemplary embodiments, during the repeated execution of the step of forming the doped stack, the amount of P-type dopant provided by the step of forming the doped stack increases progressively. During the formation of the multi-period doped layer 72, in two consecutive executions of the step of forming the doped stack, the amount of P-type dopant provided in the step of providing the P-type dopant in the later execution of the step of forming the doped stack is greater than the amount of P-type dopant provided in the step of providing the P-type dopant in the previous execution of the step of forming the doped stack.

[0205] like Figure 5 As shown, the amount of P-type dopant provided in the second execution of the process of forming the doped stack to grow the second doped stack 722 is greater than the amount of P-type dopant provided in the first execution of the process of forming the doped stack to grow the first doped stack 721; the amount of P-type dopant provided in the third execution of the process of forming the doped stack to grow the third doped stack 723 is greater than the amount of P-type dopant provided in the second execution of the process of forming the doped stack to grow the second doped stack 722; ...; the amount of P-type dopant provided in the third execution of the process of forming the doped stack to grow the third doped stack 723 is greater than the amount of P-type dopant provided in the N3rd execution of the process of forming the doped stack to grow the N3rd doped stack 72N3. Wherein, N3 ranges from 3 to 5.

[0206] In some embodiments, the injection rate of the provided P-type dopant source remains stable during each execution of the step of forming the doped stack. During each execution of the step of forming the doped stack, the injection rate of the P-type dopant source provided during the formation of the ternary doped layer 72a and the injection rate of the P-type dopant source provided during the formation of the binary doped layer 72b remain stable, and the injection rate of the P-type dopant source provided during the formation of the ternary doped layer 72a and the injection rate of the P-type dopant source provided during the formation of the binary doped layer 72b are equal.

[0207] like Figure 5As shown, during the first execution of forming the doped stack to grow the first doped stack 721, the second execution of forming the doped stack to grow the second doped stack 722, the third execution of forming the doped stack to grow the third doped stack 723, ..., the N3rd execution of forming the doped stack to grow the N3rd doped stack 72N3, the amount of P-type dopant source provided during the formation of the ternary doped layer 72a and the amount of P-type dopant source provided during the formation of the binary doped layer 72b remain stable.

[0208] In other embodiments, in each execution of the step of forming the doped stack, in the steps of forming the ternary doped layer and forming the binary doped layer, the amount of P-type dopant provided in the later execution step is greater than the amount of P-type dopant provided in the earlier execution step. For example, in each execution of the step of forming the doped stack, a ternary doped layer is first grown on the functional well structure; then a binary doped layer is grown on the ternary doped layer. In each execution of the step of forming the doped stack, the amount of P-type dopant provided during the formation of the binary doped layer is greater than the amount of P-type dopant provided during the formation of the ternary doped layer; however, the amounts of P-type dopant provided during the formation of the binary doped layer and the amounts of P-type dopant provided during the formation of the ternary doped layer remain stable.

[0209] For example, during the first execution of the step of forming a doped stack to grow a first doped stack, the amount of P-type dopant provided during the formation of the binary doped layer is greater than the amount of P-type dopant provided during the formation of the ternary doped layer, but the amount of P-type dopant provided during the formation of the binary doped layer and the amount of P-type dopant provided during the formation of the ternary doped layer remain stable respectively; during the second execution of the step of forming a doped stack to grow a second doped stack, the amount of P-type dopant provided during the formation of the binary doped layer is greater than the amount of P-type dopant provided during the formation of the ternary doped layer, but the amount of P-type dopant provided during the formation of the binary doped layer and the amount of P-type dopant provided during the formation of the ternary doped layer remain stable respectively. During the third execution of the step of forming a doped stack to grow the third doped stack, the amount of P-type dopant source provided during the formation of the binary doped layer is greater than the amount of P-type dopant source provided during the formation of the ternary doped layer, but the amount of P-type dopant source provided during the formation of the binary doped layer and the amount of P-type dopant source provided during the formation of the ternary doped layer remain stable respectively; ...; During the N3rd execution of the step of forming a doped stack to grow the N3rd doped stack, the amount of P-type dopant source provided during the formation of the binary doped layer is greater than the amount of P-type dopant source provided during the formation of the ternary doped layer, but the amount of P-type dopant source provided during the formation of the binary doped layer and the amount of P-type dopant source provided during the formation of the ternary doped layer remain stable respectively.

[0210] In other embodiments, the amount of P-type dopant source provided gradually increases in each step of forming the doped stack. In each step of forming the doped stack, the amount of P-type dopant source provided during the formation of the binary doped layer is greater than the amount of P-type dopant source provided during the formation of the ternary doped layer; and the amounts of P-type dopant source provided during the formation of the binary doped layer and the ternary doped layer gradually increase, respectively.

[0211] For example, during the first execution of the step of forming a doped stack to grow a first doped stack, the amount of P-type dopant provided during the formation of the binary doped layer is greater than the amount of P-type dopant provided during the formation of the ternary doped layer, and the amount of P-type dopant provided during the formation of the binary doped layer and the amount of P-type dopant provided during the formation of the ternary doped layer gradually increase, respectively; during the second execution of the step of forming a doped stack to grow a second doped stack, the amount of P-type dopant provided during the formation of the binary doped layer is greater than the amount of P-type dopant provided during the formation of the ternary doped layer, and the amount of P-type dopant provided during the formation of the binary doped layer and the amount of P-type dopant provided during the formation of the ternary doped layer gradually increase, respectively. During the third execution of the step of forming a doped stack to grow the third doped stack, the amount of P-type dopant source provided during the formation of the binary doped layer is greater than the amount of P-type dopant source provided during the formation of the ternary doped layer, and the amounts of P-type dopant source provided during the formation of the binary doped layer and the formation of the ternary doped layer gradually increase; ...; During the N3rd execution of the step of forming a doped stack to grow the N3rd doped stack, the amount of P-type dopant source provided during the formation of the binary doped layer is greater than the amount of P-type dopant source provided during the formation of the ternary doped layer, and the amounts of P-type dopant source provided during the formation of the binary doped layer and the formation of the ternary doped layer gradually increase.

[0212] In some embodiments, the step of forming the doped stack includes: growing a ternary doped layer 72a on the functional well structure; and growing a binary doped layer 72b on the ternary doped layer 72a. For example, in the step of forming the doped stack, the temperature setting range of the epitaxial growth apparatus is set to 720°C to 950°C, and the pressure range is set to 100 Torr to 300 Torr.

[0213] In some embodiments, in the step of forming the ternary doped layer 72a, an In source, a Ga source, an N source, and a P-type doped source are provided to form the ternary doped layer 72a, wherein the ternary doped layer 72a is a P-type doped InGaN layer; in the step of forming the binary doped layer 72b, a Ga source, an N source, and a P-type doped source are provided to form the binary doped layer 72b, wherein the binary doped layer 72b is a P-type doped GaN layer.

[0214] For example, in the step of growing a ternary doped layer 72a on the functional well structure, an In source (e.g., trimethylindium), a Ga source, an N source (e.g., ammonia) and a P-type doped source (e.g., at least one of a Mg source and a Zn source) are introduced into the epitaxial growth apparatus to grow a ternary doped layer 72a of P-type doped InGaN.

[0215] For example, in the step of growing a binary doped layer 72b on the ternary doped layer 72a, the supply of an In source (e.g., trimethylindium) to the epitaxial growth apparatus is stopped, and a Ga source, an N source (e.g., ammonia) and a P-type doping source are continued to be supplied to the epitaxial growth apparatus, so that a binary doped layer 72b of P-type doped GaN is grown on the ternary doped layer 72a.

[0216] In some embodiments of the present invention, during the repeated execution of the step of forming the doped stack, the amount of Ga source provided in the step of forming the doped stack performed earlier is greater than the amount of Ga source provided in the step of forming the doped stack performed later; the amount of In source provided in the step of forming the ternary doped layer 72a performed earlier is less than the amount of In source provided in the step of forming the ternary doped layer 72a performed later, thereby making the Ga component content in the multi-period doped layer away from the N-type doped layer less than the Ga component content in the multi-period doped layer near the N-type doped layer, and the In component content of the InGaN layer in the multi-period doped layer away from the N-type doped layer greater than the In component content of the InGaN layer in the multi-period doped layer near the N-type doped layer.

[0217] It should be noted that during the multiple executions of the steps for forming the doped stack, the steps for forming the doped stack performed earlier with a larger amount of Ga source provided and the steps for forming the doped stack performed later with a smaller amount of Ga source provided may not be adjacent in the time domain; similarly, the steps for forming the ternary doped layer 72a during the process of forming the doped stack with a smaller amount of In source provided earlier and the steps for forming the ternary doped layer 72a during the process of forming the doped stack with a larger amount of In source provided later may not be adjacent in the time domain.

[0218] In some exemplary embodiments, during the repeated execution of the step of forming the doped stack, the amount of Ga source provided during the step of forming the doped stack decreases successively; during the repeated execution of the step of forming the doped stack, the amount of In source provided during the step of forming the ternary doped layer 72a increases successively. During the formation of the multi-period doped layer 72, in two adjacent executions of the step of forming the doped stack, the amount of Ga source provided in the later execution of the step of forming the doped stack is less than the amount of Ga source provided in the previous execution of the step of forming the doped stack, and the amount of In source provided in the later execution of the step of forming the doped stack and the step of forming the ternary doped layer 72a is greater than the amount of In source provided in the previous execution of the step of forming the doped stack and the step of forming the ternary doped layer 72a.

[0219] like Figure 5 As shown, the amount of Ga source supplied during the second execution of forming the doped stack to grow the second doped stack 722 is less than the amount of Ga source supplied during the first execution of forming the doped stack to grow the first doped stack 721; the amount of Ga source supplied during the third execution of forming the doped stack to grow the third doped stack 723 is less than the amount of Ga source supplied during the second execution of forming the doped stack to grow the second doped stack 722; ...; the amount of Ga source supplied during the N3rd execution of forming the doped stack to grow the N3rd doped stack 72N3 is less than the amount of Ga source supplied during the N3-1th execution of forming the doped stack to grow the N3-1th doped stack 72N3-1. Wherein, N3 is greater than or equal to 5.

[0220] Furthermore, the amount of In source provided in the step of forming the ternary doped layer 72a during the second execution of forming the doped stack to grow the second doped stack 722 is greater than the amount of In source provided in the step of forming the ternary doped layer 72a during the first execution of forming the doped stack to grow the first doped stack 721; the amount of In source provided in the step of forming the ternary doped layer 72a during the third execution of forming the doped stack to grow the third doped stack 723 is greater than the amount of In source provided in the step of forming the ternary doped layer 72a during the second execution of forming the doped stack to grow the second doped stack 722; ...; the amount of In source provided in the step of forming the ternary doped layer 72a during the N3rd execution of forming the doped stack to grow the N3rd doped stack 72N3 is greater than the amount of In source provided in the step of forming the ternary doped layer 72a during the N3-1th execution of forming the doped stack to grow the N3-1th doped stack 72N3-1. Wherein, N3 is greater than or equal to 5.

[0221] In some embodiments, the amount of Ga source supplied remains stable during each step of forming the doped layer stack; the amount of In source supplied remains stable during each step of forming the ternary doped layer 72a. During each step of forming the doped layer stack, the amount of Ga source supplied during the formation of the ternary doped layer 72a and the amount of Ga source supplied during the formation of the binary doped layer 72b remain stable, and the amount of Ga source supplied during the formation of the ternary doped layer 72a and the amount of Ga source supplied during the formation of the binary doped layer 72b are equal. During each step of forming the doped layer stack, the amount of In source supplied during the formation of the ternary doped layer 72a remains stable.

[0222] like Figure 5 As shown, during the first execution of forming the doped stack to grow the first doped stack 721, the second execution of forming the doped stack to grow the second doped stack 722, the third execution of forming the doped stack to grow the third doped stack 723, ..., the N3rd execution of forming the doped stack to grow the N3rd doped stack 72N3, the amount of Ga source provided during the formation of the ternary doped layer 72a and the amount of Ga source provided during the formation of the binary doped layer 72b remain stable.

[0223] During the first execution of forming the doped stack to grow the first doped stack 721, the second execution of forming the doped stack to grow the second doped stack 722, the third execution of forming the doped stack to grow the third doped stack 723, ..., the N3rd execution of forming the doped stack to grow the N3rd doped stack 72N3, the amount of In source provided during the formation of the ternary doped layer 72a remains stable.

[0224] In other embodiments, in each execution of the step of forming the doped stack, the amount of Ga source supplied in the step of forming the binary doped layer is less than the amount of Ga source supplied in the step of forming the ternary doped layer. For example, in each execution of the step of forming the doped stack, a ternary doped layer is first grown on the functional well structure; then a binary doped layer is grown on the ternary doped layer. In each execution of the step of forming the doped stack, the amount of Ga source supplied during the formation of the binary doped layer is less than the amount of Ga source supplied during the formation of the ternary doped layer; however, the amounts of Ga source supplied during the formation of the binary doped layer and the amounts of Ga source supplied during the formation of the ternary doped layer remain stable.

[0225] For example, during the first execution of the step of forming a doped stack to grow a first doped stack, the amount of Ga source provided during the formation of the binary doped layer is less than the amount of Ga source provided during the formation of the ternary doped layer, but the amount of Ga source provided during the formation of the binary doped layer and the amount of Ga source provided during the formation of the ternary doped layer remain stable respectively; during the second execution of the step of forming a doped stack to grow a second doped stack, the amount of Ga source provided during the formation of the binary doped layer is less than the amount of Ga source provided during the formation of the ternary doped layer, but the amount of Ga source provided during the formation of the binary doped layer and the amount of Ga source provided during the formation of the ternary doped layer remain stable respectively. During the third execution of the step of forming a doped stack to grow the third doped stack, the amount of Ga source provided during the formation of the binary doped layer is less than the amount of Ga source provided during the formation of the ternary doped layer, but the amount of Ga source provided during the formation of the binary doped layer and the amount of Ga source provided during the formation of the ternary doped layer remain stable respectively; ...; During the N3rd execution of the step of forming a doped stack to grow the N3rd doped stack, the amount of Ga source provided during the formation of the binary doped layer is less than the amount of Ga source provided during the formation of the ternary doped layer, but the amount of Ga source provided during the formation of the binary doped layer and the amount of Ga source provided during the formation of the ternary doped layer remain stable respectively.

[0226] In other embodiments, the amount of Ga source supplied gradually decreases during each step of forming the doped stack; and the amount of In source supplied gradually increases during each step of forming the ternary doped layer. During each step of forming the doped stack, the amount of Ga source supplied during the formation of the binary doped layer is less than the amount of Ga source supplied during the formation of the ternary doped layer; and the amounts of Ga source supplied during the formation of the binary doped layer and the formation of the ternary doped layer gradually decrease.

[0227] For example, during the first execution of the step of forming a doped stack to grow a first doped stack, the amount of Ga source provided during the formation of the binary doped layer is less than the amount of Ga source provided during the formation of the ternary doped layer, and the amount of Ga source provided during the formation of the binary doped layer and the amount of Ga source provided during the formation of the ternary doped layer gradually decrease; during the second execution of the step of forming a doped stack to grow a second doped stack, the amount of Ga source provided during the formation of the binary doped layer is less than the amount of Ga source provided during the formation of the ternary doped layer, and the amount of Ga source provided during the formation of the binary doped layer and the amount of Ga source provided during the formation of the ternary doped layer gradually decrease; During the third execution of the step of forming a doped stack to grow the third doped stack, the amount of Ga source provided during the formation of the binary doped layer is less than the amount of Ga source provided during the formation of the ternary doped layer, and the amounts of Ga source provided during the formation of the binary doped layer and the formation of the ternary doped layer gradually decrease; ...; During the N3rd execution of the step of forming a doped stack to grow the N3rd doped stack, the amount of Ga source provided during the formation of the binary doped layer is less than the amount of Ga source provided during the formation of the ternary doped layer, and the amounts of Ga source provided during the formation of the binary doped layer and the formation of the ternary doped layer gradually decrease.

[0228] The amount of In source provided in the step of forming a ternary doped layer during the second execution of the process of forming a doped stack to grow a second doped stack is greater than the amount of In source provided in the step of forming a ternary doped layer during the first execution of the process of forming a doped stack to grow a first doped stack; the amount of In source provided in the step of forming a ternary doped layer during the third execution of the process of forming a doped stack to grow a third doped stack is greater than the amount of In source provided in the step of forming a ternary doped layer during the second execution of the process of forming a doped stack to grow a second doped stack; ...; the amount of In source provided in the step of forming a ternary doped layer during the N3rd execution of the process of forming a doped stack to grow an N3-1 doped stack is greater than the amount of In source provided in the step of forming a ternary doped layer during the N3-1th execution of the process of forming a doped stack to grow an N3-1 doped stack. Furthermore, during the first execution of forming the doped stack to grow the first doped stack, the second execution of forming the doped stack to grow the second doped stack, the third execution of forming the doped stack to grow the third doped stack, ..., the N3rd execution of forming the doped stack to grow the N3rd doped stack 72N3, the amount of In source provided during the formation of the ternary doped layer gradually increases. Here, N3 is greater than or equal to 5.

[0229] It should be noted that in the step of forming the multi-period doped layer 72, the Ga source provided can be at least one of trimethylgallium or triethylgallium; the Ga source introduced into the epitaxial growth apparatus can be at least one of trimethylgallium or triethylgallium.

[0230] The step of forming the P-type doped structure 70 further includes: after forming the multi-period doped layer 72, forming the P-type layer 71 on the multi-period doped layer 72.

[0231] For example, in the step of growing the P-type layer 71, the temperature of the epitaxial growth apparatus is set to a range of 720°C to 950°C, and the pressure is set to a range of 100 Torr to 300 Torr. An In source (e.g., trimethylindium), a Ga source, an N source (e.g., ammonia), and a P-type doped source (e.g., at least one of a Mg source and a Zn source) are introduced into the epitaxial growth apparatus to grow a P-type layer 71 of P-type doped InGaN on the multi-period doped layer 72. The Ga source can be at least one of trimethylgallium and triethylgallium.

[0232] In some embodiments, during the multiple executions of the step of forming a doped stack, the step of forming a doped stack is performed at least 5 times.

[0233] Continue to refer to Figure 7The preparation method further includes: after forming the N-type doped layer 40, the functional well structure 60, and the P-type doped structure 70, performing step S103, annealing. For example, annealing is performed after forming the P-type doped structure.

[0234] In some embodiments, the annealing temperature is in the range of 500°C to 780°C during the annealing step.

[0235] In some embodiments, step S110, forming the N-type doped layer 40 on the substrate, step S120, forming the functional well structure 60, and step S130, forming the P-type doped structure 70, are all performed using an epitaxial growth apparatus. In the annealing step, the temperature of the epitaxial growth apparatus is set to an annealing temperature. Specifically, the annealing step is performed at a temperature between 500°C and 780°C.

[0236] refer to Figure 9 The diagram shows a flowchart of some embodiments of the epitaxial wafer preparation method of the present invention.

[0237] Reference Figure 1 , showed Figure 7 The diagram shows a cross-sectional structure of the epitaxial wafer formed by some embodiments of the epitaxial wafer preparation method.

[0238] The method for preparing the epitaxial wafer includes: performing step S210 to form an N-type doped layer 40 on a substrate; performing step S220 to form a functional well structure 60 on the N-type doped layer 40, wherein the step of forming the functional well structure 60 on the N-type doped layer 40 includes: forming a redundant barrier layer 622 on the N-type doped layer 40; and performing step S230 to form a P-type doped structure 70 on the redundant barrier layer 622.

[0239] In some embodiments of the present invention, such as Figure 2 As shown, the method for preparing the epitaxial wafer further includes: performing step S210, before forming an N-type doped layer 40 on the substrate 10, performing step S201 to provide a substrate; after providing the substrate, performing step S202 to sequentially form a buffer layer 20 and an undoped layer 30 on the substrate 10; then, sequentially performing steps S210, S220 and S230 to sequentially form the N-type doped layer 40, the functional well structure 60 and the P-type doped structure 70 on the undoped layer 30.

[0240] The steps S201, providing the substrate, and S202, sequentially forming the buffer layer 20 and the undoped layer 30 on the substrate 10, are similar to or the same as those in the embodiments of the aforementioned epitaxial wafer fabrication method. Specific technical solutions for steps S201, providing the substrate, and S202, sequentially forming the buffer layer 20 and the undoped layer 30 on the substrate 10 can be found in the embodiments of the aforementioned epitaxial wafer fabrication method.

[0241] In some embodiments of the present invention, the step of forming a functional well structure 60 on the N-type doped layer 40 further includes: forming a multi-periodic light-emitting layer 621 on the side of the N-type doped layer 40 away from the substrate 10 before the step of forming the redundant barrier layer 622.

[0242] The step of forming a multi-period light-emitting layer 621 on the side of the N-type doped layer 40 away from the substrate 10 is similar to or the same as the embodiment of the aforementioned epitaxial wafer fabrication method. Specific technical solutions for the step of forming the multi-period light-emitting layer 621 on the side of the N-type doped layer 40 away from the substrate 10 can be found in the embodiment of the aforementioned epitaxial wafer fabrication method.

[0243] In some embodiments, the step of forming the functional well structure 60 further includes forming a stress-adjusting structure 50 on the side of the N-type doped layer 40 away from the substrate 10 before forming the multi-period light-emitting layer 621.

[0244] The step of forming the stress adjustment structure 50 on the side of the N-type doped layer 40 away from the substrate 10 is similar to or the same as in the embodiments of the aforementioned epitaxial wafer fabrication method. Specific technical solutions for the step of forming the stress adjustment structure 50 on the side of the N-type doped layer 40 away from the substrate 10 can be found in the embodiments of the aforementioned epitaxial wafer fabrication method.

[0245] In some embodiments of the present invention, the step of forming the P-type doped structure 70 includes: forming a multi-period doped layer 72 on the side of the redundant barrier layer 622 away from the N-type doped layer 40; and forming a P-type layer 71 on the side of the multi-period doped layer 72 away from the N-type doped layer 40.

[0246] The steps of forming a multi-period doped layer 72 on the side of the redundant barrier layer 622 away from the N-type doped layer 40 and forming a P-type layer 71 on the side of the multi-period doped layer 72 away from the N-type doped layer 40 are similar to or the same as those in the aforementioned epitaxial wafer fabrication method embodiments. Specific technical solutions for the steps of forming a multi-period doped layer 72 on the side of the redundant barrier layer 622 away from the N-type doped layer 40 and forming a P-type layer 71 on the side of the multi-period doped layer 72 away from the N-type doped layer 40 can be found in the aforementioned epitaxial wafer fabrication method embodiments.

[0247] In some embodiments of the present invention, the method for preparing the epitaxial wafer further includes: performing step S230, after the step of forming the P-type doped structure 70, performing step S203, and annealing.

[0248] In step S203, the annealing step is similar to or the same as in the aforementioned epitaxial wafer preparation method embodiments. The specific technical solution for step S203, the annealing step, can be referred to in the aforementioned epitaxial wafer preparation method embodiments. In summary, the functional well structure located between the N-type doped layer and the P-type doped structure includes: a luminescent substructure and a transition substructure, wherein the transition substructure is located between the luminescent substructure and the N-type doped layer. In the luminescent substructure, the multi-period luminescent layer is a multi-quantum well structure. The barrier layer and the redundant barrier layer of the multi-quantum well structure have a weaker blocking effect on holes, which can increase the migration distance of holes, thereby increasing the number of luminescent quantum wells and improving the luminescence efficiency of the epitaxial wafer. The transition substructure is located between the light-emitting substructure and the N-type doped layer. It can effectively control the electron concentration of the light-emitting layer without setting an N-type current diffusion layer between the N-type doped layer and the light-emitting substructure, thereby improving the electron-hole balance in the light-emitting layer and effectively improving the luminous efficiency of the epitaxial wafer. Moreover, the method of controlling the electron concentration in the light-emitting layer through the transition substructure eliminates the need for an electron blocking layer between the P-type doped layer and the light-emitting substructure, and can also effectively increase the hole migration distance, thereby effectively improving the luminous efficiency of the epitaxial wafer.

[0249] Furthermore, the P-type doped structure includes a P-type layer and a multi-period doped layer, wherein the multi-period doped layer is located between the P-type layer and the functional well structure. The multi-period doped layer comprises multiple doped stacks, including ternary doped layers and binary doped layers, wherein the ternary doped layer is located between the binary doped layer within the same doped stack and the functional well structure. The multi-period doped layer can increase the effective hole concentration, improve hole injection efficiency, and enhance the electron-hole balance in the photonic structure. It can also lower the annealing temperature of subsequent annealing processes, effectively reducing the impact of the annealing process on the potential well in the functional well structure.

[0250] The epitaxial wafers described above can be used in microdisplay panels.

[0251] The aforementioned microdisplay panel has a very small volume, with length and width dimensions between 500 μm and 50,000 μm. The light-emitting area of ​​the microdisplay panel is very small, for example, 1 mm × 1 mm, 2.64 mm × 2.02 mm, 3 mm × 5 mm, etc. The light-emitting area of ​​the microdisplay panel includes multiple micro-LED pixels arranged in an array, specifically in a pixel arrangement of 320 × 240, 640 × 480, 1600 × 1200, 1920 × 1080, or 2560 × 1440. The size of a single micro-LED pixel is between 100 nm and 100 μm. In some embodiments, the size of a single micro-LED pixel is between 150 nm and 15 μm. In some embodiments, the size of a single micro-LED pixel can be less than 10 μm.

[0252] A driving backplane is disposed on the back of the micro-LED pixel array. The driving backplane is electrically connected to the micro-LEDs in the micro-LED pixel array. The driving backplane can acquire signals such as image data from the outside world and can control the corresponding micro-LEDs to emit light or not emit light. The driving backplane is a TFT (Thin Film Transistor) board or an IC (Integrated Circuit) board.

[0253] For example, the driving backplane of the aforementioned micro-display panel integrates a frame buffer, a column driving circuit, and a row driving circuit. The frame buffer includes a first pixel storage area, and the micro-LED pixel array includes a second pixel storage area. A complete frame of pixel grayscale data from the outside world can first enter the first pixel storage area of ​​the frame buffer. The column driving circuit can load the pixel grayscale data in the first pixel storage area of ​​the frame buffer into the second pixel storage area of ​​the micro-LED pixel array. The row driving circuit can scan the pixel grayscale data in the second pixel storage area and generate a pulse modulation signal to achieve the purpose of displaying different grayscale levels. When driving multiple micro-LED pixels in the micro-LED pixel array, either a single pixel can be driven independently, or multiple pixel units can be driven independently. The specific driving method should not constitute a limitation of the present invention.

[0254] It should be noted that the application of the epitaxial wafer described above in microdisplay panels should not constitute a limitation on the application of this invention.

[0255] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An epitaxial wafer, characterized in that, include: The stacked N-type doped layer, functional well structure and P-type doped structure; The functional well structure is located between the N-type doped layer and the P-type doped structure, and the functional well structure includes: a luminescent substructure and a transition substructure, wherein the transition substructure is located between the luminescent substructure and the N-type doped layer; The transition substructure includes: multiple transition layers, the transition layers including: a second barrier layer and a second well layer.

2. The epitaxial wafer as described in claim 1, characterized in that, The light-emitting substructure includes a multi-period light-emitting layer, which is located between the transition substructure and the p-type doped structure.

3. The epitaxial wafer as described in claim 2, characterized in that, The luminescent substructure further includes a redundant barrier layer located between the multi-period luminescent layer and the P-type doped structure.

4. The epitaxial wafer as described in claim 1, characterized in that, The functional well structure is one of the III-V group multiple quantum well structure and the II-VI group multiple quantum well structure.

5. The epitaxial wafer as described in claim 2 or 3, characterized in that, The multi-period light-emitting layer includes: a plurality of light-emitting stacks, each light-emitting stack including: a first barrier layer and a first well layer, wherein the first barrier layer is located between the first well layer and the N-type doped layer of the same light-emitting stack.

6. The epitaxial wafer as described in claim 5, characterized in that, The first well layer is In w Ga 1-w N layers, where 0.1≤w≤0.4; the first barrier layer is an N-type doped GaN layer.

7. The epitaxial wafer as described in claim 5, characterized in that, The thickness of the first well layer ranges from 2.0 nm to 4.0 nm, and the thickness of the first barrier layer ranges from 9.0 nm to 14.0 nm.

8. The epitaxial wafer as described in claim 5, characterized in that, The multi-period light-emitting layer has 5 to 10 light-emitting stacks.

9. The epitaxial wafer as described in claim 3, characterized in that, The redundant barrier layer is an intrinsic layer.

10. The epitaxial wafer as described in claim 3 or 9, characterized in that, The redundant barrier layer is one of the III-V group intrinsic layers and the II-VI group intrinsic layers.

11. The epitaxial wafer as described in claim 9, characterized in that, The redundant barrier layer is a GaN intrinsic layer.

12. The epitaxial wafer as described in claim 5, characterized in that, The thickness of the redundant barrier layer is equal to the thickness of the first barrier layer.

13. The epitaxial wafer as described in any one of claims 1 to 4, characterized in that, The second barrier layer is located between the second well layer and the N-type doped layer in the same transition stack.

14. The epitaxial wafer as described in claim 13, characterized in that, The second well layer is an In x Ga 1-x N layer, where 0 < x ≤ 0.3; the second barrier layer is an N-type doped Al y Ga 1-y N layer, where 0 ≤ y ≤ 0.

2.

15. The epitaxial wafer as described in claim 14, characterized in that, The proportion of Al component in the second barrier layer on the side away from the N-type doped layer is greater than the proportion of Al component in the second barrier layer on the side closer to the N-type doped layer.

16. The epitaxial wafer as described in claim 15, characterized in that, Along the direction away from the N-type doped layer, the proportion of Al component in the second barrier layer gradually increases; or, Along the direction away from the N-type doped layer, the proportion of Al component in the second barrier layer increases layer by layer.

17. The epitaxial wafer as described in claim 13, characterized in that, The thickness of the second well layer ranges from 2.0 nm to 4.0 nm, and the thickness of the second barrier layer ranges from 7.0 nm to 12.0 nm.

18. The epitaxial wafer as described in claim 13, characterized in that, The transition substructure has 3 to 5 of the aforementioned transition layers.

19. The epitaxial wafer as claimed in claim 1, characterized in that, The P-type doped structure includes a P-type layer and a multi-period doped layer, wherein the multi-period doped layer is located between the P-type layer and the functional well structure.

20. The epitaxial wafer as described in claim 19, characterized in that, The multi-period doped layer includes multiple doped stacks, each doped stack including a ternary doped layer and a binary doped layer, wherein the ternary doped layer is located between the binary doped layer and the functional well structure within the same doped stack.

21. The epitaxial wafer as described in claim 19, characterized in that, The concentration of P-type dopant in the multi-period doped layer on the side farther from the N-type doped layer is greater than the concentration of P-type dopant in the multi-period doped layer on the side closer to the N-type doped layer.

22. The epitaxial wafer as described in claim 21, characterized in that, Along the direction away from the N-type doped layer, the concentration of P-type dopant in the multi-period doped layer increases periodically.

23. The epitaxial wafer as described in claim 22, characterized in that, In the same doped stack, the concentration of the P-type dopant is uniform; Alternatively, within the same doped stack, the concentration of the P-type dopant increases layer by layer along the direction away from the N-type doped layer; Alternatively, within the same doped stack, the concentration of the P-type dopant gradually increases along the direction away from the N-type doped layer.

24. The epitaxial wafer as described in claim 20, characterized in that, The ternary doped layer is a P-type doped InGaN layer, and the binary doped layer is a P-type doped GaN layer.

25. The epitaxial wafer as described in claim 24, characterized in that, The Ga content in the multi-period doped layer on the side away from the N-type doped layer is less than the Ga content in the multi-period doped layer on the side closer to the N-type doped layer; The In content of the InGaN layer in the multi-period doped layer on the side away from the N-type doped layer is greater than the In content of the InGaN layer in the multi-period doped layer on the side closer to the N-type doped layer.

26. The epitaxial wafer as described in claim 25, characterized in that, Along the direction away from the N-type doped layer, the Ga content in the multi-period doped layer decreases periodically, while the In content increases periodically.

27. The epitaxial wafer as described in claim 26, characterized in that, In the same doped stack, the Ga component content is uniform, and the In component content in the InGaN layer is uniform. Alternatively, within the same doped stack, the Ga content decreases layer by layer along the direction away from the N-type doped layer; Alternatively, within the same doped stack, the Ga content gradually decreases along the direction away from the N-type doped layer, while the In content gradually increases in the InGaN layer.

28. The epitaxial wafer as described in claim 20, characterized in that, The thickness of the doped stack ranges from 5 nm to 10 nm.

29. The epitaxial wafer as described in claim 20, characterized in that, The multi-period doped layer has at least five doped stacks.

30. The epitaxial wafer as described in claim 1, characterized in that, The concentration range of the P-type dopant in the P-type doped structure is 3 × 10⁻⁶. 18 atoms / cm 3 Up to 5×10 20 atoms / cm 3 .

31. The epitaxial wafer as described in claim 1, characterized in that, The N-type doped layer includes at least one of GaN, AlGaN, and AlInGaN layers.

32. The epitaxial wafer as described in claim 31, characterized in that, The concentration range of the N-type dopant in the N-type doped layer is 8 × 10⁻⁶. 18 atoms / cm 3 Up to 1×10 21 atoms / cm 3 .

33. The epitaxial wafer as described in claim 1, characterized in that, The functional trap structure also includes: a stress adjustment structure. The stress-regulating structure is located between the N-type doped layer and the transition substructure.

34. The epitaxial wafer as described in claim 33, characterized in that, The stress-adjusting structure includes multiple stress-adjusting stacks, each stress-adjusting stack including a third well layer and a third barrier layer, wherein the third barrier layer is located between the third well layer and the N-type doped layer of the same stress-adjusting stack.

35. The epitaxial wafer as described in claim 34, characterized in that, The third well layer is an In z Ga 1-z N layer, where 0 < z ≤ 0.1, and the third barrier layer is a GaN layer.

36. The epitaxial wafer as described in claim 34, characterized in that, The thickness of the third well layer ranges from 1.0 nm to 2.5 nm, and the thickness of the third barrier layer ranges from 2.0 nm to 4.0 nm.

37. The epitaxial wafer as described in claim 34, characterized in that, The stress-adjusting structure has at least nine stress-adjusting stacks.

38. The epitaxial wafer as described in claim 1, characterized in that, Also includes: Undoped layer, buffer layer, and substrate; The substrate is located on the side of the N-type doped layer away from the P-type doped structure; The buffer layer is located between the substrate and the N-type dopant; The undoped layer is located between the buffer layer and the N-type doped layer.

39. The epitaxial wafer as described in claim 38, characterized in that, The undoped layer is at least one of GaN, AlGaN, and AlInGaN layers.

40. The epitaxial wafer as described in claim 38, characterized in that, The buffer layer is at least one of AlN layer, GaN layer, AlGaN layer and AlInGaN layer.

41. The epitaxial wafer as described in claim 38, characterized in that, The thickness of the buffer layer ranges from 15 nm to 50 nm.

42. An epitaxial wafer, characterized in that, include: An N-type doped layer, a functional well structure, and a P-type doped structure are stacked sequentially. The functional well structure includes a light-emitting substructure, which includes a redundant barrier layer, which is an intrinsic layer; the redundant barrier layer is located between the N-type doped layer and the P-type doped structure.

43. The epitaxial wafer as described in claim 42, characterized in that, The light-emitting substructure further includes a multi-period light-emitting layer, which is located between the N-type doped layer and the redundant barrier layer.

44. The epitaxial wafer as described in claim 43, characterized in that, The P-type doped structure includes a P-type layer and a multi-period doped layer, wherein the multi-period doped layer is located between the P-type layer and the functional well structure.

45. The epitaxial wafer as described in claim 44, characterized in that, The functional trap structure also includes: a stress adjustment structure. The stress-modulating structure is located between the N-type doped layer and the luminescent substructure.

46. ​​The epitaxial wafer as described in claim 42, characterized in that, Also includes: Undoped layer, buffer layer, and substrate; The substrate is located on the side of the N-type doped layer away from the P-type doped structure; The buffer layer is located between the substrate and the N-type dopant; The undoped layer is located between the buffer layer and the N-type doped layer.

47. A display device, characterized in that, include: An epitaxial wafer, as described in any one of claims 1 to 46.

48. A method for preparing an epitaxial wafer, characterized in that, include: An N-type doped layer is formed on the substrate; A functional well structure is formed on the N-type doped layer, wherein the step of forming the functional well structure on the N-type doped layer includes: sequentially forming a transition substructure and a light-emitting substructure on the N-type doped layer; The transition substructure includes: a plurality of transition stacks, wherein the transition stacks include: a second barrier layer and a second well layer; A P-type doped structure is formed on the luminescent structure.

49. The method for preparing an epitaxial wafer as described in claim 48, characterized in that, The step of forming the light-emitting substructure includes: forming a multi-periodic light-emitting layer on the transition substructure.

50. The method for preparing an epitaxial wafer as described in claim 49, characterized in that, The step of forming the light-emitting substructure further includes forming a redundant barrier layer on the multi-period light-emitting layer.

51. The method for preparing an epitaxial wafer as described in claim 49, characterized in that, The step of forming a multi-period light-emitting layer includes: forming a light-emitting stack on the transition substructure, wherein the step of forming a light-emitting stack on the transition substructure includes: forming a first barrier layer; forming a first well layer on the side of the first barrier layer away from the N-type doped layer; In the step of forming a multi-period light-emitting layer, the step of forming a light-emitting stack on the transition substructure is performed multiple times to form a plurality of light-emitting stacks stacked along the line connecting the N-type doped layer and the P-type doped structure.

52. The method for preparing an epitaxial wafer as described in claim 48, characterized in that, The step of forming the transition substructure includes: forming a transition stack on the N-type doped layer, wherein the step of forming the transition stack on the N-type doped layer includes: forming a second barrier layer; forming a second well layer on the side of the second barrier layer away from the N-type doped layer; In the step of forming the transition substructure, the step of forming a transition stack on the N-type doped layer is performed multiple times to form a plurality of the transition stacks stacked along the line connecting the N-type doped layer and the P-type doped structure.

53. The method for preparing an epitaxial wafer as described in claim 52, characterized in that, The step of forming the second barrier layer includes: providing an Al source, a Ga source, and an N source to form the second barrier layer, wherein the second barrier layer is Al. y Ga 1-y N layers, where 0 <y≤0.2; During the repeated execution of the transition layer formation step, the Al source provided in the later execution of the transition layer formation step to form the second barrier layer is greater than the Al source provided in the earlier execution of the transition layer formation step to form the second barrier layer.

54. The method for preparing an epitaxial wafer as described in claim 53, characterized in that, The step of forming the second barrier layer includes: providing a Ga source and an N source to form the second barrier layer, wherein the second barrier layer is a GaN layer.

55. The method for preparing an epitaxial wafer as described in claim 53, characterized in that, During the repeated execution of the transition layer formation step, the amount of Al source provided during the formation of the second barrier layer in the transition layer formation step is increased successively; Alternatively, during the repeated execution of the transition layer formation step, the amount of Al source supplied during the formation of the second barrier layer in the transition layer formation step gradually increases.

56. The method for preparing an epitaxial wafer as described in claim 48, characterized in that, The step of forming the functional well structure further includes: forming a stress-modulating structure on the side of the N-type doped layer away from the substrate before the step of forming the transition substructure.

57. The method for preparing an epitaxial wafer as described in claim 56, characterized in that, The step of forming the stress-adjusting structure includes: forming a stress-adjusting stack on the side of the N-type doped layer away from the substrate; the step of forming the stress-adjusting stack on the side of the N-type doped layer away from the substrate includes: forming a third barrier layer; forming a third well layer on the side of the third barrier layer away from the substrate. In the step of forming the stress-adjusting structure, the step of forming a stress-adjusting stack on the side of the N-type doped layer away from the substrate is performed multiple times to form a plurality of stress-adjusting stacks stacked along the line connecting the N-type doped layer and the P-type doped structure.

58. The method for preparing an epitaxial wafer as described in claim 48, characterized in that, The step of forming a P-type doped structure includes: forming a multi-period doped layer on the side of the photonic structure away from the N-type doped layer; and forming a P-type layer on the side of the multi-period doped layer away from the N-type doped layer.

59. The method for preparing an epitaxial wafer as described in claim 58, characterized in that, The step of forming a multi-period doped layer includes: forming a doped stack, the step of forming a doped stack includes: forming a ternary doped layer; forming a binary doped layer on the side of the ternary doped layer away from the substrate; In the step of forming a multi-period doped layer, the step of forming a doped stack is performed multiple times to form a plurality of doped stacks stacked along the line connecting the N-type doped layer and the P-type doped structure.

60. The method for preparing an epitaxial wafer as described in claim 59, characterized in that, The step of forming the doped stack includes: providing a P-type doping source; During the repeated execution of the doped stack formation step, the amount of P-type dopant source provided in a later doped stack formation step is greater than the amount of P-type dopant source provided in an earlier doped stack formation step.

61. The method for preparing an epitaxial wafer as described in claim 60, characterized in that, During the repeated execution of the doped stack formation step, the amount of P-type dopant source provided by the doped stack formation step increases successively.

62. The method for preparing an epitaxial wafer as described in claim 61, characterized in that, During each step of forming the doped stack, the amount of P-type dopant provided remains stable. Alternatively, in each step of forming the doped stack, the amount of P-type dopant source provided in the step of forming the ternary doped layer is less than the amount of P-type dopant source provided in the step of forming the binary doped layer. Alternatively, in each step of forming the doped stack, the amount of P-type dopant provided gradually increases.

63. The method for preparing an epitaxial wafer as described in claim 59, characterized in that, In the step of forming the ternary doped layer, an In source, a Ga source, an N source and a P-type doped source are provided to form the ternary doped layer, wherein the ternary doped layer is a P-type doped InGaN layer. In the step of forming the binary doped layer, a Ga source, an N source, and a P-type doping source are provided to form the binary doped layer, which is a P-type doped GaN layer.

64. The method for preparing an epitaxial wafer as described in claim 63, characterized in that, During the repeated execution of the doped stack formation step, the amount of Ga source provided in the earlier doped stack formation step is greater than the amount of Ga source provided in the later doped stack formation step; the amount of In source provided in the earlier doped stack formation step in the step of forming the ternary doped layer is less than the amount of In source provided in the later doped stack formation step in the step of forming the ternary doped layer.

65. The method for preparing an epitaxial wafer as described in claim 64, characterized in that, In the repeated execution of the doped stack formation step, the amount of Ga source provided in the doped stack formation step decreases successively; in the repeated execution of the doped stack formation step, the amount of In source provided in the step of forming ternary doped layer 72a increases successively.

66. The method for preparing an epitaxial wafer as described in claim 65, characterized in that, During each execution of the doped stack formation step, the influx of the provided Ga source remains stable; during each execution of the step of forming the ternary doped layer in the doped stack formation step, the influx of the provided In source remains stable. Alternatively, in each step of forming the doped stack, the amount of Ga source provided in the step of forming the binary doped layer is less than the amount of Ga source provided in the step of forming the ternary doped layer. Alternatively, in each step of forming the doped stack, the amount of Ga source provided gradually decreases; and in each step of forming the ternary doped layer, the amount of In source provided gradually increases.

67. The method for preparing an epitaxial wafer as described in claim 59, characterized in that, In the step of forming a multi-period doped layer, the step of forming the doped stack is performed at least 5 times.

68. The method for preparing an epitaxial wafer as described in claim 48, characterized in that, Also includes: Prior to the step of forming the N-type doped layer, a buffer layer and an undoped layer are sequentially formed on the substrate.

69. The method for preparing an epitaxial wafer as described in claim 48, characterized in that, Also includes: Annealing is performed after the step of forming the P-type doped structure.

70. The method for preparing an epitaxial wafer as described in claim 69, characterized in that, In the annealing step, the annealing temperature is in the range of 500°C to 780°C, and the annealing time is in the range of 2 minutes to 10 minutes.

71. A method for preparing an epitaxial wafer, characterized in that, include: An N-type doped layer is formed on the substrate; A functional well structure is formed on the N-type doped layer. The step of forming the functional well structure on the N-type doped layer includes: forming a redundant barrier layer on the N-type doped layer, wherein the redundant barrier layer is an intrinsic layer. A P-type doped structure is formed on the redundant barrier layer.

72. The method for preparing an epitaxial wafer as described in claim 71, characterized in that, The step of forming a functional well structure on the N-type doped layer further includes: forming a multi-period light-emitting layer on the side of the N-type doped layer away from the substrate before the step of forming a redundant barrier layer.

73. The method for preparing an epitaxial wafer as described in claim 72, characterized in that, The step of forming the functional well structure further includes: forming a stress-modulating structure on the side of the N-type doped layer away from the substrate before forming the multi-period light-emitting layer.

74. The method for preparing an epitaxial wafer as described in claim 71, characterized in that, The step of forming a P-type doped structure includes: forming a multi-period doped layer on the side of the redundant barrier layer away from the N-type doped layer; and forming a P-type layer on the side of the multi-period doped layer away from the N-type doped layer.

75. The method for preparing an epitaxial wafer as described in claim 71, characterized in that, Also includes: Prior to the step of forming the N-type doped layer, a buffer layer and an undoped layer are sequentially formed on the substrate.

76. The method for preparing an epitaxial wafer as described in claim 71, characterized in that, Also includes: Annealing is performed after the step of forming the P-type doped structure.

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