Time interval measurement method, time-to-digital converter and fpga

Abstract

The application discloses a time interval measurement method, a time-to-digital converter and an FPGA. The method comprises the following steps: inputting a to-be-measured signal and a clock frequency signal into a carry chain description module and a coarse measurement module in the time-to-digital converter; processing the to-be-measured signal into signal data based on a tap delay line of the carry chain description module; processing the to-be-measured signal and the clock frequency signal based on the coarse measurement module, and outputting the number of reference clock periods in a time interval corresponding to the to-be-measured signal; processing the signal data based on an encoder data operation integration module to obtain an encoder data integration result; inputting the encoder data integration result and the number of reference clock periods into a coarse and fine measurement combination module to output a time interval value corresponding to the to-be-measured signal; and transmitting the time interval value corresponding to the to-be-measured signal to a target device based on a serial port transmission module. The application solves the technical problem that the time precision is not high due to the long dead time of the time-to-digital converter.

Description

Technical Field

[0001] This invention relates to the field of timing, and more specifically, to a time interval measurement method, a time-to-digital converter, and an FPGA. Background Technology

[0002] In many applications, high-precision digital conversion of time intervals is required. Different researchers have implemented various time interpolation methods on FPGAs to improve time resolution. The primary task of a time-to-digital converter (TDC) is to perform high-resolution measurements of the time delay between simultaneous events, while also requiring high throughput to handle the large number of measurements from parallel detector modules.

[0003] Traditional Time-Delay Measurement (TDC) techniques use tapped delay lines (TDL) for measurement. The length of the delay line is estimated by using carry propagation delay, thus obtaining resolution. However, a problem with this traditional approach is its long dead time, requiring two clock cycles to reset the delay line. This long dead time reduces the TDC measurement rate and accuracy, especially in applications requiring high-speed continuous measurements, potentially leading to data loss or inaccurate measurements.

[0004] There is currently no effective solution to the above problems. Summary of the Invention

[0005] This invention provides a time interval measurement method, a time-to-digital converter, and an FPGA to at least solve the technical problem of low time accuracy caused by excessively long dead time in the time-to-digital converter.

[0006] According to one aspect of the present invention, a time interval measurement method is provided, comprising: inputting a signal to be measured and a clock frequency signal into a carry chain description module and a coarse measurement module in a time-to-digital converter, wherein the clock frequency signal is provided by a programmable logic array, the signal to be measured is an analog signal, and the time-to-digital converter includes the carry chain description module, an encoder data processing and integration module, a coarse and fine measurement combination module, a coarse measurement module, a coarse and fine measurement combination module, and a serial port transmission module; processing the signal to be measured into signal data based on the tap delay lines of the carry chain description module, wherein the tap delay lines include multiple carry chains, each of which... The chain executes the start carry chain function and stop carry chain function respectively in different clock cycles; the encoder data processing and integration module processes the signal data to obtain the encoder data integration result; based on the coarse measurement module, the signal under test and the clock frequency signal are processed to output the number of reference clock cycles within the time interval corresponding to the signal under test, wherein the number of reference clock cycles is used to adjust the dynamic range of the measurement; the encoder data integration result is input into the coarse and fine measurement combination module to output the time interval value corresponding to the signal under test; based on the serial port transmission module, the time interval value corresponding to the signal under test is transmitted to the target device.

[0007] Optionally, if the carry chain description module further includes a dual-mode combination counter, the method further includes: switching the input stage of the tap delay line within adjacent clock cycles, such that the tap delay line receives different level signals from the dual-mode combination counter encoder in the adjacent clock cycles, wherein the level signals include high level and low level, and the dual-mode combination counter includes a first mode and a second mode; in the first mode, the high level output by the dual-mode combination counter indicates that the carry chain performs a start carry chain function, and the low level output by the dual-mode combination counter indicates that the carry chain performs a stop carry chain function; in the second mode, the low level output by the dual-mode combination counter indicates that the carry chain performs a start carry chain function, and the high level output by the dual-mode combination counter indicates that the carry chain performs a stop carry chain function; receiving the level signals from the dual-mode combination counter through the input stage of the tap delay line, and controlling the plurality of carry chains to perform a start carry chain function or a stop carry chain function according to the level signals.

[0008] Optionally, the method further includes: when each carry chain includes a main branch and a sub-branch, determining the output result difference corresponding to each carry chain, wherein the output result difference is the output result difference between the main branch and the sub-branch of the corresponding carry chain; determining the average value of the output result difference; and correcting the nonlinear error of the time-to-digital converter based on the average value.

[0009] Optionally, the method further includes: judging the output results of the echo channels in the multiple sets of redundant timing links included in the encoder data processing and integration module according to the calibration decision logic, wherein each set of multiple sets of redundant timing links includes a main wave channel and an even number of echo channels, half of the echo channels are located to the left of the corresponding main wave channel, and the other half of the echo channels are located to the right of the corresponding main wave channel. The calibration decision logic includes: judging the echo input gate of the echo channels in the multiple sets of redundant timing links, removing unreasonable timing values ​​outside the gate, and outputting the reasonable timing value corresponding to each set of redundant timing links according to the priority of the multiple sets of redundant timing links; wherein, if there are at least two reasonable timing values ​​in the output results of the echo channels of each set of redundant timing links, the reasonable timing value of that set of redundant timing links is output according to the preset echo channel priority.

[0010] Optionally, inputting the encoder data integration result and the number of reference clock cycles into the coarse and fine measurement combination module, and outputting the time interval value corresponding to the signal under test, includes: inputting the encoder data integration result into the fine measurement unit in the coarse and fine measurement combination module to obtain the fine measurement time interval value corresponding to the signal under test, wherein the fine measurement unit includes a delay chain composed of multiple cascaded CARRY4 units; the coarse and fine measurement combination module determines whether the time interval of the signal under test is greater than a preset time interval threshold based on the number of reference clock cycles; if the time interval of the signal under test is greater than the preset time interval threshold, outputting the number of reference clock cycles as the time interval value corresponding to the signal under test; if the time interval of the signal under test is less than or equal to the preset time interval threshold, outputting the fine measurement time interval value as the time interval value corresponding to the signal under test.

[0011] Optionally, the step of inputting the integrated encoder data result into the fine measurement unit in the coarse and fine measurement combination module to obtain the fine measurement time interval value corresponding to the signal under test includes: the fine measurement unit adopts segmented delay line technology to sample the state of the delay chain at a preset deviation time point at the rising edge of the stop signal to obtain the sampling result; analyzes the sampling result of the stop signal on the delay chain, calculates the time difference between the start signal and the stop signal, and obtains the fine measurement time interval value.

[0012] According to another aspect of the present invention, a time-to-digital converter is also provided, comprising: a carry chain description module for receiving a signal under test and a clock frequency signal, wherein the clock frequency signal is provided by a programmable logic array and the signal under test is an analog signal; the carry chain description module is further configured to process the signal under test into signal data based on tapped delay lines, wherein the tapped delay lines include multiple carry chains, each of the carry chains performing a start carry chain function and a stop carry chain function in different clock cycles; a coarse measurement module for receiving the signal under test and the clock frequency signal, and further configured to process the signal under test and the clock frequency signal, and output the number of reference clock cycles within the time interval corresponding to the signal under test, wherein the number of reference clock cycles is used to adjust the dynamic range of the measurement; an encoder data processing and integration module for processing the signal data to obtain an encoder data integration result; a coarse and fine measurement combination module for receiving the encoder data integration result and the number of reference clock cycles, and outputting the time interval value corresponding to the signal under test; and a serial port transmission module for transmitting the time interval value corresponding to the signal under test to a target device.

[0013] According to another aspect of the present invention, a field-programmable gate array (FPGA) is also provided, the FPGA including the above-described time-to-digital converter.

[0014] According to another aspect of the present invention, a non-volatile storage medium is also provided, the non-volatile storage medium including a stored program, wherein, when the program is executed, the device where the non-volatile storage medium is located is controlled to perform any of the above-described time interval measurement methods.

[0015] According to another aspect of the present invention, a computer device is also provided, the computer device including a memory and a processor, the memory being used to store a program, and the processor being used to run the program stored in the memory, wherein the program, when running, executes any of the time interval measurement methods described above.

[0016] According to another aspect of the present invention, a computer program product is also provided, comprising a computer program, characterized in that, when the computer program is executed by a processor, it implements the steps of any of the above-described time interval measurement methods.

[0017] In this embodiment of the invention, the start carry chain and stop carry chain are combined into one function in the carry chain description module. Each carry chain is controlled to alternately perform the start carry chain function and the end carry chain function in different clock cycles. This achieves the goal of reducing the dead time of the time-to-digital converter to one clock cycle, thereby improving the measurement efficiency of the time-to-digital converter and solving the technical problem of low time accuracy caused by excessive dead time of the time-to-digital converter. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0019] Figure 1 This is a flowchart illustrating the time interval measurement method provided according to an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the structure of a time-to-digital converter provided according to an optional embodiment of the present invention;

[0021] Figure 3 This is a diagram showing the rising edge differential nonlinearity result of a time-to-digital converter according to an optional embodiment of the present invention;

[0022] Figure 4 This is a diagram showing the falling edge differential nonlinearity result of a time-to-digital converter according to an optional embodiment of the present invention;

[0023] Figure 5 This is a graph showing the rising edge integration nonlinearity result of a time-to-digital converter according to an optional embodiment of the present invention;

[0024] Figure 6 This is a diagram showing the falling edge integration nonlinearity result of a time-to-digital converter according to an optional embodiment of the present invention;

[0025] Figure 7 This is a time-to-digital converter code density test diagram provided according to an optional embodiment of the present invention;

[0026] Figure 8 This is a structural block diagram of a time-to-digital converter provided according to an embodiment of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows:

[0030] FPGA, or Field Programmable Gate Array, also known as Programmable Logic Gate Array, is a type of semi-custom circuit within Application-Specific Integrated Circuits (ASICs). It effectively solves the problem of not being able to upgrade or modify the logic function after the device is manufactured. The basic structure of an FPGA includes programmable input / output units, configurable logic blocks, a digital clock management module, embedded block RAM, routing resources, embedded dedicated hard cores, and low-level embedded functional units. FPGA chips offer abundant logic resources, are reprogrammable, and have a fast time-to-market, making them widely used in numerous market sectors.

[0031] A Time-to-Digital Converter (TDC) in FPGA is a time-to-digital converter implemented using an FPGA. It is a key component for measuring time intervals or delays. The basic principle of a TDC is to measure time based on the edges (rising or falling edges) of the input signal. It typically consists of two main parts: a time measurement unit and a counter unit. The time measurement unit is responsible for measuring the time interval of the signal. When an edge of the input signal arrives, the time measurement unit records the current counter value and resets the counter for the next measurement. By measuring the difference in counter values ​​between different edges, the corresponding time interval can be obtained. The counter unit is used to record the counter value of the time measurement unit. It is typically implemented using a programmable counter in the FPGA. The counter unit increments the counter value according to the clock signal and resets when the time measurement unit is triggered.

[0032] CARRY4 is a commonly used logic unit in FPGAs, used to implement functions such as adders and accumulators. It is a 4-bit carry logic unit used to handle carry operations of 4-bit binary numbers. Its main function is to perform carry propagation in binary addition. It receives two input signals, A and B, representing the corresponding bits of the two 4-bit binary numbers to be added. Additionally, it receives one input signal, Cin, representing the carry input. The Cin signal can typically be the carry output from the previous bit or an external carry signal. By performing logical operations on the three input signals A, B, and Cin, two output signals, Sum and Cout, are generated. Sum represents the corresponding bit of the addition result, and Cout represents the carry output. CARRY4 can perform continuous addition of multi-bit binary numbers; by cascading multiple CARRY4 units, adders with larger bit sizes can be implemented.

[0033] The CARRY4's internal structure includes basic logic elements such as logic gates and flip-flops. It employs a cascaded logic gate structure to implement carry-pass functionality. Specifically, CARRY4 contains four CARRY cells, each corresponding to one bit of a four-bit binary number. Each CARRY cell contains logic gates and flip-flops. Regarding logic gates, CARRY4 uses multiple XOR, AND, and OR gates to implement carry-pass logic. The flip-flops are used to store the carry output and pass it to the next CARRY4 cell. CARRY4's advantages lie in its high-speed performance and resource efficiency. It can operate at a high clock frequency and consumes relatively few resources in an FPGA. This makes CARRY4 an ideal choice for implementing functions such as adders and accumulators.

[0034] Delay lines: In TDC, delay lines are used to generate a series of time intervals that can be used to measure the time of an input signal. Typically, they consist of a series of logic gates or flip-flops to achieve small, uniform delays.

[0035] Tapped delay lines (TDLs) are a special type of delay line that uses multiple taps to allow signals to be retrieved from different taps after a delay, resulting in multiple signal copies with different delay times. TDLs are commonly used in applications such as multipath channel modeling, signal processing, and timing adjustments.

[0036] Carry chain: A carry chain is a series of counters connected together, each with its own maximum value. When one counter reaches its maximum value, it sends a signal to tell the next counter to start counting. This design allows us to extend the range of the counters, enabling them to record longer periods. When the last counter reaches its maximum value, we know that a long time interval has been measured. The advantage of a carry chain is not only that it extends the measurement range but also that it maintains high measurement accuracy.

[0037] Dead time: This is the time required for a TDC system to complete a conversion and prepare for a new measurement, defining the measurement rate at which the TDC can operate. Low dead time design is crucial in modern measurement.

[0038] Bubble errors: These are errors that can occur in digital logic circuits (such as counters), where some logic states may be skipped or repeated incorrectly. These errors can be caused by timing problems or design flaws.

[0039] Linearity: Linearity refers to the degree to which the TDC output is proportional to the time interval between the input and output. High linearity means that the output more accurately reflects the input.

[0040] Carry chain: This typically refers to the mechanism in adder or counter circuits where the output of one cell carries over to the next. It is similar to a carry chain, but is commonly used for digital addition and counting.

[0041] Differential nonlinearity (DNL) and integral nonlinearity (INL): DNL refers to the difference between the actual and ideal differences between two adjacent measurements of a TDC. INL refers to the cumulative deviation between the actual and ideal outputs of a TDC. These two parameters are important indicators for measuring the accuracy of a TDC.

[0042] LSB width: LSB (Least Significant Bit) width refers to the minimum resolution of TDC, that is, the minimum measurable time interval.

[0043] Bin: In the context of TDC, a bin typically refers to a unit of measurement or interval of time. Each bin represents a certain amount of time difference.

[0044] Slice Resources: In FPGAs, a slice refers to a set of configurable logic resources. When designing a TDC (Transformer Controlled Dataset), it is necessary to consider how to effectively use these resources.

[0045] External EEPROM: An external EEPROM is a non-volatile memory used to retain data when the power is off. In FPGA applications, it can be used to store configuration data or other important information.

[0046] State Machine: A state machine is a crucial design element used to control logic flow and decision-making. In FPGAs, state machines are typically implemented using hardware description languages ​​(such as VHDL or Verilog). There are two main types of state machines: Moore and Mealy (Moore state machine: output depends only on the current state; Mealy state machine: output depends on both the current state and inputs). States: A state machine contains a series of predefined states, each corresponding to a specific point in the logic flow. Transitions: Transitions between states are based on a set of inputs or internal conditions. Outputs: A state machine generates an output based on the current state (and, in a Mealy state machine, the inputs).

[0047] Code density: The ratio of the number of output codewords of a Time Domain Controller (TDC) to the measured time range. Code density describes the temporal resolution that a TDC can provide within a given time range. A higher code density means that the TDC can provide higher temporal resolution because it can subdivide the time range into smaller time intervals and generate more output codewords. Conversely, a lower code density means that the TDC has lower temporal resolution because it divides the time range into larger time intervals and generates fewer output codewords.

[0048] Combinational logic is a fundamental type of digital circuit. Its characteristic is that at any given moment, the output depends only on the current input value, and not on previous inputs or states. This distinguishes it from another type of digital circuit—sequential logic—whose output depends not only on the current input but also on historical inputs or internal states.

[0049] According to an embodiment of the present invention, an embodiment of a time interval measurement method is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0050] The method embodiments provided in this application can be executed in a programmable logic array or similar computing device. It should be noted that the aforementioned computing device is generally referred to herein as a "data processing circuit." This data processing circuit can be wholly or partially embodied in software, hardware, firmware, or any other combination thereof. Furthermore, the data processing circuit can be a single, independent processing module, or wholly or partially integrated into any other element in the programmable logic array. As involved in the embodiments of this application, the data processing circuit acts as a processor control.

[0051] This invention aims to propose an efficient FPGA-based TDC design and implementation method. The design employs a dual-mode tapped delay line (TDL) to propagate rising and falling edges during alternating measurement cycles, thereby reducing the dead time to one system clock cycle.

[0052] Figure 1 This is a flowchart illustrating a time interval measurement method provided according to an embodiment of the present invention. This method can be applied to, for example... Figure 2 The time-to-digital converter (TDC) shown is used in this example. Figure 2 In this context, RX represents the input of the TDC, TX represents the output of the TDC, carrychain_128bit represents the carry chain description module, priority_encoder_128 represents the encoder data processing and integration module, pulse_filter_pxnx represents the coarse and fine measurement combination module, course_counter represents the coarse measurement module, and uart_send_block represents the serial port transmission module. Figure 2 The TDC shown, Figure 1 The time interval measurement method shown may include the following steps:

[0053] Step S101: Input the signal to be tested and the clock frequency signal into the carry chain description module and the coarse measurement module of the time-to-digital converter. The clock frequency signal is provided by a programmable logic array, the signal to be tested is an analog signal, and the time-to-digital converter includes a carry chain description module, an encoder data processing and integration module, a coarse measurement module, a coarse and fine measurement combination module, and a serial port transmission module.

[0054] Step S102: Based on the tap delay line of the carry chain description module, the signal under test is processed into signal data. The tap delay line includes multiple carry chains, and each carry chain executes the start carry chain function and stop carry chain function in different clock cycles.

[0055] Optionally, the carry chain description module may include 64 carry chains to process the signal under test into 128-bit wide signal data. Each carry chain is both a start carry chain and a stop carry chain, combining the functions of the start carry chain and the stop carry chain into one carry chain for estimating the length of the delay line. The purpose of this architecture is to reduce the dead time of the TDC, so that the tap delay line can propagate different signals in different measurement cycles without resetting.

[0056] As an optional embodiment, the dual-mode tapped delay line architecture may also include a dual-mode combination counter to eliminate bubbles that may occur during propagation and to encode 1s and 0s. The combination counter features low resource consumption and adaptability to different operating modes, achieving resource savings and fast measurement. In this case, step S102 may further include the following steps: During adjacent clock cycles, the input stage of the tap delay line is switched, so that the tap delay line receives different level signals from the dual-mode combined counter encoder during adjacent clock cycles, wherein the level signals include high level and low level, and the dual-mode combined counter includes a first mode and a second mode; in the first mode, the high level output of the dual-mode combined counter indicates that the carry chain performs the start carry chain function, and the low level output of the dual-mode combined counter indicates that the carry chain performs the stop carry chain function; in the second mode, the low level output of the dual-mode combined counter indicates that the carry chain performs the start carry chain function, and the high level output of the dual-mode combined counter indicates that the carry chain performs the stop carry chain function; the level signals are received from the dual-mode combined counter through the input stage of the tap delay line, and multiple carry chains are controlled to perform the start carry chain function or the stop carry chain function according to the level signals.

[0057] In this optional embodiment, the first mode and the second mode are merely general names for modes and do not imply a sequential execution order or causal relationship between the two modes. The difference between the first mode and the second mode lies in the relationship between the level type and the carry chain function. In different modes, the same level emitted by the dual-mode combined counter will instruct the carry chain in the tap delay line to perform different functions. In one optional embodiment, the dual-mode combined counter can be in different modes at different times. When the counter is in the first mode, a high level emitted by the counter can instruct the carry chain to perform the "start carry chain function," and a low level emitted by the counter can instruct the carry chain to perform the "stop carry chain function." When the counter is in the second mode, a low level emitted by the counter can instruct the carry chain to perform the "start carry chain function," and a high level emitted by the counter can instruct the carry chain to perform the "stop carry chain function." In other optional embodiments, the names "first mode" and "second mode" can be interchanged.

[0058] In this configuration, a high level represents 1 and a low level represents 0. Based on the aforementioned optional embodiment, a mechanism for alternating propagation of 1s and 0s is introduced into the dual-mode tapped delay line architecture. In one clock cycle, the tapped delay line propagates a 1, while in the next cycle, it propagates a 0. This reduces the dead time of the TDC to one system clock cycle. By switching the input stage, the TDL can propagate different signals in different measurement cycles without requiring a reset.

[0059] As an optional embodiment, sub-branches can be used to correct the nonlinearity error of the time-to-digital converter (TDC). In cases where each carry chain includes a main branch and sub-branches, the output difference corresponding to each carry chain is determined, where the output difference is the difference between the main branch and sub-branch of the corresponding carry chain; the average value of the output difference is determined; and the nonlinearity error of the time-to-digital converter is corrected based on the average value.

[0060] The key to this optional embodiment is embedding multiple sub-branches within the carry chain and comparing and averaging the outputs of the sub-branches with those of the main branch. By integrating the output data from multiple sub-branches, the nonlinear error of the main branch is reduced. These sub-branches are essentially smaller carry chains, with delay times slightly different from those of the main branch.

[0061] In this specific implementation, each carry chain embeds a sub-branch, whose output is compared with the output of the corresponding main branch. This comparison and averaging is achieved using a digital comparator and an accumulator. The digital comparator compares the output differences between the sub-branch and the main branch, while the accumulator accumulates the output differences of all sub-branch outputs and calculates their average. This method utilizes the outputs of the sub-branches to correct the nonlinearity error of the main branch. Since the delay times of each sub-branch vary slightly, their outputs will also differ. Through comparison and averaging, these differences can be eliminated, thereby reducing the nonlinearity error of the main branch and improving linearity performance. Furthermore, by performing timing tests on the branch delay lines, the delay time of each branch delay line can be determined, which can then be used to calibrate the nonlinearity error of the TDC.

[0062] like Figure 3 The figure shown is a graph of the differential nonlinearity results on the rising edge of TDC. Figure 4 The graph shows the differential nonlinearity results of the TDC falling edge. The vertical axis represents LSB (the least significant bit of the TDC output), and the horizontal axis represents bin (different values ​​or ranges of the input signal). When observing the trend of the nonlinearity graph, pay attention to how LSB changes with bin. For example, LSB tends to stabilize around bin = 20; around bin = 40; and around bin = 60. If the nonlinearity is small, meaning the relationship between the TDC output and the input signal is relatively linear, then LSB may maintain a relatively stable value at different bins, indicating that the measurement accuracy of the TDC remains consistent.

[0063] If the nonlinearity is significant, meaning the relationship between the TDC's output and the input signal is highly nonlinear, then the LSB may vary considerably across different bins. This implies that the TDC's measurement accuracy will vary significantly across different input signal values. Therefore... Figure 3 and Figure 4 The LSB remains relatively stable across different bins, indicating that the nonlinearity is stable.

[0064] Figure 5 and Figure 6The graph illustrates the integral nonlinearity of the TDC on both the rising and falling edges. The horizontal axis represents the range of input signal variation, and the vertical axis represents the TDC output value under the corresponding input signal. By observing the integral nonlinearity graph, one can understand the TDC's response characteristics under different input signals. Nonlinearity manifests as the shape or degree of deviation of the curve in the graph. If the TDC has good linear response characteristics, its output value will change in an approximately linear manner within the range of input signal variation. This means that when plotting the integral nonlinearity graph, one can see a curve that approaches a straight line. If the TDC exhibits nonlinear response characteristics, its output value may not change linearly within the range of input signal variation. This may result in the integral nonlinearity graph appearing as a curve, possibly convex or concave. The shape and degree of deviation of the curve depend on the TDC's degree of nonlinearity.

[0065] Step S103: The signal data is processed by the encoder data processing and integration module to obtain the encoder data integration result. The encoder data processing and integration module can reduce the amount of data, thus performing a "compression" function on the data.

[0066] As an optional embodiment, for the encoder data processing and integration module, this method may further include the following steps: According to the calibration decision logic, the output results of the echo channels in the multiple sets of redundant timing links included in the encoder data processing and integration module are judged. Each set of multiple redundant timing links includes one main wave channel and an even number of echo channels. Half of the even number of echo channels are located to the left of the corresponding main wave channel, and the other half are located to the right of the corresponding main wave channel. The calibration decision logic includes: performing echo input gate judgment on the echo channels in the multiple sets of redundant timing links, removing unreasonable timing values ​​outside the gate, and outputting the reasonable timing value corresponding to each set of redundant timing links according to the priority of the multiple sets of redundant timing links; wherein, if there are at least two reasonable timing values ​​in the output results of the echo channels of each set of redundant timing links, the reasonable timing value of that set of redundant timing links is output according to the preset echo channel priority.

[0067] To ensure timing accuracy, path delays must be fully considered. Inherent trace delay calibration is required for each group with inconsistent delays. This necessitates careful layout and routing design to minimize delay differences and ensure accurate and consistent measurement results. In this optional embodiment, the encoder data processing and integration module priority_encoder_128 can use tri-modal redundancy logic, including three redundant timing links: GroupA, GroupB, and GroupC. Each redundant timing link contains one main wave channel and eight echo channels. The main wave channel is located in the middle of the nine channels, with the other eight echo channels located to the left and right of the main wave channel, respectively. Each redundant timing link can use a dedicated counter to measure delays. When the main wave arrives, the counter is reset and restarted. To reduce the transmission delay of the counter results, two relay registers (CounterA and CounterB) are configured in the data processing and integration module priority_encoder_128, enabling the counter to operate at a 200MHz clock frequency.

[0068] Due to inherent delay biases introduced by layout and routing, the results of the three redundant timing links (Group A, Group B, and Group C) for the same echo channel exhibit a fixed deviation. To calibrate and correct these deviations, an external EEPROM can be used to perform calibration decision output on the measurement results of the redundant timing links for the three channels, achieving channel uniformity calibration accuracy better than 30 ps. The decision logic first performs echo input gate interpretation (based on a preset priority) and removes unreasonable timing results outside the gate (i.e., the aforementioned unreasonable test values; test results outside the preset time window are judged as unreasonable).

[0069] In an optional embodiment, the encoder data processing and integration module may include two sets of redundant timing links, denoted as the first set of links and the second set of links, respectively. The first set of links includes channel A with a corresponding timing value of 'a', and channel B with a corresponding timing value of 'b'. The second set of links includes channel C with a corresponding timing value of 'c', and channel D with a corresponding timing value of 'd'. In this case, the echo channel output results can be interpreted as follows:

[0070] In the first group of links, determine whether the timing value 'a' of channel A and the timing value 'b' of channel B are reasonable. If both 'a' and 'b' are reasonable, then according to the preset rule that channel A takes precedence over channel B, output the order and values ​​of the reasonable timing values ​​corresponding to the first group of links as 'a' and 'b'.

[0071] In the second group of links, determine whether the timing value c of channel C is reasonable and whether the timing value d of channel D is reasonable. If both c and d are reasonable, then according to the preset rule that channel C takes precedence over D, output the order and values ​​of the reasonable timing values ​​corresponding to the second group of links as c, d.

[0072] Based on the above interpretation, and according to the preset link priority interpretation rule that the priority of the first group of links is higher than that of the second group of links, the order and value of the reasonable timing values ​​corresponding to the two groups of links are output as a, b, c, d.

[0073] Optionally, in the encoder data integration module, binary search and interpolation search techniques can also be used to determine the target time. Binary search is a divide-and-conquer algorithm that gradually narrows the search range by dividing the search area into two parts and determining whether the target element is located on the left or right. In the encoder data processing and integration module `priority_encoder_128`, the time interval can be divided into a series of intervals, and binary search can be used to determine which interval the target time falls into. First, the upper and lower bounds of the intervals are initialized. Initially, the upper bound is the maximum time interval, and the lower bound is the minimum time interval. The middle position is calculated, which is the average of the upper and lower bounds. The set target time is compared with the value of the middle position. If the target time is less than the middle position, the upper bound is updated to the middle position; if the set target time is greater than the middle position, the lower bound is updated to the middle position. This process is repeated until the interval encoding containing the target time is found and temporarily stored in a FIFO.

[0074] Meanwhile, interpolation lookup techniques can also be used in the encoder data integration module. First, the data points used for interpolation lookup are determined. These data points can be pre-measured or calculated, or acquired through sampling and measurement. The data points should be dense enough to allow for accurate interpolation near the target time. Once the data points are determined, an interpolation algorithm can be used to estimate the value at the target time. For example, the interpolation algorithm can be linear interpolation. First, relevant time data needs to be collected (e.g., data u1 is collected at time t1, and data u2 is collected at time t2). This typically involves recording the precise moments when time events occur. Then, a linear interpolation algorithm is used to process this data. If two time points (e.g., t1, t2) and their corresponding values ​​(e.g., v1, v2) are known, V = V1 + ((V2 - V1)) / ((t2 - t1)) * (t - t1) can be used to estimate the value of any time point t between t1 and t2. Implementing interpolation lookup in an FPGA can be achieved using hardware modules for computation. These hardware modules can be designed according to the requirements of the interpolation algorithm, including the storage of data points and the logic circuitry for calculating the interpolation.

[0075] Once the interpolation calculation is completed and the target time interval is determined, the encoding and interpolation results for that interval can be combined using combinational logic to produce a single output as the encoder data integration result, which is then transmitted to the coarse and fine measurement integration module. The encoding can use binary, Gray code, or other suitable encoding methods.

[0076] Step S104: Based on the coarse measurement module, the signal to be measured and the clock frequency signal are processed, and the number of reference clock cycles within the time interval corresponding to the signal to be measured is output. The number of reference clock cycles is used to adjust the dynamic range of the measurement.

[0077] The coarse measurement module course_counter can use a lower frequency clock (such as a reference frequency signal provided by the FPGA) to calculate the number of reference clock cycles within the time interval to be measured, which is used to adjust the dynamic range of the measurement.

[0078] Step S105: Input the encoder data integration result and the number of reference clock cycles into the coarse and fine measurement combination module, and output the time interval value corresponding to the signal under test. The coarse and fine measurement combination module can output either the coarse measurement result or the fine measurement result as the final output of the TDC.

[0079] As an optional embodiment, the encoder data integration result and the number of reference clock cycles are input into the coarse and fine measurement combination module, and the time interval value corresponding to the signal under test is output. This includes the following steps: inputting the encoder data integration result into the fine measurement unit in the coarse and fine measurement combination module to obtain the fine measurement time interval corresponding to the signal under test, wherein the fine measurement unit includes a delay chain composed of multiple cascaded CARRY4 units; the coarse and fine measurement combination module determines whether the time interval of the signal under test is greater than a preset time interval threshold based on the number of reference clock cycles; if the time interval of the signal under test is greater than the preset time interval threshold, the number of reference clock cycles is output as the time interval value corresponding to the signal under test; if the time interval of the signal under test is less than or equal to the preset time interval threshold, the fine measurement time interval value is output as the time interval value corresponding to the signal under test.

[0080] The combination of coarse and fine measurements can be achieved through the following methods: dynamic switching between the two modes, using coarse measurement mode for longer time intervals and switching to fine measurement mode for shorter time intervals; ensuring that the coarse measurement counter and the fine measurement counter maintain consistency in the time coordination of the delay chain by using the clock delay principle of the counter; and using two independent state machines to process positive and negative input signals, thereby fusing the data and achieving accurate time measurement.

[0081] As an optional embodiment, the encoder data integration result is input into the fine measurement unit in the coarse and fine measurement combination module to obtain the fine measurement time interval value corresponding to the signal under test. This includes: the fine measurement unit uses segmented delay line technology to sample the state of the delay chain at a preset deviation time point at the rising edge of the stop signal to obtain the sampling result; the sampling result of the stop signal on the delay chain is analyzed to calculate the time difference between the start signal and the stop signal to obtain the fine measurement time interval value.

[0082] When the start and stop signals propagate through the Carrychain_128bit description module and the coarse / fine measurement combination module pulse_filter_pxnx (for example, when Carrychain_128bit is about to output data, it will queue and transmit it to priority_encoder_128 in bytes, and after priority_encoder_128 has completed data processing, it will then transmit the data to pulse_filter_pxnx), a clock signal can be used as the stop signal to ensure the consistency of the width of each interval of fine time measurement, thereby reducing nonlinear errors. Because the clock signal has high uniformity of distribution on the clock distribution network and minimal deviation, it can effectively maintain the width consistency of each measurement interval. The code density test diagram is shown below. Figure 7 As shown, the horizontal axis represents the time interval (or counting interval), and the vertical axis represents the number of times the corresponding time interval (or counting interval) occurs. By observing the code density graph, the code density distribution of the FPGA TDC can be understood. Dense areas indicate that the time interval (or counting interval) occurs more frequently, while sparse areas indicate that it occurs less frequently.

[0083] Step S106: Transmit the time interval value corresponding to the signal under test to the target device. This step can be implemented by the serial port transmission module in the time-to-digital converter. The target device can be an application device, which can implement its own application functions based on the time interval value calculated by the time-to-digital converter.

[0084] In the above steps, the start carry chain and stop carry chain are combined into one function in the carry chain description module. Each carry chain is controlled to alternately perform the start carry chain function and the stop carry chain function in different clock cycles. This achieves the goal of reducing the dead time of the time-to-digital converter to one clock cycle, thereby improving the measurement efficiency of the time-to-digital converter and solving the technical problem of poor converter performance caused by excessive dead time.

[0085] Based on the above embodiments or optional embodiments, this application provides the following specific implementation methods: First, by Figure 2The tdc_test project receives an analog signal and a clock frequency signal clk_tdc. The clock frequency signal clk_tdc corresponds to the input clock frequency of the FPGA development board. The development board processes the signal according to the clock frequency. The signal enters the carry chain description module carrychain_128bit (containing 64 carry chains, each of which is both a start carry chain and a stop carry chain, totaling 128 bits) in the pulse_tdc_block data pulse interaction module. Through the cascading connection of multiple Carry4 units within it, the delay transmission and storage of Carry4 are realized according to the analog signal and the clock frequency signal, and the output result [127:0]chain_data is generated. The output result is encoded by the encoder data processing and integration module priority_encoder_128. The device performs calculations and integrates data. The output data encoded_data_n enters the coarse and fine measurement combination module pulse_filter_pxnx. Simultaneously or before this, the coarse measurement module course_counter converts the preset data bit width value into a coarse measurement data output value through a counter. coursecounter transmits the coarse and fine measurement combination module pulse_filter_pxnx to the coarse and fine measurement combination module. Then, the coarse and fine measurement combination module pulse_filter_pxnx performs fusion and outputs data_out and a data validity signal data_vaild. The data_out is stored in the FIFO (first-in, first-out data buffer) of the serial port transmission module uart_send_block. Finally, the serial port transmits the data_out data from the FIFO through the data validity signal data_vaild.

[0086] Based on the above specific implementation methods, the following technical effects can be achieved: High and low levels are propagated in the alternating measurement cycle within the TDC, thereby reducing the dead time of the TDC to one system clock cycle. The TDL sampling sequence for each operating mode is individually adjusted, and a low-resource dual-mode combined counter is used to eliminate bubble errors. Binary search encoding is employed in the encoder that converts thermometer codes to binary codes, thereby improving the linearity of the TDC, reducing storage space, and facilitating data processing. Time interpolation is performed using a dedicated carry chain, enabling more than three time measurements to be performed in a single carry chain; this design allows for stable picosecond-level resolution and accuracy. Multi-channel multiplexing is implemented, effectively reducing resource power consumption and enabling highly accurate time measurements. Through continuous measurement and calibration, the differential nonlinearity (DNL) and integral nonlinearity (INL) results are stable, ensuring the accuracy and stability of the beneficial effects of the above design.

[0087] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0088] Through the above description of the embodiments, those skilled in the art can clearly understand that the time interval measurement method according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, FIFO) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of the present invention.

[0089] According to embodiments of the present invention, a time-to-digital converter for implementing the above-described method is also provided. Figure 8 This is a structural block diagram of a time-to-digital converter provided according to an embodiment of the present invention, such as... Figure 8 As shown, the time-to-digital converter includes: a carry chain description module 81, a coarse measurement module 82, an encoder data processing and integration module 83, a coarse and fine measurement combination module 84, and a serial port transmission module 85. The time-to-digital converter will be described below.

[0090] The carry chain description module 81 is used to receive the signal under test and a clock frequency signal, wherein the clock frequency signal is provided by a programmable logic array and the signal under test is an analog signal; the carry chain description module is also used to process the signal under test into signal data based on a tapped delay line, wherein the tapped delay line includes multiple carry chains, and each carry chain executes a start carry chain function and a stop carry chain function in different clock cycles respectively;

[0091] The coarse measurement module 82 is used to receive the signal under test and the clock frequency signal, and is also used to process the signal under test and the clock frequency signal, and output the number of reference clock cycles within the time interval corresponding to the signal under test. The number of reference clock cycles is used to adjust the dynamic range of the measurement.

[0092] The encoder data processing and integration module 83 is used to process the signal data and obtain the encoder data integration result.

[0093] The coarse and fine measurement combination module 84 is used to receive the encoder data integration result and the number of reference clock cycles, and output the time interval value corresponding to the signal under test;

[0094] The serial port transmission module 85 is used to transmit the time interval value corresponding to the signal under test to the target device.

[0095] Embodiments of the present invention may provide a computer device. Optionally, in this embodiment, the computer device may be located in at least one of a plurality of network devices in a computer network. The computer device includes a memory and a processor.

[0096] The memory can be used to store software programs and modules, such as the program instructions / modules corresponding to the time interval measurement method and apparatus in this embodiment of the invention. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, thereby realizing the aforementioned time interval measurement method. The memory may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include memory remotely located relative to the processor, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0097] The processor can access information and application programs stored in memory via a transmission device to perform the following steps: Inputting the signal under test and the clock frequency signal into the carry chain description module and coarse measurement module of the time-to-digital converter, wherein the clock frequency signal is provided by a programmable logic array, the signal under test is an analog signal, and the time-to-digital converter includes a carry chain description module, an encoder data processing and integration module, a coarse and fine measurement combination module, a coarse measurement module, a coarse and fine measurement combination module, and a serial port transmission module; processing the signal under test into signal data based on the tap delay lines of the carry chain description module, wherein the tap delay lines include multiple carry... The system consists of several modules: a carry chain, where each carry chain executes the start carry chain function and the stop carry chain function within different clock cycles; an encoder data processing and integration module processes the signal data to obtain the encoder data integration result; a coarse measurement module processes the signal to be measured and the clock frequency signal, outputting the number of reference clock cycles within the time interval corresponding to the signal to be measured, where the number of reference clock cycles is used to adjust the dynamic range of the measurement; the encoder data integration result is input into the coarse and fine measurement combination module, which outputs the time interval value corresponding to the signal to be measured; and a serial port transmission module transmits the time interval value corresponding to the signal to be measured to the target device.

[0098] Optionally, the processor may also execute program code with the following steps: If the carry chain description module further includes a dual-mode combination counter, the method further includes: switching the input stage of the tap delay line within adjacent clock cycles, such that the tap delay line receives different level signals from the dual-mode combination counter encoder in adjacent clock cycles, wherein the level signals include high and low levels, and the dual-mode combination counter includes a first mode and a second mode; in the first mode, a high level output by the dual-mode combination counter indicates that the tap delay line performs the start carry chain function, and a low level output by the dual-mode combination counter indicates that the tap delay line performs the stop carry chain function; in the second mode, a low level output by the dual-mode combination counter indicates that the tap delay line performs the start carry chain function, and a high level output by the dual-mode combination counter indicates that the tap delay line performs the stop carry chain function; receiving level signals from the dual-mode combination counter through the input stage of the tap delay line, and controlling multiple carry chains to perform the start carry chain function or the stop carry chain function according to the level signals.

[0099] Optionally, the processor may also execute program code that performs the following steps: in the case that each carry chain includes a main branch and a sub-branch, determine the output result difference corresponding to each carry chain, wherein the output result difference is the output result difference between the main branch and the sub-branch of the corresponding carry chain; determine the average value of the output result difference; and correct the nonlinearity error of the time-to-digital converter based on the average value.

[0100] Optionally, the processor may also execute program code with the following steps: Based on the calibration decision logic, the output results of the echo channels in the multiple sets of redundant timing links included in the encoder data processing and integration module are interpreted. Each set of redundant timing links includes one main wave channel and an even number of echo channels. Half of the even number of echo channels are located to the left of the corresponding main wave channel, and the other half are located to the right of the corresponding main wave channel. The calibration decision logic includes: performing echo input gate interpretation on the echo channels in the multiple sets of redundant timing links, removing unreasonable timing values ​​outside the gate, and outputting the reasonable timing value corresponding to each set of redundant timing links according to the priority of the multiple sets of redundant timing links; wherein, if there are at least two reasonable timing values ​​in the output results of the echo channels of each set of redundant timing links, the reasonable timing value of that set of redundant timing links is output according to the preset echo channel priority.

[0101] Optionally, the processor may also execute program code with the following steps: inputting the encoder data integration result and the number of reference clock cycles into the coarse and fine measurement combination module, and outputting the time interval value corresponding to the signal under test, including: inputting the encoder data integration result into the fine measurement unit in the coarse and fine measurement combination module to obtain the fine measurement time interval value corresponding to the signal under test, wherein the fine measurement unit includes a delay chain composed of multiple cascaded CARRY4 units; the coarse and fine measurement combination module determines whether the time interval of the signal under test is greater than a preset time interval threshold based on the number of reference clock cycles; if the time interval of the signal under test is greater than the preset time interval threshold, the number of reference clock cycles is output as the time interval value corresponding to the signal under test; if the time interval of the signal under test is less than or equal to the preset time interval threshold, the fine measurement time interval value is output as the time interval value corresponding to the signal under test.

[0102] Optionally, the processor may also execute program code for the following steps: inputting the encoder data integration result into the fine measurement unit in the coarse and fine measurement combination module to obtain the fine measurement time interval value corresponding to the signal under test, including: the fine measurement unit adopts segmented delay line technology to sample the state of the delay chain at a preset offset time point at the rising edge of the stop signal to obtain the sampling result; analyzing the sampling result of the stop signal on the delay chain, calculating the time difference between the start signal and the stop signal, and obtaining the fine measurement time interval value.

[0103] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing the hardware related to the terminal device. The program can be stored in a non-volatile storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc.

[0104] Embodiments of the present invention also provide a non-volatile storage medium. Optionally, in this embodiment, the non-volatile storage medium can be used to store the program code executed by the time interval measurement method provided in the above embodiments.

[0105] Optionally, in this embodiment, the non-volatile storage medium may be located in any computer terminal in a group of computer terminals in a computer network, or in any mobile terminal in a group of mobile terminals.

[0106] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: inputting the signal under test and the clock frequency signal into the carry chain description module and the coarse measurement module of the time-to-digital converter, wherein the clock frequency signal is provided by a programmable logic array, the signal under test is an analog signal, and the time-to-digital converter includes a carry chain description module, an encoder data processing and integration module, a coarse and fine measurement combination module, a coarse measurement module, a coarse and fine measurement combination module, and a serial port transmission module; processing the signal under test into signal data based on the tap delay lines of the carry chain description module, wherein the tap delay lines include multiple... The carry chain executes the start and stop carry chain functions respectively within different clock cycles; the encoder data processing and integration module processes the signal data to obtain the encoder data integration result; the coarse measurement module processes the signal to be measured and the clock frequency signal, and outputs the number of reference clock cycles within the time interval corresponding to the signal to be measured, where the number of reference clock cycles is used to adjust the dynamic range of the measurement; the encoder data integration result is input into the coarse and fine measurement combination module, which outputs the time interval value corresponding to the signal to be measured; and the serial port transmission module transmits the time interval value corresponding to the signal to be measured to the target device.

[0107] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: If the carry chain description module further includes a dual-mode combination counter, the method further includes: switching the input stage of the tap delay line within adjacent clock cycles, such that the tap delay line receives different level signals from the dual-mode combination counter encoder in adjacent clock cycles, wherein the level signals include high and low levels, and the dual-mode combination counter includes a first mode and a second mode; in the first mode, a high level output by the dual-mode combination counter indicates that the carry chain performs a start carry chain function, and a low level output by the dual-mode combination counter indicates that the carry chain performs a stop carry chain function; in the second mode, a low level output by the dual-mode combination counter indicates that the carry chain performs a start carry chain function, and a high level output by the dual-mode combination counter indicates that the carry chain performs a stop carry chain function; receiving level signals from the dual-mode combination counter through the input stage of the tap delay line, and controlling multiple carry chains to perform a start carry chain function or a stop carry chain function according to the level signals.

[0108] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: in the case that each carry chain includes a main branch and a sub-branch, determine the output result difference corresponding to each carry chain, the output result difference being the output result difference between the main branch and the sub-branch of the corresponding carry chain; determine the average value of the output result difference; and correct the nonlinear error of the time-to-digital converter based on the average value.

[0109] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: According to the calibration decision logic, the output results of the echo channels in the multiple sets of redundant timing links included in the encoder data processing and integration module are judged. Each set of multiple redundant timing links includes a main wave channel and an even number of echo channels. Half of the even number of echo channels are located to the left of the corresponding main wave channel, and the other half are located to the right of the corresponding main wave channel. The calibration decision logic includes: performing echo input gate judgment on the echo channels in the multiple sets of redundant timing links, removing unreasonable timing values ​​outside the gate, and outputting the reasonable timing value corresponding to each set of redundant timing links according to the priority of the multiple sets of redundant timing links; wherein, if there are at least two reasonable timing values ​​in the output results of the echo channels of each set of redundant timing links, the reasonable timing value of that set of redundant timing links is output according to the preset echo channel priority.

[0110] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: inputting the encoder data integration result and the number of reference clock cycles into the coarse and fine measurement combination module, and outputting the time interval value corresponding to the signal under test, including: inputting the encoder data integration result into the fine measurement unit in the coarse and fine measurement combination module to obtain the fine measurement time interval value corresponding to the signal under test, wherein the fine measurement unit includes a delay chain composed of multiple cascaded CARRY4 units; the coarse and fine measurement combination module determines whether the time interval of the signal under test is greater than a preset time interval threshold based on the number of reference clock cycles; if the time interval of the signal under test is greater than the preset time interval threshold, the number of reference clock cycles is output as the time interval value corresponding to the signal under test; if the time interval of the signal under test is less than or equal to the preset time interval threshold, the fine measurement time interval value is output as the time interval value corresponding to the signal under test.

[0111] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: inputting the encoder data integration result into the fine measurement unit in the coarse and fine measurement combination module to obtain the fine measurement time interval value corresponding to the signal under test, including: the fine measurement unit adopts segmented delay line technology to sample the state of the delay chain at a preset offset time point at the rising edge of the stop signal to obtain the sampling result; analyzing the sampling result of the stop signal on the delay chain, calculating the time difference between the start signal and the stop signal, and obtaining the fine measurement time interval value.

[0112] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0113] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0114] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between units or modules may be electrical or other forms.

[0115] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0116] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0117] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a non-volatile storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0118] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for measuring time intervals, characterized in that, include: The signal to be tested and the clock frequency signal are input into the carry chain description module and the coarse measurement module of the time-to-digital converter. The clock frequency signal is provided by a programmable logic array, and the signal to be tested is an analog signal. The time-to-digital converter includes the carry chain description module, the encoder data processing and integration module, the coarse measurement module, the coarse and fine measurement combination module, and the serial port transmission module. Based on the tap delay line of the carry chain description module, the signal under test is processed into signal data. The tap delay line includes multiple carry chains, and each carry chain executes the start carry chain function and stop carry chain function in different clock cycles. The encoder data processing and integration module processes the signal data to obtain the encoder data integration result. Based on the coarse measurement module, the signal under test and the clock frequency signal are processed to output the number of reference clock cycles within the time interval corresponding to the signal under test. The number of reference clock cycles is used to adjust the dynamic range of the measurement. The encoder data integration result and the number of reference clock cycles are input into the coarse and fine measurement combination module, and the time interval value corresponding to the signal under test is output. Based on the serial port transmission module, the time interval value corresponding to the signal under test is transmitted to the target device; If the carry chain description module further includes a dual-mode combination counter, the method further includes: Within adjacent clock cycles, the input stage of the tapped delay line is switched, such that the tapped delay line receives different level signals from the dual-mode combination counter in the adjacent clock cycles. The level signals include high and low levels. The dual-mode combination counter includes a first mode and a second mode. In the first mode, a high level output by the dual-mode combination counter indicates that the carry chain starts its carry chain function, and a low level output by the dual-mode combination counter indicates that the carry chain stops its carry chain function. In the second mode, a low level output by the dual-mode combination counter indicates that the carry chain starts its carry chain function, and a high level output by the dual-mode combination counter indicates that the carry chain stops its carry chain function. The input stage of the tap delay line receives the level signal from the dual-mode combination counter, and controls the multiple carry chains to perform the start carry chain function or the stop carry chain function according to the level signal.

2. The method according to claim 1, characterized in that, The method further includes: In the case that each carry chain includes a main branch and a sub-branch, the output result difference corresponding to each carry chain is determined, and the output result difference is the output result difference between the main branch and the sub-branch of the corresponding carry chain; Determine the average value of the differences in the output results; The nonlinear error of the time-to-digital converter is corrected based on the average value.

3. The method according to claim 1, characterized in that, The method further includes: According to the calibration decision logic, the output results of the echo channels in the multiple sets of redundant timing links included in the encoder data processing and integration module are interpreted. Each set of redundant timing links includes a main wave channel and an even number of echo channels. Half of the echo channels are located to the left of the corresponding main wave channel, and the other half are located to the right of the corresponding main wave channel. The calibration decision logic includes: performing echo input gate interpretation on the echo channels of the multiple sets of redundant timing links, removing unreasonable timing values ​​outside the gate, and outputting reasonable timing values ​​corresponding to each set of redundant timing links according to the priority of the multiple sets of redundant timing links; wherein, if there are at least two reasonable timing values ​​in the output results of the echo channels of each set of redundant timing links, the reasonable timing values ​​of that set of redundant timing links are output according to the preset echo channel priority.

4. The method according to claim 1, characterized in that, The encoder data integration result and the number of reference clock cycles are input into the coarse and fine measurement combination module, which outputs the time interval value corresponding to the signal under test, including: The encoder data integration result is input into the fine measurement unit in the coarse and fine measurement combination module to obtain the fine measurement time interval value corresponding to the signal under test. The fine measurement unit includes a delay chain composed of multiple CARRY4 units cascaded together. The coarse and fine measurement combination module determines whether the time interval of the signal under test is greater than a preset time interval threshold based on the number of reference clock cycles. If the time interval of the signal under test is greater than the preset time interval threshold, the number of reference clock cycles is output as the time interval value corresponding to the signal under test. If the time interval of the signal under test is less than or equal to the preset time interval threshold, the fine measurement time interval value is output as the time interval value corresponding to the signal under test.

5. The method according to claim 4, characterized in that, The step of inputting the integrated encoder data result into the fine measurement unit in the coarse and fine measurement combination module to obtain the fine measurement time interval value corresponding to the signal under test includes: The fine measurement unit uses segmented delay line technology to sample the state of the delay chain at a preset offset time point on the rising edge of the stop signal to obtain the sampling result; By analyzing the sampling results of the stop signal on the delay chain, the time difference between the start signal and the stop signal is calculated to obtain the fine measurement time interval value.

6. A time-to-digital converter, characterized in that, include: The carry chain description module is used to receive the signal under test and a clock frequency signal, wherein the clock frequency signal is provided by a programmable logic array and the signal under test is an analog signal; the carry chain description module is also used to process the signal under test into signal data based on a tapped delay line, wherein the tapped delay line includes multiple carry chains, and each carry chain executes a start carry chain function and a stop carry chain function in different clock cycles respectively; The coarse measurement module is used to receive the signal under test and the clock frequency signal, and to process the signal under test and the clock frequency signal, and output the number of reference clock cycles within the time interval corresponding to the signal under test. The number of reference clock cycles is used to adjust the dynamic range of the measurement. The encoder data processing and integration module is used to process the signal data and obtain the encoder data integration result; The coarse and fine measurement combination module is used to receive the encoder data integration result and the number of reference clock cycles, and output the time interval value corresponding to the signal under test; The serial port transmission module is used to transmit the time interval value corresponding to the signal under test to the target device; The carry chain description module further includes a dual-mode combination counter. Within adjacent clock cycles, the input stage of the tap delay line is switched, causing the tap delay line to receive different level signals from the dual-mode combination counter in each adjacent clock cycle. These level signals include high and low levels. The dual-mode combination counter includes a first mode and a second mode. In the first mode, a high level output by the dual-mode combination counter indicates that the carry chain is executing a start carry chain function, and a low level output by the dual-mode combination counter indicates that the carry chain is executing a stop carry chain function. In the second mode, a low level output by the dual-mode combination counter indicates that the carry chain is executing a start carry chain function, and a high level output by the dual-mode combination counter indicates that the carry chain is executing a stop carry chain function. The input stage of the tap delay line receives the level signal from the dual-mode combination counter, and controls the multiple carry chains to perform the start carry chain function or the stop carry chain function according to the level signal.

7. A field-programmable gate array, characterized in that, The field-programmable gate array includes the time-to-digital converter of claim 6.

8. A computer device, characterized in that, The computer device includes a memory and a processor, the memory being used to store a program, and the processor being used to run the program stored in the memory, wherein the program, when running, executes the time interval measurement method according to any one of claims 1 to 5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the time interval measurement method according to any one of claims 1 to 5.

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