A sigma-delta based chip temperature control system

Abstract

The application belongs to the field of integrated circuit technology design, and discloses a chip temperature control system based on sigma-delta, which comprises two current generators with opposite polarities and generates two currents with opposite polarities respectively. A selector selects the current generated by the current generator and then flows into an integrator. A quantizer is composed of a dynamic comparator, compares a reference voltage Vref with an integrator voltage, and the output of the quantizer is the input of the selector selection signal, thereby forming a negative feedback system. Meanwhile, the output of the quantizer controls an on-chip heating module, and only the linear relationship between the current generator and the heater needs to be controlled, which is equivalent to that the negative feedback system also acts on the heater, so that the precise control of the heater temperature can be realized. The application realizes higher temperature resolution and a larger temperature control range, has simple circuit structure, low power consumption, does not need a SoC outside the chip, has higher integration, and is more convenient and direct.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology design and relates to a chip temperature control system based on sigma-delta. Background Technology

[0002] The basic principle of biosensors is to use the interactions between biomolecules to specifically detect the presence and abundance of biomolecules such as deoxyribonucleic acid (DNA), proteins, toxins, and hormones.

[0003] Polymerase chain reaction (PCR) is a method for synthesizing and amplifying specific nucleic acid fragments in vitro, based on the semi-conservative replication mechanism of DNA. A standard PCR reaction involves three processes: high-temperature denaturation (95°C), complementary annealing (55°C), and extension polymerization (72°C). Therefore, the temperature control system not only needs to accurately generate these three specific reaction temperatures but also needs to be able to switch smoothly between them to meet the reaction conditions. Not only the accuracy and uniformity of temperature control in the PCR thermal cycling module, but also the heating and cooling rates, affect the stability of PCR experimental results. The heating and cooling rates of the thermal cycling module can alter the banding pattern of PCR products during condensation electrophoresis. Accurate and effective temperature control is the soul of the PCR reaction. Improving the accuracy of temperature control and the uniformity of internal temperature within the reaction module, ensuring that PCR reaction components are as close as possible to the set favorable temperature rather than deviating from it, can improve PCR amplification efficiency and reduce errors and non-specific reactions.

[0004] Traditional integrated thermal managers often use glass as the primary material for heaters, acquiring data via temperature sensors and feeding it back to a proportional-integral-derivative (PID) control system to regulate the reaction chamber temperature. However, this testing method requires numerous external controllers and temperature sensors, resulting in a complex, costly, and inconvenient system. We prefer to perform PCR reactions directly on-chip, making the design of a highly integrated, temperature-accurate, and automatically temperature-controlled on-chip heating system crucial. Summary of the Invention

[0005] To address the aforementioned technical problems in the existing technology, this invention proposes a chip temperature control system based on sigma-delta, the specific technical solution of which is as follows: A sigma-delta-based chip temperature control system includes a control system and a heating module. The control system includes a first current generator, a second current generator, a selector, an integrator, and a quantizer. The heating module includes a heater. The first and second current generators generate two currents of opposite polarity connected to the selector. The selector selects one of the currents to flow into the integrator. The integrator is composed of a large capacitor connected to one end of a quantizer composed of a dynamic comparator. The other end of the quantizer is connected to a reference voltage Vref. The output of the quantizer is fed back to the selector, forming a negative feedback sigma-delta modulator. This ensures that the voltage of the integrator always fluctuates near the reference voltage. Simultaneously, the output of the quantizer controls the heater. The bit stream generated by the quantizer not only ensures the stability of the sigma-delta modulator but also controls the temperature stability of the heater. The temperature of the heater is adjusted by changing the reference voltage Vref, and the temperature accuracy is adjusted by regulating the current magnitudes of the first and second current generators.

[0006] Furthermore, the +ΔQ1 of current generator one and the -ΔQ2 of current generator two consist of a PMOS charging circuit and an NMOS discharging circuit. The PMOS charging circuit and the NMOS discharging circuit include two IDACs, two buffers, an adder, a subtractor, and a current charging / discharging module. The IDACs are either P-type or N-type. The reference current of the IDAC is controlled by an external variable resistor. Adjusting the external resistor adjusts the values ​​of Vn and Vp, thereby controlling the charging / discharging current. The two IDACs are a P-IDAC1 and an N-IDAC. The P-IDAC1 outputs current I1, which is connected to ground in series with an external resistor R1 to generate Vp and Vn values. The N-IDAC inputs current I2, which is connected to the power supply in series with an external resistor R2 to generate Vn value. The P-IDAC1 and N-IDAC outputs are each connected to a buffer. The two buffers are connected to an adder and a subtractor, respectively. The adder and subtractor are connected to the current charging / discharging module. The buffers are used for isolation. The adder and subtractor are used to eliminate the threshold voltages of NMOS and PMOS, respectively. The current charging / discharging module selects charging or discharging via a selector.

[0007] Furthermore, the current charging and discharging module includes a discharging circuit and a charging circuit. The discharging circuit includes four NMOS transistors N0-N3 arranged in parallel, with a parallel ratio of 1:2:4:8. The magnitude of the discharge current, i.e., the power dissipation, is controlled proportionally by three switches S1, S2, and S3. Switch S0 is applied to the gate voltage. When switch S0 is on, the gate voltage drives the NMOS transistor to generate a discharge current In. When switch S0 is off, the gate voltage is pulled to ground, turning off the discharge current, eliminating the influence of clock feedthrough, and reducing charge sharing. The charging circuit includes a switch P1, a charging transistor P0, and a switch N4. Switch P1 is connected in series with the charging transistor P0. An off-chip large capacitor C1 is added to the gate of the charging transistor P0 to reduce the fluctuation of the gate voltage of P0 due to clock feedthrough. At the same time, a switch N4 connected to ground is added to the source of P0. When the charging circuit is off, the charge accumulated by the gate-source capacitance of the charging transistor P0 is discharged through the switch N4, eliminating the influence of charge sharing.

[0008] Furthermore, the quantizer is implemented using a dynamic comparator. The clock is input via on-chip or off-chip circuitry. Changing the clock speed adjusts the temperature accuracy; a faster clock results in higher accuracy but also higher power consumption. The digital signal output by the quantizer controls the heater P-IDAC2 of the current charging and discharging module. When the integrated voltage of the integrator is greater than the reference voltage, it indicates that the heating power is greater than the reference power. The quantizer output controls the charging circuit to turn off and the discharging circuit to turn on, while simultaneously controlling the heater P-IDAC2 to turn off, achieving a cooling effect. Conversely, when the integrated voltage is less than the reference voltage, the quantizer output controls the charging circuit to turn on and the discharging circuit to turn off, while simultaneously controlling the heater P-IDAC2 to turn on, achieving a heating effect.

[0009] Furthermore, the integrator is a large capacitor C2, which simulates the electrical power of the heating resistor by the charge on the large capacitor C2, thereby achieving the sigma-delta function and providing feedback control for the accumulation of residual error.

[0010] Furthermore, the magnitudes of the three IDAC currents can be manually adjusted by setting the ratio between the heating resistor R and the two external resistors R1 and R2: the external resistors R1 and R2 are set to be n times the heating resistor, and I1 and I2 are 1 / n times the heating current I.

[0011] Furthermore, the reference voltage of the dynamic comparator is selected by calculation. First, the resistance value of the heating resistor is measured at different temperatures in the constant temperature chamber. By adjusting the current of the heater P-IDAC2, the power value at a specific temperature is obtained. The power on the external resistor is directly proportional to the voltage of the integrating capacitor C2. Similarly, the reference voltage value is also directly proportional to the power value measured at a specific temperature, and the reference voltage is calculated.

[0012] Furthermore, during normal system operation, different controllers control the two IDACs to output different currents. The currents flow through two different external variable resistors R1 and R2, generating voltages Vn and Vp. These voltages control the switching of the PMOS charging transistor and the NMOS discharging transistor to integrate the power on the integrating capacitor C2. The accumulated charge in the integrating capacitor C2 is converted into voltage to simulate power. The reference voltage and the voltage of the integrating capacitor are compared to determine whether the chip temperature has reached the set value. The output X[n] of the dynamic comparator acts on the charging and discharging current switches and the heater P-IDAC2. The temperature of the heater P-IDAC2 is achieved by periodically switching the load current output of the heater P-IDAC2 through the output of the dynamic comparator. The negative feedback of the sigma-delta system ensures that the temperature is maintained at the set value.

[0013] Furthermore, the P-IDAC circuit includes transistors NM0-NM3 and PM0-PM21. The reference current flows in from the drain of transistor NM0. The gates of NM0 and NM2 are connected. The drain of NM1 is connected to the source of NM0. The gates of NM1 and NM3 are connected. The sources of NM1 and NM3 are grounded. The reference current is replicated 1:1 into the NMOS current mirror. The drain of PM20 is connected to the drain of NM2. The source of PM20 is connected to the drain of PM21. The source of PM21 is connected to VDD. The gates of transistors PM1, PM3...PM19 are all connected to PM21 through a switch, and their sources are all connected to VDD. The switch on each PMOS current source represents a specific bit in the N-bit signal output by the P-IDAC current module. One bit: When the digital control module controls a certain current input to 1, the corresponding gate switch closes. All PMOS transistors use the same unit of PMOS transistors, and the number of parallel transistors m increases in binary order. PM1 is connected in parallel with 1 transistor, PM3 in parallel with 2 transistors, PM5 in parallel with 4 transistors, and so on. Similarly, the gates of PM0, PM2...PM20 transistors are connected to PM20 via switches. The settings of all transistors are the same as those of PM1, PM3...PM19. The control of the N-bit switch is achieved through digital logic in the digital module. The substrates of all PMOS transistors are connected to VDD, and the substrates of all NMOS transistors are grounded. The drains of PM0, PM2...PM20 are all connected to OUT, and the sources of PM1, PM3...PM19 are all connected to VDD.

[0014] Furthermore, the N-IDAC circuit includes NM0-NM21 transistors. The reference current Iref flows into the drain of NM0. The source of NM0 and the drain of NM1 are connected together. The source of NM1 is grounded. The gates and drains of NM0 and NM1 are connected together, similar to the IDAC constructed from PMOS transistors. The number m of parallel transistors NM1, NM3, NM5... and NM2, NM4, NM6... increases in binary. All NMOS transistors use the same unit of NMOS transistors. The gates of NM2, PM4...PM20 are connected to the gate of NM0 through a switch. The gates of NM1, PM3...PM19 are connected to the gate of NM1 through a switch. The digital logic in the digital module controls the N-bit switch. When a certain bit is 0, the corresponding switch is open, and when it is 1, the switch is closed. The drains of NM2, PM4...PM20 are all connected to OUT. The sources of NM1, PM3...PM19 are all grounded. All NMOS substrates are grounded. Beneficial effects

[0015] This invention innovatively constructs a sigma-delta-based chip temperature control system. This system utilizes capacitor power integration and sigma-delta modulation for power feedback regulation, thereby achieving higher temperature control resolution. It also innovatively improves the current generator structure, eliminating the influence of transistor threshold voltage, and innovatively improves the charge pump charging and discharging structure. The charging circuit can almost eliminate the effects of clock feedthrough and charge sharing, achieving high accuracy. Furthermore, the circuit structure is simple, avoiding the use of complex, high-power, and large-area modules such as integrators. This structure also provides a simpler solution for implementing mathematical square operations in circuits. Attached Figure Description

[0016] Figure 1 This is a system architecture diagram of the present invention; Figure 2 This is an embodiment of the sigma-delta-based chip temperature control system module in this invention.

[0017] Figure 3 This is an embodiment of P-IDAC in the sigma-delta-based chip temperature control system module of the present invention.

[0018] Figure 4 This is an embodiment of N-IDAC in the sigma-delta-based chip temperature control system module of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and technical effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings.

[0020] The heating power P of a micro-heater composed of resistors can be generated by applying a voltage V across the resistor R. We know that... The smaller the resistance, the greater the heating power and the faster the temperature rises. According to the data, when a DC voltage source is applied across the resistor, the temperature is directly proportional to the power. Similarly, when the resistance value remains constant, the power is directly proportional to the square of the current flowing through the resistor, that is, the temperature is directly proportional to the square of the current.

[0021] We designed the heater using the spatial layout of the internal metal layers of the chip. The design process required consideration of the heater's temperature distribution uniformity and the independence of contact resistance measurements. CMOSOL software was used to design the heater's shape and simulate the temperature of the heater's reaction zone. By changing the length, width, and spacing of the metal wires, while simultaneously increasing power consumption at the outer boundary and decreasing power consumption at the inner center, the heater's uniformity was optimized. We know that the resistance of the metal wire varies at different temperatures. By setting a specific temperature in a thermostat and applying an external current to measure the voltage, the resistance of the metal wire at that temperature can be obtained, eliminating the need for a separate temperature sensor.

[0022] like Figure 1 As shown, a sigma-delta-based chip temperature control system includes a control system and a heating module. The control system includes a current generator (1), a current generator (2), a selector, an integrator, and a quantizer. The heating module includes a heater. Current generators 1 and 2 generate two currents of opposite polarity connected to the selector. The selector selects one current to flow into the integrator, which consists of a large capacitor connected to one end of a quantizer composed of a dynamic comparator. The other end of the quantizer is connected to a reference voltage Vref. The quantizer output is fed back to the selector, forming a negative feedback sigma-delta modulator, ensuring that the integrator voltage always fluctuates near the reference voltage. Simultaneously, the quantizer output controls the heater. The bit stream generated by the quantizer not only ensures the stability of the sigma-delta modulator but also controls the temperature stability of the heater. If the heater temperature needs to be changed, the reference voltage Vref can be directly changed. Furthermore, the current magnitudes of current generators 1 and 2 are adjustable, allowing for temperature precision adjustment.

[0023] like Figure 2 The figure shown is an embodiment of a sigma-delta modulator in a sigma-delta chip temperature control system according to the present invention.

[0024] Current generator one +ΔQ1 and current generator two -ΔQ2It consists of two circuits: a PMOS charging circuit and an NMOS discharging circuit. It includes two IDACs (one N-IDAC and one P-IDAC1), two buffers, an adder, a subtractor, and a current charging and discharging module.

[0025] The IDAC is divided into P-type IDAC and N-type IDAC. The reference current of the IDAC is controlled by an external variable resistor. The value of Vn and Vp can be adjusted by adjusting the value of the external resistor, thereby controlling the charging and discharging current. The two IDACs are designated as a P-IDAC1 and an N-IDAC. The P-IDAC1 outputs current I1, which is connected to ground in series with an external resistor R1, generating the Vp and Vn values. The N-IDAC inputs current I2, which is connected to the power supply in series with an external resistor R2, generating the Vp value. These two different connection methods are designed to more easily and conveniently eliminate the influence of the threshold voltage of NMOS and PMOS transistors.

[0026] The outputs of P-IDAC1 and N-IDAC are each connected to a buffer. These buffers are then connected to an adder and a subtractor, respectively. The adder and subtractor are connected to a current charging / discharging module. The buffers serve as isolation because the IDAC output of the preceding stage is connected to a resistor, and the inputs of the subsequent adder and subtractor also have resistors connected to ground. Without isolation, the resistor at the IDAC output would be in parallel with the resistors of the adder and subtractor, reducing the resistance value and causing both stages to malfunction. Using unity-gain op-amps for isolation results in approximately infinite input impedance and approximately zero output impedance, thus not affecting the output and input resistances of the preceding and following stages. The bandwidth and gain of the two unity-gain op-amps need to be simulated in the system because the outputs are connected to resistors, and the stability and isolation performance of the buffers must be ensured.

[0027] The adder and subtractor are used to eliminate the threshold voltages of NMOS and PMOS transistors, respectively. The threshold voltage value can be obtained by voltage division using two resistors; it is a fixed value that can be obtained through simulation. The choice of resistors in the adder and subtractor affects power consumption; the larger the resistor, the lower the power consumption.

[0028] The current charging / discharging module includes a discharging circuit and a charging circuit. The module selects whether to charge or discharge via a selector. A charge pump can be used instead, but charge pumps have many non-ideal factors, such as charge sharing and clock feedthrough, which can lead to overshoot and large current errors during charging / discharging. The discharging circuit includes four NMOS transistors (N0-N3) connected in parallel in a ratio of 1:2:4:8. Three switches (S1, S2, S3) proportionally control the discharge current, i.e., the power dissipation. Since the power dissipation cannot be precisely calculated for actual on-chip resistors, a multi-bit adjustable current is used to find the optimal simulated power dissipation. Traditional charge pump circuits use a series-connected switching MOSFET and a charging / discharging MOSFET, with two configurations. One configuration connects the source of the switching MOSFET to the drain of the charging / discharging MOSFET, while the source of the charging / discharging MOSFET is grounded. This results in a significant clock feedthrough effect. The other configuration connects the source of the charging / discharging MOSFET to the drain of the switching MOSFET, while the source of the switching MOSFET is grounded. This configuration affects the source voltage and also introduces charge sharing. For the discharging circuit, we apply the switch (S0) to the gate voltage. When the switch is on, the gate voltage drives the NMOS transistor to generate a discharge current In. When the switch is off, the gate voltage is pulled to ground, stopping the discharge current. This eliminates the clock feedthrough effect and reduces charge sharing. For the charging circuit, if a gate switch with the same current as the discharge current is used, when the switch is off, the gate voltage is pulled to VDD, stopping the discharge current. However, when the switch is on, the gate voltage should be VGP. In this case, the accumulated charge at the gate cannot be released, leading to voltage instability. Here, our charging circuit includes a switching transistor P1, a charging transistor P0, and a switching transistor N4. Switching transistor P1 is connected in series with charging transistor P0. When the width-to-length ratio of switching transistor P1 is set to be large enough, the influence of its drain-source voltage can be ignored. In order to reduce the influence of non-ideal factors during P0 charging, an off-chip large capacitor C1 is added to the gate of P0, which can greatly reduce the fluctuation of the gate voltage of P0 caused by clock feedthrough. At the same time, a switching transistor N4 to ground is added to the source of P0. When the charging circuit is turned off, the charge accumulated in the gate-source capacitance of P0 is discharged through the switching transistor N4, which can eliminate the influence of charge sharing.

[0029] The quantizer is implemented using a dynamic comparator. The clock can be input via on-chip or off-chip circuitry. Changing the clock speed adjusts the temperature accuracy; a faster clock results in higher accuracy but also higher power consumption. The digital signal output by the quantizer controls a charge / discharge transistor (current charge / discharge module) and an IDAC (heater P-IDAC2). When the integrated voltage of the integrator is greater than the reference voltage, it indicates that the heating power is greater than the reference power (i.e., the chip temperature is greater than the set temperature). The quantizer output controls the charging circuit to turn off and the discharging circuit to turn on, while simultaneously controlling P-IDAC2 to turn off, achieving a cooling effect. Conversely, when the integrated voltage is less than the reference voltage, the quantizer output controls the charging circuit to turn on and the discharging circuit to turn off, while simultaneously controlling P-IDAC2 to turn on, achieving a heating effect. The integrator is a large capacitor C2. The charge on capacitor C2 simulates the electrical power of the heating resistor, achieving a sigma-delta effect and providing feedback control for residual error accumulation. The magnitudes of the three IDAC currents can be manually adjusted. We set the relationship between the three IDAC currents by defining the ratio of the heating resistor R and the two external resistors R1 and R2 (setting R1 and R2 to be n times the heating resistor's resistance, and I1 and I2 to be 1 / n times the heating current I). This significantly reduces the IDAC current in the current generator, lowering system power consumption. The reference voltage for the dynamic comparator is calculated. First, the resistance of the heating resistor is measured at different temperatures in a constant temperature chamber. By adjusting the current to heater P-IDAC2, the power value at a specific temperature is obtained. As explained above, the power across the external resistor is directly proportional to the voltage across the integrating capacitor C2. Similarly, the reference voltage is also directly proportional to the measured power value at a specific temperature, allowing the reference voltage to be calculated.

[0030] When the system is working normally, different controllers control the two IDACs to output different currents. The currents flow through two different external variable resistors R1 and R2 (R1 and R2 in the figure include three resistors to switch the control and generate three temperatures), generating voltages Vn and Vp. Two buffers are used for isolation to avoid mutual interference between the resistors of the adder and subtractor and the resistors of the preceding stage. At this time, the adder and subtractor are used to eliminate the threshold voltages Vthn and Vthp of the NMOS and PMOS transistors, respectively. The switching of the PMOS charging tube and the NMOS discharging tube can be controlled by integrating the power on the integrating capacitor C2. The charge accumulated by the integrating capacitor C2 is converted into voltage to simulate power. The reference voltage and the voltage of the integrating capacitor are compared to determine whether the chip temperature has reached the set value. The output X[n] of the dynamic comparator acts on the charging and discharging current switches and the heater P-IDAC2. The temperature of the heater P-IDAC2 is achieved by periodically switching the load current output of the heater P-IDAC2 through the output of the dynamic comparator. The negative feedback of the sigma-delta system ensures that the temperature is maintained at the set value.

[0031] According to the formula It can be seen that for n-tubes, ,because Vs = 0 , ,but For p-tubes: ,because , , ,but Assuming the power generated by the current I1 flowing through the resistor R1 is P1, then ,so Similarly, assuming the power generated by the current I2 flowing through resistor R2 is P2, then ,so Therefore, the power generated by currents I1 and I2 is directly proportional to the MOS currents In and Ip, and the integral of currents In and Ip is equivalent to the integral of the squares of currents I1 and I2. We set the P-IDAC2 reference current to be n times the N-IDAC reference current, and simultaneously, the heating resistor R is 1 / n times the resistor R2. The quantizer output X[n] simultaneously controls the on / off states of currents Ip, In, and the heating current I, thus ensuring a constant temperature at the set temperature. The temperature is determined by the reference voltage Vref.

[0032] From the above calculation formula, we know that controlling the temperature also requires controlling the power flowing through the heating resistor in the heater. When the heating resistor R is known, we need to square the current flowing through the heater. According to the square relationship between the gate-source voltage and the current in the saturation region of the MOSFET, the integral of the current Ip flowing through P0 is proportional to the square integral of the current I2 flowing through resistor R2. The current I2 is also proportional to the current flowing through the heating resistor R. Therefore, the value of the integral of Ip is proportional to the value of the integral of the power of the heating resistor R. The temperature of the heating resistor R can be directly measured by the voltage across C2. The current generator and selector here control the magnitude of the MOSFET gate voltage or drain-source current and the switching (S0). We generate currents of different magnitudes through two 10-bit IDACs. This current flows through external resistors, generating two voltages, the magnitude of which can be adjusted by the IDACs. Two buffers are used to input the voltage values ​​generated by the previous stage into the subtractor and adder, respectively. Two buffers are needed here for isolation to prevent mutual interference between the resistors of the two stages. For PMOS transistors, a subtractor is needed to subtract the threshold voltage. For NMOS transistors, an adder is needed to eliminate the threshold voltage. For P0 and N0, N1, N2, and N3, the gate voltage is the voltage after eliminating the threshold voltage. Therefore, the current generated by this voltage is quadratic with respect to voltages Vn and Vp, i.e., quadratic with respect to currents I1 and I2. In the discharge circuit, the control signal output from the quantizer controls the gate voltage of the transistors. When switch S0 is on, the gate voltage equals the output of the previous stage; when switch S0 is off, the gate is grounded. For the charging transistors, we place the switch at P1. The aspect ratio of P1 can be slightly larger to reduce the impact of the drain-source voltage drop on the charging current. Simultaneously, since the gate-source parasitic capacitance of transistor P0 stores charge, the accumulation of charge during the alternating conduction and turn-off of P1 affects the stability of the P0 gate voltage. Therefore, transistor N4 is added. When P1 is turned off, the charge accumulated in the P0 gate-source capacitance is released. By adding transistor N4, charge sharing during charging can be eliminated, resulting in an ideal charging current. We connect a large capacitor to the gate of transistor P0. This capacitor mainly reduces the impact of clock feedthrough during PM1 switching on the P0 gate voltage. When the capacitor is above 100pF, the clock feedthrough effect is negligible. Discharge transistors N0, N1, N2, and N3 are set in a 1:2:4:8 ratio. Switches S1, S2, and S3 control whether N1, N2, and N3 participate in operation, respectively. The binary arrangement of the discharge transistors simulates the heat dissipation effect of a heater.

[0033] like Figure 3The diagram shows an embodiment of a P-IDAC circuit in a sigma-delta-based chip temperature control system. A reference current flows in from the drain of transistor NM0. The gates of NM0 and NM2 are connected, the drain of NM1 is connected to the source of NM0, and the gates of NM1 and NM3 are connected. The sources of NM1 and NM3 are grounded. The reference current is replicated 1:1 into the NMOS current mirror. The drain of PM20 is connected to the drain of NM2, and the source of PM20 is connected to the drain of PM21. The source of PM21 is connected to VDD. The gates of PM1, PM3...PM19 are all connected to PM21 via a switch, and their sources are all connected to VDD. The switch on each PMOS current source represents a bit of the N-bit signal output by the P-IDAC current module. When the digital control module controls a current input of 1, the corresponding gate switch closes. All PMOS transistors use the same unit of PMOS transistors, and the number m in parallel increases in binary order: PM1 has 1 in parallel, PM3 has 2 in parallel, PM5 has 4 in parallel, and so on. Similarly, the gates of PM0, PM2...PM20 are connected to PM20 via a switch, and the settings of all transistors are the same as PM1, PM3...PM19. The control of the N-bit switch is achieved through digital logic in the digital module. Figure 3 All PMOS substrates are connected to VDD, all NMOS substrates are grounded, the drains of PM0, PM2...PM20 are connected to OUT, and the sources of PM1, PM3...PM19 are connected to VDD.

[0034] Figure 4 This is an example of an N-IDAC circuit in a sigma-delta-based chip temperature control system. A reference current Iref flows into the drain of NM0. The source of NM0 is connected to the drain of NM1, and the source of NM1 is grounded. The gates and drains of NM0 and NM1 are connected, similar to an IDAC constructed from PMOS transistors. The number m of parallel transistors NM1, NM3, NM5… and NM2, NM4, NM6… increases in binary increments. All NMOS transistors use the same unit of NMOS transistors. The gates of NM2, PM4…PM20 are connected to the gate of NM0 via a switch, and the gates of NM1, PM3…PM19 are connected to the gate of NM1 via a switch. Digital logic in the digital module controls an N-bit switch; when a bit is 0, the corresponding switch is open, and when it is 1, the switch is closed. Figure 4 The drains of NM2, PM4...PM20 are all connected to OUT, the sources of NM1, PM3...PM19 are all grounded, and all NMOS substrates are grounded.

[0035] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the implementation process of the present invention has been described in detail above, those skilled in the art can still modify the technical solutions described in the foregoing examples or make equivalent substitutions for some of the technical features. All modifications and equivalent substitutions made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A sigma-delta-based chip temperature control system, comprising a control system and a heating module, wherein the control system includes a current generator, a current generator, a selector, an integrator, and a quantizer, and the heating module includes a heater, characterized in that, The current generator 1 and current generator 2 generate two currents of opposite polarity, which are connected to a selector. The selector selects one of the currents to flow into an integrator. The integrator is composed of a large capacitor, which is connected to one end of a quantizer composed of a dynamic comparator. The other end of the quantizer is connected to a reference voltage Vref. The output of the quantizer is fed back to the selector, forming a negative feedback sigma-delta modulator. This ensures that the voltage of the integrator always fluctuates near the reference voltage. At the same time, the output of the quantizer controls the heater. The bit stream generated by the quantizer not only ensures the stability of the sigma-delta modulator but also controls the stability of the heater temperature. The temperature of the heater is adjusted by changing the reference voltage Vref, and the temperature accuracy is adjusted by adjusting the current magnitudes of current generator 1 and current generator 2. The current generator one +ΔQ1 and current generator two -ΔQ2 It consists of two circuits: a PMOS charging circuit and an NMOS discharging circuit. The PMOS charging circuit and the NMOS discharging circuit include two IDACs, two buffers, an adder, a subtractor, and a current charging / discharging module. The IDACs are either P-type or N-type. The reference current of the IDAC is controlled by an external variable resistor. Adjusting the external resistor adjusts the values ​​of Vn and Vp, thereby controlling the charging / discharging current. The two IDACs are designated as P-IDAC1 and N-IDAC1. P-IDAC1 outputs current I1, which is connected to ground in series with an external resistor R1 to generate the value Vp. N-IDAC inputs current I2, which is connected to the power supply in series with an external resistor R2 to generate the value Vn. The P-IDAC1 and N-IDAC outputs are each connected to a buffer. The two buffers are connected to an adder and a subtractor, respectively. The adder and subtractor are connected to the current charging / discharging module. The buffers are used for isolation. The adder and subtractor are used to eliminate the threshold voltages of NMOS and PMOS, respectively. The current charging / discharging module selects charging or discharging via a selector.

2. The chip temperature control system based on sigma-delta according to claim 1, characterized in that, The current charging and discharging module includes a discharging circuit and a charging circuit. The discharging circuit includes four NMOS transistors N0-N3 arranged in parallel, with a parallel ratio of 1:2:4:

8. The magnitude of the discharge current, i.e., the power dissipation, is controlled proportionally by three switches S1, S2, and S3. When switch S0 is turned on, the gate voltage drives the NMOS transistor to generate a discharge current In. When switch S0 is turned off, the gate voltage is pulled to ground, turning off the discharge current, eliminating the influence of clock feedthrough, and reducing charge sharing. The charging circuit includes a switch P1, a charging transistor P0, and a switch N4. Switch P1 is connected in series with the charging transistor P0. An off-chip large capacitor C1 is added to the gate of the charging transistor P0 to reduce the fluctuation of the gate voltage of P0 due to clock feedthrough. At the same time, a switch N4 connected to ground is added to the source of P0. When the charging circuit is turned off, the charge accumulated by the gate-source capacitance of the charging transistor P0 is discharged through the switch N4, eliminating the influence of charge sharing.

3. The chip temperature control system based on sigma-delta according to claim 2, characterized in that, The quantizer is implemented using a dynamic comparator. The clock is input via on-chip or off-chip circuitry. Changing the clock speed adjusts the temperature accuracy; a faster clock results in higher accuracy but also higher power consumption. The digital signal output by the quantizer controls the heater P-IDAC2 of the current charging and discharging module. When the integrated voltage of the integrator is greater than the reference voltage, it indicates that the heating power is greater than the reference power. The quantizer output controls the charging circuit to turn off and the discharging circuit to turn on, while simultaneously controlling the heater P-IDAC2 to turn off, achieving a cooling effect. Conversely, when the integrated voltage is less than the reference voltage, the quantizer output controls the charging circuit to turn on and the discharging circuit to turn off, while simultaneously controlling the heater P-IDAC2 to turn on, achieving a heating effect.

4. The chip temperature control system based on sigma-delta according to claim 3, characterized in that, The integrator is a large capacitor C2. The charge on the large capacitor C2 simulates the electrical power of the heating resistor, thus achieving the sigma-delta effect and providing feedback control for the accumulation of residual error.

5. The chip temperature control system based on sigma-delta according to claim 3, characterized in that, The magnitudes of the three IDAC currents can be manually adjusted by setting the ratio between the heating resistor R and the two external resistors R1 and R2: set the external resistors R1 and R2 to be n times the heating resistor, and set I1 and I2 to be 1 / n times the heating current I.

6. The chip temperature control system based on sigma-delta according to claim 3, characterized in that, The reference voltage of the dynamic comparator is selected by calculation. First, the resistance value of the heating resistor is measured at different temperatures in the constant temperature chamber. By adjusting the current of the heater P-IDAC2, the power value at a specific temperature is obtained. The power on the external resistor is directly proportional to the voltage of the integrating capacitor C2. Similarly, the reference voltage value is also directly proportional to the power value measured at a specific temperature. The reference voltage is then calculated.

7. The chip temperature control system based on sigma-delta according to claim 3, characterized in that, When the system is working normally, different controllers control the two IDACs to output different currents. The currents flow through two different external variable resistors R1 and R2, generating voltages Vn and Vp. The switching of the PMOS charging tube and the NMOS discharging tube controls the integration of power on the integrating capacitor C2. The charge accumulated by the integrating capacitor C2 is converted into voltage to simulate power. The reference voltage and the voltage of the integrating capacitor are compared to determine whether the chip temperature has reached the set value. The output X[n] of the dynamic comparator acts on the charging and discharging current switches and the heater P-IDAC2. The temperature of the heater P-IDAC2 is achieved by the periodic sequence switching of the load current output by the heater P-IDAC2 by the output of the dynamic comparator. The negative feedback of the sigma-delta system ensures that the temperature is maintained at the set value.

8. The chip temperature control system based on sigma-delta according to claim 3, characterized in that, The P-IDAC circuit includes transistors NM0-NM3 and PM0-PM21. The reference current flows in from the drain of NM0. The gates of NM0 and NM2 are connected. The drain of NM1 is connected to the source of NM0, and the gates of NM1 and NM3 are connected. The sources of NM1 and NM3 are grounded. The reference current is replicated 1:1 into the NMOS current mirror. The drain of PM20 is connected to the drain of NM2, and the source of PM20 is connected to the drain of PM21. The source of PM21 is connected to VDD. The gates of transistors PM1, PM3…PM19 are all connected to PM21 via a switch, and their sources are all connected to VDD. The switch on each PMOS current source represents a specific ratio of the N-bit signal output by the P-IDAC current module. Specifically, when the digital control module controls a certain current input 1, the corresponding gate switch closes. All PMOS transistors use the same unit of PMOS transistors, and the number of parallel transistors m increases in binary order. PM1 is connected in parallel with 1 transistor, PM3 with 2 transistors, PM5 with 4 transistors, and so on. Similarly, the gates of PM0, PM2...PM20 transistors are connected to PM20 via switches. The settings of all transistors are the same as those of PM1, PM3...PM19. The control of the N-bit switch is achieved through the digital logic in the digital module. The substrates of all PMOS transistors are connected to VDD, and the substrates of all NMOS transistors are grounded. The drains of PM0, PM2...PM20 are all connected to OUT, and the sources of PM1, PM3...PM19 are all connected to VDD.

9. The chip temperature control system based on sigma-delta according to claim 8, characterized in that, The N-IDAC circuit includes NM0-NM21 transistors. The reference current Iref flows into the drain of NM0. The source of NM0 is connected to the drain of NM1, and the source of NM1 is grounded. The gates and drains of NM0 and NM1 are connected, similar to the IDAC constructed from PMOS transistors. The number m of parallel transistors NM1, NM3, NM5... and NM2, NM4, NM6... increases in binary. All NMOS transistors use the same unit of NMOS transistors. The gates of NM2, PM4...PM20 are connected to the gate of NM0 through a switch. The gates of NM1, PM3...PM19 are connected to the gate of NM1 through a switch. The digital logic in the digital module controls the N-bit switch. When a certain bit is 0, the corresponding switch is open, and when it is 1, the switch is closed. The drains of NM2, PM4...PM20 are all connected to OUT. The sources of NM1, PM3...PM19 are all grounded. All NMOS substrates are grounded.

Images