Method and device for characterizing a quantum chip, electronic device and storage medium
By constructing a topological structure diagram and distance weights for a quantum chip, a characterization diagram is generated, solving the characterization problem of unknown quantum chips and realizing efficient drawing of quantum chip and sub-chip topological structures, supporting subsequent computing tasks.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING BAIDU NETCOM SCI & TECH CO LTD
- Filing Date
- 2023-10-20
- Publication Date
- 2026-06-12
AI Technical Summary
Existing technologies struggle to efficiently generate patterns for unknown quantum chips, impacting the execution of subsequent computational tasks.
By determining the number of qubits and communication relationships in a quantum chip, a first topological structure diagram is constructed, and a characterization diagram is generated based on distance weights, providing an efficient characterization method.
It enables efficient generation of characterization maps in the case of unknown quantum chips, supports the execution of subsequent computing tasks, and can systematically characterize the topological structure of sub-chips.
Smart Images
Figure CN118095465B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of computer technology, and in particular to the fields of quantum computing and chip fabrication technology. Background Technology
[0002] Quantum computing has become an important area of research and development in both academia and industry in recent years. Compared to traditional computing, quantum computing has shown significant advantages in solving problems such as large number factorization. Furthermore, it is of great importance to cutting-edge research areas such as quantum many-body systems and quantum chemical simulations. In terms of hardware implementation, quantum computing offers a variety of technological solutions, including superconducting circuits, ion traps, and photonic quantum computing. Summary of the Invention
[0003] This disclosure provides a method, apparatus, device, and storage medium for characterizing a quantum chip.
[0004] According to one aspect of this disclosure, a method for characterizing a quantum chip is provided, comprising:
[0005] Based on the chip information of the quantum chip, the number of qubits and the quantum gate information of the quantum chip are determined. The quantum gate information characterizes the communication relationship between the qubits of the quantum chip.
[0006] Based on the quantity information and quantum gate information, a first topological structure diagram of the quantum chip is determined, wherein the first topological structure diagram is composed of multiple nodes representing each quantum bit and edges representing the communication relationship between every two directly adjacent quantum bits of the quantum chip.
[0007] Based on the quantum gate information, determine the distance weights between each qubit; and
[0008] Based on the distance weights and the first topological structure diagram, the characterization of the quantum chip is obtained.
[0009] According to another aspect of this disclosure, a quantum chip patterning apparatus is provided, comprising:
[0010] The first determining module is used to determine the number of qubits and the quantum gate information of the quantum chip based on the chip information of the quantum chip, wherein the quantum gate information characterizes the communication relationship between each qubit of the quantum chip;
[0011] The second determining module is used to determine the first topological structure diagram of the quantum chip based on the quantity information and the quantum gate information. The first topological structure diagram is composed of multiple nodes representing each quantum bit and edges representing the communication relationship between every two directly adjacent quantum bits of the quantum chip.
[0012] The third determining module is used to determine the distance weights between each qubit based on the quantum gate information; and
[0013] The generation module is used to obtain the characterization pattern of the quantum chip based on the distance weights and the first topological structure diagram.
[0014] According to another aspect of this disclosure, an electronic device is provided, comprising:
[0015] At least one processor; and
[0016] The memory is communicatively connected to the at least one processor; wherein,
[0017] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform any of the methods described in the present disclosure.
[0018] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause the computer to perform any of the methods according to embodiments of this disclosure.
[0019] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements any of the methods according to embodiments of this disclosure.
[0020] According to the technology disclosed herein, a pattern of a quantum chip can be generated efficiently when the pattern of a manufactured quantum chip is unknown, so that the quantum chip can perform subsequent computing tasks.
[0021] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description
[0022] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:
[0023] Figure 1 This is a schematic diagram of a method for patterning a quantum chip according to an embodiment of the present disclosure;
[0024] Figure 2 This is a schematic diagram of a first topological structure of a quantum chip according to an embodiment of the present disclosure;
[0025] Figure 3 This is a schematic diagram of a first topological structure of a quantum chip according to an embodiment of the present disclosure;
[0026] Figure 4 This is a schematic diagram of a first topological structure of a quantum chip according to an embodiment of the present disclosure;
[0027] Figure 5 This is a schematic diagram of a first topological structure of a quantum chip according to an embodiment of the present disclosure;
[0028] Figure 6 This is a schematic diagram of a sub-chip of a quantum chip according to an embodiment of the present disclosure;
[0029] Figure 7 This is a schematic diagram of a quantum chip patterning apparatus according to an embodiment of the present disclosure;
[0030] Figure 8 This is a block diagram of an electronic device used to implement the quantum chip characterization method of the embodiments of this disclosure. Detailed Implementation
[0031] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.
[0032] like Figure 1 As shown, this disclosure provides a method for characterizing a quantum chip, including:
[0033] Step S101: Based on the chip information of the quantum chip, determine the number of qubits and the quantum gate information of the quantum chip, wherein the quantum gate information characterizes the communication relationship between each qubit of the quantum chip.
[0034] Step S102: Based on the quantity information and quantum gate information, determine the first topological structure diagram of the quantum chip, wherein the first topological structure diagram is composed of multiple nodes representing each quantum bit and edges representing the communication relationship between every two directly adjacent quantum bits of the quantum chip.
[0035] Step S103: Determine the distance weights between each qubit based on the quantum gate information. And Step S104: Obtain the pattern of the quantum chip based on the distance weights and the first topological structure diagram.
[0036] According to the embodiments of this disclosure, it should be noted that:
[0037] The quantum chip disclosed in this embodiment can be understood as a chip that has been manufactured but whose quantum chip layout is unknown. The quantum chip layout includes the arrangement and interconnection of each quantum bit. The required quantum chip can be manufactured based on the quantum chip layout.
[0038] Chip information can be understood as information that can be directly read from a quantum chip, including but not limited to information on the number of qubits, quantum gate information, and the fidelity between each qubit.
[0039] Quantitative information can characterize the total number of qubits contained in a quantum chip, or it can characterize the number of undamaged, intact qubits contained in a quantum chip.
[0040] Quantum gate information characterizes the communication relationship between the qubits of a quantum chip. It can be understood that quantum gate information can be used to know whether any two qubits are directly or indirectly connected.
[0041] The first topological graph is formed by multiple nodes and edges connecting the nodes. Each node represents a qubit, and each node can have corresponding coordinates in the coordinate system of the first topological graph (e.g., ...). Figure 2 (As shown). An edge connecting two adjacent nodes indicates that the corresponding qubits of the nodes have a communication relationship. When any two qubits are directly coupled, there is a communication relationship between them. When any two qubits are indirectly coupled through other qubits, there is a communication relationship between them and other qubits.
[0042] The structure of the first topological structure depends on the number of qubits contained in the quantum chip and the communication relationships between them. Based on the different numbers of qubits and the different communication relationships between them, the first topological structure of the quantum chip can be determined as follows: Figures 3 to 5 The diagram shows rectangular tiling structures, circular tiling structures, or 45° angled square tiling structures. It should be noted that... Figures 3 to 5 The first topology shown is illustrative and can be a non-standard topology diagram. Figures 3 to 5 The arbitrary structure shown.
[0043] The distance weight between each qubit can be determined based on whether there is a communication relationship and / or communication overhead between the qubits.
[0044] The characterization of a quantum chip can be understood as the distance weight between the qubits corresponding to the two nodes connected by the associated edges on each edge of the first topological structure graph.
[0045] Two directly adjacent qubits can be understood as being adjacent on a quantum chip when a two-qubit quantum gate is applied.
[0046] According to the technology of this disclosure, an efficient and systematic method for characterizing a quantum chip is provided. This method can graphically describe the characterization of a quantum chip using its chip information, even when the topological structure diagram of a manufactured quantum chip is unknown. Furthermore, based on the characterization diagram determined by a first topological structure diagram and distance weights, the distance characteristics of the quantum chip can be quantitatively described, providing an operable method for efficiently drawing quantum chip topological structure diagrams. When the characterization diagram of a manufactured quantum chip is unknown, it can be generated efficiently to facilitate subsequent computational tasks. In practical applications of quantum computers, not all qubits on the quantum chip will necessarily be used. Therefore, how to select a portion of qubits on a given quantum chip and virtually construct a superconducting quantum chip becomes a very important issue.
[0047] After generating the pattern of the quantum chip using the method of this embodiment, the second topological diagram of the required sub-chip (composed of some qubits of the quantum chip) can be efficiently and systematically drawn based on the pattern of the quantum chip, thereby realizing the selection of some qubits on the quantum chip to form a sub-chip, so as to use the sub-chip to perform subsequent computing tasks.
[0048] The technology disclosed herein has a wide range of applications, applicable to quantum chips with different structures, and is not limited by the implementation method of quantum chips. The technology disclosed herein is highly systematic and architectural, capable of systematically characterizing quantum chips and quantum sub-chips, providing a system architecture for subsequent research. The technology disclosed herein is highly operable, enabling efficient and convenient drawing of topological structure diagrams of quantum chips with different structures, as well as the topological structure diagrams of their sub-chips. The technology disclosed herein is highly practical, helping researchers further study the optimal sub-chip problem on quantum chips and providing strong support for solving practical problems.
[0049] In one example, based on the quantity information in the quantum chip's chip information, it can be known that the quantum chip includes Q0 to Q... 11 There are 12 usable qubits. Based on the quantum gate information in the quantum chip's chip information, it can be seen that Q0 communicates with Q1 and Q3; Q1 communicates with Q0, Q2, and Q4; Q2 communicates with Q1 and Q5; Q3 communicates with Q0, Q4, and Q6; Q4 communicates with Q1, Q3, Q5, and Q7; Q5 communicates with Q2, Q4, and Q8; Q6 communicates with Q3, Q7, and Q9; and Q7 communicates with Q4, Q6, Q8, and Q9. 10 There is a communication relationship between Q8 and Q5, Q7, and Q6. 11 There is a communication relationship between Q9 and Q6, Q 10 There is a communication relationship, Q 10 Compared with Q7, Q9, Q11 There is a communication relationship, Q 11 With Q8, Q 10 There is a communication relationship. Based on the above information, a graph can be drawn in a custom coordinate system as follows. Figure 2 The first topological structure diagram is shown. Further, based on the quantum gate information, the distance weights between each qubit of the quantum chip are determined. Based on the distance weights and the first topological structure diagram, a characterization diagram of the quantum chip is obtained.
[0050] In one example, the first topological graph consists of a set of nodes and a set of edges. The nodes correspond to the qubits of the quantum chip. The edges correspond to the communication relationships between directly adjacent qubits. Specifically, a quantum chip C with N qubits has a set of nodes Q. Using the qubits as nodes in the first topological graph (i.e., using Q as the set of nodes), an undirected edge is connected between two qubits that can operate a two-qubit quantum gate. With Q j Using the set of undirected edges of a two-qubit gate as the topological graph, an undirected graph G = (Q, E) is constructed, which serves as the first topological graph of the quantum chip C. Specifically, when {Q... i Q j When}∈E, then the quantum bit Q can be... i Q j When a two-qubit quantum gate is applied, the quantum bit Q is called a quantum bit. i Q j They are adjacent on the quantum chip C.
[0051] In one embodiment, the quantum chip characterization method of this disclosure includes steps S101 to S104, wherein step S103: determining the distance weights between each qubit based on quantum gate information, including:
[0052] Step S1031: Determine every two directly adjacent qubits in the quantum chip based on the quantum gate information.
[0053] Step S1032: Determine the fidelity of the two-qubit gate between every two directly adjacent qubits based on the chip information.
[0054] Step S1033: Determine the distance weights between each qubit based on the fidelity.
[0055] According to the embodiments of this disclosure, it should be noted that:
[0056] The method of calculating distance weights based on fidelity can be selected and adjusted as needed. For example, let Q... i With Qj For any two adjacent qubits on the quantum chip C, the distance d(Q) between them is... i Q j It can be based on Q i With Q j The fidelity F(Q) between two qubit gates i Q j The definition is given by () and there are no restrictions here. For example:
[0057] d(Q i Q j )=1-F(Q i Q j ) or d(Q i Q j ) = -log a F(Q i Q j )
[0058] Among them, F(Q) i Q j ()∈[0,1], a is a fixed constant greater than 0 and not equal to 1. We can take a=e as a natural constant. The choice of a here will not make a practical difference to the scheme.
[0059] Determining the distance weights between each qubit can be understood as determining the distance weights between any two directly adjacent or indirectly adjacent qubits in a quantum chip.
[0060] According to the technology of this disclosure, the weight distance between any two directly adjacent qubits and the weight distance between any two indirectly adjacent qubits can be accurately calculated based on the fidelity of the two-qubit gates between directly adjacent qubits. This facilitates the planning of the target qubits required for the computational task based on the distance weights between each qubit.
[0061] In one example, the process of determining the distance weights includes:
[0062] Define the distance between adjacent qubits, and then define the distance between any two qubits based on this distance. Let Q be the distance between adjacent qubits. i With Q j For any two adjacent qubits on the quantum chip C, the distance d(Q) between them is... i Q j It can be based on Q i With Q j The fidelity F(Q) between two qubit gates i Q j The definition is given by () and there are no restrictions here. For example:
[0063] d(Q i ,Q j ) = 1 - F(Q i ,Q j ) or d(Q i ,Q j ) = -logaF(Q i ,Q j )
[0064] where F(Q i , Q j ) ∈ [0, 1], a is a fixed constant greater than 0 and not equal to 1. We can take a = e as the natural constant. The selection of a here will not make a practical difference to the solution.
[0065] Furthermore, if each element in the quantum bit sequence is adjacent on the quantum chip C to the previous element (t, j are non - negative integers, j < t), and all elements are pairwise different, then the quantum bit sequence p is called a path connecting the quantum bits . As shown in Figure 6 , p = (Q0, Q3, Q6, Q7, Q8, Q5) is a path connecting the quantum bits Q0 and Q5. The distance d(p) of the path p is defined as the sum of the distances between each two consecutive quantum bits in the quantum bit sequence p In this way, the distance between quantum bits can be extended to the non - adjacent case, that is, the distance between two non - directly adjacent quantum bits Q i , Q j is defined as the minimum value of the distances of the paths connecting these two quantum bits. In particular, when the path does not exist, the distance is defined as positive infinity.
[0066] d Q (Q i , Q j ) = min{d(p) | path p ∈ Q t connects Q i and Q j , t is a non - negative integer}.
[0067] In one implementation, the method for characterizing a quantum chip in an embodiment of the present disclosure includes steps S101 to S104, and S1031 to S1033. Among them, step S1033: Determine the distance weights between each quantum bit according to the fidelity, including:
[0068] Determine the first distance weight between each two directly adjacent quantum bits according to the fidelity.
[0069] Determine the second distance weight between each two indirectly adjacent quantum bits according to the first distance weight.
[0070] Based on the first distance weight and the second distance weight, the distance weight between each qubit is obtained.
[0071] According to the technology of this disclosure, the weight distance between any two directly adjacent qubits and the weight distance between any two indirectly adjacent qubits can be accurately calculated based on the fidelity of the two-qubit gates between directly adjacent qubits. This facilitates the planning of the target qubits required for the computational task based on the distance weights between each qubit.
[0072] In one embodiment, the quantum chip characterization method of this disclosure includes steps S101 to S104, wherein step S102: determining a first topological structure diagram of the quantum chip based on quantity information and quantum gate information, including:
[0073] Step S1021: Determine the target drawing function based on the quantity information and quantum gate information.
[0074] Step S1022: Generate the first topological structure diagram of the target structure shape of the quantum chip according to the target drawing function.
[0075] According to the embodiments of this disclosure, it should be noted that:
[0076] The target drawing function can be understood as a drawing function that can draw the first topological structure diagram of the target structure shape. With the quantity and quantum gate information remaining constant, the target drawing function can also be different depending on the requirements. That is to say, even when the number of qubits and the communication relationships between them are fixed, different first topological structure diagrams can be obtained by adjusting the layout positions (coordinates) of the nodes corresponding to each qubit.
[0077] For example, quantum chips include Q0 to Q10. 11 There are 12 usable qubits. Based on the quantum gate information in the quantum chip's chip information, it can be seen that Q0 communicates with Q1 and Q3; Q1 communicates with Q0, Q2, and Q4; Q2 communicates with Q1 and Q5; Q3 communicates with Q0, Q4, and Q6; Q4 communicates with Q1, Q3, Q5, and Q7; Q5 communicates with Q2, Q4, and Q8; Q6 communicates with Q3, Q7, and Q9; and Q7 communicates with Q4, Q6, Q8, and Q9. 10 There is a communication relationship between Q8 and Q5, Q7, and Q6. 11 There is a communication relationship between Q9 and Q6, Q 10 There is a communication relationship, Q 10 Compared with Q7, Q9, Q 11 There is a communication relationship, Q11 With Q8, Q 10 There is a communication relationship. Based on this, the target drawing function can be determined as a function that can draw the first topological structure diagram of different target structure shapes, such as rectangular tiling structure, one-dimensional chain structure, ring tiling structure, or 45° oblique square tiling structure.
[0078] According to the technology of this disclosure, an efficient and systematic method for characterizing quantum chips is provided. This method can, even when the topological structure of a quantum chip already manufactured by another party is unknown, utilize the chip information of the quantum chip and a determined drawing function to graphically describe a first topological structure diagram of the quantum chip. Furthermore, based on the characterization diagram determined by the first topological structure diagram and distance weights, the distance characteristics of the quantum chip can be quantitatively described, providing an operable method for efficiently drawing quantum chip topological structure diagrams. The technology of this disclosure is highly operable and can efficiently and easily draw topological structure diagrams of quantum chips with different structures, as well as the topological structure diagrams of their sub-chips.
[0079] In one embodiment, the quantum chip patterning method of this disclosure includes steps S101 to S104, and steps S1021 and S1022, wherein step S1021: determining the target drawing function based on quantity information and quantum gate information, including:
[0080] Based on the quantity information and quantum gate information, multiple initial drawing functions are determined.
[0081] Based on preset characterization rules and multiple initial drawing functions, the target drawing function is determined.
[0082] According to the embodiments of this disclosure, it should be noted that:
[0083] With the quantity and gate information remaining constant, the drawing function can differ depending on the requirements. That is, even when the number of qubits and the communication relationships between them are fixed, multiple different initial drawing functions can be obtained by adjusting the layout positions (coordinates) of the nodes corresponding to each qubit. Each initial drawing function will produce a different first topological structure diagram.
[0084] Based on preset characterization rules, a target drawing function that meets the requirements can be selected from multiple initial drawing functions. These preset characterization rules can be selected and adjusted according to the computational task or design needs. For example, preset characterization rules may include: requiring the generated first topological structure graph to include intersecting edges; requiring the generated first topological structure to include intersecting edges; requiring the generated first topological structure to be a rectangular tiling structure; requiring the generated first topological structure to be a one-dimensional chain structure; requiring the generated first topological structure to be a circular tiling structure; requiring the generated first topological structure to be arranged along the X-axis; requiring the generated first topological structure to be arranged along the Y-axis, etc.
[0085] According to the technology of this disclosure, an efficient and systematic method for characterizing quantum chips and their sub-chips is provided. Based on a first topological structure diagram of the quantum chip, a distance weight is introduced to quantitatively describe the distance characteristics of the quantum chip and its sub-chips. Simultaneously, a drawing function is proposed, providing an operable method for efficiently drawing the topological structure diagram of the quantum chip and its sub-chips, and representing the relationship between the sub-chip's topological structure diagram and its parent chip. By combining the concepts of topological structure diagram and distance weight, and introducing a drawing function for the quantum chip, a novel characterization method for quantum chips is presented, and this method can be further extended to quantum sub-chips.
[0086] In one embodiment, the quantum chip characterization method of this disclosure includes steps S101 to S104, and steps S1021 and S1022, wherein step S1022: generating a first topological structure map of the target structure shape of the quantum chip according to the target drawing function, including:
[0087] Based on the point drawing function in the target drawing function, multiple nodes representing each qubit are generated in the coordinate system, where each node contains corresponding coordinate information.
[0088] Based on the edge drawing function in the target drawing function, an edge is generated between the two nodes corresponding to every two adjacent qubits, where the two nodes belong to multiple nodes.
[0089] Based on the positional relationships of multiple nodes and edges, the correspondence between multiple nodes and multiple qubits of the quantum chip is determined.
[0090] Based on multiple nodes, edges, and corresponding relationship information, a first topological structure diagram of the target structure shape of the quantum chip is generated.
[0091] According to the embodiments of this disclosure, it should be noted that:
[0092] The point drawing function is used to draw each node in the first topology graph, and each drawn node contains coordinate information.
[0093] The edge drawing function is used to draw the edges between qubits that have a communication relationship.
[0094] Determining the correspondence between multiple nodes and multiple qubits on a quantum chip can be understood as mapping the qubits on the quantum chip corresponding to each node. For example, as... Figure 2 As shown, the quantum chip includes Q0 to Q10. 11 There are a total of 12 fully functional qubits, corresponding to 12 nodes drawn in the first topology diagram. Here, Q2: (0,2) represents the qubit Q2 associated with this node in the quantum chip, and the coordinates of this node are (0,2). Figure 2 The other nodes are similar, and will not be elaborated here.
[0095] According to the technology of this disclosure, an efficient and systematic method for characterizing quantum chips and their sub-chips is provided. Based on a first topological structure diagram of the quantum chip, a distance weight is introduced to quantitatively describe the distance characteristics of the quantum chip and its sub-chips. Simultaneously, a drawing function is proposed, providing an operable method for efficiently drawing the topological structure diagram of the quantum chip and its sub-chips, and representing the relationship between the sub-chip's topological structure diagram and its parent chip. By combining the concepts of topological structure diagram and distance weight, and introducing a drawing function for the quantum chip, a novel characterization method for quantum chips is presented, and this method can be further extended to quantum sub-chips.
[0096] In one implementation, the first topological graph consists of a set of nodes and a set of edges. The nodes correspond to the multiple qubits of the quantum chip. The edges correspond to the communication relationships between directly adjacent qubits. Specifically, for a quantum chip C with N qubits, the qubits are defined as forming a set of nodes Q. Using the qubits as nodes in the first topological graph, i.e., using Q as the set of nodes in the first topological graph, an undirected edge is connected between two qubits that can operate a two-qubit quantum gate, i.e., an edge is defined as... With Q j Using the set of undirected edges of a two-qubit gate as the topological graph, an undirected graph G = (Q, E) is constructed, which serves as the first topological graph of the quantum chip C. Specifically, when {Q... i Q j When}∈E, then the quantum bit Q can be... i Q j When a two-qubit quantum gate is applied, the quantum bit Q is called a quantum bit. i Q j They are adjacent on the quantum chip C.
[0097] Define the distance between adjacent qubits, and then define the distance between any two qubits based on this distance. Let Q be the distance between adjacent qubits. iWith Q j If Q i i and Q j j are any two adjacent qubits on the quantum chip C, then the distance d(Q i and Q j j ) can be defined based on the fidelity F(Q i , Q j j ) of the two-qubit gate between them. There is no restriction here. For example:
[0098] d(Q i i and Q j j ) = 1 - F(Q i i , Q j j ) or d(Q i i , Q j j ) = -logaF(Q i i , Q j j )
[0099] where F(Q i i , Q j j ) ∈ [0, 1], a is a fixed constant greater than 0 and not equal to 1. We can take a = e as the natural constant. The selection of a here will not make a practical difference to the scheme.
[0100] Furthermore, if each element in the qubit sequence is adjacent to the previous element on the quantum chip C (t, j are non-negative integers, j < t), and all elements are pairwise different, then the qubit sequence p is called a path connecting the qubits . As shown in Figure 6 , p = (Q0, Q3, Q6, Q7, Q8, Q5) is a path connecting the qubits Q0 and Q5. The distance d(p) of the path p is defined as the sum of the distances between each two consecutive qubits in the qubit sequence p In this way, the distance between qubits can be extended to the non-adjacent case, that is, the distance between two non-directly adjacent qubits Q i and Q j j is defined as the minimum value of the distances of the paths connecting these two qubits. In particular, when the path does not exist, the distance is defined as positive infinity.
[0101] d Q (Q i and Q j j ) = min{d(p) | path p ∈ Qt connects Q i and Q j j , t is a non-negative integer}.
[0102] When drawing the topological structure diagram of the quantum chip C on a plane, the qubit Qi Plotted at position g(Q) i )∈R 2 If g:Q→R 2 If it is injective, then it is called a plotting function of the quantum chip C, and its range is denoted as g(Q)={g(Q)}. i )|Q i Let R be the set of real numbers, ∈Q. Based on g and g(Q), the inverse function g can be calculated. -1 :g(Q)→Q. Here g -1 It is bijective, which allows the quantum bit Q to be... i And its plotting function is like g(Q) i They are equivalent to each other.
[0103] Furthermore, we can define the target drawing function g(G) = g(Q), g(E)) for the first topological graph G = (Q, E), which is an undirected graph. The vertex set and edge set are represented by the vertex drawing function g(Q) and the edge drawing function g(E), respectively, where g(E) = {{g(Q)} i ),g(Q j )}|{Q i Q j}∈E}. Since graph G is isomorphic to graph g(G), the first topological graph G can also be equated with the target drawing function g(G) of the topological graph. Thus, a complete characterization of the quantum chip C can be obtained:
[0104] C = (Q, E, d) Q (g).
[0105] In one embodiment, the method for patterning a quantum chip according to this disclosure includes steps S101 to S104, and further includes:
[0106] Step S105: Determine the target number of qubits required for the sub-chip based on the computation task.
[0107] Step S106: Based on the target number and the characterization pattern, determine the multiple target qubits included in the sub-chip.
[0108] Step S107: Determine the second topological structure diagram of the sub-chip based on multiple target qubits.
[0109] Step S108: Visualize the second topology diagram in the characterization diagram.
[0110] According to the embodiments of this disclosure, it should be noted that:
[0111] A quantum subchip can be understood as a chip composed of a subset of the qubits of a quantum chip. In practical applications of quantum computers, not all the qubits on a quantum chip are necessarily used. Therefore, a subset of qubits can be selected from a given quantum chip, and a superconducting quantum subchip can be virtually constructed. This allows the qubits of the subchip to be used to perform corresponding computational tasks, saving the overall computational resources of the quantum chip.
[0112] Multiple target qubits belong to the qubits of the quantum chip; that is, multiple target qubits are part of the qubits of the quantum chip.
[0113] The second topological structure graph consists of multiple nodes and edges connecting them. Each node represents a target qubit, and each node can have corresponding coordinates in the coordinate system of the second topological structure graph. An edge connecting two adjacent nodes indicates a communication relationship between the target qubits corresponding to those nodes. When any two target qubits are directly coupled, they have a communication relationship. When any two target qubits are indirectly coupled through other qubits, they have a communication relationship with those other qubits.
[0114] The structure of the second topology depends on the target number of qubits required by the sub-chip and the communication relationship between each qubit. Depending on the number of qubits and the communication relationship between each qubit, the second topology of the quantum chip can be determined as a rectangular tiled structure, a chain structure, a ring tiled structure, or a 45° oblique square tiled structure.
[0115] Based on the characterization graph, each node in the second topological graph is associated with coordinate information and information about the target qubit it is associated with. Based on the distance weights between the qubits in the characterization graph, the distance weights between the target qubits in the second topological graph can be obtained.
[0116] According to the technology of this disclosure, an operable method is provided for efficiently drawing the topological structure diagram of a quantum chip and its sub-chips, and the relationship between the sub-chip topological structure diagram and its parent chip is represented. In practical applications of quantum computers, not all qubits on a quantum chip are necessarily used. Therefore, how to select a portion of qubits on a given quantum chip and virtually construct a superconducting quantum sub-chip becomes a very important problem. After generating the characterization diagram of the quantum chip using the method of this disclosure, the required sub-chips can be efficiently and systematically characterized based on the characterization diagram, so that the sub-chips can be used to perform subsequent computing tasks. The technology of this disclosure can quantitatively compare the distance characteristics of different sub-chips, providing strong support for further solving the optimal sub-chip problem. In addition, this solution also helps in the design and development of novel quantum chip topologies. The technology of this disclosure has a wide range of applications and can be applied to quantum chips with different structures, without being limited by the implementation path of the quantum chip. The technology of this disclosure has strong systematicity and architecture, and can systematically characterize quantum chips and quantum sub-chips, providing a system architecture for subsequent research. The technology disclosed herein is highly operable, enabling efficient and convenient drawing of topological structure diagrams of quantum chips with different structures, as well as topological structure diagrams of their sub-chips. The technology disclosed herein is highly practical, helping researchers further study the optimal sub-chip problem on quantum chips and providing strong support for solving practical problems.
[0117] In one embodiment, the quantum chip patterning method of this disclosure includes steps S101 to S108, wherein step S106: based on the patterned pattern, determining the plurality of target qubits included in the sub-chip according to the target number, including:
[0118] Step S1061: Determine the target configuration of the sub-chip based on the target quantity.
[0119] Step S1062: Based on the characterization pattern, determine multiple candidate characterization patterns corresponding to the target configuration, wherein multiple nodes on the characterization path of each candidate characterization pattern correspond one-to-one with some qubits of the quantum chip.
[0120] Step S1063: Based on the connectivity of multiple candidate characterization maps, determine the target sub-chip and the multiple target qubits included in the target sub-chip from the multiple candidate sub-chips corresponding to the multiple candidate characterization maps.
[0121] According to the embodiments of this disclosure, it should be noted that:
[0122] The target configuration can be a rectangular tiling structure, a chain structure, a ring tiling structure, or a 45° oblique square tiling structure, etc., without specific limitations.
[0123] The number of candidate characterization maps can be determined as needed. For example, all candidate characterization maps identical to the target configuration structure can be traversed from the characterization map, or a predetermined number of candidate characterization maps identical to the target configuration structure can be traversed from the characterization map. For example, ... Figure 2 As shown, when the target configuration is a rectangle formed by four qubits, it is possible to... Figure 2 The first topological structure diagram of the quantum chip is traversed to obtain six candidate characterization diagrams.
[0124] According to the technology of the embodiments of this disclosure, based on connectivity calculation, the most suitable sub-chip can be found quickly and accurately from the quantum chip.
[0125] In one embodiment, the quantum chip characterization method of this disclosure includes steps S101 to S108, and steps S1061 to S1063, wherein step S1063: determining a target sub-chip and a plurality of target qubits included in the target sub-chip from a plurality of candidate sub-chips corresponding to a plurality of candidate characterization maps based on the connectivity of a plurality of candidate characterization maps, including:
[0126] Based on the distance weights between the qubits of the quantum chip, the distance weights between the qubits corresponding to each candidate pattern are determined.
[0127] Based on the distance weights between some qubits, the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization patterns is determined.
[0128] Based on connectivity, the target sub-chip and the multiple target qubits included in the target sub-chip are determined from multiple candidate sub-chips.
[0129] According to the technology of the embodiments of this disclosure, based on connectivity calculation, the most suitable sub-chip can be found quickly and accurately from the quantum chip.
[0130] In one example, based on the number of qubits required for the sub-chip, for the quantum chip C = Q, E, d Q A subset is constructed from some of the qubits on g). Sub-chips can be defined similarly.
[0131] Where Q is the set of points of the quantum chip's qubits, E is the set of edges representing the communication relationships between the qubits of the quantum chip, and d Q Let be the distance weights between the qubits of the quantum chip, and g be the plotting function of the quantum chip. s The set of points representing the qubits of the sub-chip. Let d represent the set of edges that allow communication between the qubits of a sub-chip.s The distance weights between the qubits of the sub-chip. This is the function for drawing the sub-chip.
[0132] The point set Q of the sub-chip based on the point set Q of the quantum chip s We can define the first topological graph G = (Q, E) in Q. s The above restrictions, namely the second topology diagram This refers to the set of edges in the second topological graph.
[0133] Regarding d s There are several ways to define the choice: one is to choose d s =d Q One approach is to select all qubits on the quantum chip C when calculating the path; the other is based on d and Q. s ,definition Right now
[0134] At this point, when calculating the path, only set Q can be selected. s The qubits in the array.
[0135] Drawing function That is, the function g in the set Q s The limitations on the above. Similarly, the topology diagram of the sub-chip can be... Rather than drawing function like Equivalent to. inverse mapping That is, g -1 In g(Q) s Restrictions on )
[0136] In one example, the method for drawing the first topological structure diagram of a quantum chip includes: given a quantum chip C = (Q, E, d... Q Establish a Cartesian coordinate system on the plane (g). Traverse the quantum bits Q. i ∈Q, in the rectangular coordinate system g(Q) i Plot the qubit Q at ) i Then traverse the edges {Q i Q j}∈E, connecting qubit Q i Q j .
[0137] In one example, the method for drawing the second topological structure diagram of the sub-chip includes: given a quantum chip C = (Q, E, d... Q Sub-chips on g) Traversing the Q qubit i ∈Qs Q i Change to highlighting (visual display). Then traverse the edges. Connecting qubit Q i Q j The border should be highlighted.
[0138] In one example, such as Figure 2 As shown, based on the chip information, the quantum chip includes 12 intact qubits, namely Q0 to Q10. 11 .
[0139] For Q: = {Q0, Q1, ..., Q} 11}, take the plotting function g(Q) i ):=(i / / 3,i mod3),
[0140] Edge set E := {{Q i Q j}|g(Q i )-g(Q j )∈{(0,1),(1,0),(0,-1),(-1,0)}},
[0141] Take any distance function d Q The quantum chip C = (Q, E, d) can be plotted. Q The topology diagram of g) is as follows: Figure 2 As shown, Q4:(1,1) represents the plotting function g(Q4)=(1,1) of the quantum bit Q4. / / Represents the floor division, i.e., the largest integer not exceeding the quotient of the two numbers. Based on this, as Figure 6 As shown, when the target qubits of the sub-chip are determined to be Q0, Q3, Q6, Q7, Q8, and Q5, then in Figure 2 Based on the first topology diagram, the second topology diagram of the display sub-chip is visualized.
[0142] In one example, based on the chip information, the quantum chip may consist of 80 intact qubits. For example... Figure 4 The diagram shown is a first topological structure diagram of the Rigetti 80-qubit superconducting quantum chip. It can be characterized using the characterization method of any embodiment of this disclosure as follows:
[0143] Take the set of all qubit formation points of the quantum chip, Q: = {Q i |i=100i1+10i2+i3,i1=0,1,i2=0,1,…,4,i3=0,1,…,7};
[0144] Take the drawing function as
[0145] Where (i1,i2,i3) = (i / / 100,i / / 10,imod 10);
[0146] Take the edge set of the quantum chip:
[0147]
[0148] This allows us to draw the first topological diagram of the Rigetti 80-qubit superconducting quantum chip.
[0149] like Figure 7 As shown, this disclosure provides a quantum chip characterization apparatus, comprising:
[0150] The first determining module 701 is used to determine the number of qubits and the quantum gate information of the quantum chip based on the chip information of the quantum chip, wherein the quantum gate information characterizes the communication relationship between each qubit of the quantum chip.
[0151] The second determining module 702 is used to determine a first topological structure diagram of the quantum chip based on the quantity information and the quantum gate information, wherein the first topological structure diagram is composed of multiple nodes representing each quantum bit and edges representing the communication relationship between every two directly adjacent quantum bits of the quantum chip.
[0152] The third determining module 703 is used to determine the distance weights between each qubit based on the quantum gate information.
[0153] The generation module 704 is used to obtain the characterization pattern of the quantum chip based on the distance weight and the first topological structure diagram.
[0154] In one implementation, the third determining module 703 includes:
[0155] The first determining submodule is used to determine every two directly adjacent qubits in the quantum chip based on the quantum gate information.
[0156] The second determining submodule is used to determine the fidelity of the two-qubit gate between every two directly adjacent qubits based on the chip information.
[0157] The third determination submodule is used to determine the distance weights between each quantum bit based on the fidelity.
[0158] In one implementation, the third determining submodule is used to:
[0159] Based on the fidelity, determine the first distance weight between every two directly adjacent qubits.
[0160] Based on the first distance weight, the second distance weight between every two indirectly adjacent qubits is determined.
[0161] Based on the first distance weight and the second distance weight, the distance weight between each qubit is obtained.
[0162] In one implementation, the second determining module 702 includes:
[0163] The fourth determination submodule is used to determine the target drawing function based on the quantity information and quantum gate information.
[0164] The fifth determining submodule is used to generate the first topological structure diagram of the target structure shape of the quantum chip based on the target drawing function.
[0165] In one embodiment, the target structure shape is a rectangular tiling structure, a one-dimensional chain structure, a ring tiling structure, or a 45° oblique square tiling structure.
[0166] In one implementation, the fourth determining submodule is used to:
[0167] Based on the quantity information and quantum gate information, multiple initial drawing functions are determined.
[0168] Based on preset characterization rules and multiple initial drawing functions, the target drawing function is determined.
[0169] In one implementation, the fifth determining submodule is used to:
[0170] Based on the point drawing function in the target drawing function, multiple nodes representing each qubit are generated in the coordinate system, where each node contains corresponding coordinate information.
[0171] Based on the edge drawing function in the target drawing function, an edge is generated between the two nodes corresponding to every two adjacent qubits, where the two nodes belong to multiple nodes.
[0172] Based on the positional relationships of multiple nodes and edges, the correspondence between multiple nodes and multiple qubits of the quantum chip is determined.
[0173] Based on multiple nodes, edges, and corresponding relationship information, a first topological structure diagram of the target structure shape of the quantum chip is generated.
[0174] In one embodiment, the quantum chip patterning apparatus further includes:
[0175] The fourth determining module is used to determine the target number of qubits required for the sub-chip based on the computing task.
[0176] The fifth determining module is used to determine the multiple target qubits included in the sub-chip based on the target quantity and the characterization pattern.
[0177] The sixth determining module is used to determine the second topological structure diagram of the sub-chip based on multiple target qubits.
[0178] The visualization module is used to visualize the second topology diagram in the characterization diagram.
[0179] In one implementation, the fifth determining module includes:
[0180] The sixth determination submodule is used to determine the target configuration of the sub-chip based on the target quantity.
[0181] The seventh determination submodule is used to determine multiple candidate characterization patterns corresponding to the target configuration based on the characterization pattern. Among them, multiple nodes on the characterization path of each candidate characterization pattern correspond one-to-one with some qubits of the quantum chip.
[0182] The eighth determination submodule is used to determine the target subchip and the target qubits included in the target subchip from the multiple candidate subchips corresponding to the multiple candidate characterization maps based on the connectivity of the multiple candidate characterization maps.
[0183] In one implementation, the eighth determining submodule is used for:
[0184] Based on the distance weights between the qubits of the quantum chip, the distance weights between the qubits corresponding to each candidate pattern are determined.
[0185] Based on the distance weights between some qubits, the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization patterns is determined.
[0186] Based on connectivity, the target sub-chip and the multiple target qubits included in the target sub-chip are determined from multiple candidate sub-chips.
[0187] The specific functions and examples of each module and submodule of the apparatus in this disclosure can be found in the relevant descriptions of the corresponding steps in the above method embodiments, and will not be repeated here.
[0188] The acquisition, storage, and application of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.
[0189] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.
[0190] Figure 8A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.
[0191] like Figure 8 As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 802 or a computer program loaded from storage unit 808 into random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interface 805 is also connected to bus 804.
[0192] Multiple components in device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of monitors, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.
[0193] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as the quantum chip characterization method. For example, in some embodiments, the quantum chip characterization method can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the quantum chip characterization method described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform the quantum chip characterization method by any other suitable means (e.g., by means of firmware).
[0194] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.
[0195] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.
[0196] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
[0197] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).
[0198] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.
[0199] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.
[0200] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.
[0201] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A method for patterning a quantum chip, comprising: Based on the chip information of the quantum chip, the number of qubits and the quantum gate information of the quantum chip are determined, wherein the quantum gate information characterizes the communication relationship between each qubit of the quantum chip; Based on the quantity information and the quantum gate information, a first topological structure diagram of the quantum chip is determined, wherein the first topological structure diagram is composed of multiple nodes representing each quantum bit and edges representing the communication relationship between every two directly adjacent quantum bits of the quantum chip; Based on the fidelity obtained from the quantum gate information, the distance weights between the qubits are determined; and Based on the distance weights and the first topological structure diagram, a pattern of the quantum chip is obtained; Also includes: Based on the computational task, determine the target number of qubits required for the sub-chip; Based on the target quantity, determine the target configuration of the sub-chip; Based on the characterization pattern, multiple candidate characterization patterns corresponding to the target configuration are determined, wherein multiple nodes on the characterization path of each candidate characterization pattern correspond one-to-one with a portion of the qubits of the quantum chip; Based on the distance weights between the qubits of the quantum chip, the distance weights between the qubits corresponding to each candidate pattern are determined; Based on the distance weights between the partial qubits, the connectivity of the multiple candidate sub-chips corresponding to the multiple candidate characterization patterns is determined; Based on the connectivity, a target sub-chip and a plurality of target qubits included in the target sub-chip are determined from the plurality of candidate sub-chips; Based on the plurality of target qubits, a second topological structure diagram of the sub-chip is determined; The second topology diagram is visualized in the characterization diagram.
2. The method according to claim 1, wherein, Determining the distance weights between each qubit based on the fidelity obtained from the quantum gate information includes: Based on the quantum gate information, determine every two directly adjacent qubits in the quantum chip; Based on the chip information, determine the fidelity of the two-qubit gate between every two directly adjacent qubits; Based on the fidelity, the distance weights between each quantum bit are determined.
3. The method according to claim 2, wherein, Based on the fidelity, the distance weights between the qubits are determined, including: Based on the fidelity, a first distance weight is determined between every two directly adjacent qubits; Based on the first distance weight, a second distance weight is determined between every two indirectly adjacent qubits; Based on the first distance weight and the second distance weight, the distance weight between each qubit is obtained.
4. The method according to claim 1, wherein, Based on the quantity information and the quantum gate information, the first topological structure diagram of the quantum chip is determined, including: Based on the quantity information and the quantum gate information, the target drawing function is determined; Based on the target drawing function, a first topological structure diagram of the target structure shape of the quantum chip is generated.
5. The method according to claim 4, wherein, The target structure can be a rectangular tiling structure, a one-dimensional chain structure, a ring tiling structure, or a 45° oblique square tiling structure.
6. The method according to claim 4, wherein, Based on the quantity information and the quantum gate information, the target drawing function is determined, including: Based on the quantity information and the quantum gate information, multiple initial drawing functions are determined; Based on the preset characterization rules and the multiple initial drawing functions, the target drawing function is determined.
7. The method according to claim 4, wherein, Based on the target drawing function, a first topological structure diagram of the target structure shape of the quantum chip is generated, including: Based on the point drawing function in the target drawing function, multiple nodes representing each qubit are generated in the coordinate system, wherein each of the multiple nodes contains corresponding coordinate information; According to the edge drawing function in the target drawing function, an edge is generated between the two nodes corresponding to every two adjacent qubits, wherein the two nodes belong to the plurality of nodes; Based on the positional relationship between the plurality of nodes and the edges, the correspondence information between the plurality of nodes and the plurality of qubits of the quantum chip is determined; Based on the multiple nodes, the edges, and the corresponding relationship information, a first topological structure diagram of the target structural shape of the quantum chip is generated.
8. A patterning apparatus for a quantum chip, comprising: The first determining module is used to determine the number of qubits and the quantum gate information of the quantum chip based on the chip information of the quantum chip, wherein the quantum gate information characterizes the communication relationship between each qubit of the quantum chip; The second determining module is used to determine a first topological structure diagram of the quantum chip based on the quantity information and the quantum gate information, wherein the first topological structure diagram is composed of multiple nodes representing each quantum bit and edges representing the communication relationship between every two directly adjacent quantum bits of the quantum chip; The third determining module is used to determine the distance weights between the qubits based on the fidelity obtained from the quantum gate information; and A generation module is used to obtain a pattern of the quantum chip based on the distance weights and the first topological structure diagram. Also includes: The fourth determining module is used to determine the target number of qubits required for the sub-chip based on the computing task. The fifth determining module is used to: determine the target configuration of the sub-chip based on the target quantity; determine multiple candidate characterization patterns corresponding to the target configuration based on the characterization pattern, wherein multiple nodes on the characterization path of each candidate characterization pattern correspond one-to-one with some qubits of the quantum chip; determine the distance weight between the qubits corresponding to each candidate characterization pattern based on the distance weight between each qubit of the quantum chip; determine the connectivity of the multiple candidate sub-chips corresponding to the multiple candidate characterization patterns based on the distance weight between the qubits; and determine the target sub-chip and the multiple target qubits included in the target sub-chip from the multiple candidate sub-chips based on the connectivity. The sixth determining module is used to determine the second topological structure diagram of the sub-chip based on the plurality of target qubits; A visualization module is used to visualize the second topology diagram in the characterization diagram.
9. The apparatus according to claim 8, wherein, The third determining module includes: The first determining submodule is used to determine every two directly adjacent qubits in the quantum chip based on the quantum gate information; The second determining submodule is used to determine the fidelity of the two-qubit gate between every two directly adjacent qubits based on the chip information. The third determining submodule is used to determine the distance weights between each quantum bit based on the fidelity.
10. The apparatus according to claim 9, wherein, The third determining submodule is used for: Based on the fidelity, a first distance weight is determined between every two directly adjacent qubits; Based on the first distance weight, a second distance weight is determined between every two indirectly adjacent qubits; Based on the first distance weight and the second distance weight, the distance weight between each qubit is obtained.
11. The apparatus according to claim 8, wherein, The second determining module includes: The fourth determining submodule is used to determine the target drawing function based on the quantity information and the quantum gate information; The fifth determining submodule is used to generate a first topological structure diagram of the target structure shape of the quantum chip according to the target drawing function.
12. The apparatus according to claim 11, wherein, The target structure can be a rectangular tiling structure, a one-dimensional chain structure, a ring tiling structure, or a 45° oblique square tiling structure.
13. The apparatus according to claim 11, wherein, The fourth determining submodule is used for: Based on the quantity information and the quantum gate information, multiple initial drawing functions are determined; Based on the preset characterization rules and the multiple initial drawing functions, the target drawing function is determined.
14. The apparatus according to claim 11, wherein, The fifth determining submodule is used for: Based on the point drawing function in the target drawing function, multiple nodes representing each qubit are generated in the coordinate system, wherein each of the multiple nodes contains corresponding coordinate information; According to the edge drawing function in the target drawing function, an edge is generated between the two nodes corresponding to every two adjacent qubits, wherein the two nodes belong to the plurality of nodes; Based on the positional relationship between the plurality of nodes and the edges, the correspondence information between the plurality of nodes and the plurality of qubits of the quantum chip is determined; Based on the multiple nodes, the edges, and the corresponding relationship information, a first topological structure diagram of the target structural shape of the quantum chip is generated.
15. An electronic device comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.
16. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-7.
17. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1-7.