Scanning control circuit, display module and display device

Abstract

Embodiments of the present application relate to a scanning control circuit, a display module and a display device. The scanning control circuit is used to be connected with a gate drive module and at least one P-type transistor in a pixel circuit. The scanning control circuit is configured to receive an enable control signal and an initial scanning signal from the gate drive module respectively, and output a target scanning signal to the connected P-type transistor according to the enable control signal and the initial scanning signal. If the enable control signal is in a first level state, the level state of the target scanning signal is the same as that of the initial scanning signal. If the enable control signal is in a second level state, the level state of the target scanning signal is a high level state. The first level state and the second level state are different. Based on the above structure, the scanning control circuit can realize local refresh of a display screen provided with multiple pixel circuits.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a scanning control circuit, a display module, and a display device. Background Technology

[0002] With the continuous development of technology, people have increasingly higher requirements for electronic devices, such as higher refresh rates for displays. However, when a display is operating at high refresh rates, its power consumption is high, which significantly affects the battery life of portable electronic devices. Summary of the Invention

[0003] Therefore, it is necessary to provide a scanning control circuit, display module, and display device that can perform partial refresh of the display screen to reduce power consumption, thereby addressing the aforementioned technical problems.

[0004] In a first aspect, this application provides a scan control circuit for connection to a gate driving module and to at least one first target transistor in a pixel circuit. The scan control circuit is configured to receive an enable control signal and an initial scan signal from the gate driving module, respectively, and output a target scan signal to the connected first target transistor according to the enable control signal and the initial scan signal.

[0005] Wherein, if the enable control signal is at a first level, the level of the target scan signal is the same as that of the initial scan signal; if the enable control signal is at a second level, the level of the target scan signal is a target level, the first level and the second level are different, and the target level is the level that turns off the first target transistor.

[0006] Secondly, this application provides a display module, including:

[0007] A gate driving module is used to generate a first initial scan signal for controlling the first target transistor;

[0008] The first scan control circuit includes the scan control circuit described above, and is used to output a first target scan signal to the connected first target transistor according to a first enable control signal and a first initial scan signal.

[0009] Multiple pixel circuits, each pixel circuit including at least one first target transistor, wherein at least a portion of the first target transistor in the pixel circuits is connected to the scan control circuit.

[0010] Thirdly, this application provides a display device, including:

[0011] As shown in the above display module;

[0012] The controller is connected to the gate driving module and the first scan control circuit of the display module, respectively, and is used to drive the gate driving module to generate a first initial scan signal and generate the first enable control signal.

[0013] The aforementioned scanning control circuit, display module, and display device, by placing a scanning control circuit between the gate driving module and the pixel circuit, allow the scanning control circuit to generate a target scanning signal that can periodically turn the first target transistor on and off only when it receives an enable control signal at a first level, thereby refreshing the pixel circuit that receives the target scanning signal. Furthermore, when it receives an enable control signal at a second level, the scanning control circuit can generate a target scanning signal that remains at the target level, controlling the connected first target transistor to remain off, thus preventing data refresh of the corresponding pixel circuit and maintaining the data from the previous frame. Based on this structure, the scanning control circuit can achieve signal control based on the initial scanning signal generated by the gate driving module, thereby enabling partial refresh of a display screen with multiple pixel circuits. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 The circuit diagram for the pixel circuit of the 7T1C architecture;

[0016] Figure 2 The circuit diagram for the pixel circuit of the 8T1C architecture;

[0017] Figure 3 This is a circuit diagram of the GOA circuit used to generate the scan signal for the P-type transistor.

[0018] Figure 4 for Figure 3 Signal timing diagram of the GOA circuit in the embodiment;

[0019] Figure 5 This is a circuit diagram of the GOA circuit used to generate the scan signal for an N-type transistor.

[0020] Figure 6 for Figure 5 Signal timing diagram of the GOA circuit in the embodiment;

[0021] Figure 7This is one of the connection structure diagrams of a scanning control circuit according to an embodiment;

[0022] Figure 8 This is a second schematic diagram of the connection structure of a scanning control circuit according to an embodiment;

[0023] Figure 9 One of the timing diagrams for a scanning control circuit according to an embodiment;

[0024] Figure 10 The second timing diagram of a scanning control circuit is shown in one embodiment.

[0025] Figure 11 This is a schematic diagram illustrating the refresh area division of a display screen according to one embodiment;

[0026] Figure 12 This is one of the schematic diagrams of a scanning control circuit according to an embodiment;

[0027] Figure 13 This is a second schematic diagram of the scanning control circuit in one embodiment;

[0028] Figure 14 This is the third schematic diagram of the scanning control circuit in one embodiment;

[0029] Figure 15 for Figure 14 One of the operating modes of the scanning control circuit in the embodiment;

[0030] Figure 16 for Figure 14 The second operating mode of the scanning control circuit in the embodiment;

[0031] Figure 17 for Figure 14 The third mode of operation of the scanning control circuit in the embodiment;

[0032] Figure 18 for Figure 14 The fourth mode of operation of the scanning control circuit in the embodiment;

[0033] Figure 19 This is a fourth schematic diagram of the scanning control circuit in one embodiment;

[0034] Figure 20 for Figure 19 One of the operating modes of the scanning control circuit in the embodiment;

[0035] Figure 21 for Figure 19 The second operating mode of the scanning control circuit in the embodiment;

[0036] Figure 22 for Figure 19 The third mode of operation of the scanning control circuit in the embodiment;

[0037] Figure 23 for Figure 19 The fourth mode of operation of the scanning control circuit in the embodiment;

[0038] Figure 24 This is a schematic diagram of the structure of a display module according to one embodiment;

[0039] Figure 25 This is a schematic diagram of the structure of a display device according to one embodiment.

[0040] Component designation explanation:

[0041] Scan control circuit: 10; First switch module: 100; Second switch module: 200; First switch unit: 210; Second switch unit: 220; First scan control circuit: 11; Second scan control circuit: 12; Gate drive module: 20; Pixel circuit: 30. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0043] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first level state may be referred to as a second level state, and similarly, a second level state may be referred to as a first level state. Both the first level state and the second level state are level states, but they are not the same level state.

[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. In the description of this application, "several" means at least one, such as one, two, etc., unless otherwise explicitly specified.

[0045] This application provides a scanning control circuit, which works in conjunction with the gate driving module and the display screen in a display module to display an image. The display screen has a display area (Active Area, AA) and a non-display area. The display area has multiple pixel circuits and multiple light-emitting elements. The pixel circuits are respectively connected to the multiple light-emitting elements, and the pixel circuits control the brightness of the light-emitting elements so that the multiple pixel circuits work together to display the image to be displayed.

[0046] Figure 1 The circuit diagram for the pixel circuit of the 7T1C architecture is shown in the reference. Figure 1 The pixel circuit of the 7T1C architecture includes 7 transistors and 1 storage capacitor. The driving circuit includes a gate reset unit, an anode reset unit, a data writing unit, a threshold compensation unit, and a light-emitting control unit.

[0047] Specifically, transistor T3 can be called a driving transistor. The first terminal of transistor T3 receives the data signal Data, and the second terminal outputs the driving current. The value of the driving current is determined by the data signal Data and directly affects the brightness of the light-emitting device. The gate reset unit includes transistor T1. The first terminal of transistor T1 is connected to the reset voltage signal Vinit1, and the second terminal of transistor T1 is connected to the gate of transistor T3. Transistor T1 is used to pull down the gate voltage of transistor T3 to the voltage of the reset voltage signal Vinit1 based on the scan signal received at the gate, thereby resetting the gate of transistor T3. The anode reset unit includes transistor T7. The first terminal of transistor T7 receives the reset voltage signal Vinit2, and the second terminal of transistor T7 is connected to the anode of the light-emitting device. After the gate of transistor T3 is reset, transistor T7 is used to pull down the anode voltage of the light-emitting device to the voltage of the reset voltage signal Vinit2 based on the scan signal received at the gate, thereby resetting the anode of the light-emitting device. The voltage of the reset voltage signal Vinit2 can be understood as the initial charging voltage of the anode of the light-emitting device.

[0048] The data writing unit includes transistor T4. The first terminal of transistor T4 is connected to the data signal line, and the second terminal of transistor T4 is connected to the first terminal of transistor T3. Transistor T4 is used to control the on / off state of the signal transmission path between the data signal and the first terminal of transistor T3 according to the scan signal. The threshold compensation unit includes transistor T2 and storage capacitor C1. Storage capacitor C1 is connected to the first voltage terminal ELVDD and the gate of transistor T3. The first terminal of transistor T2 is connected to the second terminal of transistor T3, and the second terminal of transistor T2 is connected to the gate of transistor T3. Transistor T2 is used to control the on / off state of the signal transmission path between the gate and the second terminal of transistor T3 according to the scan signal, thereby storing the compensation result in storage capacitor C1. By setting the threshold compensation unit, the threshold voltage of transistor T3 can be compensated, thereby avoiding the threshold voltage of transistor T3 from affecting the brightness of the light-emitting device. The light-emitting control unit includes transistor T5 and transistor T6. The first terminal of transistor T5 is connected to the first voltage terminal ELVDD, and the second terminal of transistor T5 is connected to the first terminal of transistor T3. Transistor T5 is used to control the on / off state of the signal transmission path between the first voltage terminal ELVDD and the first electrode of transistor T3 according to the light emission control signal EM. The first electrode of transistor T6 is connected to the second electrode of transistor T3, and the second electrode of transistor T6 is connected to the anode of the light-emitting device. Transistor T6 is used to control the on / off state of the signal transmission path between the second electrode of transistor T3 and the anode of the light-emitting device according to the light emission control signal EM.

[0049] It should be noted that the transistors in the pixel circuit can be either P-type or N-type transistors, and the types of transistors do not have to be exactly the same. Specifically, if the pixel circuit is a Low Temperature Poly-silicon (LTPS) type circuit, then all transistors in the pixel circuit can be P-type transistors. Based on the driving timing of the pixel circuit, transistors T2, T4, and T7 can be connected to the same scan signal, transistor T1 can be connected to another scan signal, and transistors T5 and T6 can be connected to the light emission control signal. If the pixel circuit is a Low Temperature Polycrystalline Oxide (LTPO) type circuit, then some transistors in the pixel circuit can be N-type transistors, for example... Figure 1 Transistors T1 and T2 shown are N-type transistors, while the remaining transistors T3-T7 are P-type transistors. Accordingly, transistors T2 and T4 need to be connected to different scan signals. In some embodiments, all transistors in the pixel circuit may be N-type transistors. It is understood that the pixel circuit may also be... Figure 2Other architectures, such as the 8T1C shown, will not be described in detail here. The scanning control circuit of this embodiment can be applied to any pixel circuit that includes P-type transistors.

[0050] The gate driving module is used to generate scan signals to control the on and off states of each transistor in the pixel circuit. The gate driving module can be a gate-driven-on-array (GOA) circuit, which can reduce the size and manufacturing cost of the display module. In all embodiments of this application, the GOA circuit is used as an example for the provided figures. When the pixel circuit includes only one type of transistor, the gate driving module can include only two GOA circuits, which are used to generate the light emission control signal and the transistor scan signal, respectively. When the pixel circuit includes both P-type and N-type transistors, since the P-type transistor turns on in response to a low-level signal and the N-type transistor turns on in response to a high-level signal, the gate driving module also needs to include three or five GOA circuits to control the on / off states of each transistor. The three GOA circuits are used to generate the light emission control signal, the scan signal for the P-type transistor, and the scan signal for the N-type transistor, respectively. For pixel circuits with more complex architectures, a greater number of GOA circuits are required, such as five groups. Optionally, if the gate drive module includes a large number of GOA circuit groups, multiple GOA circuit groups can be placed on both sides of the display to avoid excessively wide black borders on one side of the display. In related technologies, to reduce the power consumption of the display, only an overall frequency reduction method can be used, but the overall frequency conversion strategy is not flexible enough, thus affecting the user's viewing experience.

[0051] Specifically, the circuit diagram of the GOA circuit can be determined according to the type of scan signal generated for the P-type transistor and the N-type transistor as needed. Figure 3 The circuit diagram is for the GOA circuit used to generate the scan signal of the P-type transistor. The circuit in this embodiment can be referred to as the GOA circuit of the 8T2C architecture. Figure 4 for Figure 3 The signal timing diagram of the GOA circuit in the embodiment is shown in the reference diagram. Figure 4 The low-level state of the scan signal G_out is enabled to control the P-type transistor that receives the scan signal G_out to turn on. Figure 5 The circuit diagram is for a GOA circuit used to generate scan signals for N-type transistors. The circuit in this embodiment can be referred to as a 10T3C architecture GOA circuit. Figure 6 for Figure 5 The signal timing diagram of the GOA circuit in the embodiment is shown in the reference diagram. Figure 6The high-level state of the scan signal G_out enables the N-type transistor that receives the scan signal G_out to turn on. The STV signal received by the GOA circuit can come from an external controller, which can be, but is not limited to, any of a display driver IC (DDIC) and an application processor (AP).

[0052] Therefore, this application provides a scanning control circuit 10 that can partially refresh the display screen to reduce the power consumption of the display screen. Figure 7 This is one of the connection structure diagrams of the scanning control circuit 10 in one embodiment, with reference to... Figure 7 The scan control circuit 10 is connected to the gate drive module 20 and to at least one first target transistor in the pixel circuit 30. Here, the first target transistor refers to a certain type of transistor, not specifically a particular transistor in the pixel circuit 30. Specifically, the first target transistor can be either a P-type transistor or an N-type transistor. It is understood that... Figure 7 Only one scan control circuit 10, a gate drive module 20, and a pixel circuit 30 connected to the scan control circuit 10 are shown. In actual products, the display module will include multiple gate drive modules 20 and multiple pixel circuits 30. Moreover, when the pixel circuit 30 includes multiple first target transistors, the gate drive module 20 can be connected to any number of the first target transistors. Therefore, Figure 7 The image does not specify which first target transistor in the gate driving module 20 the pixel circuit 30 is connected to. The scan control circuit 10 is configured to receive an enable control signal EN and an initial scan signal Scan from the gate driving module 20, and output a target scan signal OP to the connected first target transistor according to the enable control signal EN and the initial scan signal Scan.

[0053] In one exemplary embodiment, the enable control signal EN can originate from the display driver chip, which is the mainstream controller in current display devices. It is understood that some display driver chips can integrate touch functionality and can be called Touch and Display Driver Integration (TDDI) chips. In another exemplary embodiment, the enable control signal EN can also originate from the application processor, which can also be called an application chip. Application chips are typically system-on-chips (SoCs). Due to the high integration of SoCs, the size of the display device can be significantly reduced. Therefore, the appropriate controller can be selected to generate the enable control signal EN according to the specific hardware scheme of the display device; this embodiment does not impose any limitations.

[0054] Specifically, the enable control signal EN can be understood as a clock signal. If the enable control signal EN is in a first level state, then the level state of the target scan signal OP is the same as that of the initial scan signal Scan. That is, based on the initial scan signal Scan with the first level state, the scan control circuit 10 can generate a target scan signal OP that can drive the first target transistor to periodically switch on and off, so that the pixel circuit 30 receiving the target scan signal OP will be refreshed. If the enable control signal EN is in a second level state, then the level state of the target scan signal OP is the target level state, which is the level state that turns off the first target transistor. That is, based on the initial scan signal Scan with the second level state, the scan control circuit 10 can generate a target scan signal OP that remains in the target level state to control the connected first target transistor to remain off, thereby preventing the corresponding pixel circuit 30 from being refreshed and thus maintaining the data of the previous frame. In this embodiment, the first level state and the second level state are different. For example, the first level state can be a low level state and the second level state can be a high level state, or the first level state can be a high level state and the second level state can be a low level state. The first level state and the second level state can be determined according to the type of the first target transistor, which is not limited in this embodiment.

[0055] Therefore, based on the above structure, only by changing the level of the enable control signal EN received by the scan control circuit 10, partial refresh of the display screen equipped with multiple pixel circuits 30 can be achieved. Specifically, Figure 8 This is a second schematic diagram of the connection structure of the scanning control circuit 10 in one embodiment. Figure 8 Multiple scan control circuits 10 are shown, along with correspondingly connected multiple gate drive modules 20 and multiple pixel circuits 30. (Reference) Figure 8Multiple pixel circuits 30 are arranged in an array. A scan control circuit 10 is connected to the multiple pixel circuits 30 located in the same row and to a corresponding gate driving module 20. The multiple gate driving modules 20 are connected in series and transmit the initial scan signal Scan line by line from top to bottom. Thus, the gate driving module 20 of the previous level triggers the gate driving module 20 of the next level to generate the initial scan signal Scan, so that all gate driving modules 20 output the initial scan signal Scan in sequence, thereby realizing the line-by-line refresh of the pixel circuits 30 that need to be refreshed.

[0056] Taking the first level state as a low level state as an example, Figure 9 One of the timing diagrams for a scanning control circuit 10 according to an embodiment, see reference. Figure 9 When the scan control circuit 10 receives a low-level enable control signal EN, the target scan signal OP output by it is at the same level as the initial scan signal Scan, and the pixel circuit 30 of the corresponding row refreshes the data. Conversely, when the scan control circuit 10 receives a high-level enable control signal EN, the target scan signal OP output by it is at a high level, and the pixel circuit 30 of the corresponding row retains its data unchanged. Taking the first high-level state as an example... Figure 10 This is a second timing diagram of the scanning control circuit 10 according to one embodiment, referencing... Figure 10 When the scan control circuit 10 receives the high-level enable control signal EN, the target scan signal OP output by the scan control circuit 10 is at the same level as the initial scan signal Scan, and the pixel circuit 30 of the corresponding row refreshes the data. When the scan control circuit 10 receives the low-level enable control signal EN, the target scan signal OP output by the scan control circuit 10 is at a low level, and the pixel circuit 30 of the corresponding row keeps the data unchanged.

[0057] Figure 11 This is a schematic diagram of the refresh area division of a display screen according to one embodiment, with reference to... Figure 11 Depending on the display scenario, the required refresh frequency for each pixel circuit 30 can be determined. If the required refresh frequencies for each pixel circuit 30 are the same, each refresh control circuit can be controlled to output a target scan signal OP with the same waveform as the initial scan signal Scan, thereby controlling the display screen to perform a global refresh. If the required refresh frequencies for each pixel circuit 30 are not completely identical, the display screen can be divided into multiple refresh areas based on the refresh frequency. Each refresh area includes at least one row of pixel circuits 30, and adjacent refresh areas have different refresh frequencies. Figure 11In the illustrated embodiment, the display screen can be divided into three refresh areas. The pixel circuits 30 in the upper and lower refresh areas have the same refresh frequency, while the refresh frequency of the pixel circuits 30 in the middle refresh area is different. For example, the refresh area of ​​the pixel circuits 30 in the middle refresh area can be larger than the other two refresh areas. It is understood that the above three refresh areas are for illustrative purposes only and are not intended to limit the scope of protection of this embodiment. The display screen can also be divided into other numbers of refresh areas, such as two, four, etc. Moreover, when the display screen is divided into three or more refresh areas, the refresh frequencies of the pixel circuits 30 in each refresh area can also be different, which is not limited in this embodiment. Therefore, based on the scanning control circuit 10 of this embodiment, the display screen can be partially refreshed and adaptively down-clocked according to the partial content of the image to be displayed, thereby making the frequency conversion strategy more flexible and intelligent. Moreover, the scanning control circuit 10 of this embodiment can be configured according to the transistor type in the pixel circuit 30, which can avoid the problem that the pixel circuit 30 cannot support partial refresh due to transistor type mismatch.

[0058] Figure 12 This is one of the structural schematic diagrams of a scanning control circuit 10 according to an embodiment, with reference to... Figure 12 In one embodiment, the scanning control circuit 10 includes a first switch module 100 and a second switch module 200.

[0059] Specifically, the first switch module 100 is used to receive the enable control signal EN and generate a first node signal based on the enable control signal EN. The first node signal V A1 The voltage level of the first node signal V is different from that of the enable control signal EN. That is, if the enable control signal EN is high, then the voltage level of the first node signal V... A1 The level state is low. If the enable control signal EN is low, then the first node signal V A1 The voltage level is high. The second switch module 200 is connected to the first switch module 100 and is used to connect to the gate drive module 20, and according to the initial scan signal Scan and the first node signal V A1 The target scan signal OP is generated. In this embodiment, the first switch module 100 operates in response to the enable control signal EN, and the second switch module 200 operates in response to the initial scan signal Scan, so that the scan control circuit 10 can determine the level state of the target scan signal OP according to the enable control signal EN and the initial scan signal Scan, so as to output the corresponding target scan signal OP and realize the partial refresh of the display screen.

[0060] Figure 13This is a second schematic diagram of the scanning control circuit 10 according to one embodiment, with reference to... Figure 13 In one embodiment, the first switching module 100 includes a first P-type transistor T1 and a first N-type transistor T2. The first terminal of the first P-type transistor T1 is connected to a first voltage terminal Vdc1, which transmits a high-level signal. The gate of the first P-type transistor T1 receives the enable control signal EN. The first terminal of the first N-type transistor T2 is connected to the second terminal of the first P-type transistor T1. The second terminal of the first N-type transistor T2 is connected to a second voltage terminal Vdc2, which transmits a low-level signal. The gate of the first N-type transistor T2 receives the enable control signal EN. A high-level signal at the first voltage terminal Vdc1 means Vdc1 > Vth_T1, and a low-level signal at the second voltage terminal Vdc2 means Vdc2 > Vth_T2. Specifically, the connection node between the first P-type transistor T1 and the first N-type transistor T2 is a first node A1 for outputting the first node signal. That is, if the enable control signal EN is at a low level, the first P-type transistor T1 turns on the first node A1 and the first voltage terminal Vdc1, making the first node signal high. If the enable control signal EN is at a high level, the first N-type transistor T2 turns on the first node A1 and the second voltage terminal Vdc2, making the first node signal low. Therefore, in this embodiment, by setting the first P-type transistor T1 and the first N-type transistor T2, the level of the first node signal can be controlled to be different from the level of the enable control signal EN.

[0061] Continue to refer to Figure 13In one embodiment, the first switching module 100 further includes a second P-type transistor T3 and a second N-type transistor T4. The first terminal of the second P-type transistor T3 is connected to the first voltage terminal Vdc1, and the gate of the second P-type transistor T3 is connected to the first node A1. The first terminal of the second N-type transistor T4 is connected to the second terminal of the second P-type transistor T3, and the second terminal of the second N-type transistor T4 is connected to the second voltage terminal Vdc2. The gate of the second N-type transistor T4 is connected to the first node A1. Specifically, if the level of the first node signal is low, the second P-type transistor T3 conducts the gate of the first N-type transistor T2 and the first voltage terminal Vdc1, so that the gate of the first N-type transistor T2 is at a high level, thereby keeping the first N-type transistor T2 on. If the level of the first node signal is high, the second N-type transistor T4 conducts the gate of the first P-type transistor T1 and the second voltage terminal Vdc2, so that the gate of the first P-type transistor T1 is at a low level, thereby keeping the first P-type transistor T1 on. Therefore, in this embodiment, by setting the second P-type transistor T3 and the second N-type transistor T4, positive feedback can be achieved to the first P-type transistor T1 and the first N-type transistor T2, thereby clamping the voltage of the gate of the first P-type transistor T1 and the gate of the first N-type transistor T2, thus maintaining the conduction state of one of the first P-type transistor T1 and the first N-type transistor T2. By maintaining the above-mentioned conduction state, the influence of environmental factors such as temperature changes on the level state of the first node signal can be avoided, thereby preventing the second switching module 200 from making incorrect switching due to fluctuations in the level state of the first node signal, and thus improving the stability and reliability of the scan control circuit 10.

[0062] Figure 14 This is a third schematic diagram of the scanning control circuit 10 according to one embodiment, referencing... Figure 14 In one embodiment, the first target transistor is of type P, and the target level state is high. The second switch module 200 is configured to generate the target scan signal OP in a low-level state if the level state of the first node signal is high and the level state of the initial scan signal Scan is low; otherwise, it generates the target scan signal OP in a high-level state. In this embodiment, the switching of the second switch module 200 can be controlled by the cooperation of the first node signal and the initial scan signal Scan, so that the scan control circuit 10 outputs the required target scan signal OP, thereby achieving partial refresh of the display screen.

[0063] Continue to refer to Figure 14In one embodiment, the second switching module 200 includes a first switching unit 210 and a second switching unit 220. The first switching unit 210 is connected to the first switching module 100 and is used to connect to the gate driving module 20. If the level of the initial scan signal Scan is high, the first switching unit 210 generates a second node signal with a low level. That is, if the level of the initial scan signal Scan is high, the level of the second node signal is low regardless of the level of the first node signal. If the level of the initial scan signal Scan is low, the first switching unit 210 generates a second node signal with the same level as the first node signal. That is, if the levels of the initial scan signal Scan and the first node signal are low, the level of the second node signal is also low. If the level of the initial scan signal Scan is low and the level of the first node signal is high, the level of the second node signal is also high. The second switching unit 220 is connected to the first switching unit 210 and is used to generate the target scanning signal OP based on the second node signal. The level state of the second node signal is opposite to the level state of the target scanning signal OP. That is, if the level state of the second node signal is low, the level state of the target scanning signal OP is high; if the level state of the second node signal is high, the level state of the target scanning signal OP is low.

[0064] Continue to refer to Figure 14In one embodiment, the first switching unit 210 includes a third P-type transistor T5 and a third N-type transistor T6. The first terminal of the third P-type transistor T5 is connected to the first node A1, and the gate of the third P-type transistor T5 is used to receive the initial scan signal Scan. The first terminal of the third N-type transistor T6 is connected to the second terminal of the third P-type transistor T5, and the second terminal of the third N-type transistor T6 is used to connect to the second voltage terminal Vdc2. The gate of the third N-type transistor T6 is used to receive the initial scan signal Scan. Specifically, the connection node between the third P-type transistor T5 and the third N-type transistor T6 is the second node A2, which is used to output the second node signal. That is, if the level of the initial scan signal Scan is low, the third P-type transistor T5 turns on the first node A1 and the second node A2, so that the level states of the first node signal and the second node signal are the same. If the level of the initial scan signal Scan is high, the third N-type transistor T6 turns on the second node A2 and the second voltage terminal Vdc2, so that the second node signal is low. Therefore, in this embodiment, the level state of the second node signal can be controlled by setting the third P-type transistor T5 and the third N-type transistor T6.

[0065] Continue to refer to Figure 14 In one embodiment, the second switching unit 220 includes a fourth P-type transistor T7 and a fourth N-type transistor T8. The first terminal of the fourth P-type transistor T7 is connected to a first voltage terminal Vdc1, and the gate of the fourth P-type transistor T7 is connected to the first switching unit 210. The first terminal of the fourth N-type transistor T8 is connected to the second terminal of the fourth P-type transistor T7, and the second terminal of the fourth N-type transistor T8 is connected to a second voltage terminal Vdc2. The gate of the fourth N-type transistor T8 is connected to the first switching unit 210. Specifically, the connection node between the fourth P-type transistor T7 and the fourth N-type transistor T8 is used to output the target scan signal OP. That is, if the level of the second node signal is low, the fourth P-type transistor T7 turns on the output node of the target scan signal OP and the first voltage terminal Vdc1, so that the level of the target scan signal OP and the first voltage terminal Vdc1 are the same. If the signal level of the second node is high, the fourth N-type transistor T8 turns on the second node A2 and the second voltage terminal Vdc2, thus making the signal level of the second node low. Therefore, in this embodiment, the signal level of the second node can be controlled by setting the fourth P-type transistor T7 and the fourth N-type transistor T8.

[0066] Understandable, Figure 14Only one of the feasible embodiments is mentioned, and the first switch module 100 and the second switch module 200 may not be used simultaneously. Figure 14 In this embodiment, the first switch unit 210 and the second switch unit 220 may not be used simultaneously. Figure 14 The configuration of the embodiments, as long as the first switch module 100 and the second switch module 200 can satisfy the aforementioned functions, are all within the protection scope of this application. For example, the first switch module 100 can be any inverter circuit capable of inverting signals.

[0067] based on Figure 14 The circuit diagram of the scanning control circuit 10 in the embodiment, combined with Figures 15 to 18 The operation mode of the scan control circuit 10 is explained. Specifically, Figure 15 for Figure 14 One of the operating modes of the scanning control circuit 10 in the embodiment is as follows: Figure 15 When the enable control signal EN is low, the first P-type transistor T1 is turned on, thereby pulling the level of the first node signal to the high level of the first voltage terminal Vdc1. When the initial scan signal Scan is low, the third P-type transistor T5 is turned on, thereby pulling the level of the second node signal to the high level of the first node signal. The high level of the second node signal causes the fourth N-type transistor T8 to turn on, thereby pulling the target scan signal OP to the low level of the second voltage terminal Vdc2.

[0068] Figure 16 for Figure 14 The second operation mode of the scanning control circuit 10 in the embodiment, referred to Figure 16 When the enable control signal EN is low, the first P-type transistor T1 is turned on, thereby pulling the level of the first node signal to the high level of the first voltage terminal Vdc1. When the initial scan signal Scan is high, the third N-type transistor T6 is turned on, thereby pulling the level of the second node signal to the low level of the second voltage terminal Vdc2. The low level of the second node signal causes the fourth P-type transistor T7 to turn on, thereby pulling the target scan signal OP to the high level of the first voltage terminal Vdc1.

[0069] Figure 17 for Figure 14 The third mode of operation of the scanning control circuit 10 in the embodiment, referred to Figure 17When the enable control signal EN is high, the second N-type transistor T2 is turned on, thereby pulling the level of the first node signal to the low level of the second voltage terminal Vdc2. When the initial scan signal Scan is low, the third P-type transistor T5 is turned on, thereby pulling the level of the second node signal to the low level of the first node signal. The low level of the second node signal causes the fourth P-type transistor T7 to turn on, thereby pulling the target scan signal OP to the high level of the first voltage terminal Vdc1.

[0070] Figure 18 for Figure 14 The fourth mode of operation of the scanning control circuit 10 in the embodiment, referred to Figure 18 When the enable control signal EN is high, the second N-type transistor T2 is turned on, thereby pulling the level of the first node signal to the low level of the second voltage terminal Vdc2. When the initial scan signal Scan is high, the third N-type transistor T6 is turned on, thereby pulling the level of the second node signal to the low level of the second voltage terminal Vdc2. The low level of the second node signal causes the fourth P-type transistor T7 to turn on, thereby pulling the target scan signal OP to the high level of the first voltage terminal Vdc1.

[0071] Figure 19 This is a fourth schematic diagram of the scanning control circuit 10 according to one embodiment, with reference to... Figure 19In one embodiment, the first target transistor is of type N, and the target level state is a low level state. The second switching module 200 includes a first switching unit 210 and a second switching unit 220. The first switching unit 210 is connected to the first switching module 100 and is used to connect to the gate driving module 20. If the level state of the initial scan signal Scan is low, the first switching unit 210 generates a second node signal with a high level state. That is, if the level state of the initial scan signal Scan is low, the level state of the second node signal is high regardless of the level state of the first node signal. If the level state of the initial scan signal Scan is high, the first switching unit 210 generates a second node signal with the same level state as the first node signal. That is, if the level states of the initial scan signal Scan and the first node signal are both high, the level state of the second node signal is also high. If the initial scan signal Scan is at a high level and the first node signal is at a low level, then the second node signal is also at a low level. The second switching unit 220 is connected to the first switching unit 210 and is used to generate the target scan signal OP based on the second node signal. The level of the second node signal is opposite to the level of the target scan signal OP. That is, if the second node signal is at a low level, the target scan signal OP is at a high level; conversely, if the second node signal is at a high level, the target scan signal OP is at a low level.

[0072] Continue to refer to Figure 19In one embodiment, the first switching unit 210 includes a third P-type transistor T5 and a third N-type transistor T6. The first terminal of the third P-type transistor T5 is connected to the first voltage terminal Vdc1, and the gate of the third P-type transistor T5 is used to receive the initial scan signal Scan. The first terminal of the third N-type transistor T6 is connected to the second terminal of the third P-type transistor T5, and the second terminal of the third N-type transistor T6 is connected to a first node A1. The gate of the third N-type transistor T6 is used to receive the initial scan signal Scan. Specifically, the connection node between the third P-type transistor T5 and the third N-type transistor T6 is a second node A2 used to output the second node signal. That is, if the level of the initial scan signal Scan is high, the third N-type transistor T6 turns on the first node A1 and the second node A2, so that the level states of the first node signal and the second node signal are the same. If the level of the initial scan signal Scan is low, the third P-type transistor T5 turns on the second node A2 and the first voltage terminal Vdc1, so that the second node signal is high. Therefore, in this embodiment, the level state of the second node signal can be controlled by setting the third P-type transistor T5 and the third N-type transistor T6.

[0073] Continue to refer to Figure 19 In one embodiment, the second switching unit 220 includes a fourth P-type transistor T7 and a fourth N-type transistor T8. The first terminal of the fourth P-type transistor T7 is connected to a first voltage terminal Vdc1, and the gate of the fourth P-type transistor T7 is connected to the first switching unit 210. The first terminal of the fourth N-type transistor T8 is connected to the second terminal of the fourth P-type transistor T7, and the second terminal of the fourth N-type transistor T8 is connected to a second voltage terminal Vdc2. The gate of the fourth N-type transistor T8 is connected to the first switching unit 210. Specifically, the connection node between the fourth P-type transistor T7 and the fourth N-type transistor T8 is used to output the target scan signal OP. That is, if the level of the second node signal is low, the fourth P-type transistor T7 turns on the output node of the target scan signal OP and the first voltage terminal Vdc1, so that the level of the target scan signal OP and the first voltage terminal Vdc1 are the same. If the signal level of the second node is high, the fourth N-type transistor T8 turns on the second node A2 and the second voltage terminal Vdc2, thus making the signal level of the second node low. Therefore, in this embodiment, the signal level of the second node can be controlled by setting the fourth P-type transistor T7 and the fourth N-type transistor T8.

[0074] Understandable, Figure 19Only one of the feasible embodiments is mentioned, and the first switch module 100 and the second switch module 200 may not be used simultaneously. Figure 19 In this embodiment, the first switch unit 210 and the second switch unit 220 may not be used simultaneously. Figure 19 The configuration of the embodiments, as long as the first switch module 100 and the second switch module 200 can satisfy the aforementioned functions, are all within the protection scope of this application. For example, the first switch module 100 can be any inverter circuit capable of inverting signals.

[0075] based on Figure 19 The circuit diagram of the scanning control circuit 10 in the embodiment, combined with Figures 20 to 23 The operation mode of the scan control circuit 10 is explained. Specifically, Figure 20 for Figure 19 One of the operating modes of the scanning control circuit 10 in the embodiment is as follows: Figure 20 When the enable control signal EN is low, transistor T1 is turned on, thereby pulling the level of the first node signal to the high level of the first voltage terminal Vdc1. When the initial scan signal Scan is low, the third P-type transistor T5 is turned on, thereby pulling the level of the second node signal to the high level of the first voltage terminal Vdc1. The high level of the second node signal causes the fourth N-type transistor T8 to turn on, thereby pulling the target scan signal OP to the low level of the second voltage terminal Vdc2.

[0076] Figure 21 for Figure 19 The second operation mode of the scanning control circuit 10 in the embodiment, referred to Figure 21 When the enable control signal EN is low, transistor T1 is turned on, thereby pulling the level of the first node signal to the high level of the first voltage terminal Vdc1. When the initial scan signal Scan is high, the third N-type transistor T6 is turned on, thereby pulling the level of the second node signal to the high level of the first node signal. The high level of the second node signal causes the fourth N-type transistor T8 to turn on, thereby pulling the target scan signal OP to the low level of the second voltage terminal Vdc2.

[0077] Figure 22 for Figure 19 The third mode of operation of the scanning control circuit 10 in the embodiment, referred to Figure 22When the enable control signal EN is high, the first N-type transistor T2 is turned on, pulling the level of the first node signal to the low level of the second voltage terminal Vdc2. When the initial scan signal Scan is low, the third P-type transistor T5 is turned on, pulling the level of the second node signal to the high level of the first voltage terminal Vdc1. The high level of the second node signal turns on the fourth N-type transistor T8, pulling the target scan signal OP to the low level of the second voltage terminal Vdc2.

[0078] Figure 23 for Figure 19 The fourth mode of operation of the scanning control circuit 10 in the embodiment, referred to Figure 23 When the enable control signal EN is high, the first N-type transistor T2 is turned on, thereby pulling the level of the first node signal to the low level of the second voltage terminal Vdc2. When the initial scan signal Scan is high, the third N-type transistor T6 is turned on, thereby pulling the level of the second node signal to the low level of the first node signal. The low level of the second node signal causes the fourth P-type transistor T7 to turn on, thereby pulling the target scan signal OP to the high level of the first voltage terminal Vdc1.

[0079] This application also provides a display module. Figure 24 This is a schematic diagram of the structure of a display module according to one embodiment, with reference to... Figure 24 The display module includes a first scan control circuit 11, a gate driving module 20, and multiple pixel circuits 30. The gate driving module 20 generates a first initial scan signal Scan for controlling a first target transistor. The first scan control circuit 11 includes a scan control circuit 10 as described above, which outputs a first target scan signal OP to the connected first target transistor based on a first enable control signal EN and the first initial scan signal Scan. Each pixel circuit 30 includes at least one first target transistor, and at least a portion of the first target transistors in the pixel circuits 30 are connected to the scan control circuit 10. In this embodiment, based on the aforementioned scan control circuit 10, the display module can perform partial refreshes when needed, thereby reducing the power consumption of the display module.

[0080] Continue to refer to Figure 24In one embodiment, there are multiple scan control circuits 10, and the multiple pixel circuits 30 are arranged in multiple rows. Multiple pixel circuits 30 located in the same row are connected to the first scan control circuit 11. The first target transistors of the multiple pixel circuits 30 connected to the first scan control circuit 11 have the same function, or can be understood as being turned on at the same stage in multiple stages of pixel refresh. These multiple stages include, but are not limited to, an anode reset stage, a gate reset stage, a threshold compensation stage, and a data writing stage. In this embodiment, the above arrangement enables row-by-row partial refresh.

[0081] In one embodiment, the first target transistor is of type P, and the first target transistor connected to the scan control circuit 10 in the pixel circuit 30 is used to conduct during the data writing phase of the pixel circuit 30. By connecting the first target transistor for conducting during the data writing phase, data of the new frame cannot be written to the pixel circuit 30, thereby preserving the data of the previous frame. The first target transistor for conducting during the data writing phase of the pixel circuit 30 is, for example, a P-type transistor. Figure 1 and Figure 2 The transistor T4 in the embodiment. It is understood that the scan control circuit 10 is not limited to transistor T4, but may also be the first target transistor that is turned on in other stages.

[0082] In one embodiment, the first target transistor is of type N. The first target transistor connected to the scan control circuit 10 in the pixel circuit 30 is used to conduct during the gate reset phase or threshold compensation phase of the pixel circuit 30. By connecting the first target transistor for conduction during the gate reset phase or threshold compensation phase, the written data can be prevented from being reset or recompensated, thereby preserving the data from the previous frame. The first target transistor used during the gate reset phase of the pixel circuit 30 is, for example, an N-type transistor. Figure 1 and Figure 2 In the embodiment, transistor T1 is used as the first target transistor for turning on during the threshold compensation phase of the pixel circuit 30, for example, Figure 1 and Figure 2 The transistor T2 in the embodiment. It is understood that the scan control circuit 10 is not limited to transistors T1 and T2, but may also be a first target transistor that is turned on at other stages.

[0083] Continue to refer to Figure 24In one embodiment, the gate driving module 20 is further configured to generate a second initial scan signal Scan' for controlling a second target transistor, the type of which is different from that of the first target transistor. Specifically, as described above, the gate driving module 20 may include multiple sets of GOA circuits, some of which generate the first initial scan signal Scan for controlling the first target transistor, and others generate the second initial scan signal Scan' for controlling the second target transistor. The two sets of GOA circuits may be respectively disposed on both sides of the AA area for setting the pixel circuit 30. The display module further includes a second scan control circuit 12, which is connected to at least one second target transistor in the gate driving module 20 and the pixel circuit 30. The second scan control circuit 12 is configured to receive a second enable control signal EN' and the second initial scan signal Scan', and output a second target scan signal OP' to the connected second target transistor according to the second enable control signal EN' and the second initial scan signal Scan'. Wherein, if the second enable control signal EN' is in the second level state, then the level state of the second target scan signal OP' is the same as that of the second initial scan signal Scan'; if the second enable control signal EN' is in the first level state, then the level state of the second target scan signal OP' is a level state different from the target level state.

[0084] For example, if the first target transistor is of type N and the second target transistor is of type P, when the second enable control signal EN' is low, the level of the second target scan signal OP' is the same as the level of the second initial scan signal Scan'; when the second enable control signal EN' is high, the level of the second target scan signal OP' is high. If the first target transistor is of type P and the second target transistor is of type N, if the second enable control signal EN' is high, the level of the second target scan signal OP' is the same as the level of the second initial scan signal Scan'; if the second enable control signal EN' is low, the level of the second target scan signal OP' is low.

[0085] In this embodiment, by providing a second scan control circuit 12, the first scan control circuit 11 and the second scan control circuit 12 can work together to control the pixel circuit 30, which includes both a first target transistor and a second target transistor, for example, to control an LTPO type pixel circuit 30, thereby supporting partial refresh of more complex types of pixel circuits 30. This application also provides a display device. Figure 25This is a schematic diagram of the structure of a display device according to an embodiment, with reference to... Figure 25 The display device includes a controller and a display module as described above. The controller is connected to the gate driving module 20 and the first scan control circuit 11 of the display module, respectively, and is used to drive the gate driving module 20 to generate a first initial scan signal Scan and a first enable control signal EN. Based on the display module in the foregoing embodiment, the display device of this embodiment can perform flexible partial refresh, thereby reducing power consumption during refresh.

[0086] In one embodiment, when the display module further includes a second scan control circuit 12, the controller is also connected to the second scan control circuit 12 to drive the gate drive module 20 to generate a second initial scan signal Scan' and a second enable control signal EN'. The first enable control signal EN and the second enable control signal EN' can be inverse signals.

[0087] In one embodiment, the controller acquires the image to be displayed, determines a refresh area and a non-refresh area based on the image to be displayed, outputs a first enable control signal with a first level state to the first scan control circuit 11 connected to the pixels in the refresh area, and outputs a first enable control signal with a second level state to the first scan control circuit 11 connected to the pixels in the non-refresh area. Specifically, the image to be displayed in the next frame can be compared with the image displayed in the current frame. If the data of some rows of pixel circuits 30 remains unchanged, only the data of the pixel circuits 30 in the rows where the data has changed can be refreshed, thereby reducing the power consumption of the display screen.

[0088] In one embodiment, the controller is a display driver chip or an application processor.

[0089] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The above-described embodiments are merely illustrative of several implementation methods of the embodiments of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the embodiments of this application, and these all fall within the protection scope of the embodiments of this application. Therefore, the protection scope of the patent for the embodiments of this application should be determined by the appended claims.

Claims

1. A scanning control circuit, characterized in that, The scan control circuit is used to connect to the gate driving module and to at least one first target transistor in the pixel circuit. The scan control circuit includes... A first switching module is used to receive an enable control signal and generate a first node signal according to the enable control signal. The level state of the first node signal is different from the level state of the enable control signal. The first switching module includes a first P-type transistor and a first N-type transistor. The first terminal of the first P-type transistor is connected to a first voltage terminal, which is used to transmit a high-level signal. The gate of the first P-type transistor is used to receive the enable control signal. The first terminal of the first N-type transistor is connected to the second terminal of the first P-type transistor. The second terminal of the first N-type transistor is connected to a second voltage terminal, which is used to transmit a low-level signal. The gate of the first N-type transistor is used to receive the enable control signal. The connection node between the first P-type transistor and the first N-type transistor is a first node for outputting the first node signal. The second switching module is connected to the first switching module and is used to connect to the gate driving module and generate a target scanning signal to the connected first target transistor based on the initial scan signal from the gate driving module and the first node signal. Wherein, if the enable control signal is at a first level, the level of the target scan signal is the same as that of the initial scan signal; if the enable control signal is at a second level, the level of the target scan signal is a target level, the first level and the second level are different, and the target level is the level that turns off the first target transistor.

2. The scanning control circuit according to claim 1, characterized in that, The first switch module also includes: The second P-type transistor has a first terminal connected to the first voltage terminal and a gate connected to the first node. The second N-type transistor has its first terminal connected to the second terminal of the second P-type transistor, the second terminal of the second N-type transistor being connected to the second voltage terminal, and its gate being connected to the first node.

3. The scanning control circuit according to any one of claims 1 to 2, characterized in that, The first target transistor is of type P, and the target level state is a high level state; The second switch module is used to generate the target scan signal in a low-level state if the level state of the first node signal is high and the level state of the initial scan signal is low, otherwise generate the target scan signal in a high-level state.

4. The scanning control circuit according to claim 3, characterized in that, The second switch module includes: The first switching unit, connected to the first switching module, is used to connect to the gate driving module. If the level of the initial scan signal is high, it generates a second node signal with a low level; if the level of the initial scan signal is low, it generates a second node signal with the same level as the first node signal. The second switching unit, connected to the first switching unit, is used to generate the target scanning signal based on the second node signal, wherein the level state of the second node signal is opposite to the level state of the target scanning signal.

5. The scanning control circuit according to claim 4, characterized in that, The first switching unit includes: The third P-type transistor has its first terminal connected to the first node, and its gate is used to receive the initial scan signal. The third N-type transistor has its first terminal connected to the second terminal of the third P-type transistor. The second terminal of the third N-type transistor is used to connect to the second voltage terminal, and the gate of the third N-type transistor is used to receive the initial scan signal. The connection node between the third P-type transistor and the third N-type transistor is a second node used to output the signal of the second node.

6. The scanning control circuit according to claim 4, characterized in that, The second switching unit includes: A fourth P-type transistor, wherein the first terminal of the fourth P-type transistor is connected to the first voltage terminal, and the gate of the fourth P-type transistor is connected to the first switching unit; The fourth N-type transistor has its first terminal connected to the second terminal of the fourth P-type transistor. The second terminal of the fourth N-type transistor is used to connect to the second voltage terminal. The gate of the fourth N-type transistor is connected to the first switching unit. The connection node between the fourth P-type transistor and the fourth N-type transistor is used to output the target scanning signal.

7. The scanning control circuit according to any one of claims 1 to 2, characterized in that, The first target transistor is of type N, and the target level state is a low level state; The second switch module is used to generate the target scan signal in a high-level state if the level state of the first node signal is low and the level state of the initial scan signal is high; otherwise, it generates the target scan signal in a low-level state.

8. The scanning control circuit according to claim 7, characterized in that, The second switch module includes: The first switching unit, connected to the first switching module, is used to connect to the gate driving module. If the level of the initial scan signal is low, it generates a second node signal with a high level; if the level of the initial scan signal is high, it generates a second node signal with the same level as the first node signal. The second switching unit, connected to the first switching unit, is used to generate the target scanning signal based on the second node signal, wherein the level state of the second node signal is opposite to the level state of the target scanning signal.

9. The scanning control circuit according to claim 8, characterized in that, The first switching unit includes: The third P-type transistor has a first terminal for connection to a first voltage terminal and a gate for receiving the initial scan signal. The third N-type transistor has its first terminal connected to the second terminal of the third P-type transistor, and its second terminal connected to the first node. The gate of the third N-type transistor is used to receive the initial scan signal. The connection node between the third P-type transistor and the third N-type transistor is a second node used to output the signal of the second node.

10. The scanning control circuit according to claim 8, characterized in that, The second switching unit includes: A fourth P-type transistor, wherein the first terminal of the fourth P-type transistor is connected to the first voltage terminal, and the gate of the fourth P-type transistor is connected to the first switching unit; The fourth N-type transistor has its first terminal connected to the second terminal of the fourth P-type transistor. The second terminal of the fourth N-type transistor is used to connect to the second voltage terminal. The gate of the fourth N-type transistor is connected to the first switching unit. The connection node between the fourth P-type transistor and the fourth N-type transistor is used to output the target scanning signal.

11. A display module, characterized in that, include: A gate driving module is used to generate a first initial scan signal for controlling the first target transistor; The first scan control circuit includes the scan control circuit as described in any one of claims 1 to 10, configured to output a first target scan signal to the connected first target transistor according to a first enable control signal and a first initial scan signal; Multiple pixel circuits, each pixel circuit including at least one first target transistor, wherein at least a portion of the first target transistor in the pixel circuits is connected to the scan control circuit.

12. The display module according to claim 11, characterized in that, The number of scanning control circuits is multiple, and the multiple pixel circuit arrays are arranged in multiple rows. The multiple pixel circuits located in the same row are connected to the same first scanning control circuit.

13. The display module according to claim 11, characterized in that, The first target transistor is of type P, and the first target transistor connected to the scan control circuit in the pixel circuit is used to turn on during the data writing phase of the pixel circuit.

14. The display module according to claim 11, characterized in that, The first target transistor is of type N, and the first target transistor connected to the scan control circuit in the pixel circuit is used to turn on during the gate reset phase or threshold compensation phase of the pixel circuit.

15. The display module according to any one of claims 11 to 14, characterized in that, The gate driving module is further configured to generate a second initial scan signal for controlling a second target transistor, the second target transistor being of a different type than the first target transistor. The display module also includes: The second scan control circuit is connected to at least one second target transistor in the gate driving module and the pixel circuit, respectively. The second scan control circuit is configured to receive a second enable control signal and a second initial scan signal, respectively, and output a second target scan signal to the connected second target transistor according to the second enable control signal and the second initial scan signal. Wherein, if the second enable control signal is at a second level, the level of the second target scan signal is the same as that of the second initial scan signal; if the second enable control signal is at a first level, the level of the second target scan signal is a level different from that of the target level.

16. A display device, characterized in that, include: The display module as described in any one of claims 11 to 15; The controller is connected to the gate driving module and the first scan control circuit of the display module, respectively, and is used to drive the gate driving module to generate a first initial scan signal and generate the first enable control signal.

17. The display device according to claim 16, characterized in that, The controller is used to acquire the image to be displayed, determine the refresh area and non-refresh area based on the image to be displayed, output the first enable control signal with a first level state to the first scan control circuit connected to the pixels in the refresh area, and output the first enable control signal with a second level state to the first scan control circuit connected to the pixels in the non-refresh area.

18. The display device according to any one of claims 16 to 17, characterized in that, The controller is a display driver chip or an application processor.

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