Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises an initialization signal line, a scanning signal line, and a plurality of pixel circuits arranged in an array; the pixel circuit comprises an initialization transistor, the initialization transistor is electrically connected with the corresponding scanning signal line, the initialization signal line is electrically connected with the active part of the initialization transistor through an access structure, and the scanning signal line and the initialization signal line extend along the row direction. The application can make the display panel give consideration to high pixel density and high display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of display technology, the application of display panels is becoming more and more widespread, and the requirements for display panels are correspondingly becoming higher and higher.

[0003] However, existing display panels suffer from the problem of not being able to simultaneously achieve high pixel density and high display quality, which limits the further application of display panels. Summary of the Invention

[0004] The present invention provides a display panel and a display device, so that the display panel can achieve both high pixel density and high display effect.

[0005] According to one aspect of the present invention, a display panel is provided, the display panel including initialization signal lines, scan signal lines, and a plurality of pixel circuits arranged in an array;

[0006] The pixel circuit includes an initialization transistor, which is electrically connected to a corresponding scan signal line. The initialization signal line is electrically connected to the active part of the initialization transistor through an access structure. The scan signal line and the initialization signal line extend along the row direction.

[0007] Optionally, the pixel circuit includes a first initialization transistor and a second initialization transistor, which are used to initialize different parts of the pixel circuit; an initialization signal line extending along the row direction is provided between two adjacent rows of pixel circuits; each initialization signal line is provided with multiple access structures, and each access structure connects the initialization signal line, the first initialization transistor of the first row of pixel circuits in the same column and two adjacent rows of pixel circuits corresponding to the initialization signal line, and the second initialization transistor of the second row of pixel circuits; wherein, the first initialization transistor of the first row of pixel circuits and the second initialization transistor of the second row of pixel circuits are located on opposite sides of the initialization signal line along the column direction;

[0008] Alternatively, an initialization signal line extending along the row direction is provided between two adjacent rows of pixel circuits; each initialization signal line is provided with multiple access structures, and each access structure connects the initialization signal line, the initialization transistor of the first row of pixel circuits in the same column and two adjacent rows of pixel circuits corresponding to the initialization signal line, and the initialization transistor of the second row of pixel circuits; wherein, the initialization transistor of the first row of pixel circuits and the initialization transistor of the second row of pixel circuits are located on opposite sides of the initialization signal line along the column direction.

[0009] Optionally, the display panel includes an active layer and a first conductive layer;

[0010] The channels of the first initialization transistor and the second initialization transistor are arranged in the active layer, the gates of the first initialization transistor and the second initialization transistor are arranged in the first conductive layer, and the initialization signal line is arranged in the first conductive layer.

[0011] Optionally, the display panel further comprises a second conductive layer; the access structure comprises a first via hole, a second via hole, a third via hole and an interconnection structure; the interconnection structure is arranged in the second conductive layer, and the interconnection structure is connected to the initialization signal line through the first via hole; the interconnection structure is connected to the corresponding first initialization transistor through the second via hole, and the interconnection structure is connected to the corresponding second initialization transistor through the third via hole;

[0012] Optionally, the display panel further comprises data lines extending along the column direction and / or power signal lines, and the data lines and / or power signal lines are arranged in the second conductive layer;

[0013] Optionally, the second conductive layer is located on a side of the first conductive layer away from the active layer.

[0014] Optionally, the second via hole and the third via hole are arranged along the column direction, and the first via hole and the second via hole are arranged along a direction intersecting the column direction;

[0015] Optionally, the first via hole, the second via hole and the third via hole form a "pin-shaped" arrangement.

[0016] Optionally, a first notch is provided at a position of the initialization signal line corresponding to the second via hole, and along the thickness direction of the display panel, the projection of the second via hole overlaps with the projection of the first notch; and / or,

[0017] a second notch is provided at a position of the initialization signal line corresponding to the third via hole, and along the thickness direction of the display panel, the projection of the third via hole overlaps with the projection of the second notch.

[0018] Optionally, the access structure comprises a fourth via hole; the first initialization transistor and the second initialization transistor connected to the access structure are further connected through a connection structure located in the active layer, and the initialization signal line is electrically connected to the connection structure through the fourth via hole.

[0019] Optionally, in two adjacent rows of pixel circuits, the active layer between the first initialization transistor of the pixel circuit in the first row and the second initialization transistor of the pixel circuit in the second row is continuously arranged; or, the active layer between the first initialization transistor of the pixel circuit in the first row and the second initialization transistor of the pixel circuit in the second row is disconnected at a position corresponding to the initialization signal line.

[0020] Optionally, the display panel is provided with a plurality of first scan signal lines and a plurality of second scan signal lines extending along the row direction;

[0021] The second initialization transistor of the pixel circuit is electrically connected to the first scan signal line, and the first initialization transistor of the pixel circuit is electrically connected to the second scan signal line.

[0022] The display panel has a display area and a non-display area surrounding at least a portion of the display area, and a first scan signal line and a second scan signal line extend into the non-display area;

[0023] Optionally, the non-display area is provided with multiple gate driving circuits. In two adjacent rows of pixel circuits, the second scan signal line corresponding to the first row of pixel circuits is connected to the first scan signal line corresponding to the second row of pixel circuits, and connected to the output terminal of the same gate driving circuit.

[0024] Alternatively, multiple gate drive circuits are provided in the non-display area. In two adjacent rows of pixel circuits, the second scan signal line corresponding to the first row of pixel circuits and the first scan signal line corresponding to the second row of pixel circuits are connected to the output terminals of different gate drive circuits.

[0025] Optionally, the pixel circuit also includes a driving transistor;

[0026] The first terminal of the second initialization transistor is connected to the corresponding initialization signal line via the access structure, the second terminal of the second initialization transistor is electrically connected to the control terminal of the driving transistor, and the control terminal of the second initialization transistor is connected to the first scan signal line.

[0027] The first terminal of the first initialization transistor is connected to the initialization signal line via the access structure, the second terminal of the first initialization transistor is electrically connected to the first electrode of the light-emitting element, and the control terminal of the first initialization transistor is connected to the second scan signal line.

[0028] Optionally, the pixel circuit also includes a threshold compensation transistor, a data writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, and a storage capacitor;

[0029] The control terminal of the driving transistor is electrically connected to the first terminal of the storage capacitor, the first terminal of the driving transistor is electrically connected to the second terminal of the first light-emitting control transistor, and the second terminal of the driving transistor is electrically connected to the first terminal of the threshold compensation transistor.

[0030] The first terminal of the data writing transistor is electrically connected to the corresponding data line, the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor, and the control terminal of the data writing transistor is connected to the third scan signal line.

[0031] The second terminal of the threshold compensation transistor is electrically connected to the control terminal of the driving transistor, and the control terminal of the threshold compensation transistor is connected to the third scan signal line.

[0032] The first terminal of the first light-emitting control transistor is connected to the power signal line, and the control terminal of the first light-emitting control transistor is connected to the enable signal line.

[0033] The first terminal of the second light-emitting control transistor is electrically connected to the second terminal of the driving transistor, the second terminal of the second light-emitting control transistor is electrically connected to the first electrode of the light-emitting element, and the control terminal of the second light-emitting transistor is connected to the enable signal line.

[0034] The second end of the storage capacitor is connected to the power signal line.

[0035] Optionally, the display panel includes an active layer and a first conductive layer;

[0036] The channel of the initialization transistor is disposed in the active layer, and the gate of the initialization transistor, the scan signal line connected to the gate of the initialization transistor, and the initialization signal line are disposed in the first conductive layer.

[0037] And / or, the display panel further includes a second conductive layer; the access structure includes a first via, a second via, and an interconnect structure; the interconnect structure is disposed on the second conductive layer, and the interconnect structure is connected to the initialization signal line through the first via; the interconnect structure is connected to the initialization transistor through the second via.

[0038] And / or, the display panel also includes data lines and / or power signal lines extending along the column direction, the data lines and / or power signal lines being disposed on the second conductive layer;

[0039] And / or, the second conductive layer is located on the side of the first conductive layer away from the active layer;

[0040] And / or, the access structure includes a fourth via; the initialization transistor connected to the access structure is connected through a connection structure located in the active layer, and the initialization signal line is electrically connected to the connection structure through the fourth via;

[0041] And / or, the active layers in two adjacent rows of pixel circuits are set continuously, or they are set separately, such that the projection of the disconnected position of the active layer in two adjacent rows of pixel circuits overlaps with the projection of the initialization signal line along the thickness direction of the display panel.

[0042] According to another aspect of the present invention, a display device is provided, the display device including the display panel as described above.

[0043] The technical solution of this invention employs a display panel including initialization signal lines, scan signal lines, and multiple pixel circuits arranged in an array. Each pixel circuit includes an initialization transistor, which is electrically connected to a corresponding scan signal line. The initialization signal lines are electrically connected to the active portion of the initialization transistor via an access structure. The scan signal lines and initialization signal lines extend along the row direction. By setting the initialization signal lines to extend along the row direction, the number of signal lines extending along the column direction in the display panel can be reduced, thereby increasing the pixel density. Furthermore, the continuous arrangement of the initialization signal lines ensures normal load on the initialization signal lines. By setting the access structure to interconnect the initialization signal lines and their corresponding initialization transistors, the structure of the pixel circuit remains unchanged even if the initialization signal lines are continuously arranged, thus not affecting the display effect of the display panel.

[0044] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of the layout structure of a display panel provided in an embodiment of the present invention;

[0048] Figure 3 A schematic diagram of the pixel circuit structure provided in an embodiment of the present invention;

[0049] Figure 4 To and Figure 3 A corresponding timing diagram;

[0050] Figure 5 for Figure 2 A magnified schematic diagram of the mid-pixel circuit;

[0051] Figure 6 for Figure 2 A schematic diagram of the active layer structure;

[0052] Figure 7 for Figure 2 A schematic diagram of the structure of the first conductive layer in the middle;

[0053] Figure 8 for Figure 2 A schematic diagram of the structure of the second conductive layer in the middle;

[0054] Figure 9 for Figure 2 An enlarged schematic diagram of the access structure region in the middle;

[0055] Figure 10 for Figure 9 Cross-sectional view along the B1B2 direction;

[0056] Figure 11 This is a schematic diagram of another type of active layer structure;

[0057] Figure 12 This is another enlarged schematic diagram of the access structure area;

[0058] Figure 13 for Figure 12 Cross-sectional view along the C1C2 direction;

[0059] Figure 14 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0060] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0061] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0062] Display panels in related technologies suffer from the inability to simultaneously achieve high pixel density and high display quality. After careful research, the inventors discovered that the cause of this problem lies in the pixel circuitry's use of a two-layer metal design. While fewer metal layers reduce costs, this design results in vertical (column-direction) arrangement of initialization signal lines, data lines, and power signal lines, and horizontal (row-direction) arrangement of scan signal lines. This leads to an excessive number of vertical signal lines, requiring more space and consequently resulting in lower pixel density. One approach to increase pixel density in related technologies is to reduce the size of capacitors in the pixel circuitry, which undoubtedly degrades the display quality.

[0063] To address the aforementioned technical problems, the present invention proposes the following solutions:

[0064] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the layout structure of a display panel provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the pixel circuit structure provided in an embodiment of the present invention, with reference to... Figures 1 to 3 The display panel includes an initialization signal line Vref, a scan signal line, and a plurality of pixel circuits Px arranged in an array. Each pixel circuit Px (e.g., each pixel circuit Px in at least one pixel circuit Px) includes an initialization transistor, which may be used to initialize the gate, source, or drain of a driving transistor in the pixel circuit, or to initialize the first electrode of a light-emitting element in the pixel circuit. The initialization transistor is electrically connected to the corresponding scan signal line; for example, the gate of the initialization transistor is electrically connected to the corresponding scan signal line. The initialization signal line Vref is electrically connected to the active portion of the initialization transistor through an access structure 20. The scan signal line and the initialization signal line Vref extend along the row direction X.

[0065] Specifically, such as Figure 1As shown, the display panel may include a display area AA and a non-display area NAA surrounding at least a portion of the display area AA. Multiple pixel circuits Px are arranged in an array within the display area AA. Multiple scan signal lines extending along the row direction X are also provided in the display area AA. Scan signals on the scan signal lines are used to control the state of initialization transistors in the pixel circuits Px. The active portion of the initialization transistor may be located in an active layer. The active portion of the initialization transistor may include a channel, a source region, and a drain region, with the channel located between the source and drain regions. The pixel circuit Px may include one or more initialization transistors. The multiple initialization transistors are used to initialize at least two of the first electrode of the light-emitting element, the gate of the driving transistor, the source, and the drain. A portion of the scan signal line may be multiplexed as the gate of the initialization transistor. The portion of the scan signal line overlapping with the active portion of the initialization transistor may serve as the gate of the initialization transistor.

[0066] The display area AA also includes multiple data lines Data extending along the column direction Y. For example, each column of pixel circuits Px is connected to one data line Data. The data lines Data are used to provide data signals to the pixel circuits, and different data signals cause the light-emitting elements to display different gray levels. The display panel may include light-emitting elements of three colors, such as red, green, and blue light-emitting elements. By combining different colored light-emitting elements and different display gray levels, the display panel can achieve full-color display. The data lines Data extend along the column direction Y into the non-display area NAA of the display panel. A data driver can be set in the portion of the non-display area NAA corresponding to the lower border. The data driver is used to provide data signals to each data line Data. Of course, in some embodiments, a multiplexer can also be set in the lower border of the display panel. The data driver provides data signals to each data line through the multiplexer. By setting a multiplexer, the number of leads required by the data driver can be reduced.

[0067] The light-emitting element can be an OLED (Organic Light Emitting Diode), Micro-LED, QLED, or Mini-LED, etc. Taking OLED as an example, an OLED may include an anode layer, a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a cathode layer. Different colors of light-emitting elements can be achieved by using different emissive layer materials. The light-emitting principle of light-emitting elements is well known to those skilled in the art and will not be elaborated here.

[0068] In this embodiment, the initialization signal line Vref extends along the row direction X. Compared to the related art where it extends along the column direction Y, the number of signal lines extending along the column direction Y in this embodiment is less. This allows the display panel to have more space to accommodate pixel circuits or increase the size of the storage capacitors in the pixel circuits, thereby improving pixel density or display performance. Furthermore, since the display panel has a large column dimension, setting the initialization signal line to extend along the row direction and arrange it in the column direction does not increase the size of the display panel in the column direction.

[0069] Furthermore, in this embodiment, each initialization signal line Vref is continuously set, eliminating the need for disconnection. The resistive load on the continuously set initialization signal lines Vref is normal, thus preventing issues like abnormal resistive loads in different parts of the initialization signal lines Vref that could lead to poor display quality, and consequently, maintaining the display panel's performance. Additionally, the access structure 20 connects the initialization signal lines Vref and their corresponding initialization transistors. This access structure 20 short-circuits parasitic devices formed between the initialization signal lines and the active layer. In other words, the parasitic devices formed between the continuously set initialization signal lines and the active layer are short-circuited by the access structure 20, preventing any impact on the normal operation of the pixel circuitry and, consequently, the display panel's performance.

[0070] The technical solution of this embodiment uses a display panel including initialization signal lines, scan signal lines, and multiple pixel circuits arranged in an array. Each pixel circuit includes an initialization transistor, the gate of which is electrically connected to the corresponding scan signal line. The initialization signal lines are electrically connected to the active portion of the initialization transistor via an access structure. The scan signal lines and initialization signal lines extend along the row direction. By setting the initialization signal lines to extend along the row direction, the number of signal lines extending along the column direction in the display panel can be reduced, thereby increasing the pixel density. Furthermore, the continuous arrangement of the initialization signal lines ensures normal load on the initialization signal lines. By setting the access structure to interconnect the initialization signal lines and their corresponding initialization transistors, the structure of the pixel circuit will not be changed even if the initialization signal lines are arranged continuously, thus not affecting the display effect of the display panel.

[0071] Optionally, continue to refer to Figures 1 to 3The display panel includes multiple pixel circuits Px arranged in an array; each pixel circuit Px includes a first initialization transistor T7 and a second initialization transistor T4, which are used to initialize different parts of the pixel circuit; an initialization signal line Vref extending along the row direction X is provided between two adjacent rows of pixel circuits; each initialization signal line Vref is provided with multiple access structures 20, and each access structure 20 connects the initialization signal line Vref, the first initialization transistor T7 of the first row of pixel circuits in the same column and two adjacent rows of pixel circuits Px corresponding to the initialization signal line Vref, and the second initialization transistor T4 of the second row of pixel circuits; wherein, the first initialization transistor T7 of the first row of pixel circuits and the second initialization transistor T4 of the second row of pixel circuits are located on opposite sides of the initialization signal line Vref along the column direction.

[0072] Specifically, the display area AA is further provided with multiple first scan signal lines S1 and second scan signal lines S3 extending along the row direction X. Each row of pixel circuits is electrically connected to one first scan signal line S1 and one second scan signal line S3. The first scan signal line S1 can be used to control the state of the second initialization transistor T4 in the pixel circuit Px, and the second scan signal line S3 can be used to control the state of the first initialization transistor T7 in the pixel circuit Px. In this embodiment, the pixel circuit Px includes the first initialization transistor T7 and the second initialization transistor T4. The two initialization transistors initialize different parts of the pixel circuit. For example, the first initialization transistor T7 initializes the first electrode (e.g., the anode) of the light-emitting element in the pixel circuit, and the second initialization transistor T4 initializes the gate of the driving transistor in the pixel circuit.

[0073] Furthermore, in this embodiment, each initialization signal line Vref is continuously set, eliminating the need for disconnection. The resistive load on the continuously set initialization signal lines Vref is normal, preventing issues like abnormal resistive loads in different parts of the initialization signal lines Vref that could lead to poor display quality, and thus maintaining the display panel's performance. Additionally, the access structure 20 connects the initialization signal line Vref, the corresponding first initialization transistor T7, and the corresponding second initialization transistor T4, interconnecting them. Parasitic devices formed between the continuous initialization signal lines and the active layer are short-circuited by the access structure 20, preventing interference with the normal operation of the pixel circuitry and thus maintaining the display panel's performance.

[0074] The technical solution of this embodiment employs a display panel comprising multiple pixel circuits arranged in an array. Each pixel circuit includes a first initialization transistor and a second initialization transistor, which are used to initialize different parts of the pixel circuit. An initialization signal line extending along the row direction is provided between two adjacent rows of pixel circuits. Each initialization signal line corresponds to multiple access structures, and each access structure connects the initialization signal line, the first initialization transistor of the first row of pixel circuits in the same column and two adjacent rows of pixel circuits corresponding to the initialization signal line, and the second initialization transistor of the second row of pixel circuits. The first initialization transistor of the first row of pixel circuits and the second initialization transistor of the second row of pixel circuits are located on different sides of the initialization signal line. By setting the initialization signal line to extend along the row direction, the number of signal lines extending along the column direction in the display panel can be reduced, thereby increasing the pixel density. Furthermore, the continuous arrangement of the initialization signal lines ensures normal load on the initialization signal lines. By setting access structures to interconnect the initialization signal lines, the corresponding first initialization transistors, and the second initialization transistors, the structure of the pixel circuit will not be changed even if the initialization signal lines are continuously arranged, thus not affecting the display effect of the display panel.

[0075] Optionally, in some other embodiments, an initialization signal line extending along the row direction is provided between two adjacent rows of pixel circuits; each initialization signal line is provided with multiple access structures, and each access structure connects the initialization signal line, the initialization transistor of the first row of pixel circuits in the same column and two adjacent rows of pixel circuits corresponding to the initialization signal line, and the initialization transistor of the second row of pixel circuits; wherein, the initialization transistor of the first row of pixel circuits and the initialization transistor of the second row of pixel circuits are located on opposite sides of the initialization signal line along the column direction.

[0076] Specifically, in this embodiment, the pixel circuit includes only one initialization transistor. This initialization transistor can be an initialization transistor used to initialize the gate of the driving transistor in the pixel circuit, or it can be an initialization transistor used to initialize the first electrode (e.g., the anode) of the light-emitting element. In this embodiment, the pixel circuit includes only one initialization transistor, which makes the pixel circuit smaller in size and requires less layout area, thereby further increasing the pixel density of the display panel.

[0077] Optionally, in this embodiment, since the initialization signal line connects to the same initialization transistor in two adjacent rows of pixel circuits, the two adjacent rows of pixel circuits can be configured to be symmetrical about the initialization signal line between them.

[0078] Optionally, for ease of subsequent description, the specific structure of the pixel circuit will be introduced first. Of course, in this embodiment, the "7T1C" pixel circuit is used as an example. In other embodiments, the pixel circuit may have other structures. Figure 4 To and Figure 3 A corresponding timing diagram, Figure 5 for Figure 2 A magnified schematic diagram of the mid-pixel circuit, see reference. Figures 3 to 5 The pixel circuit may further include a driving transistor T1, a first initialization transistor T7, and a second initialization transistor T4. The first initialization transistor T7 is used to initialize the first electrode of the light-emitting element. The second initialization transistor T4 is used to initialize the gate of the driving transistor T1. Optionally, the first initialization transistor T7 is an N-type transistor or a P-type transistor. Optionally, the second initialization transistor T4 is an N-type transistor or a P-type transistor.

[0079] Optionally, the first terminal of the second initialization transistor T4 is connected to the corresponding initialization signal line via an access structure, the second terminal of the second initialization transistor T4 is electrically connected to the control terminal of the driving transistor T1, and the control terminal of the second initialization transistor T4 is connected to the first scan signal line S1.

[0080] Optionally, the first terminal of the first initialization transistor T7 is connected to the initialization signal line via an access structure, the second terminal of the first initialization transistor T7 is electrically connected to the first electrode (e.g., anode) of the light-emitting element, and the control terminal of the first initialization transistor T7 is connected to the second scan signal line S3.

[0081] Optionally, the pixel circuit may also include some or all of the following: threshold compensation transistor T3, data writing transistor T2, first light-emitting control transistor T5, first light-emitting control transistor T6, and storage capacitor C1.

[0082] The control terminal of driving transistor T1 is electrically connected to the first terminal of storage capacitor C1. The first terminal of driving transistor T1 is electrically connected to the second terminal of the first light-emitting control transistor T5. The second terminal of driving transistor T1 is electrically connected to the first terminal of threshold compensation transistor T3. The first terminal of data writing transistor T2 is electrically connected to the corresponding data line Data. The second terminal of data writing transistor T2 is electrically connected to the first terminal of driving transistor T1. The control terminal of data writing transistor T2 is connected to the third scan signal line S2. The second terminal of threshold compensation transistor T3 is electrically connected to the control terminal (or gate) of driving transistor T1. The control terminal of threshold compensation transistor T3 is connected to the third... The scanning signal line S2 is electrically connected; the first terminal of the first light-emitting control transistor T5 is connected to the power signal line Vdd (which can be used to transmit high voltage), and the control terminal of the first light-emitting control transistor T5 is connected to the enable signal line EM; the first terminal of the second light-emitting control transistor T6 is electrically connected to the second terminal of the driving transistor T1, and the second terminal of the second light-emitting control transistor T6 is electrically connected to the first electrode (e.g., anode) of the light-emitting element, and the control terminal of the second light-emitting control transistor T6 is connected to the enable signal line EM; the second terminal of the storage capacitor C1 is connected to the power signal line Vdd; the second electrode (e.g., cathode) of the light-emitting element is connected to the second power signal line Vss (which can be used to transmit low voltage).

[0083] Specifically, the operation of the pixel circuit may include a first initialization stage, a data writing stage, a second initialization stage, and a light emission stage.

[0084] In the first initialization phase t1, the first scan signal on the first scan signal line S1 controls the second initialization transistor T4 to turn on, transmitting the voltage on the initialization signal line Vref to the gate of the driving transistor T1, thereby initializing the gate of the driving transistor T1.

[0085] During the data writing phase t2, the third scan signal of the third scan signal line S2 controls the data writing transistor T2 and the threshold compensation transistor T3 to turn on. The data signal on the data line Data is transmitted to the control terminal of the driving transistor T1 after passing through the data writing transistor T2, the driving transistor T1, and the threshold compensation transistor T3. When the voltage difference between the control terminal of the driving transistor T1 and its first terminal is equal to the threshold voltage of the driving transistor, the driving transistor T1 is turned off, completing the threshold compensation process.

[0086] In the second initialization phase t3, the second scan signal on the second scan signal line S3 controls the first initialization transistor T7 to turn on, transmitting the voltage on the initialization signal line Vref to the first electrode (e.g., anode) of the light-emitting element, thereby initializing the first electrode (e.g., anode) of the light-emitting element.

[0087] During the light-emitting stage t4, the signal on the enable signal line EM controls the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to turn on, driving the transistors to generate a driving current, and the light-emitting element responds to the driving current to emit light.

[0088] Optionally, the second initialization transistor T4 is a dual-gate transistor. Dual-gate transistors have lower leakage current, which can reduce the leakage current of the driving transistor. Optionally, the threshold compensation transistor T3 is a dual-gate transistor, which can further reduce the leakage current of the driving transistor.

[0089] Optionally, the second initialization phase t3 may overlap with or not overlap with the data writing phase t2. Optionally, the second initialization phase t3 may coincide with the data writing phase t2.

[0090] Optionally, the display panel further includes an active layer and a first conductive layer; the channel (or active portion) of the initialization transistor is disposed in the active layer, and the gate of the initialization transistor, the scan signal line connected to the gate of the initialization transistor, and the initialization signal line are disposed in the same layer, for example, in the first conductive layer. Optionally, the film layer containing the active portion of the initialization transistor is located between the substrate and the film layer containing the initialization signal line. Optionally, the initialization transistor is an N-type transistor or a P-type transistor.

[0091] Optionally, the display panel further includes data lines and / or power signal lines extending along the column direction. Optionally, the display panel further includes a second conductive layer. The data lines and / or power signal lines are disposed on the second conductive layer. The data lines and initialization signal lines are disposed on different layers. The power signal lines and initialization signal lines are disposed on different layers.

[0092] It should be noted that, Figure 3 The parasitic transistor Ts in the image is formed by the overlap of the initialization signal line Vref and the active layer. Due to the presence of an access structure, it is equivalent to short-circuiting the gate, source, and drain of the parasitic transistor Ts (for example, through the first via 201, the second via 202, the third via 203, and the interconnect structure 204 in the access structure 20). Therefore, the parasitic transistor Ts does not function in the pixel circuit. It should be noted that... Figure 3 For ease of understanding, the parasitic transistor Ts is illustrated by representing it as a single pixel circuit. In the actual equivalent circuit, a pixel circuit is connected to two initialization signal lines, and each pixel circuit, along with two adjacent pixel circuits located above and below it, forms a parasitic transistor.

[0093] Optionally, Figure 6 for Figure 2 A schematic diagram of the active layer structure. Figure 7 for Figure 2 A schematic diagram of the structure of the first conductive layer. Figure 8 for Figure 2A schematic diagram of the structure of the second conductive layer is shown in the reference diagram. Figures 2 to 8 The display panel includes an active layer, a first conductive layer, and a second conductive layer. Initialization signal lines, the gates of each transistor, the first electrode of the storage capacitor (which can be reused as the gate of the driving transistor), each scan signal line (the portion of the scan signal line overlapping the active layer can be reused as the gate of the corresponding transistor), and enable signal lines are disposed on the same layer, for example, on the first conductive layer. Power signal lines (the portion of the power signal line overlapping the first electrode of the storage capacitor can be reused as the second electrode of the storage capacitor) and data lines are disposed on the same layer, for example, on the second conductive layer. In this embodiment, the channels of each transistor are formed in the active layer. In this embodiment, the pixel circuit includes only two conductive layers, namely the first conductive layer and the second conductive layer. Compared to the traditional three- or four-conductive-layer configuration, the display panel of this embodiment has fewer conductive layers, which reduces the number of processes and thus saves on process costs. The first conductive layer may include a metal layer. The second conductive layer may include a metal layer or an indium tin oxide (ITO) layer.

[0094] Optionally, the display panel further includes a second conductive layer; the access structure includes a first via, a second via, and an interconnect structure; the interconnect structure is disposed on the second conductive layer, and the interconnect structure is connected to the initialization signal line through the first via; the interconnect structure is connected to the initialization transistor through the second via.

[0095] Optionally, the interconnect structure and the initialization signal line are disposed on different layers. The film layer containing the initialization signal line is located between the film layer containing the interconnect structure and the film layer containing the active part of the initialization transistor.

[0096] Optionally, Figure 9 for Figure 2 An enlarged schematic diagram of the access structure region. Figure 10 for Figure 9 Cross-sectional view along the B1B2 direction, see reference. Figure 2 , Figure 5 , Figure 9 and Figure 10 The display panel also includes a second conductive layer; the access structure 20 includes a first via 201, a second via 202, a third via 203, and an interconnect structure 204; the interconnect structure 204 is disposed on the second conductive layer, and the interconnect structure 204 is connected to the initialization signal line Vref through the first via 201; the interconnect structure 204 is connected to the corresponding first initialization transistor through the second via 202, and the interconnect structure 204 is connected to the corresponding second initialization transistor through the third via 203.

[0097] Optionally, the interconnect structure 204 is connected to the active portion of the corresponding first initialization transistor through the second via 202, and the interconnect structure 204 is connected to the active portion of the corresponding second initialization transistor through the third via 203.

[0098] Optionally, the orthographic projection of the interconnect structure 204 on the substrate overlaps with the orthographic projection of the initialization signal line on the substrate. The orthographic projection of the first via 201 on the substrate overlaps with the orthographic projection of the initialization signal line on the substrate. The orthographic projection of the first via 201 on the substrate overlaps with the orthographic projection of the interconnect structure 204 on the substrate.

[0099] Optionally, the orthographic projection of the second via 202 on the substrate overlaps with the orthographic projection of the interconnect structure 204 on the substrate. The orthographic projection of the second via 202 on the substrate overlaps with the orthographic projection of the active portion of the corresponding first initialization transistor on the substrate.

[0100] Optionally, the orthographic projection of the third via 203 on the substrate overlaps with the orthographic projection of the interconnect structure 204 on the substrate. The orthographic projection of the third via 203 on the substrate overlaps with the orthographic projection of the corresponding second initialization transistor on the substrate.

[0101] Specifically, such as Figure 9 and Figure 10 As shown, the first via 201 is a via penetrating the insulating layer between the first conductive layer and the second conductive layer; the second via 202 and the third via 203 are vias penetrating the insulating layer between the active layer and the second conductive layer. The access structure 20 of this embodiment includes three vias and an interconnect structure. These three vias and the interconnect structure can be fabricated simultaneously when fabricating other structures in the prior art, without adding any process steps. For example, in related technologies, vias are provided between the first and second conductive layers to connect the power signal line VDD and its corresponding daemon, thereby connecting the power signal lines into a mesh structure. Vias are provided between the active layer and the second conductive layer to guide signals on the data lines to the active portion of the corresponding data writing transistor. For example, the data line, power signal line Vdd, and the interconnect structure can be obtained simultaneously by patterning the same conductive layer without adding a film layer process. The first via 201, the second via 202, and the third via 203 can be fabricated simultaneously with vias penetrating the insulating layer between the first and second conductive layers or vias penetrating the insulating layer between the active layer and the second conductive layer. Therefore, the entire structure of the access structure 20 in this embodiment can be manufactured without adding any process steps, which can save costs.

[0102] Optionally, the display panel further comprises a substrate 51, a gate insulating layer 52 and an interlayer insulating layer 53. The connection structure 30 is disposed on the substrate 51, the gate insulating layer 52 is disposed between the connection structure 30 and the first conductive layer where the initialization signal line Vref is located, and the interlayer insulating layer 53 is disposed between the first conductive layer and the second conductive layer. The first via hole 201 penetrates through the interlayer insulating layer 53, and the second via hole 202 and the third via hole 203 penetrate through the gate insulating layer 52 and the interlayer insulating layer 53.

[0103] Optionally, the second via hole 202 and the third via hole 203 corresponding to the same interconnection structure are located on opposite sides of the corresponding initialization signal line along the column direction Y.

[0104] Optionally, as Figure 9 shown, the second via hole 202 and the third via hole 203 are arranged along the column direction Y. Optionally, the first via hole 201 and the second via hole 202 are arranged along a direction intersecting the column direction Y.

[0105] Specifically, in this embodiment, the three via holes are respectively arranged in two columns. Compared with arranging the three via holes in one column, the size of the interconnection structure 205 in the column direction can be reduced, which is beneficial to improving the space utilization efficiency in the display panel and increasing the pixel density of the display panel. Optionally, the first via hole 201, the second via hole 202 and the third via hole 203 form a delta shape. The interconnection structure 204 is arranged corresponding to the shape of the three via holes, as long as it can interconnect the three via holes.

[0106] Optionally, as Figure 9 shown, a first notch 401 is provided at a position of the initialization signal line corresponding to the second via hole 202. Optionally, along the thickness direction of the display panel, the projection of the second via hole 202 overlaps with the projection of the first notch 401, that is, the orthographic projection of the second via hole 202 on the substrate 51 overlaps with the orthographic projection of the first notch 401 on the substrate 51. At least part of the projection of the second via hole 202 on the substrate 51 is embedded into the projection of the first notch 401 on the substrate 51. The width of the initialization signal line at the first notch 401 is reduced.

[0107] Specifically, by providing the first notch 401, the position of the initialization signal line Vref corresponding to the second via hole 202 is narrower than other positions, and the second via hole 202 is arranged overlapping with the first notch, so that the overall size of the initialization signal line and the second via hole 202 in the column direction is small, and more space in the display panel can be used for arranging pixel circuits, which is beneficial to increasing the pixel density.

[0108] Optionally, as Figure 9As shown, a second notch 402 is provided at the position of the initialization signal line corresponding to the third via 203. Optionally, along the thickness direction of the display panel, the projection of the third via 203 overlaps with the projection of the second notch 402, that is, the orthographic projection of the third via 203 on the substrate 51 overlaps with the orthographic projection of the second notch 402 on the substrate 51. At least a portion of the projection of the third via 203 on the substrate 51 is embedded in the projection of the second notch 402 on the substrate 51. The width of the initialization signal line decreases at the second notch 402. The first notch 401 and the second notch 402 are located on opposite sides of the initialization signal line along the column direction Y.

[0109] Specifically, by setting the second notch 402, the position of the initialization signal line Vref corresponding to the third via 203 is narrower than other positions, and the third via 203 is set to overlap with the first notch, so that the overall size of the initialization signal line and the third via 203 in the column direction is smaller, and there is more space in the display panel to set the pixel circuit, which is beneficial to increasing the pixel density.

[0110] When the initialization signal line and the scan signal line are set on the same layer, and the active layers in adjacent rows of pixel circuits are set continuously, the active layers in the overlapping area of ​​the orthographic projection of the initialization signal line on the substrate and the orthographic projection of the active layer on the substrate cannot be heavily doped during the heavy doping process due to the obstruction of the initialization signal line, resulting in low conductivity, which is equivalent to forming parasitic transistors. Therefore, the interconnect structure 204 is set to connect the initialization signal line and the active parts of multiple initialization transistors through at least three vias to ensure reliable transmission of the initialization signal.

[0111] Optionally, in the above embodiments, the access structure 20 may include a conductive material, such as a metal or indium tin oxide (ITO). The conductive layer described above may be a metal layer.

[0112] Optionally, the active layers in adjacent rows of pixel circuits are continuously arranged, or disconnected. Optionally, along the thickness direction of the display panel, the projection of the disconnected position 301 of the active layer in adjacent rows of pixel circuits overlaps with the projection of the initialization signal line. That is, the orthogonal projection of the disconnected position 301 of the active layer in adjacent rows of pixel circuits on the substrate overlaps with the orthogonal projection of the initialization signal line on the substrate.

[0113] Optionally, in the two rows of pixel circuits corresponding to the initialization signal line Vref, a connection structure 30 is provided between the first initialization transistor corresponding to the first row of pixel circuits and the second initialization transistor corresponding to the second row of pixel circuits. Optionally, as... Figure 9 and Figure 6As shown, the connection structure 30 is continuous, meaning that the active layer between the first initialization transistor in the first row of pixel circuits and the second initialization transistor in the second row of pixel circuits is continuously arranged. This arrangement is more conducive to saving display panel space and to more uniform charge diffusion in the active layer. It can be understood that the connection structure 30 is part of the active layer.

[0114] In some implementations... Figure 11 This is a schematic diagram of another type of active layer structure, which can be replaced. Figure 2 The active layer in the middle, refer to Figure 11 The active layer can be disconnected at the corresponding initialization signal line Vref. That is, the active layer between the first initialization transistor in the first row pixel circuit and the second initialization transistor in the second row pixel circuit is disconnected at the position corresponding to the initialization signal line. Figure 11 The disconnection point is 301.

[0115] Optionally, the second conductive layer is located on the side of the first conductive layer away from the active layer. Optionally, the active layer, the first conductive layer, and the second conductive layer are stacked sequentially in a direction away from the substrate.

[0116] Optionally, the access structure includes a fourth via 205; the initialization signal line Vref is connected to the active portion of the initialization transistor through the fourth via 205. The fourth via is provided in the overlapping area of ​​the orthographic projection of the initialization signal line on the substrate and the orthographic projection of the active portion of the initialization transistor on the substrate. Optionally, the active layers in adjacent rows of pixel circuits are continuously provided.

[0117] Alternatively, in other embodiments, such as Figure 12 and Figure 13 As shown, Figure 12 This is another enlarged schematic diagram of the access structure area, which can be replaced. Figure 2 The access structure in the middle, Figure 13 for Figure 12 In the cross-sectional view along the C1C2 direction, the access structure includes a fourth via 205. The first initialization transistor and the second initialization transistor connected to the access structure are also connected through a connection structure 30 located in the active layer. The initialization signal line is electrically connected to the connection structure 30 through the fourth via 205. Specifically, in this embodiment, by adding a process step, namely, adding a process to set a via in the gate insulating layer between the first conductive layer and the active layer, the initialization signal line is directly connected to the corresponding connection structure, that is, the function of the access structure is realized through the fourth via. In this embodiment, the size of the access structure is smaller, which is more conducive to increasing pixel density. In addition, the fourth via 205 in this embodiment penetrates the gate insulating layer 52.

[0118] Compared to Figure 12 and Figure 13 The corresponding solution, Figure 9 and Figure 10 The corresponding solution can simplify the process. Figure 9 and Figure 10 In the corresponding scheme, the first via 201, the second via 202, and the third via 203 can be fabricated simultaneously with the via penetrating the insulating layer between the second conductive layer and the first conductive layer, and / or the via penetrating the insulating layer between the second conductive layer and the active layer, thus avoiding the additional fabrication process of the first via 201, the second via 202, and the third via 203. For example, the gate connection line L1 of the second conductive layer is connected to the gate of the driving transistor (located in the first conductive layer) through the fifth via, and the gate connection line L1 is connected to the active part of the second initialization transistor (located in the active layer) through the sixth via. For example, the gate connection line L1 of the second conductive layer is connected to the gate of the driving transistor (located in the first conductive layer) through the fifth via, and the gate connection line L1 is connected to the active part of the threshold compensation transistor (located in the active layer) through the seventh via. For example, the active part of the first light-emitting control transistor T5 (located in the active layer) is connected to the power signal line Vdd (located in the second conductive layer) through the eighth via. The first via 201, the second via 202, and the third via 203 can be fabricated simultaneously with at least one of the fifth, sixth, seventh, and eighth vias. Data lines, power signal lines Vdd, and interconnect structures can be obtained simultaneously by patterning the same conductive layer, without the need for additional film layer processes.

[0119] Optionally, such as Figure 2 As shown, the display panel has multiple first scan signal lines S1 and multiple second scan signal lines S3 extending along the row direction X; the second initialization transistor T4 of the pixel circuit is electrically connected to the first scan signal line S1, and the first initialization transistor T7 of the pixel circuit is electrically connected to the second scan signal line S3. Optionally, the second initialization transistor T4 of each row of pixel circuits is electrically connected to one first scan signal line S1, and the first initialization transistor T7 of each row of pixel circuits is electrically connected to one second scan signal line S3. The first scan signal lines S1 and second scan signal lines S3 are disposed on the same layer as the initialization signal lines, for example, on the first conductive layer.

[0120] Optionally, the display panel includes a display area AA and a non-display area NAA surrounding at least a portion of the display area. The first scan signal line S1 and the second scan signal line S3 extend into the non-display area NAA. The non-display area NAA contains multiple cascaded gate drive circuits (i.e., shift registers). The gate drive circuits are used to provide scan signals to the scan signal lines. Their specific circuit structure and working principle are well known to those skilled in the art and will not be described in detail here.

[0121] In some implementations, such as Figure 2As shown, in two adjacent rows of pixel circuits, the second scan signal line S3 corresponding to the first row of pixel circuits is connected to the first scan signal line S1 corresponding to the second row of pixel circuits, and is connected to the output terminal of the same gate drive circuit GOA. During display, each row of pixel circuits is scanned and displayed sequentially, that is, the first row of pixel circuits is scanned first, and the second row of pixel circuits is scanned later. With this setting, when the first row of pixel circuits performs the second initialization stage and initializes the first electrode (e.g., anode) of the light-emitting element, the second row of pixel circuits performs the first initialization stage. This configuration can improve timing utilization, thereby helping to increase the refresh rate. In some other embodiments, in two adjacent rows of pixel circuits, the second scan signal line corresponding to the first row of pixel circuits and the first scan signal line corresponding to the first row of pixel circuits are connected to the output terminals of different gate drive circuits. With this configuration, the first electrode (e.g., anode) of the light-emitting element of each row of pixel circuits can be initialized in advance, thereby improving the screen flickering situation in Always-on Display (AOD) mode.

[0122] Optionally, the display area of ​​the display panel may be free of initialization signal lines extending along the column direction.

[0123] Optionally, each signal line (e.g., initialization signal line, scan signal line, data line, power signal line, etc.) may extend along the corresponding extension direction in one or more ways, such as a straight line, a curve, or a broken line. Each signal line may extend along the corresponding extension direction in one or more ways, such as with a constant width or a variable width. The specific shape of the signal lines is not limited in the embodiments of the present invention.

[0124] This invention also provides a display device, such as... Figure 14 As shown, Figure 14 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes mobile phones, tablet computers, MP3 players, MP4 players, smartwatches, smart helmets, or other wearable devices, etc. Since they include the display panel provided in any embodiment of the present invention, they also have the same beneficial effects, and will not be described in detail here.

[0125] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0126] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, The display panel comprises an initialization signal line, scan signal lines, and a plurality of pixel circuits arranged in an array; The pixel circuit comprises an initialization transistor, the initialization transistor is electrically connected to the corresponding scan signal line, the initialization signal line is electrically connected to the active portion of the initialization transistor through a connection structure, and the scan signal lines and the initialization signal line extend along a row direction; The pixel circuit comprises a first initialization transistor and a second initialization transistor, wherein the first initialization transistor and the second initialization transistor are configured to initialize different parts of the pixel circuit; an initialization signal line extending along the row direction is disposed between two adjacent rows of pixel circuits; each said initialization signal line is correspondingly provided with a plurality of said connection structures, each said connection structure connects the initialization signal line, the first initialization transistor of the first row of pixel circuits and the second initialization transistor of the second row of pixel circuits in the same column corresponding to the initialization signal line and the two adjacent rows of pixel circuits; wherein the first initialization transistor of the first row of pixel circuits and the second initialization transistor of the second row of pixel circuits are located on opposite sides of the initialization signal line in the column direction; Alternatively, an initialization signal line extending along the row direction is disposed between two adjacent rows of pixel circuits; each said initialization signal line is correspondingly provided with a plurality of said connection structures, each said connection structure connects the initialization signal line, the initialization transistor of the first row of pixel circuits and the initialization transistor of the second row of pixel circuits in the same column corresponding to the initialization signal line and the two adjacent rows of pixel circuits; wherein the initialization transistor of the first row of pixel circuits and the initialization transistor of the second row of pixel circuits are located on opposite sides of the initialization signal line in the column direction; two adjacent rows of pixel circuits are symmetrical with respect to the initialization signal line therebetween.

2. The display panel according to claim 1, characterized in that, The display panel comprises an active layer and a first conductive layer; Channels of the first initialization transistor and the second initialization transistor are disposed on the active layer, gates of the first initialization transistor and the second initialization transistor are disposed on the first conductive layer, and the initialization signal line is disposed on the first conductive layer.

3. The display panel according to claim 2, characterized in that, The display panel further comprises a second conductive layer; the connection structure comprises a first via hole, a second via hole, a third via hole and an interconnection structure; the interconnection structure is disposed on the second conductive layer, and the interconnection structure is connected to the initialization signal line through the first via hole; the interconnection structure is connected to the corresponding first initialization transistor through the second via hole, and the interconnection structure is connected to the corresponding second initialization transistor through the third via hole.

4. The display panel according to claim 3, characterized in that, The display panel further comprises data lines and / or power signal lines extending along the column direction, and the data lines and / or the power signal lines are disposed on the second conductive layer.

5. The display panel according to claim 4, characterized in that, The second conductive layer is located on a side of the first conductive layer away from the active layer.

6. The display panel according to claim 5, characterized in that, The second via hole and the third via hole are arranged along the column direction, and the first via hole and the second via hole are arranged along a direction intersecting the column direction.

7. The display panel according to claim 6, characterized in that, The first via hole, the second via hole and the third via hole form a "pin-shaped" arrangement.

8. The display panel according to claim 7, characterized in that, The initialization signal line has a first notch corresponding to the position of the second via, and along the thickness direction of the display panel, the projection of the second via overlaps with the projection of the first notch; and / or, The initialization signal line has a second notch corresponding to the position of the third via. Along the thickness direction of the display panel, the projection of the third via overlaps with the projection of the second notch.

9. The display panel according to claim 2, characterized in that, The access structure includes a fourth via; the first initialization transistor and the second initialization transistor connected to the access structure are also connected through a connection structure located in the active layer, and the initialization signal line is electrically connected to the connection structure through the fourth via.

10. The display panel according to claim 1, characterized in that, In two adjacent rows of pixel circuits, the active layer between the first initialization transistor in the first row of pixel circuits and the second initialization transistor in the second row of pixel circuits is continuously arranged; or, the active layer between the first initialization transistor in the first row of pixel circuits and the second initialization transistor in the second row of pixel circuits is disconnected at the position corresponding to the initialization signal line.

11. The display panel according to claim 1, characterized in that, The display panel is provided with multiple first scan signal lines and multiple second scan signal lines extending along the row direction; The second initialization transistor of the pixel circuit is electrically connected to the first scan signal line, and the first initialization transistor of the pixel circuit is electrically connected to the second scan signal line. The display panel has a display area and a non-display area surrounding at least a portion of the display area, and the first scan signal line and the second scan signal line extend into the non-display area.

12. The display panel according to claim 11, characterized in that, The non-display area is provided with multiple gate driving circuits. In two adjacent rows of pixel circuits, the second scan signal line corresponding to the first row of pixel circuits is connected to the first scan signal line corresponding to the second row of pixel circuits, and is connected to the output terminal of the same gate driving circuit. Alternatively, the non-display area may be provided with multiple gate driving circuits, and in two adjacent rows of pixel circuits, the second scan signal line corresponding to the first row of pixel circuits and the first scan signal line corresponding to the second row of pixel circuits may be connected to the output terminals of different gate driving circuits.

13. The display panel according to claim 12, characterized in that, The pixel circuit also includes a driving transistor; The first terminal of the second initialization transistor is connected to the corresponding initialization signal line via the access structure, the second terminal of the second initialization transistor is electrically connected to the control terminal of the driving transistor, and the control terminal of the second initialization transistor is connected to the first scan signal line. The first terminal of the first initialization transistor is connected to the initialization signal line via the access structure, the second terminal of the first initialization transistor is electrically connected to the first electrode of the light-emitting element, and the control terminal of the first initialization transistor is connected to the second scan signal line.

14. The display panel according to claim 13, characterized in that, The pixel circuit also includes a threshold compensation transistor, a data writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, and a storage capacitor; The control terminal of the driving transistor is electrically connected to the first terminal of the storage capacitor, the first terminal of the driving transistor is electrically connected to the second terminal of the first light-emitting control transistor, and the second terminal of the driving transistor is electrically connected to the first terminal of the threshold compensation transistor. The first terminal of the data writing transistor is electrically connected to the corresponding data line, the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor, and the control terminal of the data writing transistor is connected to the third scan signal line. The second terminal of the threshold compensation transistor is electrically connected to the control terminal of the driving transistor, and the control terminal of the threshold compensation transistor is connected to the third scan signal line; The first terminal of the first light-emitting control transistor is connected to the power signal line, and the control terminal of the first light-emitting control transistor is connected to the enable signal line. The first terminal of the second light-emitting control transistor is electrically connected to the second terminal of the driving transistor, the second terminal of the second light-emitting control transistor is electrically connected to the first electrode of the light-emitting element, and the control terminal of the second light-emitting control transistor is connected to the enable signal line; The second end of the storage capacitor is connected to the power signal line.

15. The display panel according to claim 1, characterized in that, The display panel includes an active layer and a first conductive layer; The channel of the initialization transistor is disposed in the active layer, and the gate of the initialization transistor, the scan signal line connected to the gate of the initialization transistor, and the initialization signal line are disposed in the first conductive layer. And / or, the display panel further includes a second conductive layer; the access structure includes a first via, a second via, and an interconnect structure; the interconnect structure is disposed on the second conductive layer, and the interconnect structure is connected to the initialization signal line through the first via; the interconnect structure is connected to the initialization transistor through the second via. And / or, the display panel further includes data lines and / or power signal lines extending along the column direction, the data lines and / or the power signal lines being disposed on the second conductive layer; And / or, the second conductive layer is located on the side of the first conductive layer away from the active layer; And / or, the access structure includes a fourth via; the initialization signal line is connected to the active portion of the initialization transistor through the fourth via; And / or, the active layers in two adjacent rows of the pixel circuit are continuously arranged, or they are disconnected, and along the thickness direction of the display panel, the projection of the disconnected position of the active layer in two adjacent rows of the pixel circuit overlaps with the projection of the initialization signal line.

16. A display device, characterized in that, The display device includes the display panel as described in any one of claims 1-15.

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