Superconducting interface circuit with clock comparator

Abstract

The application belongs to the technical field of superconducting integrated circuits, and particularly relates to a superconducting interface circuit with a clock comparator. The application inserts a clock comparator at the input end of the interface circuit, and converts a reference clock with the same frequency as the AC bias of the Josephson latch driver JLD in the subsequent stage into a pulse clock available for the comparator through the addition of a DC-SFQ Converter, so that the influence of interference signals such as input end noise glitches can be greatly reduced. In addition, the DC bias of the input end of the comparator can be controlled separately, so that the recognition interval of the input signal can be adjusted, the adaptation capability between the superconducting circuit to be amplified and the previous stage is further improved, and thus a superconducting interface circuit with both anti-interference capability and flexibility is realized.

Description

Technical Field

[0001] This invention belongs to the field of superconducting integrated circuit technology, specifically relating to a superconducting interface circuit with a clock comparator. Background Technology

[0002] Superconducting single-flux quantum (SFQ) circuits, due to their zero resistance, low signal amplitude, small duty cycle, and quantum-based information transmission and storage, offer lower power consumption and higher operating speeds compared to CMOS circuits. With their unique technological potential and application prospects, they are attracting significant attention as an emerging research direction in the field of integrated circuit technology. As superconducting electronics technology develops, superconducting circuits have been extensively researched and developed in areas such as high-performance processors and analog-to-digital (A / D) converters. However, research on large-scale superconducting memories is currently limited by the low driving capability of superconducting circuits and the difficulty in achieving high-density integration. Therefore, combining superconducting SFQ circuit systems with mature large-scale CMOS memories provides a good solution for the research of high-performance superconducting computers. Thus, studying how to achieve interconnection and transmission between superconducting circuits and CMOS circuits has significant theoretical and practical application value.

[0003] The SFQ signal generated by a superconducting circuit is only a pulse signal of a few hundred microvolts, while CMOS circuits typically transmit signals in the volt-ampere range. Generally, signal transmission from a CMOS circuit to an SFQ circuit can be achieved using a superconducting circuit DC-SFQ converter. However, transmission from an SFQ circuit to a CMOS circuit requires an interface circuit capable of detecting the tiny SFQ pulse signal and achieving high amplification to drive the CMOS circuit. There are two main superconducting interface circuit structures that enable superconducting SFQ-CMOS circuit transmission: one uses a DC-biased superconducting quantum interference device (SQUID); the other uses an AC-biased Suzuki stack (SS). SQUIDs have unique advantages in signal sensitivity detection, but as an interface circuit requiring high amplification, they are implemented using multi-segment SQUID arrays, resulting in larger area and higher power consumption. The Suzuki Stack achieves high amplification while maintaining a small area by increasing the number of series Josephson junctions (JJs). However, it struggles to detect minute inputs and has a fixed range for recognizing input signals, reducing its flexibility in adapting to pre-amplifier systems. Furthermore, it is susceptible to interference from input noise and glitches, leading to incorrect recognition and amplification. To address these shortcomings of traditional superconducting interface circuits, a more flexible and interference-resistant interface circuit is needed. Summary of the Invention

[0004] To address the issues of fixed input signal detection range and weak anti-interference capability in existing superconducting interface circuits, this invention proposes a superconducting interface circuit with a clock comparator. Compared to traditional interface circuits, this circuit can adjust the threshold of the input signal detection, improve the flexibility of adaptation to the input end, and enhance the circuit's anti-interference capability.

[0005] The technical solution of this invention is:

[0006] A superconducting interface circuit with a clock comparator includes:

[0007] A DC-SFQ converter is used to convert an external level clock into a pulse clock, which can be used as a comparison clock that can be recognized by a clock comparator.

[0008] The comparator is connected to the input signal and the pulse clock output by the DC-SFQ Converter, respectively, and is used to compare the input signal and the clock pulse signal.

[0009] The Josephson Latch Driver (JLD) is connected to a clock comparator and is used to amplify the input signal detected by the clock comparator.

[0010] The DC-SFQ Converter consists of a Josephson junction and a Josephson Transmission Line (JTL) connected in series.

[0011] The comparator includes two input terminals, which are connected via a superconducting ring composed of Josephson junctions.

[0012] The Josephson latch driver consists of two stages of amplification units. The first stage amplification unit is a 4-Josephson latch (4JL) structure composed of two Josephson junctions connected in series in two rows. The second stage amplification unit is a Suzuki stack (SS) structure composed of eighteen Josephson junctions connected in series in two rows.

[0013] The DC-to-single-throughput quantum converter includes a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, a seventh inductor, an eighth inductor, a ninth inductor, a first Josephson junction, a second Josephson junction, a third Josephson junction, a fourth Josephson junction, a fifth Josephson junction, a first bias current source, and a second bias current source. The first inductor, third inductor, first Josephson junction, fourth inductor, fifth inductor, sixth inductor, seventh inductor, eighth inductor, and ninth inductor are connected in series. The first inductor is connected to the input terminal, and the ninth inductor is connected to the output terminal. One end of the second inductor is connected to the junction point of the first and third inductors, and the other end of the second inductor is grounded. One end of the second Josephson junction is connected to the junction point of the first and fourth Josephson junctions, and the other end of the second Josephson junction is grounded. The first bias current source... The output is connected to the junction of the fourth and fifth inductors; one end of the third Josephson junction is connected to the junction of the fifth and sixth inductors, and the other end is grounded; the output of the second bias current source is connected to the junction of the sixth and seventh inductors; one end of the fourth Josephson junction is connected to the junction of the seventh and eighth inductors, and the other end is grounded; one end of the fifth Josephson junction is connected to the junction of the eighth and ninth inductors, and the other end is grounded; the rising edge of the input level signal, together with the first and second bias current sources, causes the second, third, fourth, and fifth Josephson junctions to be triggered sequentially, generating superconducting single-flux quantum pulses; the falling edge of the input level signal triggers the first Josephson junction, causing the flux quantum to escape and no output to be generated. The superconducting loop formed by the inductor connected in parallel at the input of the DC-SFQ Converter, the series Josephson junction, and the first Josephson structure of the Josephson transmission line serves as the clock input port, used to identify the rising edge of the level signal.

[0014] The comparator includes a tenth inductor, an eleventh inductor, a twelfth inductor, a thirteenth inductor, a fourteenth inductor, a fifteenth inductor, a sixteenth inductor, a seventeenth inductor, an eighteenth inductor, a nineteenth inductor, a twentieth inductor, a sixth Josephson junction, a seventh Josephson junction, an eighth Josephson junction, a ninth Josephson junction, a tenth Josephson junction, an eleventh Josephson junction, a third bias current source, a fourth bias current source, and a control current source. One end of the tenth inductor is the signal input terminal of the comparator, connected to the input signal, and the other end of the tenth inductor is connected in series with the eleventh, twelfth, seventeenth, eighteenth, nineteenth, and twentieth inductors. One end of the thirteenth inductor is the clock signal input terminal of the comparator, connected to the ninth inductor, and the other end of the thirteenth inductor is connected in series with the fourteenth, fifteenth, and sixteenth inductors. One end of the seventh Josephson junction is connected to the junction point of the thirteenth and fourteenth inductors, and the other end of the seventh Josephson junction is grounded. The output of the third bias current source is connected to the sixth Josephson junction. The connection point of the fourteenth and fifteenth inductors; one end of the eighth Josephson junction is connected to the connection point of the fifteenth and sixteenth inductors, and the other end of the eighth Josephson junction is grounded; one end of the ninth Josephson junction is connected to the sixteenth inductor, and the other end is connected to the connection point of the twelfth and seventeenth inductors; the output of the control current source is connected to the connection point of the tenth and eleventh inductors; one end of the sixth Josephson junction is connected to the connection point of the eleventh and twelfth inductors, and the other end of the sixth Josephson junction is grounded; one end of the tenth Josephson junction is connected to the other end of the seventeenth and eighteenth inductors, and the other end of the tenth Josephson junction is grounded; the output of the fourth bias current source is connected to the connection point of the eighteenth and nineteenth inductors; one end of the eleventh Josephson junction is connected to the connection point of the nineteenth and twentieth inductors, and the other end of the eleventh Josephson junction is grounded; the ninth Josephson junction is set to a small critical current, which means that the Josephson junction can be triggered to escape when the clock signal is absent.

[0015] Furthermore, in the four Josephson latch structure of the Josephson latch driver, the connection point of the two Josephson junctions in the first column is connected to the input terminal via a series Josephson junction.

[0016] Furthermore, the Josephson junction at the connection point is used to prevent the Josephson latch driver from generating a return current that is input to the preceding circuit and affects its normal operation after being triggered.

[0017] Furthermore, the two Josephson junctions of the first column connected to the input terminal of the quad Josephson latch structure are set to a smaller threshold current so that they can be triggered by a smaller input current, while the two Josephson junctions of the other column are set to a larger threshold current so that they can more easily trigger the subsequent Suzuki stack structure.

[0018] Furthermore, the Suzuki stack structure of the Josephson latch driver includes a dual-row Josephson junction branch. One row of branches closer to the quad Josephson latch structure is defined as the first row of Josephson junction branches, and the other row closer to the output is defined as the second row of Josephson junction branches. Each dual-row Josephson junction branch includes eighteen Josephson junctions connected in series and a distribution resistor connected to the AC bias, which are then connected in parallel and simultaneously connected to the output resistor.

[0019] Furthermore, the connection point of the double-row Josephson junction branch of the quad Josephson latch structure is connected to the connection point of the second and third Josephson junctions near the ground end of the first row of Josephson junction branches of the Suzuki stack structure via a resistor.

[0020] Furthermore, the quad Josephson latch structure first drives the two Josephson junctions connected to its output terminal on the first row of Josephson junction branches of the Suzuki stack structure, which are easier to trigger. Then, under the combined action of the bias current, it alternately triggers the double-row Josephson junction branches of the Suzuki stack, generating a stable output voltage in the tens of millivolts range.

[0021] The beneficial effects of this invention are as follows: By inserting a clocked comparator at the input of the interface circuit and adding a DC-SFQ converter to transform the reference clock, which is in sync with the AC bias of the subsequent Josephson latch driver (JLD), into a pulse clock usable by the comparator, the influence of interference signals such as input noise and glitches can be greatly reduced. Furthermore, by individually controlling the DC bias at the comparator input, the recognition range of the input signal can be adjusted, further improving the compatibility with different superconducting circuits to be amplified in the preceding stage. This results in a superconducting interface circuit that simultaneously possesses anti-interference capabilities and flexibility. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a superconducting interface circuit with a clock comparator according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the DC-SFQ Converter in an embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of the comparator in an embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the Josephson latch driver in an embodiment of the present invention;

[0026] Figure 5For comparison, (a) is the working waveform of a traditional Josephson latch driver interface circuit facing an input signal with glitches, and (b) is the waveform of a superconducting interface circuit with a clock comparator according to an embodiment of the present invention that avoids glitches and accurately identifies and amplifies the input. Detailed Implementation

[0027] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings:

[0028] like Figure 1 As shown, a superconducting interface circuit with a clock comparator in an embodiment of the present invention includes a DC-SFQConverter, a comparator, and a Josephson latch driver.

[0029] The DC-SFQ Converter receives the periodic level signal of the input clock and generates a periodic pulse clock signal;

[0030] The comparator accepts the input signal and the pulse clock signal output by the DC-SFQ Converter, and outputs the SFQ pulse signal to drive the subsequent Josephson latch driver.

[0031] The Josephson latch driver consists of two stages of amplifier circuits. The front quad Josephson latch driver structure detects the SFQ pulse signal output by the comparator. Under the combined action of its AC bias, which is in the same frequency as the clock signal of the previous stage, it outputs a level signal. Furthermore, through the combined action of the Suzuki stack structure and its own AC bias, it amplifies the signal again to generate a stable level output signal.

[0032] In the above embodiments, the DC-SFQ Converter, as a level signal conversion circuit, takes a clock level signal as input and generates an SFQ clock signal to provide a reference SFQ clock for the comparator.

[0033] The comparator compares the input signal with a reference SFQ clock and outputs an SFQ pulse signal to avoid noise glitches caused by the input signal. At the same time, by adjusting the DC bias at the comparator input, the threshold of the received input signal amplitude can be controlled, thereby changing the recognition range of the detected input signal.

[0034] The Josephson latch driver, as a two-stage amplifier circuit, accepts the SFQ pulse signal output from the comparator and generates an output voltage in the tens of millivolt range to drive CMOS circuits.

[0035] Figure 2The diagram shows the schematic of a DC-SFQ converter. The input terminals are connected sequentially to the first inductor L1, the second inductor L2, the third inductor L3, the first Josephson junction J1, and the second Josephson junction J2. The rising edge of the input level signal and the DC bias I... bias1 I bias2 The combined effect causes the second Josephson junction J2, the third Josephson junction J3, the fourth Josephson junction J4, and the fifth Josephson junction J5 to be triggered sequentially, generating SFQ pulses; the falling edge of the input level signal triggers the first Josephson junction J1, causing the magnetic flux quantum to escape and no output to be generated.

[0036] Figure 3 The diagram shows the comparator's schematic. The clock input is connected to the output of the DC-SFQ converter, and the clock pulse input is connected to the DC bias I. bias3 The combined effect causes the seventh Josephson junction J7 and the eighth Josephson junction J8 to be triggered sequentially, and only when the input signal and DC control bias I are applied. Cbias The sixth Josephson junction J6 can only be triggered when both conditions are present, and under DC bias I... bias4 Under the combined effect of these factors, the tenth Josephson node J is triggered in sequence. 10 And the Eleventh Josephson 11 This generates an SFQ pulse output.

[0037] In the above embodiment, the critical current setting value of the sixth Josephson junction J6 is greater than the critical current setting value of the ninth Josephson junction J9. If only a clock signal is input, the sixth Josephson junction J6 will not trigger, while the ninth Josephson junction J9 will trigger, resulting in magnetic flux quantum escape and no output. If only an input signal is input, the sixth Josephson junction J6 will also not trigger, effectively avoiding the output of interference signals.

[0038] Figure 4 The diagram shows the schematic of a Josephson junction latch driver, including a front-end quad Josephson latch structure and a rear-end Suzuki stack structure. The quad Josephson latch structure consists of two series-connected Josephson junctions connected in parallel in a double-row configuration, specifically the twelfth Josephson junction J... 12 And Josephson the Thirteenth 13 The Fourteenth Josephson Term 14 And the Fifteenth Josephson 15 The Suzuki stack structure consists of two rows of eighteen series-connected Josephson junctions connected in parallel. The row connected to the four-Josephson latch structure is the sixteenth Josephson junction J. 16 The Seventeenth Josephson Term 17 Until the thirty-third Josephson junction J 33 The other column of tandem Josephson nodes is the thirty-fourth Josephson node J. 34The thirty-fifth Josephson knot J 35 Until the fifty-first Josephson junction J 51 .

[0039] The twelfth Josephson node of the four Josephson latch structure J 12 And Josephson the Thirteenth 13 The connection point serves as the input terminal, connected to the comparator output terminal via a Josephson junction in series. in Connection, and the fourteenth Josephson junction J 14 And the Fifteenth Josephson 15 The connection point, serving as the output terminal, is connected to the seventeenth Josephson junction of the Suzuki stack structure via a first resistor R1. 17 And the Eighteenth Josephson 18 Connection point. AC bias AC Bias1 is connected through bias resistor R. b1 Connected to the thirteenth Josephson node J 13 And the Fifteenth Josephson 15 At the connection point, it is connected to the first resistor R1.

[0040] The thirty-third Josephson knot of the Suzuki stack structure J 33 The bias resistor R is connected to the second resistor R2 and the AC bias resistor R of AC bias AC Bias2. b2 Connection, Josephson Node J (Thirty-Fourth) 34 The third resistor R3 is connected to the second resistor R2 and the bias resistor R, respectively. b2 The connection between the output terminal and the second resistor R2 and the third resistor R3 is achieved through the output resistor R. out connect.

[0041] The input signal of the Josephson junction latch driver passes through a Josephson junction J connected in series with the input terminal. in The subsequent interaction with the AC bias AC Bias1 causes the twelfth Josephson junction J 12 Triggered, it becomes a resistive state, thus causing more of the bias current originally supplied to the dual-row Josephson junction by the AC bias (AC Bias1) in the quadruple Josephson latch structure to flow into the fourteenth Josephson junction (J). 14 And the Fifteenth Josephson 15 The current in the branch triggers both Josephson junctions on that branch, and the bias current provided by AC bias AC Bias1 flows to another branch, causing the twelfth Josephson junction J on that branch to be triggered. 12 And Josephson the Thirteenth 13All modules are triggered. The dual-row Josephson junctions continue to trigger alternately, generating output, until the AC bias (AC Bias1) goes low. Furthermore, because the Josephson junctions in the quad Josephson latch structure are designed to be underdamped, the hysteresis effect of the underdamped Josephson junctions allows the quad Josephson latch structure to output a stable level signal.

[0042] The output level of the four Josephson latch structure, after passing through the first resistor R1, is affected by the AC bias AC Bias2, causing the sixteenth Josephson junction J of the Suzuki stack structure to... 16 And the Seventeenth Josephson 17 It is the first to trigger, becoming a resistive state. Therefore, similar to the principle of the four Josephson latch structure, the bias current provided by AC bias AC Bias2 flows concentrated towards the thirty-fourth Josephson junction J. 34 The branch in question triggers all eighteen Josephson junctions in that branch. Then, under the action of AC Bias2, the dual-row underdamped Josephson junctions of the Suzuki stack are triggered alternately, generating a stable level at the output through the hysteresis effect.

[0043] In the above embodiments, Josephson junction J in The design effectively isolates the backflow current generated by the AC bias ACBias1 of the quad Josephson latch structure from the impact on the preceding comparator. Similarly, the first resistor R1 reduces the impact of the backflow current generated by the AC bias AC Bias2 of the Suzuki stack structure on the preceding circuit. The output voltage signal of the Josephson latch driver is positively correlated with the number of series-connected dual-row Josephson junctions in the Suzuki stack structure. This design uses eighteen series-connected dual-row Josephson junctions, which can generate an output voltage of over forty millivolts. Technical personnel can also design the number of series-connected Josephson junctions according to actual needs.

[0044] like Figure 5 As shown, (a) is the waveform diagram of a traditional Josephson latch driver interface circuit facing an input signal with glitches. The input signal uses a periodic level signal of "1100" and adds noise glitches that may be caused by the output of the pre-stage in actual operation. From the output waveform, it can be seen that the Josephson latch driver also amplifies the glitches and stops outputting only after the AC bias AC Bias2 drops to a low level, thus producing an incorrect output. (b) is the waveform diagram of a superconducting interface circuit with a clock comparator according to an embodiment of the present invention facing a glitchy input under the same conditions. Due to the addition of the clock signal and the comparator, the comparator will only output a pulse signal when an input signal arrives at the rising edge of the clock signal. After filtering by the comparator, the input signal is converted from a level signal to an SFQ pulse signal, and successfully avoids the glitches and is output to the Josephson latch driver, and then amplified to a level signal of more than 40 millivolts.

[0045] Optionally, the superconducting interface circuit with clock comparator of the present invention can be packaged separately, and the DC bias I at the comparator input terminal can be adjusted. Cbias Size recognition amplifies input signals of different sizes, which can be adapted to different superconducting circuits to be amplified.

Claims

1. A superconducting interface circuit with a clock comparator, characterized in that, include: A DC-to-single-flux quantum converter for converting an external level clock into a pulse clock; The comparator is connected to the input signal and the pulse clock output from the DC current-to-single-throughput quantum converter, respectively, and is used to compare the input signal and the pulse clock signal. The Josephson latch driver has its input connected to the output of a comparator, which is used to amplify the input signal detected by the comparator. The output of the Josephson latch driver is the output of the superconducting interface circuit. The DC-to-single-flux quantum converter consists of a Josephson junction and a Josephson transmission line connected in series. The two input terminals of the comparator are connected via superconducting rings composed of Josephson junctions. The Josephson latch driver consists of two stages of amplification units. The first stage amplification unit is a quad Josephson latch structure consisting of two Josephson junctions connected in series in two rows, and the second stage amplification unit is a Suzuki stack structure consisting of eighteen Josephson junctions connected in series in two rows. The comparator includes a tenth inductor, an eleventh inductor, a twelfth inductor, a thirteenth inductor, a fourteenth inductor, a fifteenth inductor, a sixteenth inductor, a seventeenth inductor, an eighteenth inductor, a nineteenth inductor, a twentieth inductor, a sixth Josephson junction, a seventh Josephson junction, an eighth Josephson junction, a ninth Josephson junction, a tenth Josephson junction, an eleventh Josephson junction, a third bias current source, a fourth bias current source, and a control current source. One end of the tenth inductor is the signal input terminal of the comparator, connected to the input signal; the other end of the tenth inductor is connected in series with the eleventh, twelfth, seventeenth, eighteenth, nineteenth, and twentieth inductors. One end of the thirteenth inductor is the clock signal input terminal of the comparator, connected to the ninth inductor; the other end of the thirteenth inductor is connected in series with the fourteenth, fifteenth, and sixteenth inductors. One end of the seventh Josephson junction is connected to the thirteenth and fourteenth inductors. The connection points are as follows: the seventh Josephson junction is connected to ground at one end; the output of the third bias current source is connected to the connection point of the fourteenth and fifteenth inductors; one end of the eighth Josephson junction is connected to the connection point of the fifteenth and sixteenth inductors, and the other end of the eighth Josephson junction is grounded; one end of the ninth Josephson junction is connected to the sixteenth inductor, and the other end is connected to the connection point of the twelfth and seventeenth inductors; the output of the control current source is connected to the connection point of the tenth and eleventh inductors; one end of the sixth Josephson junction is connected to the connection point of the eleventh and twelfth inductors, and the other end of the sixth Josephson junction is grounded; one end of the tenth Josephson junction is connected to the other end of the seventeenth and eighteenth inductors, and the other end of the tenth Josephson junction is grounded; the output of the fourth bias current source is connected to the connection point of the eighteenth and nineteenth inductors; one end of the eleventh Josephson junction is connected to the connection point of the nineteenth and twentieth inductors, and the other end of the eleventh Josephson junction is grounded. The ninth Josephson junction is configured with a small threshold current, which means that the Josephson junction can be triggered to escape when there is no input signal. The superconducting interface circuit with clock comparator is packaged separately. By adjusting the DC bias at the comparator input, it can identify and amplify input signals of different ranges, adapting to different superconducting circuits to be amplified.

2. The superconducting interface circuit with a clock comparator according to claim 1, characterized in that, The DC-to-single-throughput quantum converter includes a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, a seventh inductor, an eighth inductor, a ninth inductor, a first Josephson junction, a second Josephson junction, a third Josephson junction, a fourth Josephson junction, a fifth Josephson junction, a first bias current source, and a second bias current source. The first inductor, third inductor, first Josephson junction, fourth inductor, fifth inductor, sixth inductor, seventh inductor, eighth inductor, and ninth inductor are connected in series. The first inductor is connected to the input terminal, and the ninth inductor is connected to the output terminal. One end of the second inductor is connected to the junction point of the first and third inductors, and the other end of the second inductor is grounded. One end of the second Josephson junction is connected to the junction point of the first and fourth Josephson junctions, and the other end of the second Josephson junction is grounded. The first bias current source... The output is connected to the junction of the fourth and fifth inductors; one end of the third Josephson junction is connected to the junction of the fifth and sixth inductors, and the other end of the third Josephson junction is grounded; the output of the second bias current source is connected to the junction of the sixth and seventh inductors; one end of the fourth Josephson junction is connected to the junction of the seventh and eighth inductors, and the other end of the fourth Josephson junction is grounded; one end of the fifth Josephson junction is connected to the junction of the eighth and ninth inductors, and the other end of the fifth Josephson junction is grounded; the rising edge of the input level signal and the combined action of the first and second bias current sources cause the second, third, fourth, and fifth Josephson junctions to be triggered sequentially, generating superconducting single flux quantum pulses; the falling edge of the input level signal triggers the first Josephson junction, causing the flux quantum to escape and no output to be generated.

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