A gate driving circuit and a display panel

Abstract

This invention discloses a gate driving circuit and a display panel. The gate driving circuit includes a multi-stage shift register; the shift register includes a drive control module, a stage output module, a transmission control module, and a gate output module; the drive control module is used to output a first control signal to a second output terminal of the drive control module based on at least a first clock signal and an input signal, and to output a second control signal to a first output terminal of the drive control module; the stage output module is used to output a stage output signal to the output terminal of the stage output module based on at least the first control signal and the second control signal; the transmission control module is used to output a third control signal to the output terminal of the transmission control module based on at least a frequency control signal and the first control signal; the gate output module is used to output a gate driving signal based on at least the first control signal and the third control signal. Embodiments of this invention enable the display panel to have a segmented frequency display function.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a gate driving circuit and a display panel. Background Technology

[0002] With the development of display technology, the application scenarios of display panels are increasing, and users' display needs are becoming more diversified. Based on the release of products such as foldable phones and foldable laptops, the application scenarios of display panels have been further expanded. For users' needs to display multiple applications simultaneously on terminal products, some interfaces (such as game interfaces) require high-frequency display to ensure smooth visuals, while other interfaces can meet display requirements with low frequencies to reduce power consumption. However, existing gate drive circuits cannot meet users' needs for displaying multiple scenes on a single screen, and cannot achieve segmented frequency display on the display panel. Summary of the Invention

[0003] The present invention provides a gate driving circuit and a display panel to enable the display panel to have a segmented frequency display function.

[0004] In a first aspect, the present invention provides a gate driving circuit, comprising: a multi-stage shift register; the shift register comprising: a drive control module, a stage output module, a transmission control module, and a gate output module; a first output terminal of the drive control module is connected to a first control terminal of the stage output module, a second output terminal of the drive control module is connected to a second control terminal of the stage output module, a control terminal of the transmission control module, and a first control terminal of the gate output module, and an output terminal of the transmission control module is connected to a second control terminal of the gate output module; the drive control module is configured to output a first control signal to the second output terminal of the drive control module at least according to a first clock signal and an input signal, and to output a second control signal to the first output terminal of the drive control module; the stage output module is configured to output a stage output signal to the output terminal of the stage output module at least according to the first control signal and the second control signal; the transmission control module is configured to output a third control signal to the output terminal of the transmission control module at least according to a frequency control signal and the first control signal; the gate output module is configured to output a gate driving signal according to the first control signal and the third control signal.

[0005] Optionally, the transmission control module includes: a first inverter and an output control unit; the input terminal of the first inverter serves as the control terminal of the transmission control module, the output terminal of the first inverter is connected to the input terminal of the output control unit, the control terminal of the output control unit is used to input a frequency control signal, the output terminal of the output control unit serves as the output terminal of the transmission control module, the first inverter is used to invert the first control signal and output a first inverted control signal, and the output control unit is used to generate a third control signal based at least on the first inverted control signal and the frequency control signal; optionally, the second control signal and the first control signal have opposite potentials; optionally, the first terminal of the first inverter is used to input a first power supply signal, and the second terminal of the first inverter is used to input a second power supply signal.

[0006] Optionally, the frequency control signal includes a first frequency control signal and a second frequency control signal; the output control unit includes a first transistor and a second transistor; the gate of the first transistor serves as the first control terminal of the output control unit for inputting the first frequency control signal, the first electrode of the first transistor serves as the input terminal of the output control unit, the second electrode of the first transistor is connected to the first electrode of the second transistor and serves as the output terminal of the output control unit, the gate of the second transistor serves as the second control terminal of the output control unit for inputting the second frequency control signal, and the second electrode of the second transistor is used to input the first power supply signal.

[0007] Optionally, the frequency control signal further includes a first frequency inverse control signal, and the output control unit further includes a third transistor, the gate of which serves as the third control terminal of the output control unit for inputting the first frequency inverse control signal. Alternatively, the output control unit further includes a second inverter and a third transistor, the input terminal of the second inverter is electrically connected to the first control terminal of the output control unit for inputting the first frequency control signal, and the output terminal of the second inverter is electrically connected to the gate of the third transistor; the first terminal of the third transistor is connected to the first terminal of the first transistor, and the second terminal of the third transistor is connected to the second terminal of the first transistor; wherein the third transistor and the first transistor have different channel types; Optionally, the second inverter includes a fourth transistor and a fifth transistor; the gate of the fourth transistor is connected to the gate of the fifth transistor and serves as the input terminal of the second inverter for inputting the first frequency control signal, the first terminal of the fourth transistor is used to input a first power supply signal, the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor and the gate of the third transistor respectively, and the second terminal of the fifth transistor is used to input a second power supply signal; Optionally, at least two of the shift registers share the same second inverter.

[0008] Optionally, the shift register further includes a sixth transistor; the gate of the sixth transistor is used to input a second power supply signal, and the output of the transmission control module is connected to the second control terminal of the gate output module through the sixth transistor.

[0009] Optionally, the first inverter includes a seventh transistor and an eighth transistor; the gate of the seventh transistor is connected to the gate of the eighth transistor and serves as the input terminal of the first inverter; the first terminal of the seventh transistor serves as the first terminal of the inverter for inputting a first power supply signal; the second terminal of the seventh transistor is connected to the first terminal of the eighth transistor and serves as the output terminal of the first inverter; the second terminal of the eighth transistor serves as the second terminal of the first inverter for inputting a second power supply signal.

[0010] Optionally, the drive control module includes an input unit, a node feedback unit, a second inverting unit, and a third inverting unit. The input unit generates a second control signal based on a first clock signal and an input signal. The input terminal of the second inverting unit is connected to the output terminal of the input unit, and the second inverting unit inverts the second control signal to generate a first control signal. The input terminal of the third inverting unit is connected to the output terminal of the second inverting unit, and the third inverting unit inverts the first control signal to output a second inverted control signal. The node feedback unit is connected between the output terminal of the third inverting unit and the input terminal of the second inverting unit. The unit is used to control the potential of the second control signal according to the first clock signal and / or the first inverted clock signal and the second inverted control signal; optionally, the switching states of the input unit and the node feedback unit are opposite; optionally, the drive control module further includes a first inverting unit, the output terminal of which is connected to the input unit and / or the node feedback unit, the first inverting unit being used to invert the first clock signal and output the first inverted clock signal; the input unit is used to generate the second control signal according to the first clock signal and / or the first inverted clock signal and the input signal; optionally, at least two shift registers share the same first inverting unit. The potentials of the first clock signal and the first inverted clock signal are opposite, for example, when one of the first clock signal and the first inverted clock signal transitions to a high level, the other transitions to a low level.

[0011] Optionally, the input unit includes a ninth transistor, the gate of which is used to input a first inverted clock signal, the first terminal of which is used to receive the input signal and serves as the input terminal of the input unit, and the second terminal of which serves as the output terminal of the input unit; and / or, the input unit further includes a tenth transistor, the gate of which is used to input the first clock signal, the first terminal of which is used to receive the input signal and serves as the input terminal of the input unit, and the second terminal of which is connected as the output terminal of the input unit; optionally, the tenth transistor and the ninth transistor have different channel types. Optionally, the node feedback unit includes an eleventh transistor, the gate of which is used to input the first clock signal, the first terminal of which is used to receive a second inverted control signal and serves as the input terminal of the node feedback unit, and the second terminal of which serves as the output terminal of the node feedback unit; and / or, the node feedback unit further includes a twelfth transistor, the gate of which is used to input the first inverted clock signal, the first terminal of which is used to receive the second inverted control signal and serves as the input terminal of the node feedback unit, and the second terminal of which serves as the output terminal of the node feedback unit; optionally, the twelfth transistor and the eleventh transistor have different channel types. Optionally, the first inverting unit includes a thirteenth transistor and a fourteenth transistor. The gates of the thirteenth and fourteenth transistors are connected and serve as the input terminal of the first inverting unit for inputting a first clock signal. The first terminal of the thirteenth transistor is used to input a first power supply signal. The second terminal of the thirteenth transistor is connected to the first terminal of the fourteenth transistor and serves as the output terminal of the first inverting unit. The second terminal of the fourteenth transistor is used to input a second power supply signal. Optionally, the second inverting unit includes a fifteenth transistor and a sixteenth transistor. The gates of the fifteenth and sixteenth transistors are connected and serve as the input terminal of the second inverting unit for inputting a second control signal. The first terminal of the fifteenth transistor is used to input the first power supply signal. The second terminal of the fifteenth transistor is connected to the first terminal of the sixteenth transistor and serves as the output terminal of the second inverting unit. The second terminal of the sixteenth transistor is used to input a second power supply signal. Optionally, the third inverting unit includes a seventeenth transistor and an eighteenth transistor. The gates of the seventeenth transistor and the eighteenth transistor are connected and serve as the input terminal of the third inverting unit for inputting a first control signal. The first terminal of the seventeenth transistor is used to input a first power supply signal. The second terminal of the seventeenth transistor is connected to the first terminal of the eighteenth transistor and serves as the output terminal of the third inverting unit. The second terminal of the eighteenth transistor is used to input a second power supply signal. Optionally, the drive control module further includes a nineteenth transistor. The gate of the nineteenth transistor is used to input the second power supply signal. The first terminal of the nineteenth transistor is connected to both the output terminal of the input unit and the output terminal of the node feedback unit. The second terminal of the nineteenth transistor serves as the first output terminal of the drive control module.

[0012] Optionally, the stage output module includes a first output unit and a second output unit; the control terminal of the first output unit serves as the second control terminal of the stage output module, the input terminal of the first output unit is used to input a first power signal, and the output terminal of the first output unit is connected to the output terminal of the second output unit and serves as the output terminal of the stage output module; the control terminal of the second output unit serves as the first control terminal of the stage output module, the input terminal of the second output unit is used to input a second clock signal, and the first and second output units are used to output a first power signal or a second clock signal as stage output signals according to the first and second control signals. Optionally, the first output unit is used to output a first power signal to the output terminal of the stage output module according to the first control signal; the second output unit is used to output a second clock signal to the output terminal of the stage output module according to the second control signal. Optionally, the first output unit includes a twentieth transistor, the gate of the twentieth transistor serves as the control terminal of the first output unit, the first terminal of the twentieth transistor serves as the input terminal of the first output unit, and the second terminal of the twentieth transistor serves as the output terminal of the first output unit. Optionally, the second output unit includes a twenty-first transistor and a first capacitor; the gate of the twenty-first transistor serves as the control terminal of the second output unit, the first terminal of the twenty-first transistor serves as the output terminal of the second output unit, and the second terminal of the twenty-first transistor serves as the input terminal of the second output unit; the first capacitor is connected between the gate and the first terminal of the twenty-first transistor. Optionally, the output terminal of the stage output module of the previous stage shift register is connected to the input terminal of the drive control module of the next stage shift register.

[0013] Optionally, the gate output module includes a third output unit and a fourth output unit; the control terminal of the third output unit serves as the first control terminal of the gate output module, the input terminal of the third output unit is used to input a first power supply signal, and the output terminal of the third output unit is connected to the output terminal of the fourth output unit and serves as the output terminal of the gate output module; the control terminal of the fourth output unit serves as the second control terminal of the gate output module, the input terminal of the fourth output unit is used to input a second clock signal, and the third and fourth output units are used to output a first power supply signal or a second clock signal as a gate drive signal according to the first control signal and the third control signal. Optionally, the third output unit is used to output a first power supply signal to the output terminal of the gate output module according to the first control signal; the fourth output unit is used to output a second clock signal to the output terminal of the gate output module according to the third control signal. Optionally, the third output unit includes a second capacitor and a twenty-second transistor, the gate of the twenty-second transistor serves as the control terminal of the third output unit, the first terminal of the twenty-second transistor serves as the input terminal of the third output unit, and the second terminal of the twenty-second transistor serves as the output terminal of the third output unit; the second capacitor is connected between the gate and the first terminal of the twenty-second transistor. Optionally, the fourth output unit includes a third capacitor and a twenty-third transistor. The gate of the twenty-third transistor serves as the control terminal of the fourth output unit, the first terminal of the twenty-third transistor serves as the output terminal of the fourth output unit, and the second terminal of the twenty-third transistor serves as the input terminal of the fourth output unit. The third capacitor is connected between the gate and the first terminal of the twenty-third transistor.

[0014] In a second aspect, the present invention provides a display panel including the gate driving circuit described in any one of the first aspects.

[0015] The scanning drive circuit provided in this embodiment of the invention includes multiple shift registers, each of which includes a drive control module, a stage output module, a transmission control module, and a gate output module. By adjusting the on / off state of the transmission control module through a frequency control signal, the high / low level state of a third control signal can be controlled. The high / low level state of the third control signal can control the conduction state of the transistors in the gate output module, thereby causing the gate output module to output a gate drive signal, thus controlling the operating mode of the shift registers. By controlling the potential transition process of the frequency control signal, different combinations of operating modes for each shift register can be controlled, so that the frequencies of the gate drive signals output by at least two shift registers are different, thereby achieving segmented frequency display on the display panel. Connecting the transmission control module and the gate output module to the same end of the drive control module (i.e., the second output end of the drive control module) improves the stability of the shift register operation. Compared to connecting the transmission control module and the gate output module to different ends of the drive control module, for example, connecting the transmission control module to the first output end of the drive control module and the gate output module to the second output end of the drive control module, the influence of the transmission control module on the output pulse signal of the stage output module can be reduced. In summary, compared with the prior art, the embodiments of the present invention enable the display panel to support the function of segmented frequency display.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of a three-screen display panel provided in an embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of the structure of a shift register provided in an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0022] Figure 5 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0023] Figure 6 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0024] Figure 7 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0025] Figure 8 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0026] Figure 9 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0027] Figure 10 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0028] Figure 11 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0029] Figure 12 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0030] Figure 13 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0031] Figure 14 This is a schematic diagram of the driving timing of a shift register in the first working mode according to an embodiment of the present invention;

[0032] Figure 15 This is a schematic diagram of the driving timing of a shift register in the second working mode according to an embodiment of the present invention;

[0033] Figure 16 This is a simulation timing diagram of a gate driving circuit provided in an embodiment of the present invention;

[0034] Figure 17 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0035] Figure 18 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0036] Figure 19 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0038] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. Embodiments of this invention provide a gate driving circuit to enable a display panel to support the function of displaying at different frequencies in partitions within a screen. Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention. Figure 1 As shown, the gate drive circuit includes a multi-stage shift register 10, such as multiple shift registers 10 cascaded together. Each stage of the shift register 10 may have the same or similar structure. Figure 1 The first two stages of shift register 10 are shown as an example. Each shift register 10 (at least one shift register 10) may include: a drive control module 110, a stage output module 120, a transmission control module 130, and a gate output module 140.

[0039] Specifically, the first output terminal N1 of the drive control module 110 is connected to the first control terminal CTR1 of the stage transmission output module 120, the second output terminal N2 of the drive control module 110 is connected to the second control terminal CTR2 of the stage transmission output module 120, the control terminal N3 of the transmission control module 130 and the first control terminal Ctr1 of the gate output module 140, and the output terminal of the transmission control module 130 is connected to the second control terminal Ctr2 of the gate output module 140.

[0040] The drive control module 110 is used to output a first control signal to the second output terminal N2 of the drive control module 110 based on at least the first clock signal and the input signal, and to output a second control signal to the first output terminal N1 of the drive control module 110; the stage transmission output module 120 is used to output a stage transmission output signal to the output terminal COUT of the stage transmission output module 120 based on at least the first control signal and the second control signal; the transmission control module 130 is used to output a third control signal to the output terminal of the transmission control module 130 based on at least the frequency control signal and the first control signal; the gate output module 140 (i.e., the gate drive signal output module) is used to output a gate drive signal based on at least the first control signal and the third control signal.

[0041] The transmission control module 130 can be used to output a third control signal to the output terminal of the transmission control module 130 based on at least the frequency control signal and the first control signal, so as to control the frequency of the pulse signal of the gate drive signal output by the gate output module 140, and thus control the refresh frequency.

[0042] In some embodiments, the drive control module 110 is configured to output a first control signal to the second output terminal N2 of the drive control module 110 based on a first clock signal, a second clock signal, an input signal, a first power signal, and a second power signal, and to output a second control signal to the first output terminal N1 of the drive control module 110; the stage transmission output module 120 is configured to output a stage transmission output signal to the output terminal COUT of the stage transmission output module 120 based on the first control signal, the second control signal, the first power signal, and the second power signal; the transmission control module 130 is configured to output a third control signal to the output terminal of the transmission control module 130 based on a frequency control signal, the first control signal, the first power signal, and the second power signal; and the gate output module 140 (i.e., the gate drive signal output module) is configured to output a gate drive signal based on the first control signal, the third control signal, the first power signal, and the second power signal.

[0043] In some embodiments, the drive control module 110 is configured to output a first control signal to its second output terminal N2 and a second control signal to its first output terminal N1 based on a first clock signal, an input signal, a first power signal, and a second power signal; the stage transmission output module 120 is configured to output a stage transmission output signal to its output terminal COUT based on a first control signal, a second control signal, a second clock signal, and a first power signal; the transmission control module 130 is configured to output a third control signal to its output terminal based on a frequency control signal, a first control signal, a first power signal, and a second power signal; and the gate output module 140 (i.e., the gate drive signal output module) is configured to output a gate drive signal based on a first control signal, a third control signal, a first power signal, and a second clock signal. It should be noted that this embodiment and the following embodiments are described using this case as an example.

[0044] Optionally, the output terminal COUT of the stage output module 120 of the previous stage shift register is connected to the input terminal CIN of the drive control module 120 of the next stage shift register.

[0045] Specifically, such as Figure 1 As shown, the input terminal CIN of the drive control module 110 is used to provide the input signal, the first clock signal input terminal CLK1 is used to provide the first clock signal, and the second clock signal input terminal CLK2 is used to provide the second clock signal. The first power signal input terminal PVGH is used to provide the first power signal, the second power signal input terminal PVGL is used to provide the second power signal, the frequency control signal input terminal SW0 is used to provide the frequency control signal, and the output terminal VOUT of the shift register 10 is used to output the gate drive signal. The gate drive signal is transmitted to the pixel unit of the display area of ​​the display panel through the signal line to drive the pixel unit display. For example, the gate drive signal can be a scan signal or a light emission control signal. When the display panel includes multiple rows of pixel units, multiple shift registers 10 are cascaded to provide gate drive signals to at least one row of pixel units respectively. Among them, the input signal of the first-stage shift register can be the input signal provided by the driver chip to the input terminal CIN of the drive control module 110 of the first-stage shift register, and the input signals of other-stage shift registers are the stage output signals output by the previous-stage shift register.

[0046] For example, the first-stage shift register 101 receives the first-stage input signal and outputs a first-stage output signal based on the first-stage input signal, the first clock signal, the second clock signal, the first power supply signal, and the second power supply signal. It also outputs a first-stage gate drive signal in conjunction with the frequency control signal. The first-stage output signal serves as the second-stage input signal and is transmitted to the second-stage shift register 102. The second-stage shift register 102 outputs a second-stage output signal (serving as the third-stage input signal) based on the second-stage input signal, the first clock signal, the second clock signal, the first power supply signal, and the second power supply signal. It then outputs a second-stage gate drive signal in conjunction with the frequency control signal, and so on.

[0047] In this configuration, one of the first power supply signal and the second power supply signal is at a high level, and the other is at a low level. The first and second power supply signals can be DC voltage signals with different potentials, for example, the first power supply signal is at a high level and the second power supply signal is at a low level. Both the first and second clock signals are clock signals that alternate between high and low levels. Optionally, the first and second clock signals can be signals with opposite high and low level timings, and within the same period, any voltage transition edge of the second clock signal is later than the corresponding voltage transition edge of the first clock signal. The effective pulse signals of the first and second clock signals do not need to overlap. Figure 13 and Figure 14 An example is drawn showing the case where the effective pulse signals of the first and second clock signals are low-level pulses.

[0048] For any shift register 10, the frequency control signal, by controlling the state of the third control signal output by the transmission control module 130, can control the output state of the gate output module 140, thereby controlling the operating mode of the shift register 10. Specifically, the transmission control module 130 can control the shift register 10 to operate in the following two modes:

[0049] For example, when the second control signal of the first control terminal CTR1 of the stage transmission output module 120 is low, the stage transmission output module 120 outputs a second clock signal; when the first control signal of the second control terminal CTR2 is low, the stage transmission output module 120 outputs a first power supply signal. When the frequency control signal is low or disabled, the transmission control module 130 outputs a first power supply signal; when the frequency control signal is high or enabled, the third control signal output by the transmission control module 130 has the opposite potential to the first control signal, and the third control signal output by the transmission control module 130 has the same potential as the second control signal. When the first control terminal Ctr1 of the gate output module 140 is low, the gate output module 140 outputs a first power supply signal; when the second control terminal Ctr2 is low, the gate output module 140 outputs a second clock signal. The example is a pixel unit transistor being turned on at a low level. Optionally, when the frequency control signal is enabled, if one of the third control signal and the first control signal transitions to a high level, the other transitions to a low level. Optionally, when the frequency control signal is at the enable level, the third control signal and the second control signal simultaneously transition to a high level and then simultaneously transition to a low level. Optionally, when the frequency control signal is at the disable level, the third control signal maintains a cutoff potential.

[0050] For example, for the same shift register, when the frequency control signal is at the enable level, and the output terminal of the stage output module 120 outputs a pulse signal, the transmission control module 130 can control the output terminal of the gate output module 140 to synchronously output a pulse signal; when the frequency control signal is at the disable level, and the output terminal of the stage output module 120 outputs a pulse signal, the transmission control module 130 can control the output terminal of the gate output module 140 to maintain an ineffective potential or a cutoff potential for the pulse signal, and will not synchronously output a pulse signal. Thus, by adjusting the potential of the frequency control signal, the frequency of the pulse signal of the gate drive signal output by the gate output module 140 can be controlled, thereby controlling the refresh frequency.

[0051] Connecting the transmission control module 130 and the gate output module 140 to the same end of the drive control module 110 (i.e., the second output end of the drive control module 110) improves the stability of the shift register operation. Compared to connecting the transmission control module 130 and the gate output module 140 to different ends of the drive control module 110, for example, connecting the transmission control module 130 to the first output end of the drive control module 110 and the gate output module 140 to the second output end of the drive control module 110, this embodiment reduces the influence of the transmission control module 130 on the output pulse signal of the stage transmission output module 120.

[0052] For example, in the first operating mode, the frequency control signal is a high-level signal or an enable-level signal. The frequency control signal can control the third control signal output by the transmission control module 130 to include a low-level state, which is equivalent to including a low-level pulse signal. The effective potential of the pulse signal is low, and the ineffective potential of the pulse signal is high. The specific process is as follows:

[0053] In the first stage, the first clock signal is low, while the second clock signal, frequency control signal, and input signal are high. The frequency control signal can be an enable level. The drive control module 110 outputs an input signal at its first output terminal N1 and a second power signal at its second output terminal N2 based on the first clock signal, input signal, first power signal, and second power signal. This causes the potential of the second control signal at the first control terminal CTR1 of the stage output module 120 to be high, and the potential of the first control signal at the second control terminal CTR2 to be low. Simultaneously, this causes the first control terminal Ctr1 of the gate output module 140 to be low. The stage output module 120 outputs a first power signal as the stage output signal based on the first control signal at the second control terminal CTR2. The transmission control module 130 outputs a first power signal based on the frequency control signal, causing the potential of the second control terminal Ctr2 of the gate output module 140 to be high. The gate output module 140 outputs a first power signal based on the potential of its first control terminal Ctr1. In other words, the gate drive signal output by the shift register's output terminal VOUT is high at this time.

[0054] In the second stage, the second clock signal is low, while the first clock signal, frequency control signal, and input signal are high. The frequency control signal can be an enable level. The drive control module 110 maintains the high level of the previous stage at its first output terminal N1 according to the first clock signal, input signal, first power signal, and second power signal, and outputs a second power signal at its second output terminal N2, causing the potential of the first control terminal CTR1 of the stage output module 120 to be high and the potential of the second control terminal CTR2 to be low, simultaneously causing the first control terminal Ctr1 of the gate output module 140 to be low. The stage output module 120 outputs a first power signal as the stage output signal according to the first control signal of the second control terminal CTR2. The transmission control module 130 outputs a first power signal according to the frequency control signal, causing the potential of the second control terminal Ctr2 of the gate output module 140 to be high. The gate output module 140 outputs a first power signal according to the potential of its first control terminal Ctr1. That is, at this time, the gate drive signal output by the shift register output terminal VOUT is high.

[0055] In the third stage, the first clock signal and the input signal are at a low level, while the second clock signal and the frequency control signal are at a high level. The frequency control signal can be an enable level. The drive control module 110 outputs an input signal at its first output terminal N1 and a first power signal at its second output terminal N2 based on the first clock signal, the input signal, the first power signal, and the second power signal. This causes the potential of the first control terminal CTR1 of the stage output module 120 to be low and the potential of the second control terminal CTR2 to be high, while simultaneously causing the first control terminal Ctr1 of the gate output module 140 to be high. The stage output module 120 outputs a second clock signal as the stage output signal based on the second control signal of the first control terminal CTR1. That is, at this time, the stage output signal output by the output terminal COUT of the stage output module is high. The transmission control module 130 outputs a second power signal based on the frequency control signal, causing the potential of the second control terminal Ctr2 of the gate output module 140 to be low. The gate output module 140 outputs a second clock signal based on the potential of its second control terminal Ctr2. In other words, the gate drive signal output by the shift register's output terminal VOUT is high at this time.

[0056] In the fourth stage, the second clock signal is low, while the first clock signal, frequency control signal, and input signal are high. The frequency control signal can be an enable level. The drive control module 110 outputs a low-level state of the second control signal at its first output terminal N1 and outputs the first power signal as the first control signal at its second output terminal N2, based on the first clock signal, input signal, first power signal, and second power signal. This causes the potential of the first control terminal CTR1 of the stage output module 120 to be low and the potential of the second control terminal CTR2 to be high, while simultaneously causing the first control terminal Ctr1 of the gate output module 140 to be high. The stage output module 120 outputs a second clock signal as the stage output signal based on the second control signal of the first control terminal CTR1. That is, at this time, the stage output signal output by the output terminal COUT of the stage output module is low, thus enabling multiple shift registers to operate normally. The transmission control module 130 outputs a second power signal based on the frequency control signal, causing the potential of the second control terminal Ctr2 of the gate output module 140 to be low. The gate output module 140 outputs a second clock signal based on the potential of its second control terminal Ctr2. That is, the gate drive signal output from the shift register's output terminal VOUT is low at this time. This enables the shifted output of the input signal, meaning that within the current frame, the pixel unit connected to the shift register displays normally according to the gate drive signal, ensuring that the display refresh rate of the display panel is the same as the frequency of the input signal.

[0057] The process of the fifth stage is the same as that of the first stage, and will not be repeated here.

[0058] In the sixth stage, the second clock signal is low, the frequency control signal is off or disabled, and the first clock signal, the second frequency control signal, and the input signal are high. The drive control module 110 maintains the high level of the previous stage at its first output terminal N1 according to the first clock signal, the input signal, the first power signal, and the second power signal, and outputs the second power signal at its second output terminal N2 as the first control signal, causing the potential of the first control terminal CTR1 of the stage output module 120 to be high and the potential of the second control terminal CTR2 to be low, while simultaneously causing the first control terminal Ctr1 of the gate output module 140 to be low. The stage output module 120 outputs the first power signal as the stage output signal according to the first control signal of the second control terminal CTR2. That is, at this time, the stage output signal output by the output terminal COUT of the stage output module is high. The transmission control module 130 is turned off according to the frequency control signal, causing the potential of the second control terminal Ctr2 of the gate output module 140 to remain at the high level of the previous stage. The gate output module 140 outputs a first power supply signal based on the potential of its first control terminal Ctr1. That is, at this time, the gate drive signal output by the shift register's output terminal VOUT is at a high level. The aforementioned turn-off level is the level that controls the turn-off of each module. In some embodiments, the turn-off level is, for example, a high level, with each module turning off when at a high level and turning on when at a low level; in other embodiments, the turn-off level is, for example, a low level, with each module turning off when at a low level and turning on when at a high level.

[0059] For example, in the second operating mode, the frequency control signal is a low-level signal or an enabled level, and the third control signal output by the frequency control signal control stage transmission control module 130 only includes a high-level state (the output is maintained at an ineffective potential of the pulse signal). The specific process is as follows:

[0060] In the first stage, the first clock signal, input signal, and frequency control signal are at low levels, while the second clock signal is at a high level. The frequency control signal can be at a disabled level. The drive control module 110 outputs an input signal at its first output terminal N1 and a first power signal at its second output terminal N2 based on the first clock signal, input signal, first power signal, and second power signal, causing the potential of the first control terminal CTR1 of the stage output module 120 to be low and the potential of the second control terminal CTR2 to be high, while simultaneously causing the potential of the first control terminal Ctr1 of the gate output module 140 to be high. The stage output module 120 outputs a second clock signal as the stage output signal based on the second control signal of the first control terminal CTR1. At this time, the stage output signal output by the output terminal COUT of the stage output module 120 is at a high level. The transmission control module 130 outputs a first power signal based on the frequency control signal, causing the potential of the second control terminal Ctr2 of the gate output module 140 to be high. Because a capacitor is connected between the output terminal VOUT of the gate output module 140 and its second control terminal Ctr2, and the capacitor has a bootstrap function, the potential of the output terminal VOUT of the gate output module 140 is also high at this time. That is to say, the gate drive signal output by the output terminal VOUT of the shift register is high at this time.

[0061] In the second stage, the second clock signal and frequency control signal are at a low level, while the first clock signal and input signal are at a high level. The frequency control signal can be at a disabled level. The drive control module 110 outputs a low-level state of the second control signal at its first output terminal N1 and a first power signal at its second output terminal N2, based on the first clock signal, input signal, first power signal, and second power signal. This causes the potential of the first control terminal CTR1 of the stage output module 120 to be low and the potential of the second control terminal CTR2 to be high, while simultaneously causing the first control terminal Ctr1 of the gate output module 140 to be high. The stage output module 120 outputs a second clock signal as the stage output signal based on the second control signal of the first control terminal CTR1. That is, at this time, the stage output signal output by the output terminal COUT of the stage output module 120 is low, thus enabling multiple shift registers to operate normally. The transmission control module 130 outputs a first power signal based on the frequency control signal, causing the potential of the second control terminal Ctr2 of the gate output module 140 to be high. Because a capacitor is connected between the output terminal VOUT of the gate output module 140 and its second control terminal Ctr2, and the capacitor has a bootstrap function, the potential of the output terminal VOUT of the gate output module 140 is also high at this time. That is, the gate drive signal output by the output terminal VOUT of the shift register is high at this time. The input signal cannot be shifted and output; that is, within the current frame, the pixel unit connected to the shift register cannot be displayed normally according to the gate drive signal. This causes the display refresh rate of the display panel to be lower than the frequency of the input signal, thus controlling the display refresh rate of the pixel unit connected to the current shift register.

[0062] In the third stage, the first clock signal and frequency control signal are at low level, while the second clock signal and input signal are at high level. The frequency control signal can be at a disabled level. The drive control module 110 outputs a high-level state of the input signal at its first output terminal N1 and a second power signal at its second output terminal N2, based on the first clock signal, input signal, first power signal, and second power signal. This causes the potential of the first control terminal CTR1 of the stage output module 120 to be high and the potential of the second control terminal CTR2 to be low, while simultaneously causing the first control terminal Ctr1 of the gate output module 140 to be low. The stage output module 120 outputs a first power signal as the stage output signal based on the first control signal of the second control terminal CTR2. That is, at this time, the stage output signal output by the output terminal COUT of the stage output module 120 is high. The transmission control module 130 outputs a first power signal based on the frequency control signal, causing the potential of the second control terminal Ctr2 of the gate output module 140 to be high. The gate output module 140 outputs a first power signal based on the potential of its first control terminal Ctr1. In other words, the gate drive signal output by the shift register's output terminal VOUT is high at this time.

[0063] In the fourth stage, the second clock signal and frequency control signal are low, while the first clock signal and input signal are high. The frequency control signal can be disabled. The drive control module 110 outputs a high-level state of the second control signal at its first output terminal N1 and a second power signal at its second output terminal N2, based on the first clock signal, input signal, first power signal, and second power signal. This causes the potential of the first control terminal CTR1 of the stage output module 120 to be high and the potential of the second control terminal CTR2 to be low, while simultaneously causing the first control terminal Ctr1 of the gate output module 140 to be low. The stage output module 120 outputs a first power signal as the stage output signal based on the first control signal of the second control terminal CTR2. That is, at this time, the stage output signal output by the output terminal COUT of the stage output module 120 is high. The transmission control module 130 outputs a first power signal based on the frequency control signal, causing the potential of the second control terminal Ctr2 of the gate output module 140 to be high. The gate output module 140 outputs a first power signal based on the potential of its first control terminal Ctr1. In other words, the gate drive signal output by the shift register's output terminal VOUT is high at this time.

[0064] In some embodiments, the gate drive signals at each level are transmitted through each row of scan lines to the functional modules related to the data writing process in each row of pixel circuits. When a certain level of shift register 10 operates in a first operating mode, since the gate drive signal contains a conduction level, it can control the pixel circuit of the corresponding row to perform data refresh, making the current frame of that row of pixel circuits a refresh frame; while when a certain level of shift register 10 operates in a second operating mode, since the gate drive signal does not contain a conduction level, the pixel circuit of the corresponding row cannot perform data refresh, making the current frame of that row of pixel circuits a hold frame. Therefore, the frequency of the gate drive signal determines the data refresh frequency of the pixel circuit. Based on this, by controlling the potential transition of the frequency control signal, the operating mode of each shift register 10 can be controlled in each frame of display, thereby realizing the display of different frequencies in the column direction of the display device.

[0065] by Figure 2Taking a three-screen display as an example, assuming the display panel is divided into a first display area A1, a second display area A2, and a third display area A3 from top to bottom, and the refresh frequencies of the three display areas are, for example, the first refresh frequency f1, the second refresh frequency f2, and the third refresh frequency f3, where f1 > f2. Then, the transition from the first display area A1 to the second display area A2 is equivalent to a frequency division display where the display frequency decreases from high to low, and the transition from the second display area A2 to the third display area A3 is equivalent to a frequency division display where the display frequency increases from low to high. The size of each display area is determined by the number of shift registers 10 that provide the corresponding frequency gate drive signals. Taking two levels of shift registers 10 for each display area as an example, the frequency of the gate signal output by the shift registers 10 corresponding to the first display area A1 and the third display area A3 is the first refresh frequency f1. For example, the first, second, fifth, and sixth level shift registers 10 are set to operate in the first working mode in each display frame. The frequency of the gate drive signal output by the shift register 10 corresponding to the second display area A2 is the second refresh frequency f2. For example, the third and fourth level shift registers 10 are set to operate in the first working mode in some display frames and in the second working mode in others. That is, by controlling the frequency control signal to keep the third control signal output by the transmission control module 130 at the off level in some display frames, the shift register 10 can operate in the second working mode in some display frames. By controlling the frequency control signal to perform potential transitions in some display frames, the third control signal output by the transmission control module 130 can include a conduction level in some display frames, allowing the shift register 10 to operate in the first working mode in others. This ensures that the frequencies of the gate drive signals output by at least two shift registers 10 are different, thereby achieving segmented frequency display of the display panel. Furthermore, by adjusting the potential transition time of the frequency control signal in one frame of display, the boundary position of the shift register 10's working mode switching can be adjusted, thereby achieving adjustment of the display panel's display segment position. The first-level shift register 10 is connected to at least one row of pixel circuits. The number of shift registers 10 in the first working mode in a frame determines the number of pixel circuit rows to be refreshed in that frame.

[0066] The gate driving circuit provided in this embodiment of the invention includes multiple shift registers, each of which includes a drive control module, a stage output module, a transmission control module, and a gate output module. The on / off state of the transmission control module is adjusted by a frequency control signal, controlling the high / low level state of a third control signal. The high / low level state of the third control signal controls the conduction state of the transistors in the gate output module, thereby causing the gate output module to output a gate drive signal, thus controlling the operating mode of the shift registers. By controlling the potential transition process of the frequency control signal, different combinations of operating modes for each shift register can be controlled, so that the frequencies of the gate drive signals output by at least two shift registers are different, thereby achieving segmented frequency display on the display panel. Connecting the transmission control module and the gate output module to the same end of the drive control module (i.e., the second output end of the drive control module) improves the stability of the shift register operation. Compared to connecting the transmission control module and the gate output module to different ends of the drive control module, for example, connecting the transmission control module to the first output end of the drive control module and the gate output module to the second output end of the drive control module, the influence of the transmission control module on the output pulse signal of the stage output module can be reduced. In summary, compared with the prior art, the embodiments of the present invention can enable the display panel to support the function of segmented frequency display.

[0067] The structure of shift register 10 will be described first by example, and then the specific driving process of driving the display panel for multi-frequency partitioning based on the gate driving circuit will be described by example.

[0068] Figure 3 This is a schematic diagram of a shift register provided in an embodiment of the present invention. See also: Figure 3 Optionally, the transmission control module 130 includes a first inverter 131 and an output control unit 132.

[0069] The input terminal of the first inverter 131 serves as the control terminal N3 of the transmission control module 130. The output terminal of the first inverter 131 is connected to the input terminal of the output control unit 132. The control terminal of the output control unit 132 is used to input the frequency control signal. The output terminal of the output control unit 132 serves as the output terminal of the transmission control module 130. The first inverter 131 is used to invert the first control signal and output a first inverted control signal. The output control unit 131 is used to generate a third control signal based at least on the first inverted control signal and the frequency control signal.

[0070] Optionally, the second control signal and the first control signal have opposite potentials.

[0071] Optionally, the first terminal of the first inverter 131 is used to input a first power supply signal, and the second terminal of the first inverter 131 is used to input a second power supply signal.

[0072] In some embodiments, the output control unit 131 is configured to generate a third control signal based on a first inverting control signal, a first power supply signal, and a frequency control signal.

[0073] Figure 4 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. See also... Figure 4 Optionally, the frequency control signal includes a first frequency control signal and a second frequency control signal; the output control unit includes a first transistor M1 and a second transistor M2.

[0074] The gate of the first transistor M1 serves as the first control terminal of the output control unit 132, used to input a first frequency control signal. The first terminal of the first transistor M1 serves as the input terminal of the output control unit 132. The second terminal of the first transistor M1 is connected to the first terminal of the second transistor M2 and serves as the output terminal of the output control unit 132. The gate of the second transistor M2 serves as the second control terminal of the output control unit 132, used to input a second frequency control signal. The second terminal of the second transistor M2 is used to input a first power supply signal. For example, the output control unit 132 in this embodiment can be composed of two transistors, making the transmission control module 130 simple in structure and easy to implement.

[0075] Specifically, the first frequency control signal input terminal C1 is used to provide the first frequency control signal, and the second frequency control signal input terminal C2 is used to provide the second frequency control signal. Figure 4 The example illustrates a first transistor M1 being an N-type transistor and a second transistor M3 being a P-type transistor. The first transistor M1 is turned on or off according to a first frequency control signal. When the first frequency control signal is at its on level, the first transistor M1 is turned on and outputs an inverted first control signal to the second control terminal Ctr2 of the gate output module (equivalent to the first node Q1). Therefore, the frequency of the inverted first control signal output by the first transistor M1 can be controlled by controlling the frequency of the on level of the first frequency control signal.

[0076] The second transistor M2 is turned on or off according to the second frequency control signal. When the second frequency control signal is at the on level, the second transistor M2 is turned on and outputs the first power supply signal to the second control terminal Ctr2 (equivalent to the first node Q1) of the gate output module. Thus, the frequency of the first power supply signal output by the second transistor M2 can be controlled by the frequency of the on level of the second frequency control signal.

[0077] The aforementioned conduction level is the level that controls the conduction of each transistor. In some embodiments, when at least some of the transistors in the module include N-channel transistors, the conduction level is, for example, a high level, and the N-channel transistor is turned on when the level is high and turned off when the level is low. In other embodiments, when at least some of the transistors in the module include P-channel transistors, the conduction level is, for example, a low level, and the P-channel transistor is turned on when the level is low and turned off when the level is high.

[0078] Figure 5 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. See also... Figure 5 Optionally, the frequency control signal further includes a first frequency inverse control signal, and the output control unit 132 further includes a third transistor M3, the gate of which serves as the third control terminal of the output control unit 132 for inputting the first frequency inverse control signal.

[0079] The first terminal of the third transistor M3 is connected to the first terminal of the first transistor M1, and the second terminal of the third transistor M3 is connected to the second terminal of the first transistor M1.

[0080] The third transistor M3 has a different channel type than the first transistor M1. For example, when the first transistor M1 is a P-channel transistor, the third transistor M3 is an N-channel transistor; when the first transistor M1 is an N-channel transistor, the third transistor M3 is a P-channel transistor. Figure 5 The diagram illustrates the case where the first transistor M1 is an N-channel transistor and the third transistor M3 is a P-channel transistor.

[0081] Specifically, the first frequency inverse control signal input terminal C1B is used to provide the first frequency inverse control signal. Since the first frequency control signal and the first frequency inverse control signal are signals with opposite high and low level timings, and the third transistor M3 and the first transistor M1 have different channel types, the first transistor M1 and the third transistor M3 are simultaneously turned on and off. That is, the addition of the third transistor M3 does not affect the on and off states of the first transistor M1. This embodiment, by connecting the first transistor M1 and the third transistor M3 in parallel to form a CMOS transmission gate, fully utilizes the complementary electrical characteristics of NMOS and PMOS transistors. This results in a control switch whose on-state resistance remains low regardless of whether a high or low level is transmitted. This control switch possesses the structural characteristics of a complementary transistor transmission gate and the advantage of complete electrical signal transmission, which can increase the stability of the gate drive circuit.

[0082] Figure 6 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. See also... Figure 6 ,exist Figure 4 Optionally, based on the embodiment, the output control unit 132 further includes a second inverter 133 and a third transistor M3. The input terminal of the second inverter 133 is electrically connected to the first control terminal of the output control unit 130 for inputting a first frequency control signal, and the output terminal of the second inverter 133 is electrically connected to the gate of the third transistor M3. The first terminal of the second inverter 133 is used to input a first power supply signal, and the second terminal of the second inverter 133 is used to input a second power supply signal.

[0083] Optionally, the second inverter 133 includes a fourth transistor M4 and a fifth transistor M5; the gate of the fourth transistor M4 is connected to the gate of the fifth transistor M5 and serves as the input terminal of the second inverter 133 for inputting a first frequency control signal; the first terminal of the fourth transistor M4 is used to input a first power supply signal; the second terminal of the fourth transistor M4 is connected to the first terminal of the fifth transistor M5 and the gate of the third transistor M3 respectively; and the second terminal of the fifth transistor M5 is used to input a second power supply signal.

[0084] The first terminal of the third transistor M3 is connected to the first terminal of the first transistor M1, and the second terminal of the third transistor M3 is connected to the second terminal of the first transistor M1; wherein the channel types of the third transistor M3 and the first transistor M1 are different.

[0085] Optionally, at least two shift registers share the same second inverter 133. This can reduce the number of second inverters 133 and lower costs. For example, all shift registers share the same second inverter 133.

[0086] Specifically, the fourth transistor M4 and the fifth transistor M5 form a CMOS inverter. Therefore, when the first frequency control signal is high, the fourth transistor M4 is off and the fifth transistor M5 is on, outputting the second power supply signal (e.g., low) to the second node Q2. When the first frequency control signal is low, the fourth transistor M4 is on and the fifth transistor M5 is off, outputting the first power supply signal (e.g., high) to the second node Q2. The third transistor M3 is turned on or off according to the potential of the second node Q2. When the potential of the second node Q2 is at the on level, the third transistor M3 is on and transmits the inverted first control signal to the first node Q1.

[0087] Figure 7 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. See also... Figure 7Based on the above embodiments, the shift register 10 may optionally include a sixth transistor M6; the gate of the sixth transistor M6 is used to input a second power supply signal (equivalent to the conduction level of the sixth transistor M6), and the output terminal of the transmission control module 130 is connected to the second control terminal Ctr2 of the gate output module 140 through the sixth transistor M6.

[0088] Specifically, Figure 7 The sixth transistor M6 is shown as a P-type transistor. The second power supply signal is low. The sixth transistor M6 is equivalent to a normally open module. When the gate drive signal output from the gate drive circuit changes from high to low, the coupling effect of the capacitor in the gate output module 140 makes the potential of the first node Q1 lower than the low-level potential, thus preventing the low-level potential from being transmitted to the output control unit 132 and avoiding damage to the devices in the output control unit 132. For example, when the output control unit 132 includes the first transistor M1, the second transistor M2, and the third transistor M3, it can prevent the second electrode potential of the first transistor M1 and the third transistor M3 from being too low, which would cause device damage due to a large difference between the gate potential and the second electrode potential of the first transistor M1 and the third transistor M3, and also prevent device damage due to a large difference between the gate potential and the first electrode potential of the second transistor M2.

[0089] Figure 8 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. See also... Figure 8 Optionally, the first inverter 131 includes a seventh transistor M7 and an eighth transistor M8.

[0090] The gate of the seventh transistor M7 is connected to the gate of the eighth transistor M8 and serves as the input terminal of the first inverter 131. The first terminal of the seventh transistor M7 serves as the first terminal of the first inverter 131, used to input a first power supply signal. The second terminal of the seventh transistor M7 is connected to the first terminal of the eighth transistor M8 and serves as the output terminal of the first inverter 131. The second terminal of the eighth transistor M8 serves as the second terminal of the first inverter 131, used to input a second power supply signal. The switching states of the seventh transistor M7 and the eighth transistor M8 can be reversed; one of the seventh transistor M7 changes from on to off, and the other changes from off to on.

[0091] Specifically, the seventh transistor M7 and the eighth transistor M8 form a CMOS inverter. Therefore, when the first control signal is high, the potential of the third node Q3 is high. The high potential of the third node Q3 controls the seventh transistor M7 to turn off and the eighth transistor M8 to turn on, outputting the second power supply signal (e.g., low level) to the fourth node Q4. When the first control signal is low, the seventh transistor M7 turns on and the eighth transistor M8 turns off, outputting the first power supply signal (e.g., high level) to the fourth node Q4.

[0092] The structure of the drive control module 110 will be further described below, but this is not intended to limit the scope of this application. Figure 9 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. See also... Figure 9 Optionally, the drive control module 110 includes an input unit 111, a node feedback unit 112, a second inverting unit 114, and a third inverting unit 115.

[0093] Input unit 111 generates a second control signal based on a first clock signal and an input signal. The input terminal of the second inverting unit 114 is connected to the output terminal of input unit 111. The second inverting unit 114 inverts the second control signal to generate a first control signal. The input terminal of the third inverting unit 115 is connected to the output terminal of the second inverting unit 114. The third inverting unit 115 inverts the first control signal to output a second inverted control signal. Node feedback unit 112 is connected between the output terminal of the third inverting unit 115 and the input terminal of the second inverting unit 114. Node feedback unit 112 controls the potential of the second control signal based on the first clock signal and / or the first inverted clock signal, and the second inverted control signal. Optionally, the switching states of input unit 111 and node feedback unit 112 are opposite; one of input unit 111 changes from on to off, and the other changes from off to on.

[0094] Optionally, continue to refer to Figure 9The drive control module 110 further includes a first inverting unit 113. The output of the first inverting unit 113 is connected to the input unit 111 and / or the node feedback unit 112. The first inverting unit 113 is used to invert the first clock signal and output a first inverted clock signal. The input unit 111 is used to generate a second control signal based on the first clock signal and / or the first inverted clock signal, as well as the input signal. Optionally, at least two shift registers share the same first inverting unit 113. For example, odd-level shift registers share the same first inverting unit 113. For example, even-level shift registers share the same first inverting unit 113. The first clock signal and the first inverted clock signal have opposite potentials; for example, when one of the first clock signal and the first inverted clock signal transitions to a high level, the other transitions to a low level.

[0095] For example, when the first clock signal is high, the first inverting unit 113 transmits the low-level signal corresponding to the second power supply signal to the fifth node Q5, causing the potential of the fifth node Q5 to decrease. When the potential of the fifth node Q5 is low, the input unit 111 is turned off, the node feedback unit 112 is turned on, and the level signal corresponding to the sixth node Q6 is transmitted to the seventh node Q7, and the level signal of the seventh node Q7 is output as the second control signal. When the level signal of the seventh node Q7 is high, the second inverting unit 114 transmits the second power supply signal to the second output terminal N2 as the first control signal. When the first control signal of the second output terminal N2 is low, the third inverting unit 115 outputs the first power supply signal to the sixth node Q6. In this way, the potential of the sixth node Q6 is maintained.

[0096] When the first clock signal is low, the first inverting unit 113 transmits the high-level signal corresponding to the first power supply signal to the fifth node Q5, causing the potential of the fifth node Q5 to rise. When the potential of the fifth node Q5 is high, the node feedback unit 112 is turned off, the input unit 111 is turned on, the input signal is transmitted to the seventh node Q7, and the level signal of the seventh node Q7 is output as the second control signal. When the level signal of the seventh node Q7 is low, the second inverting unit 114 transmits the first power supply signal to the second output terminal N2 as the first control signal. When the first control signal of the second output terminal N2 is high, the third inverting unit 115 outputs the second power supply signal to the sixth node Q6.

[0097] Figure 10 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. See also... Figure 10Optionally, the input unit 111 includes a ninth transistor M9. The gate of the ninth transistor M9 is used to input a first inverted clock signal, the first terminal of the ninth transistor M9 is used to receive the input signal and serve as the input terminal of the input unit 111, and the second terminal of the ninth transistor M9 serves as the output terminal of the input unit 111.

[0098] And / or, the input unit 111 includes a tenth transistor M10, the gate of the tenth transistor M10 is used to input a first clock signal, the first terminal of the tenth transistor M10 is used to receive the input signal and serve as the input terminal of the input unit 111, and the second terminal of the tenth transistor M10 serves as the output terminal of the input unit 111; optionally, the tenth transistor M10 has a different channel type than the ninth transistor M9.

[0099] Specifically, Figure 10 An example is given where input unit 111 includes both a ninth transistor M9 and a tenth transistor M10. The switching states of the ninth transistor M9 and the tenth transistor M10 can be the same, equivalent to being simultaneously turned on and off. It is understood that in some embodiments, input unit 11 may include only the ninth transistor M9. In other embodiments, input unit 111 may include only the tenth transistor M10. In this case, the ninth transistor M9 and the tenth transistor M10 are connected in parallel to form a CMOS transmission gate, which transmits the input signal to the seventh node Q7 when it is on.

[0100] Optionally, the node feedback unit 112 includes an eleventh transistor M11. The gate of the eleventh transistor M11 is used to input a first clock signal, the first terminal of the eleventh transistor M11 is used to receive a second inverted control signal and serves as the input terminal of the node feedback unit 112, and the second terminal of the eleventh transistor M11 serves as the output terminal of the node feedback unit 112.

[0101] And / or, the node feedback unit 112 further includes a twelfth transistor M12, the gate of which is used to input a first inverted clock signal, the first terminal of which is used to receive a second inverted control signal and serves as the input terminal of the node feedback unit 112, and the second terminal of which serves as the output terminal of the node feedback unit 112; wherein, the twelfth transistor M12 has a different channel type than the eleventh transistor M11.

[0102] Specifically, Figure 10An example is given where the node feedback unit 112 includes both an eleventh transistor M11 and a twelfth transistor M12. The switching states of the eleventh transistor M11 and the twelfth transistor M12 may be the same. It is understood that in some embodiments, the node feedback unit 112 may include only the eleventh transistor M11. In other embodiments, the node feedback unit 112 may include only the twelfth transistor M12. The eleventh transistor M11 and the twelfth transistor M12 are connected in parallel to form a CMOS transmission gate, which, when turned on, transmits the second inverted signal to the first output terminal N1.

[0103] Optionally, the first inverting unit 113 includes a thirteenth transistor M13 and a fourteenth transistor M14. The gates of the thirteenth transistor M13 and the fourteenth transistor M14 are connected and serve as the input terminal of the first inverting unit for inputting a first clock signal. The first terminal of the thirteenth transistor M13 is used to input a first power supply signal. The second terminal of the thirteenth transistor M13 is connected to the first terminal of the fourteenth transistor M14 and serves as the output terminal of the first inverting unit. The second terminal of the fourteenth transistor M14 is used to input a second power supply signal. The switching states of the thirteenth transistor M13 and the fourteenth transistor M14 can be opposite; one of the thirteenth transistor M13 changes from on to off, and the other changes from off to on.

[0104] Specifically, the thirteenth transistor M13 and the fourteenth transistor M14 form a CMOS inverter. Therefore, when the first clock signal is high, the thirteenth transistor M13 is turned off and the fourteenth transistor M14 is turned on, outputting the second power supply signal (e.g., a low level) to the fifth node Q5. When the first clock signal is low, the thirteenth transistor M13 is turned on and the fourteenth transistor M14 is turned off, outputting the first power supply signal (e.g., a high level) to the fifth node Q5.

[0105] Optionally, the second inverting unit 114 includes a fifteenth transistor M15 and a sixteenth transistor M16. The gate of the fifteenth transistor M15 is connected to the gate of the sixteenth transistor M16 and serves as the input terminal of the second inverting unit for inputting a second control signal. The first terminal of the fifteenth transistor M15 is used to input a first power supply signal. The second terminal of the fifteenth transistor M15 is connected to the first terminal of the sixteenth transistor M16 and serves as the output terminal of the second inverting unit. The second terminal of the sixteenth transistor M16 is used to input a second power supply signal. The switching states of the fifteenth transistor M15 and the sixteenth transistor M16 can be opposite; one of the fifteenth transistor M15 changes from on to off, and the other changes from off to on.

[0106] Specifically, the fifteenth transistor M15 and the sixteenth transistor M16 form a CMOS inverter. Therefore, when the second control signal is high, the fifteenth transistor M15 is turned off and the sixteenth transistor M16 is turned on, outputting the second power supply signal (e.g., a low level) to the second output terminal N2. When the second control signal is low, the fifteenth transistor M15 is turned on and the sixteenth transistor M16 is turned off, outputting the first power supply signal (e.g., a high level) to the second output terminal N2.

[0107] Optionally, the third inverting unit 115 includes a seventeenth transistor M17 and an eighteenth transistor M18. The gate of the seventeenth transistor M17 is connected to the gate of the eighteenth transistor M18 and serves as the input terminal of the third inverting unit for inputting a first control signal. The first terminal of the seventeenth transistor M17 is used to input a first power supply signal. The second terminal of the seventeenth transistor M17 is connected to the first terminal of the eighteenth transistor M18 and serves as the output terminal of the third inverting unit. The second terminal of the eighteenth transistor M18 is used to input a second power supply signal. The switching states of the seventeenth transistor M17 and the eighteenth transistor M18 can be opposite; one of the seventeenth transistor M17 changes from on to off, and the other changes from off to on.

[0108] Specifically, the seventeenth transistor M17 and the eighteenth transistor M18 form a CMOS inverter. Therefore, when the first control signal is high, the seventeenth transistor M17 is turned off and the eighteenth transistor M18 is turned on, outputting the second power supply signal (e.g., a low level) to the sixth node Q6. When the first control signal is low, the seventeenth transistor M17 is turned on and the eighteenth transistor M18 is turned off, outputting the first power supply signal (e.g., a high level) to the sixth node Q6.

[0109] Optionally, the drive control module 110 further includes a nineteenth transistor M19. The gate of the nineteenth transistor M19 is used to input a second power supply signal (equivalent to the conduction level of the nineteenth transistor M19). The first terminal of the nineteenth transistor M19 is connected to the output terminal of the input unit 111 and the output terminal of the node feedback unit 112, respectively. The second terminal of the nineteenth transistor M19 serves as the first output terminal N1 of the drive control module 110. The nineteenth transistor M19 is equivalent to a normally open module.

[0110] By setting a nineteenth transistor M19 at the output terminal of the drive control module 110, when the stage output signal output from the stage output module 120 changes from high to low, the coupling effect of the capacitor in the stage output module 120 makes the potential of the first output terminal N1 less than the low-level potential, thus preventing the low-level potential from being transmitted to the drive control module 110 and avoiding damage to the devices within the drive control module 110. For example, when the drive control module 110 includes a nineteenth transistor M19, it can prevent the potential of the second electrode of the ninth transistor M9 and the tenth transistor M10 in the input unit 11 from being too low, which would cause the device damage due to a large difference between the gate potential and the second electrode potential of the ninth transistor M9 and the tenth transistor M10.

[0111] Figure 11 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. See also... Figure 11 Optionally, the stage output module 120 includes a first output unit 121 and a second output unit 122. The control terminal of the first output unit 121 serves as the second control terminal CTR2 of the stage output module 120. The input terminal of the first output unit 121 is used to input a first power signal. The output terminal of the first output unit 121 is connected to the output terminal of the second output unit 122 and serves as the output terminal of the stage output module 120. The control terminal of the second output unit 122 serves as the first control terminal CTR1 of the stage output module 120. The input terminal of the second output unit 122 is used to input a second clock signal. The first output unit 121 and the second output unit 122 are used to output a first power signal or a second clock signal as a stage output signal according to the first control signal and the second control signal. Optionally, the first output unit 121 is used to output a first power signal to the output terminal of the stage output module 120 according to the first control signal; the second output unit 122 is used to output a second clock signal to the output terminal of the stage output module 120 according to the second control signal. Optionally, the first output unit 121 includes a twentieth transistor M20, the gate of the twentieth transistor M20 serves as the control terminal of the first output unit 121, the first terminal of the twentieth transistor M20 serves as the input terminal of the first output unit 121, and the second terminal of the twentieth transistor M20 serves as the output terminal of the first output unit 121.

[0112] Optionally, the second output unit 122 includes a twenty-first transistor M21 and a first capacitor Ca1; the gate of the twenty-first transistor M21 serves as the control terminal of the second output unit 122, the first terminal of the twenty-first transistor M21 serves as the output terminal of the second output unit 122, and the second terminal of the twenty-first transistor M21 serves as the input terminal of the second output unit 122; the first capacitor Ca1 is connected between the gate and the first terminal of the twenty-first transistor M21.

[0113] Specifically, Figure 11An exemplary case is illustrated where the twentieth transistor M20 and the twentieth transistor M21 are P-type transistors. When the first control signal is low and the second control signal is high, the twentieth transistor M20 is turned on, and the twentieth transistor M21 is turned off. The twentieth transistor M20 transmits the first power supply signal to the output terminal of the stage output module 120 as the stage output signal. When the first control signal is high and the second control signal is low, the twentieth transistor M20 is turned off, and the twentieth transistor M21 is turned on. The twentieth transistor M21 transmits the second clock signal to the output terminal of the stage output module 120 as the stage output signal.

[0114] It should be noted that when the first control signal is high and the second control signal is low, that is, when the twentieth transistor M20 is off and the twenty-first transistor M21 is on, the stage output module 120 outputs the effective level of the stage output signal (i.e., the output pulse signal). In other words, when the stage output signal is effective, because the twentieth transistor M20 is off and the twenty-first transistor M21 is on, the load on the first output terminal N1 of the drive control module 110 is relatively large, while the load on the second output terminal N2 of the drive control module 110 is relatively small. Therefore, by connecting the transmission control module 130 and the gate output module 140 to the second output terminal N2 of the drive control module 110, the influence of the transmission control module 130 on the output pulse signal of the stage output module 120 can be reduced. Simultaneously, the gate of the twenty-first transistor M21 (i.e., the first output terminal N1 of the drive control module 110) is connected to the first capacitor Ca1, while the gate of the twentieth transistor M20 (i.e., the second output terminal N2 of the drive control module 110) does not have a capacitor. The stability of the potential at the second output terminal N2 of the drive control module 110 is higher than the stability of the potential at the first output terminal N1 of the drive control module 110.

[0115] Continue to refer to Figure 11 Optionally, the gate output module 140 includes a third output unit 140 and a fourth output unit 142.

[0116] The control terminal of the third output unit 141 serves as the first control terminal Ctr1 of the gate output module 140. The input terminal of the third output unit 141 is used to input the first power supply signal. The output terminal of the third output unit 141 is connected to the output terminal of the fourth output unit 142 and serves as the output terminal of the gate output module 140. The control terminal of the fourth output unit 141 serves as the second control terminal Ctr2 of the gate output module 140. The input terminal of the fourth output unit 142 is used to input the second clock signal. The third output unit 141 and the fourth output unit 142 are used to output the first power supply signal or the second clock signal as the gate drive signal according to the first control signal and the third control signal.

[0117] Optionally, the third output unit 141 is used to output a first power signal to the output terminal VOUT of the gate output module 140 according to the first control signal; the fourth output unit 142 is used to output a second clock signal to the output terminal VOUT of the gate output module 140 according to the third control signal.

[0118] Optionally, the third output unit 141 includes a second capacitor Ca2 and a 22nd transistor M22. The gate of the 22nd transistor M22 serves as the control terminal of the third output unit 141, the first terminal of the 22nd transistor M22 serves as the input terminal of the third output unit 141, and the second terminal of the 22nd transistor M22 serves as the output terminal of the third output unit 141. The second capacitor Ca2 is connected between the gate and the first terminal of the 22nd transistor M22.

[0119] Optionally, the fourth output unit 142 includes a third capacitor Ca3 and a twenty-third transistor M23. The gate of the twenty-third transistor M23 serves as the control terminal of the fourth output unit 142, the first terminal of the twenty-third transistor M23 serves as the output terminal of the fourth output unit 142, and the second terminal of the twenty-third transistor M23 serves as the input terminal of the fourth output unit 142. The third capacitor Ca3 is connected between the gate and the first terminal of the twenty-third transistor M23.

[0120] Specifically, Figure 11 An illustrative example is shown where the 22nd transistor M22 and the 23rd transistor M23 are P-type transistors. When the first control signal is low and the second control signal is high, the 22nd transistor M22 is turned on, and the 23rd transistor M23 is turned off. The 22nd transistor M22 transmits the first power supply signal to the output terminal of the gate output module 140 as a gate drive signal. When the first control signal is high and the second control signal is low, the 22nd transistor M22 is turned off, and the 23rd transistor M23 is turned on. The 23rd transistor M23 transmits the second clock signal to the output terminal of the gate output module 140 as a gate drive signal.

[0121] Figure 12 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. See also... Figure 12Optionally, the input terminal of the second output unit 122 is used to input the second power signal V2. The second output unit 122 is used to output the second power signal to the output terminal COUT of the stage output module 120 according to the second control signal. The second power signal can be the effective level of the pulse signal of the stage output signal, that is, when the second output unit is turned on, it can generate the pulse signal of the stage output signal, which is equivalent to shifting the pulse signal of the input signal for output. Optionally, the input terminal of the fourth output unit 142 is used to input the second power signal. The fourth output unit 142 is used to output the second power signal to the output terminal VOUT of the gate output module 140 according to the third control signal. The second power signal can be the effective level of the pulse signal of the gate drive signal, that is, when the fourth output unit 142 is turned on, it can generate the pulse signal of the gate drive signal, which is equivalent to shifting the pulse signal of the input signal for output. Optionally, the second power signal V2 can be a high level VGH, which can be provided through the second power signal line; the first power signal V1 can be a low level VGL, which can be provided through the first power signal line.

[0122] Figure 13 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. See also... Figure 13 Optionally, the shift register 10 includes: a drive control module 110, a stage output module 120, a transmission control module 130, and a gate output module 140.

[0123] The transmission control module 130 includes a first inverter 131 and an output control unit 132; the frequency control signals include a first frequency control signal, a second frequency control signal, and a first frequency inverse control signal; the output control unit includes a first transistor M1, a second transistor M2, and a third transistor M3. The first inverter 131 includes a seventh transistor M7 and an eighth transistor M8. Optionally, the shift register 10 also includes a sixth transistor M6.

[0124] The drive control module 110 includes an input unit 111, a node feedback unit 112, a first inverting unit 113, a second inverting unit 114, and a third inverting unit 115. The input unit 111 includes a ninth transistor M9 and a tenth transistor M10; the node feedback unit 112 includes an eleventh transistor M11 and a twelfth transistor M12; the first inverting unit 113 includes a thirteenth transistor M13 and a fourteenth transistor M14; the second inverting unit 114 includes a fifteenth transistor M15 and a sixteenth transistor M16; the third inverting unit 115 includes a seventeenth transistor M17 and an eighteenth transistor M18; optionally, the drive control module 110 also includes a nineteenth transistor M19.

[0125] The stage output module 120 includes a first output unit 121 and a second output unit 122; the first output unit 121 includes a twentieth transistor M20; the second output unit 122 includes a twenty-first transistor M21 and a first capacitor Ca1. The input terminal of the second output unit 122 is used to input a second clock signal.

[0126] The gate output module 140 includes a third output unit 141 and a fourth output unit 142. The third output unit 141 includes a second capacitor Ca2 and a twenty-second transistor M22, and the fourth output unit 142 includes a third capacitor Ca3 and a twenty-third transistor M23. The input terminal of the fourth output unit 142 is used to input a second clock signal.

[0127] Figure 14 This is a schematic diagram of the driving timing of a shift register in the first operating mode according to an embodiment of the present invention. (Combined with...) Figure 13 and Figure 14 Taking an example where the first power supply signal is high and the second power supply signal is low, the following explanation is provided. Here, cin represents the timing of the input signal provided by the input terminal CIN of the drive control module 110; clk1 represents the timing of the first clock signal provided by the first clock signal input terminal CLK1; clk2 represents the timing of the second clock signal provided by the second clock signal input terminal CLK2; c1 represents the timing of the first frequency control signal provided by the first frequency control signal input terminal C1; c1b represents the timing of the first frequency inverse control signal provided by the first frequency inverse control signal input terminal C1B; c2 represents the timing of the first frequency control signal provided by the first frequency control signal input terminal C2; and vout represents the timing of the gate drive signal output by the output terminal VOUT of the gate drive circuit in the first operating mode. The following explanation uses… Figure 13 and Figure 18 Explain the working principle of a shift register.

[0128] In the first operating mode, the driving process of this shift register includes:

[0129] In the first stage T1, the first clock signal and the first frequency inverse control signal are at low levels, while the second clock signal, the first frequency control signal, the second frequency control signal, and the input signal are at high levels. The thirteenth transistor M13 is turned on, the fourteenth transistor M14 is turned off, the first power supply signal is transmitted to the fifth node Q5, the eleventh transistor M11 and the twelfth transistor M12 are turned off, and the ninth transistor M9 and the tenth transistor M10 are turned on. The high level of the input signal is transmitted to the seventh node Q7 through the CMOS transmission gate composed of the ninth transistor M9 and the tenth transistor M10, turning on the sixteenth transistor M16. The low level of the second power supply signal serves as the first control signal, transmitted through the sixteenth transistor M16 to the second output terminal N2, turning on the seventeenth transistor M17 and the twentieth transistor M20. The seventeenth transistor M17 transmits the first power supply signal to the sixth node Q6, and the twentieth transistor M20 outputs the first power supply signal to the output terminal of the stage transmission control module 120 as the stage transmission output signal. The nineteenth transistor M19 is turned on, outputting the high level of the input signal as the second control signal, turning off the twenty-first transistor M21. Due to the coupling effect of the first capacitor Ca1, the stage output signal remains at a high level. The first control signal (i.e., the low level of the second power supply signal) is transmitted to the gate of the twenty-second transistor M22, controlling the twenty-second transistor M22 to conduct. The twenty-second transistor M22 outputs the first power supply signal to the output terminal of the gate control module 140 as a gate drive signal. The first control signal is also transmitted to the third node Q3, controlling the seventh transistor M7 to conduct. The first power supply signal is transmitted to the fourth node Q4 through the seventh transistor M7. Since the first frequency control signal and the second frequency control signal are at a high level, and the first frequency inverse control signal is at a low level, it is equivalent to each frequency control signal being at its corresponding enable level. Therefore, the first transistor M1 and the third transistor M3 are conducted, the second transistor M2 is turned off, and the high level of the fourth node Q4 is transmitted to the second control terminal Ctr2 of the gate output module 140 through the first transistor M1, the third transistor M3, and the sixth transistor M6 as a third control signal, causing the twenty-third transistor M23 to turn off.

[0130] In the second stage T2, the second clock signal and the first frequency inverse control signal are at low levels, while the first clock signal, the first frequency control signal, the second frequency control signal, and the input signal are at high levels. The thirteenth transistor M13 is turned off, the fourteenth transistor M14 is turned on, and the second power supply signal is transmitted to the fifth node Q5. The ninth transistor M9 and the tenth transistor M10 are turned off, and the eleventh transistor M11 and the twelfth transistor M12 are turned on. Since the sixth node Q6 is at a high level in the first stage T1, the high level of the sixth node Q6 is transmitted to the seventh node Q7 through the CMOS transmission gate composed of the eleventh transistor M11 and the twelfth transistor M12, turning on the sixteenth transistor M16. The low level of the second power supply signal serves as the first control signal, transmitted through the sixteenth transistor M16 to the second output terminal N2, turning on the seventeenth transistor M17 and the twentieth transistor M20. The seventeenth transistor M17 transmits the first power supply signal to the sixth node Q6, maintaining the potential of the sixth node Q6 at a high level. The twentieth transistor M20 outputs the first power supply signal to the output terminal of the stage transmission control module 120 as the stage transmission output signal. The nineteenth transistor M19 is turned on, outputting the high level of the input signal as the second control signal, while the twenty-first transistor M21 is turned off. Due to the coupling effect of the first capacitor Ca1, the stage output signal remains at a high level. The first control signal (i.e., the low level of the second power supply signal) is transmitted to the gate of the twenty-second transistor M22, controlling the twenty-second transistor M22 to turn on. The twenty-second transistor M22 outputs the first power supply signal to the output terminal of the gate control module 140 as the gate drive signal. The first control signal is also transmitted to the third node Q3, controlling the seventh transistor M7 to turn on. The first power supply signal is transmitted to the fifth node Q5 through the seventh transistor M7. Since the first frequency control signal and the second frequency control signal are at a high level, and the first frequency inverse control signal is at a low level, it is equivalent to each frequency control signal being at its corresponding enable level. Therefore, the first transistor M1 and the third transistor M3 are turned on, the second transistor M2 is turned off, and the high level of the fifth node Q5 is transmitted to the second control terminal Ctr2 of the gate output module 140 through the first transistor M1, the third transistor M3, and the sixth transistor M6 as the third control signal, causing the twenty-third transistor M23 to turn off.

[0131] In the third stage (T3), the first clock signal, the first frequency inverse control signal, and the input signal are at low levels, while the second clock signal, the first frequency control signal, and the second frequency control signal are at high levels. The thirteenth transistor M13 is turned on, the fourteenth transistor M14 is turned off, the first power supply signal is transmitted to the fifth node Q5, the ninth transistor M9 and the tenth transistor M10 are turned on, and the eleventh transistor M11 and the twelfth transistor M12 are turned off. The low level of the input signal is transmitted through the CMOS transmission gate formed by the ninth transistor M9 and the tenth transistor M10 to the seventh node Q7, turning on the fifteenth transistor M15. The high level of the first power supply signal serves as the first control signal, transmitted through the fifteenth transistor M15 to the second output terminal N2, turning on the eighteenth transistor M18 and turning off the twentieth transistor M20. The second power supply signal is transmitted through the turned-on eighteenth transistor M18 to the sixth node Q6, keeping the potential of the sixth node Q6 low. The nineteenth transistor M19 is turned on, outputting the low level of the input signal as the second control signal. The second control signal turns on the twenty-first transistor M21, which outputs the high level of the second clock signal as its gate drive signal. The first control signal (i.e., the high level of the first power supply signal) is transmitted to the gate of the twenty-second transistor M22, turning it off. The first control signal is also transmitted to the third node Q3, turning on the eighth transistor M8, which then transmits the second power supply signal to the fourth node Q4 via the eighth transistor M8. Since the first and second frequency control signals are high, and the first frequency inverse control signal is low, each frequency control signal is effectively at its corresponding enable level. Therefore, the first transistor M1 and the third transistor M3 are turned on, the second transistor M2 is turned off, and the low level of the fourth node Q4 is transmitted through the first transistor M1, the third transistor M3, and the sixth transistor M6 to the second control terminal Ctr2 of the gate output module 140 as the third control signal, turning on the twenty-third transistor M23. The twenty-third transistor M23 outputs the high level of the second clock signal as its gate drive signal.

[0132] In stage T4, the second clock signal and the first frequency inverse control signal are at low levels, while the first clock signal, the first frequency control signal, the second frequency control signal, and the input signal are at high levels. The thirteenth transistor M13 is turned off, the fourteenth transistor M14 is turned on, and the second power supply signal is transmitted to the fifth node Q5. The ninth transistor M9 and the tenth transistor M10 are turned off, and the eleventh transistor M11 and the twelfth transistor M12 are turned on. Since the sixth node Q6 is at a low level in stage T3, the low level of the sixth node Q6 is transmitted to the seventh node Q7 through the CMOS transmission gate composed of the eleventh transistor M11 and the twelfth transistor M12, turning on the fifteenth transistor M15. The high level of the first power supply signal, as the first control signal, is transmitted to the second output terminal N2 through the fifteenth transistor M15, turning on the eighteenth transistor M18 and turning off the twentieth transistor M20. The second power supply signal is transmitted to the sixth node Q6 through the turned-on eighteenth transistor M18, keeping the potential of the sixth node Q6 at a low level. The nineteenth transistor M19 is turned on, outputting the low level of the sixth node Q6 as the second control signal. The second control signal controls the twenty-first transistor M21 to turn on, and the twenty-first transistor M21 outputs the low level of the second clock signal as the stage output signal. The first control signal (i.e., the high level of the first power supply signal) is transmitted to the gate of the twenty-second transistor M22, controlling the twenty-second transistor M22 to turn off. The first control signal is also transmitted to the third node Q3, controlling the eighth transistor M8 to turn on, and the second power supply signal is transmitted to the fourth node Q4 through the eighth transistor M8. Since the first frequency control signal and the second frequency control signal are at a high level, and the first frequency inverse control signal is at a low level, it is equivalent to each frequency control signal being at its corresponding enable level. Therefore, the first transistor M1 and the third transistor M3 are turned on, the second transistor M2 is turned off, and the low level of the fourth node Q4 is transmitted through the first transistor M1, the third transistor M3, and the sixth transistor M6 to the second control terminal Ctr2 of the gate output module 140 as the third control signal, causing the twenty-third transistor M23 to turn on. The 23rd transistor M23 outputs the low level of the second clock signal as the gate drive signal.

[0133] The working process of the fifth stage T5 is the same as that of the first stage T1, and will not be repeated here.

[0134] In stage T6, the second clock signal and the first frequency control signal are at low levels, while the first clock signal, the first frequency inverse control signal, the second frequency control signal, and the input signal are at high levels. The thirteenth transistor M13 is turned off, the fourteenth transistor M14 is turned on, the second power supply signal is transmitted to the fifth node Q5, the ninth transistor M9 and the tenth transistor M10 are turned off, and the eleventh transistor M11 and the twelfth transistor M12 are turned on. Since the sixth node Q6 is at a high level in stage T1, the high level of the sixth node Q6 is transmitted to the seventh node Q7 through the CMOS transmission gate composed of the eleventh transistor M11 and the twelfth transistor M12, turning on the sixteenth transistor M16. The low level of the second power supply signal serves as the first control signal, transmitted through the sixteenth transistor M16 to the second output terminal N2, turning on the seventeenth transistor M17 and the twentieth transistor M20. The seventeenth transistor M17 transmits the first power supply signal to the sixth node Q6, maintaining the potential of the sixth node Q6 at a high level. The twentieth transistor M20 outputs the first power signal to the output terminal of the stage transmission control module 120 as the stage transmission output signal. The nineteenth transistor M19 is turned on, outputting the high level of the input signal as the second control signal, and the twenty-first transistor M21 is turned off. Due to the coupling effect of the first capacitor Ca1, the stage transmission output signal remains at a high level. The first control signal (i.e., the low level of the second power signal) is transmitted to the gate of the twenty-second transistor M22, controlling the twenty-second transistor M22 to turn on. The twenty-second transistor M22 outputs the first power signal to the output terminal of the gate control module 140 as the gate drive signal. The first control signal is also transmitted to the third node Q3, controlling the seventh transistor M7 to turn on. The first power signal is transmitted to the fifth node Q5 through the seventh transistor M7. Since the second frequency control signal and the first frequency inverse control signal are at a high level, and the first frequency control signal is at a low level, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off. Due to the storage effect of the third capacitor Ca3, the second control terminal Ctr2 of the gate output module 140 remains at a high level from the previous stage, controlling the twenty-third transistor M23 to turn off.

[0135] Figure 15 This is a schematic diagram illustrating the driving timing of a shift register in a second operating mode according to an embodiment of the present invention. (Combined with...) Figure 13 and Figure 15Taking an example where the first power signal is high and the second power signal is low, the following explanation is provided. Here, cin represents the timing of the input signal provided by the input terminal CIN of the drive control module 110; clk1 represents the timing of the first clock signal provided by the first clock signal input terminal CLK1; clk2 represents the timing of the second clock signal provided by the second clock signal input terminal CLK2; c1 represents the timing of the first frequency control signal provided by the first frequency control signal input terminal C1; c1b represents the timing of the first frequency inverse control signal provided by the first frequency inverse control signal input terminal C1B; c2 represents the timing of the first frequency control signal provided by the first frequency control signal input terminal C2; and vout represents the timing of the gate drive signal output by the output terminal VOUT of the gate drive circuit in the second operating mode. The following explanation uses… Figure 13 and Figure 15 Explain the working principle of the shift register. In the second operating mode, the driving process of this shift register includes:

[0136] In the first stage P1, the first clock signal, input signal, first frequency control signal, and second frequency control signal are at low levels, while the second clock signal and the first frequency inverse control signal are at high levels. The thirteenth transistor M13 is turned on, the fourteenth transistor M14 is turned off, the first power supply signal is transmitted to the fifth node Q5, the eleventh transistor M11 and the twelfth transistor M12 are turned off, and the ninth transistor M9 and the tenth transistor M10 are turned on. The low level of the input signal is transmitted to the seventh node Q7 through the CMOS transmission gate formed by the ninth transistor M9 and the tenth transistor M10, turning on the fifteenth transistor M15. The high level of the first power supply signal serves as the first control signal, transmitted through the fifteenth transistor M15 to the second output terminal N2, turning on the eighteenth transistor M18 and turning off the twentieth transistor M20. The second power supply signal is transmitted to the sixth node Q6 through the turned-on eighteenth transistor M18, keeping the potential of the sixth node Q6 low. The nineteenth transistor M19 is turned on, outputting the low level of the input signal as the second control signal. The second control signal turns on the twenty-first transistor M21, which outputs the high level of the second clock signal as the stage output signal. The first control signal (i.e., the high level of the first power supply signal) is transmitted to the gate of the twenty-second transistor M22, turning it off. The first control signal is also transmitted to the third node Q3, turning on the eighth transistor M8, and the second power supply signal is transmitted to the fourth node Q4 through the eighth transistor M8. Since the first and second frequency control signals are low, and the first frequency inverse control signal is high, it is equivalent to each frequency control signal being at its corresponding disabled level. Therefore, the first transistor M1 and the third transistor M3 are turned off, the second transistor M2 is turned on, and the high level of the first power supply signal is transmitted to the second control terminal Ctr2 of the gate output module 140 through the second transistor M2 and the sixth transistor M6 as the third control signal, causing the twenty-third transistor M23 to turn off. Since the third capacitor Ca3 has a bootstrap function, the gate drive signal is also high.

[0137] In the second stage P2, the second clock signal, the first frequency control signal, and the second frequency control signal are at low levels, while the first clock signal, the input signal, and the first frequency inverse control signal are at high levels. The thirteenth transistor M13 is turned off, the fourteenth transistor M14 is turned on, and the second power supply signal is transmitted to the fifth node Q5. The ninth transistor M9 and the tenth transistor M10 are turned off, and the eleventh transistor M11 and the twelfth transistor M12 are turned on. Since the sixth node Q6 in the first stage P1 is at a low level, the low level of the sixth node Q6 is transmitted to the seventh node Q7 through the CMOS transmission gate composed of the eleventh transistor M11 and the twelfth transistor M12, turning on the fifteenth transistor M15. The high level of the first power supply signal, as the first control signal, is transmitted to the second output terminal N2 through the fifteenth transistor M15, turning on the eighteenth transistor M18 and turning off the twentieth transistor M20. The second power supply signal is transmitted to the sixth node Q6 through the turned-on eighteenth transistor M18, keeping the potential of the sixth node Q6 at a low level. The nineteenth transistor M19 is turned on, outputting the low level of the input signal as the second control signal. The second control signal turns on the twenty-first transistor M21, which outputs the low level of the second clock signal as the stage output signal. The first control signal (i.e., the high level of the first power supply signal) is transmitted to the gate of the twenty-second transistor M22, turning it off. The first control signal is also transmitted to the third node Q3, turning on the eighth transistor M8, and the second power supply signal is transmitted to the fourth node Q4 through the eighth transistor M8. Since the first and second frequency control signals are low, and the first frequency inverse control signal is high, it is equivalent to each frequency control signal being at its corresponding disabled level. Therefore, the first transistor M1 and the third transistor M3 are turned off, the second transistor M2 is turned on, and the high level of the first power supply signal is transmitted to the second control terminal Ctr2 of the gate output module 140 through the second transistor M2 and the sixth transistor M6 as the third control signal, causing the twenty-third transistor M23 to turn off. Since the third capacitor Ca3 has a bootstrap function, the gate drive signal is also high.

[0138] In the third stage (P3), the first clock signal, the first frequency control signal, and the second frequency control signal are at low levels, while the second clock signal, the input signal, and the first frequency inverse control signal are at high levels. The thirteenth transistor M13 is turned on, the fourteenth transistor M14 is turned off, the first power supply signal is transmitted to the fifth node Q5, the eleventh transistor M11 and the twelfth transistor M12 are turned off, and the ninth transistor M9 and the tenth transistor M10 are turned on. The high level of the input signal is transmitted to the seventh node Q7 through the CMOS transmission gate composed of the ninth transistor M9 and the tenth transistor M10, turning on the sixteenth transistor M16. The low level of the second power supply signal serves as the first control signal, transmitted through the sixteenth transistor M16 to the second output terminal N2, turning on the seventeenth transistor M17 and the twentieth transistor M20. The seventeenth transistor M17 transmits the first power supply signal to the sixth node Q6, making the potential of the sixth node Q6 high. The twentieth transistor M20 outputs the first power supply signal to the output terminal of the stage transmission control module 120 as the stage transmission output signal. The nineteenth transistor M19 is turned on, outputting the high level of the input signal as the second control signal. Due to the coupling effect of the first capacitor Ca1, the stage output signal remains at a high level. The first control signal (i.e., the low level of the second power supply signal) is transmitted to the gate of the twenty-second transistor M22, controlling the twenty-second transistor M22 to conduct. The twenty-second transistor M22 outputs the first power supply signal to the output terminal of the gate control module 140 as the gate drive signal. The first control signal is also transmitted to the third node Q3, controlling the seventh transistor M7 to conduct. The first power supply signal is transmitted to the fourth node Q4 through the seventh transistor M7. Since the first frequency control signal and the second frequency control signal are at a low level, and the first frequency inverse control signal is at a high level, it is equivalent to each frequency control signal being at its corresponding disabled level. Therefore, the first transistor M1 and the third transistor M3 are turned off, the second transistor M2 is turned on, and the high level of the first power supply signal is transmitted to the second control terminal Ctr2 of the gate output module 140 through the second transistor M2 and the sixth transistor M6 as the third control signal, causing the twenty-third transistor M23 to turn off. Since the third capacitor Ca3 has a bootstrap function, the gate drive signal is also at a high level.

[0139] In the fourth stage (P4), the second clock signal, the first frequency control signal, and the second frequency control signal are at low levels, while the first clock signal, the input signal, and the first frequency inverse control signal are at high levels. The thirteenth transistor M13 is turned off, the fourteenth transistor M14 is turned on, and the second power supply signal is transmitted to the fifth node Q5. The ninth transistor M9 and the tenth transistor M10 are turned off, and the eleventh transistor M11 and the twelfth transistor M12 are turned on. Since the sixth node Q6 in the first stage (P1) is at a high level, the low level of the sixth node Q6 is transmitted to the seventh node Q7 through the CMOS transmission gate composed of the eleventh transistor M11 and the twelfth transistor M12, turning on the sixteenth transistor M16. The low level of the second power supply signal, as the first control signal, is transmitted to the second output terminal N2 through the sixteenth transistor M16, turning on the seventeenth transistor M17 and the twentieth transistor M20. The seventeenth transistor M17 transmits the first power supply signal to the sixth node Q6, maintaining the potential of the sixth node Q6 at a high level. The twentieth transistor M20 outputs the first power signal to the output of the stage transmission control module 120 as the stage transmission output signal. The nineteenth transistor M19 is turned on, outputting the high level of the sixth node Q6 as the second control signal. Due to the coupling effect of the first capacitor Ca1, the stage transmission output signal remains at a high level. The first control signal (i.e., the low level of the second power signal) is transmitted to the gate of the twenty-second transistor M22, controlling the twenty-second transistor M22 to turn on. The twenty-second transistor M22 outputs the first power signal to the output of the gate control module 140 as the gate drive signal. The first control signal is also transmitted to the third node Q3, controlling the seventh transistor M7 to turn on. The first power signal is transmitted to the fourth node Q4 through the seventh transistor M7. Since the first and second frequency control signals are at low levels, and the first frequency inverse control signal is at a high level, it is equivalent to each frequency control signal being at its corresponding disabled level. Therefore, the first transistor M1 and the third transistor M3 are turned off, and the second transistor M2 is turned on. The high level of the first power supply signal is transmitted through the second transistor M2 and the sixth transistor M6 to the second control terminal Ctr2 of the gate output module 140 as the third control signal, which turns off the twenty-third transistor M23. Since the third capacitor Ca3 has a bootstrap function, the gate drive signal is also at a high level.

[0140] Figure 16 This is a simulation timing diagram of a gate driving circuit provided in an embodiment of the present invention. See also... Figure 16The output is displayed as a comparison of the 13 lines of gate drive signals vout1 to vout13 between the two frames. In the first frame, the gate drive signals in all areas are normal output waveforms (i.e., low level, equivalent to including low-level pulse signals); in the second frame, the gate drive signals remain at a high level during the portions where the first and second frequency control signals are low (equivalent to an enable level), and simultaneously, the gate drive signals are normal output waveforms (i.e., low level, equivalent to including low-level pulse signals) during the portions where the first and second frequency control signals are high (equivalent to an enable level). Gate drive signals vout1 to vout3 correspond to a high-frequency refresh display zone, gate drive signals vout4 to vout7 correspond to a low-frequency refresh display zone, and gate drive signals vout8 to vout13 correspond to another high-frequency refresh display zone.

[0141] It should be noted that in the above embodiments, one of the first and second terminals of each transistor is the source, and the other is the drain. The first terminal of each transistor in the above embodiments can be called the source or the drain, and correspondingly, the second terminal can be called the drain or the source. Since the transistor structure in the display panel is symmetrical, the source and drain of each transistor are not distinguished.

[0142] This invention also provides a display panel, including the gate driving circuit provided in any embodiment of this invention, which has corresponding beneficial effects. Figure 17 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. See also... Figure 17 The display panel includes pixel circuits 20 and a gate driving circuit 30 provided in any embodiment of the present invention; the gate driving circuit 30 is connected to the pixel circuits 20 and is used to provide gate driving signals to the pixel circuits 20. The display panel may include multiple rows of pixel circuits 20, and the multi-stage shift registers 10 in the gate driving circuit 30 are respectively connected to at least one row of pixel circuits 20 and are used to provide gate driving signals to at least one row of pixel circuits 20.

[0143] Specifically, the display panel includes a display area AA and a non-display area NAA. The display area AA contains an array of pixel circuits 20, and the gate driving circuit 30 is located in the non-display area NAA. To provide the various signals required by the gate driving circuit 30, the non-display area NAA may also include a first power signal line L1 for providing a first power signal; a second power signal line L2 for providing a second power signal; a first frequency control signal line L1B for providing a first frequency control signal; a second frequency control signal line L2B for providing a second frequency control signal; and an input signal line LIN for providing the input signal to the first-stage shift register. The input signals of other shift registers are the stage output signals from the previous stage shift register. That is, the input terminal CIN of the drive control module in the first-stage shift register is connected to the input signal line, and the input terminal CIN of the drive control module in other shift registers is connected to the output terminal COUT of the stage output module in the previous stage shift register. The pixel circuit 20 can have any existing pixel circuit structure. For example, the output of the scan output module of each shift register 10 is connected to a row of pixel circuits 20 via scan line LS, for example, to a functional module in pixel circuit 20 used to control the data writing process.

[0144] Figure 17 The diagram illustrates an exemplary cascade of four shift registers. A first clock signal line L1C provides a first clock signal to the odd-numbered shift registers and a second clock signal to the even-numbered shift registers. The clock signal on the first clock signal line L1C serves as the first clock signal for the odd-numbered shift registers and the second clock signal for the even-numbered shift registers. Similarly, a second clock signal line L2C provides a second clock signal to the odd-numbered shift registers and a first clock signal to the even-numbered shift registers. The clock signal on the second clock signal line L2C serves as the second clock signal for the odd-numbered shift registers and the first clock signal for the even-numbered shift registers.

[0145] Optionally, all shift registers are connected to the same first frequency control signal line L1B (for transmitting the first frequency control signal). Optionally, all shift registers are connected to the same second frequency control signal line L2B (for transmitting the second frequency control signal). Optionally, all shift registers are connected to the same first frequency inverse control signal line L1CB (for transmitting the first frequency inverse control signal). The position of the boundary line and the refresh rate of different display zones can be adjusted by controlling the timing of the potential transitions and the pulse width of each frequency control signal.

[0146] For example, the first power signal input terminal PVGH of the odd-level shift register (e.g., the first-level shift register and the third-level shift register) is connected to the first power signal line L1, and the second power signal input terminal PVGL is connected to the second power signal line L2; the first frequency control signal input terminal C1 is connected to the first frequency control signal line L1B, the second frequency control signal input terminal C2 is connected to the second frequency control signal line L2B, the first frequency inverse control signal input terminal C1B is connected to the first frequency inverse control signal line L1CB; the first clock signal input terminal CLK1 is connected to the first clock signal line L1C, and the second clock signal input terminal CLK2 is connected to the second clock signal line L2C.

[0147] The first power signal input terminal PVGH of the even-numbered stage shift registers (e.g., the second-stage shift register and the fourth-stage shift register) is connected to the first power signal line L1, and the second power signal input terminal PVGL is connected to the second power signal line L2. The first frequency control signal input terminal C1 is connected to the first frequency control signal line L1B, the second frequency control signal input terminal C2 is connected to the second frequency control signal line L2B, and the first frequency inverse control signal input terminal C1B is connected to the first frequency inverse control signal line L1CB. The first clock signal input terminal CLK1 is connected to the second clock signal line L2C, and the second clock signal input terminal CLK2 is connected to the first clock signal line L1C. By controlling the first frequency control signal transmitted on the first frequency control signal line L1B, the second frequency control signal transmitted on the second frequency control signal line L2B, and the first frequency inverse control signal transmitted on the first frequency inverse control signal line L1CB, the display refresh rate of the pixel units connected to the first to fourth stage shift registers can be controlled. Therefore, the display refresh rate of the pixel units connected to the cascaded shift register can be controlled according to the first frequency control signal and the second frequency control signal to realize the segmented frequency display of the display panel.

[0148] Figure 18 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. For example, the drive control module 110 may include transistors T1 to T10 and capacitors C1 and C5. The pulse signals output by the stage output module 120 and the gate output module 140 may be high-level pulse signals. The second output unit 122 may also include capacitor C2.

[0149] This invention also provides a display device. Figure 19 This is a schematic diagram of a display device provided in an embodiment of the present invention. Figure 19As shown, the display device includes the display panel 1 provided in any embodiment of the present invention. This display device can be, for example, a mobile phone, tablet computer, smart wearable device, or information kiosks in public lobbies. The technical principles and effects of the display panel 1 provided in any embodiment of the present invention are similar, and will not be repeated here. Optionally, the display device also includes a driver chip. The driver chip can provide a first-stage input signal to the first-stage shift register in the gate driving circuit through input signal lines, and provide data voltages to each column of pixel circuits through data lines.

[0150] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gate driving circuit, characterized in that, include: Multi-stage shift registers; The shift register includes: a drive control module, a stage output module, a transmission control module, and a gate output module; The first output terminal of the drive control module is connected to the first control terminal of the stage transmission output module. The second output terminal of the drive control module is connected to the second control terminal of the stage transmission output module, the control terminal of the transmission control module, and the first control terminal of the gate output module. The output terminal of the transmission control module is connected to the second control terminal of the gate output module. The drive control module is used to output a first control signal to the second output terminal of the drive control module and output a second control signal to the first output terminal of the drive control module, based at least on a first clock signal and an input signal. The stage transmission output module is used to output a stage transmission output signal to the output terminal of the stage transmission output module, based at least on the first control signal and the second control signal. The transmission control module is used to output a third control signal to the output terminal of the transmission control module, based at least on a frequency control signal and the first control signal. The gate output module is used to output a gate drive signal, based at least on the first control signal and the third control signal. The transmission control module includes: a first inverter and an output control unit; The input terminal of the first inverter serves as the control terminal of the transmission control module, and the output terminal of the first inverter is connected to the input terminal of the output control unit. The control terminal of the output control unit is used to input the frequency control signal, and the output terminal of the output control unit serves as the output terminal of the transmission control module. The first inverter is used to invert the first control signal and output a first inverted control signal. The output control unit is used to generate the third control signal based at least on the first inverted control signal and the frequency control signal. The stage transmission output module includes a first output unit and a second output unit; The control terminal of the first output unit serves as the second control terminal of the stage transmission output module. The output terminal of the first output unit is connected to the output terminal of the second output unit and serves as the output terminal of the stage transmission output module. The control terminal of the second output unit serves as the first control terminal of the stage transmission output module.

2. The gate driving circuit according to claim 1, characterized in that, The second control signal and the first control signal have opposite potential levels.

3. The gate driving circuit according to claim 1, characterized in that, The first terminal of the first inverter is used to input a first power signal, and the second terminal of the first inverter is used to input a second power signal.

4. The gate driving circuit according to claim 1, characterized in that, The frequency control signal includes a first frequency control signal and a second frequency control signal; the output control unit includes a first transistor and a second transistor; The gate of the first transistor serves as the first control terminal of the output control unit, used to input the first frequency control signal. The first electrode of the first transistor serves as the input terminal of the output control unit. The second electrode of the first transistor is connected to the first electrode of the second transistor and serves as the output terminal of the output control unit. The gate of the second transistor serves as the second control terminal of the output control unit, used to input the second frequency control signal. The second electrode of the second transistor is used to input the first power supply signal.

5. The gate driving circuit according to claim 4, characterized in that, The frequency control signal further includes a first frequency inverse control signal, and the output control unit further includes a third transistor, the gate of which serves as the third control terminal of the output control unit for inputting the first frequency inverse control signal. Alternatively, the output control unit further includes a second inverter and a third transistor, wherein the input terminal of the second inverter is electrically connected to the first control terminal of the output control unit for inputting the first frequency control signal, and the output terminal of the second inverter is electrically connected to the gate of the third transistor; The first terminal of the third transistor is connected to the first terminal of the first transistor, and the second terminal of the third transistor is connected to the second terminal of the first transistor; wherein the channel type of the third transistor is different from that of the first transistor.

6. The gate driving circuit according to claim 5, characterized in that, The second inverter includes a fourth transistor and a fifth transistor; the gate of the fourth transistor is connected to the gate of the fifth transistor and serves as the input terminal of the second inverter for inputting the first frequency control signal; the first terminal of the fourth transistor is used to input the first power supply signal; the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor and the gate of the third transistor respectively; and the second terminal of the fifth transistor is used to input a second power supply signal.

7. The gate driving circuit according to claim 5, characterized in that, At least two of the shift registers share the same second inverter.

8. The gate driving circuit according to claim 1, characterized in that, The shift register further includes a sixth transistor; the gate of the sixth transistor is used to input a second power supply signal, and the output terminal of the transmission control module is connected to the second control terminal of the gate output module through the sixth transistor.

9. The gate driving circuit according to claim 1, characterized in that, The first inverter includes a seventh transistor and an eighth transistor; The gate of the seventh transistor is connected to the gate of the eighth transistor and serves as the input terminal of the first inverter. The first terminal of the seventh transistor serves as the first terminal of the first inverter for inputting a first power supply signal. The second terminal of the seventh transistor is connected to the first terminal of the eighth transistor and serves as the output terminal of the first inverter. The second terminal of the eighth transistor serves as the second terminal of the first inverter for inputting a second power supply signal.

10. The gate driving circuit according to any one of claims 1-9, characterized in that, The drive control module includes an input unit, a node feedback unit, a second inverting unit, and a third inverting unit; The input unit is used to generate the second control signal according to the first clock signal and the input signal. The input terminal of the second inverting unit is connected to the output terminal of the input unit. The second inverting unit is used to invert the second control signal to generate the first control signal. The input terminal of the third inverting unit is connected to the output terminal of the second inverting unit. The third inverting unit is used to invert the first control signal to output the second inverted control signal. The node feedback unit is connected between the output terminal of the third inverting unit and the input terminal of the second inverting unit. The node feedback unit is used to control the potential of the second control signal according to the first clock signal and / or the first inverted clock signal and the second inverted control signal.

11. The gate driving circuit according to claim 10, characterized in that, The switching states of the input unit and the node feedback unit are opposite.

12. The gate driving circuit according to claim 10, characterized in that, The drive control module further includes a first inverting unit, the output of which is connected to the input unit and / or the node feedback unit. The first inverting unit is used to invert the first clock signal and output a first inverted clock signal. The input unit is used to generate the second control signal based on the first clock signal and / or the first inverted clock signal, as well as the input signal.

13. The gate driving circuit according to claim 12, characterized in that, At least two of the shift registers share the same first inverting unit.

14. The gate driving circuit according to claim 10, characterized in that, The input unit includes a ninth transistor, the gate of which is used to input the first inverted clock signal, the first terminal of which is used to receive the input signal and serve as the input terminal of the input unit, and the second terminal of which serves as the output terminal of the input unit. And / or, the input unit includes a tenth transistor, the gate of which is used to input the first clock signal, the first terminal of which is used to receive the input signal and serve as the input terminal of the input unit, and the second terminal of which serves as the output terminal of the input unit.

15. The gate driving circuit according to claim 14, characterized in that, The tenth transistor has a different channel type than the ninth transistor.

16. The gate driving circuit according to claim 10, characterized in that, The node feedback unit includes an eleventh transistor. The gate of the eleventh transistor is used to input the first clock signal, the first terminal of the eleventh transistor is used to receive the second inverting control signal and serves as the input terminal of the node feedback unit, and the second terminal of the eleventh transistor serves as the output terminal of the node feedback unit. And / or, the node feedback unit includes a twelfth transistor, the gate of which is used to input the first inverted clock signal, the first terminal of which is used to receive the second inverted control signal and serve as the input terminal of the node feedback unit, and the second terminal of which serves as the output terminal of the node feedback unit.

17. The gate driving circuit according to claim 16, characterized in that, The twelfth transistor has a different channel type than the eleventh transistor.

18. The gate driving circuit according to claim 12, characterized in that, The first inverting unit includes a thirteenth transistor and a fourteenth transistor. The gates of the thirteenth transistor and the fourteenth transistor are connected and serve as the input terminal of the first inverting unit for inputting the first clock signal. The first terminal of the thirteenth transistor is used to input a first power supply signal. The second terminal of the thirteenth transistor is connected to the first terminal of the fourteenth transistor and serves as the output terminal of the first inverting unit. The second terminal of the fourteenth transistor is used to input a second power supply signal.

19. The gate driving circuit according to claim 10, characterized in that, The second inverting unit includes a fifteenth transistor and a sixteenth transistor. The gate of the fifteenth transistor is connected to the gate of the sixteenth transistor and serves as the input terminal of the second inverting unit for inputting the second control signal. The first terminal of the fifteenth transistor is used to input a first power supply signal. The second terminal of the fifteenth transistor is connected to the first terminal of the sixteenth transistor and serves as the output terminal of the second inverting unit. The second terminal of the sixteenth transistor is used to input a second power supply signal.

20. The gate driving circuit according to claim 10, characterized in that, The third inverting unit includes a seventeenth transistor and an eighteenth transistor. The gate of the seventeenth transistor is connected to the gate of the eighteenth transistor and serves as the input terminal of the third inverting unit for inputting the first control signal. The first terminal of the seventeenth transistor is used to input the first power supply signal. The second terminal of the seventeenth transistor is connected to the first terminal of the eighteenth transistor and serves as the output terminal of the third inverting unit. The second terminal of the eighteenth transistor is used to input the second power supply signal.

21. The gate driving circuit according to claim 10, characterized in that, The drive control module further includes a nineteenth transistor, the gate of which is used to input a second power signal, the first terminal of which is connected to the output terminal of the input unit and the output terminal of the node feedback unit, and the second terminal of which serves as the first output terminal of the drive control module.

22. The gate driving circuit according to any one of claims 1-9, characterized in that, The input terminal of the first output unit is used to input a first power signal; the input terminal of the second output unit is used to input a second clock signal, and the first output unit and the second output unit are used to output the first power signal or the second clock signal as the stage output signal according to the first control signal and the second control signal.

23. The gate driving circuit according to claim 22, characterized in that, The first output unit is used to output the first power signal to the output terminal of the stage transmission module according to the first control signal; the second output unit is used to output the second clock signal to the output terminal of the stage transmission module according to the second control signal.

24. The gate driving circuit according to claim 23, characterized in that, The first output unit includes a twentieth transistor, the gate of the twentieth transistor serves as the control terminal of the first output unit, the first terminal of the twentieth transistor serves as the input terminal of the first output unit, and the second terminal of the twentieth transistor serves as the output terminal of the first output unit.

25. The gate driving circuit according to claim 23, characterized in that, The second output unit includes a twenty-first transistor and a first capacitor; the gate of the twenty-first transistor serves as the control terminal of the second output unit, the first terminal of the twenty-first transistor serves as the output terminal of the second output unit, and the second terminal of the twenty-first transistor serves as the input terminal of the second output unit; the first capacitor is connected between the gate and the first terminal of the twenty-first transistor.

26. The gate driving circuit according to claim 1, characterized in that, The output terminal of the stage output module of the previous stage shift register is connected to the input terminal of the drive control module of the next stage shift register.

27. The gate driving circuit according to any one of claims 1-9, characterized in that, The gate output module includes a third output unit and a fourth output unit; The control terminal of the third output unit serves as the first control terminal of the gate output module. The input terminal of the third output unit is used to input a first power supply signal. The output terminal of the third output unit is connected to the output terminal of the fourth output unit and serves as the output terminal of the gate output module. The control terminal of the fourth output unit serves as the second control terminal of the gate output module. The input terminal of the fourth output unit is used to input a second clock signal. The third output unit and the fourth output unit are used to output the first power supply signal or the second clock signal as the gate drive signal according to the first control signal and the third control signal.

28. The gate driving circuit according to claim 27, characterized in that, The third output unit is used to output the first power signal to the output terminal of the gate output module according to the first control signal; the fourth output unit is used to output the second clock signal to the output terminal of the gate output module according to the third control signal.

29. The gate driving circuit according to claim 28, characterized in that, The third output unit includes a second capacitor and a twenty-second transistor. The gate of the twenty-second transistor serves as the control terminal of the third output unit, the first terminal of the twenty-second transistor serves as the input terminal of the third output unit, and the second terminal of the twenty-second transistor serves as the output terminal of the third output unit. The second capacitor is connected between the gate and the first terminal of the twenty-second transistor.

30. The gate driving circuit according to claim 28, characterized in that, The fourth output unit includes a third capacitor and a twenty-third transistor. The gate of the twenty-third transistor serves as the control terminal of the fourth output unit, the first terminal of the twenty-third transistor serves as the output terminal of the fourth output unit, and the second terminal of the twenty-third transistor serves as the input terminal of the fourth output unit. The third capacitor is connected between the gate and the first terminal of the twenty-third transistor.

31. The gate driving circuit according to claim 1, characterized in that, The input terminal of the first output unit is used to input a first power signal, and the first output unit is used to output the first power signal to the output terminal of the stage transmission module according to the first control signal. The input terminal of the second output unit is used to input the second clock signal, and the second output unit is used to output the second clock signal to the output terminal of the stage transmission output module according to the second control signal; Alternatively, the input terminal of the second output unit is used to input the second power signal, and the second output unit is used to output the second power signal to the output terminal of the stage transmission module according to the second control signal.

32. The gate driving circuit according to claim 1, characterized in that, The gate output module includes a third output unit and a fourth output unit; The control terminal of the third output unit serves as the first control terminal of the gate output module. The output terminal of the third output unit is connected to the output terminal of the fourth output unit and serves as the output terminal of the gate output module. The control terminal of the fourth output unit serves as the second control terminal of the gate output module. The input terminal of the third output unit is used to input a first power signal, and the third output unit is used to output the first power signal to the output terminal of the gate output module according to the first control signal. The input terminal of the fourth output unit is used to input the second clock signal, and the fourth output unit is used to output the second clock signal to the output terminal of the gate output module according to the third control signal; Alternatively, the input terminal of the fourth output unit is used to input the second power signal, and the fourth output unit is used to output the second power signal to the output terminal of the gate output module according to the third control signal; When the fourth output unit is turned on, a pulse signal of the gate drive signal is generated.

33. The gate driving circuit according to claim 1, characterized in that, For the same shift register, when the frequency control signal is at the enable level, when the output terminal of the stage transmission output module outputs a pulse signal, the transmission control module controls the output terminal of the gate output module to synchronously output a pulse signal. When the frequency control signal is at an inactive level, and the output terminal of the stage transmission module outputs a pulse signal, the transmission control module controls the output terminal of the gate output module to maintain an inactive or cut-off potential of the pulse signal or not to output a pulse signal synchronously. When the second output unit is turned on, a pulse signal is generated to transmit the signal from the stage.

34. A display panel, characterized in that, Includes the gate drive circuit according to any one of claims 1-33.

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