Audio analog-digital conversion chip array data time-sharing output implementation device and method

Abstract

The application discloses an audio analog-digital conversion chip array data time-sharing output implementation device and method, wherein the implementation device comprises a plurality of parallel audio analog-digital conversion chips, and the audio analog-digital conversion chip comprises a control module and a switch module; the control module comprises a field time slot control unit and a first logic operation unit, the field time slot control unit is used for generating a field time slot indication signal based on a field time slot value, the first logic operation unit is used for performing logic operation on a bit clock signal and the field time slot indication signal to obtain a first control signal, and the first control signal is used for controlling the switch module to act. Through the method of taking the inverse delay of the bit clock signal, a high-resistance state protection interval of half a bit time slot exists at the intersection of two adjacent field time slots, and since any chip cannot drive in the high-resistance state protection interval, the problem of multiple driving conflicts existing in the two adjacent field time slots is solved.

Description

Technical Field

[0001] This invention belongs to the field of audio analog-to-digital converter (ADC) chip array technology, specifically relating to an audio analog-to-digital converter chip array data time-division output implementation device and implementation method. Background Technology

[0002] With the rapid development of speech recognition technology, audio ADC (Analog-to-digital converter) chips are being used more and more widely in this field. In some demanding speech recognition applications, multiple audio ADC chips need to be integrated into an array (often called a microphone array) to improve the speech recognition effect.

[0003] There are various integration methods for audio ADC chip arrays, with two common types. The first type integrates the output audio serial data signal lines of each audio ADC chip in a tri-state manner onto a single shared audio data signal line. Each audio ADC chip then uses this shared audio data signal line in a time-sharing manner, as shown in the attached diagram. Figure 1a As shown; the second type involves each audio ADC chip containing one audio data input signal line and one audio data output signal line. The audio output signal line of the preceding stage audio ADC chip is then connected to the audio input signal line of the following stage audio ADC chip, and so on, stage by stage, until finally transmitted out through the audio output signal line of the last stage audio ADC chip, as shown in the attached diagram. Figure 1b As shown.

[0004] The first type of integration method connects the output data of multiple chips together via wired-AND. Each chip only drives data output during its own time slot, and outputs a high-impedance state during its non-time slots. For example, two chips, 1 and 2, with a sampling bit width of 16 bits and a data format of DSPB, integrated using the first type of integration method, will have the following overall ADC output diagram: Figure 2 As shown, chip 1 outputs data only in time slot 1 and outputs high impedance at other times, while chip 2 outputs data in time slot 2 and outputs high impedance at other times.

[0005] Integrating the output data lines of different chips directly via wired-AND can lead to issues where the chips are driven simultaneously for certain time periods due to varying output data delays. For example... Figure 4 As shown, chip 1 and chip 2 output data in two adjacent time slots. The output data C1D0 of chip 1 is delayed by T1, and the output data C2D15 of chip 2 is delayed by T2. Due to the difference between T1 and T2, C1D0 and C2D15 will overlap, which will result in the multi-drive problem of simultaneous driving at position T3 in the figure.

[0006] Therefore, to address the aforementioned technical problems, it is necessary to provide a novel method for data output from an audio analog-to-digital converter chip.

[0007] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0008] The purpose of this invention is to provide an audio analog-to-digital converter chip array data time-division output implementation device and method, which can solve the problem of multiple drive conflicts at the junction of two adjacent field time slots.

[0009] To achieve the above objectives, a specific embodiment of the present invention provides an audio analog-to-digital converter (ADC) chip array data time-division output implementation device. The implementation device includes multiple audio ADC chips connected in parallel, and each audio ADC chip includes a control module and a switching module.

[0010] The control module includes a field time slot control unit and a first logic operation unit. The field time slot control unit is used to generate a field time slot indication signal based on the field time slot value. The first logic operation unit is used to perform logical operations on the bit clock signal and the field time slot indication signal to obtain a first control signal. The first control signal is used to control the operation of the switching module.

[0011] In one or more embodiments of the present invention, the first logic operation unit includes a NOT gate, a delay unit, and an AND gate;

[0012] The NOT gate is used to perform a logical inversion operation on the bit clock signal to generate a bit clock inversion signal, and the delay unit is used to perform a delay operation on the bit clock inversion signal to obtain a bit slot indication signal.

[0013] The AND gate is used to perform an AND logic operation on the bit time slot indicator signal and the field time slot indicator signal to obtain the first control signal.

[0014] In one or more embodiments of the present invention, the delay time of the delay unit is greater than or equal to the largest audio analog-to-digital converter chip output data delay in the audio analog-to-digital converter chip array and less than 1 / 2 bit duration.

[0015] In one or more embodiments of the present invention, the field time slot control unit includes a time slot counter, the time slot counter is used to obtain the current time slot position count value, and the field time slot control unit is used to compare the current time slot position count value with the field time slot value to obtain a field time slot indication signal.

[0016] In one or more embodiments of the present invention, the control module further includes a word bit flag control unit and a second logic operation unit;

[0017] The word bit flag control unit is used to generate a valid word length indication signal based on the word length indication value and the bit clock signal;

[0018] The second logic operation unit is connected to the first logic operation unit and the word bit flag control unit. The second logic operation unit is used to perform an OR logic judgment on the first control signal and the effective word length indication signal to obtain the second control signal. The second control signal is used to control the operation of the switch module.

[0019] In one or more embodiments of the present invention, the word bit flag control unit includes a bit counter, which is used to mark the current field slot bit position count value; the word bit flag control unit is used to output a valid word length indication signal based on the marked current field slot bit position count value and a bit clock signal.

[0020] In one or more embodiments of the present invention, the switching module is a tri-state gate circuit, which includes an enable control terminal, an input terminal, and an output terminal; the input terminal is used to receive an input signal, the output terminal is used to send an input signal, and the enable control terminal is used to control the opening or closing of the tri-state gate circuit based on a first control signal or a second control signal.

[0021] A specific embodiment of the present invention provides a method for implementing time-division multiplexing of data output from an audio analog-to-digital converter (ADC) chip array, based on any embodiment of the audio ADC chip array data time-division multiplexing implementation apparatus, the method comprising:

[0022] The field time slot control unit generates a field time slot indication signal based on the field time slot value, and the first logic operation unit performs logic operations on the bit clock signal and the field time slot indication signal to obtain the first control signal.

[0023] The switching module is controlled to operate based on the first control signal.

[0024] In one or more embodiments of the present invention, the step of performing logical operations on the bit clock signal and the field time slot indication signal through the first logic operation unit to obtain the first control signal includes:

[0025] The bit clock signal is inverted by a logic NOT gate to generate a bit clock inverted signal, and the bit clock inverted signal is delayed by a delay unit to obtain a bit slot indication signal.

[0026] The first control signal is obtained by performing an AND logic judgment on the bit slot indication signal and the field slot indication signal through the first logic operation unit.

[0027] In one or more embodiments of the present invention, the method further includes:

[0028] The word bit flag control unit generates a valid word length indication signal based on the word length indication value and the bit clock signal;

[0029] The second control signal is obtained by performing an OR logic judgment on the first control signal and the effective word length indication signal through the second logic operation unit.

[0030] The second control signal controls the operation of the switch module.

[0031] Compared with the prior art, the audio analog-to-digital converter chip array data time-division output implementation device and method of the present invention obtains a bit time slot indication signal by inverting and delaying the bit clock signal, and obtains a first control signal by performing AND logic operation on the bit time slot indication signal and the field time slot indication signal through a logic AND gate. This method reduces the effective range of the output data of the analog-to-digital converter chip array from one bit time slot (equal to one bit clock cycle) so that there is a high impedance state protection range at the junction of two adjacent field time slots. Since no chip will drive this high configuration protection range, there will be no multi-drive conflict problem at the junction of two adjacent field time slots. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1a This is a diagram illustrating an existing multi-chip time-division multiplexing audio ADC chip array integration method.

[0034] Figure 1b This is a diagram of a serial relay-type audio ADC chip array integration method in the prior art;

[0035] Figure 2 This is a schematic diagram of the ideal output of an ADC in a series relay-type audio ADC chip array integration method in the prior art;

[0036] Figure 3 This is a schematic diagram of the actual output of an ADC in a series relay-type audio ADC chip array integration method in the prior art;

[0037] Figure 4This is a schematic diagram of the structure of an audio analog-to-digital converter chip array data time-division output implementation device according to Embodiment 1 of the present invention;

[0038] Figure 5 This is a schematic diagram of the structure of an audio analog-to-digital converter chip array data time-division output implementation device according to Embodiment 1 of the present invention;

[0039] Figure 6 This is a timing diagram of an audio analog-to-digital converter chip array data time-division output implementation device according to Embodiment 1 of the present invention;

[0040] Figure 7 This is a unit output timing diagram of any analog-to-digital converter chip in an audio analog-to-digital converter chip array data time-division output implementation device according to Embodiment 1 of the present invention;

[0041] Figure 8 This is a schematic diagram of the structure of an audio analog-to-digital converter chip array data time-division output implementation device according to Embodiment 2 of the present invention;

[0042] Figure 9 This is a schematic diagram of the structure of an audio analog-to-digital converter chip array data time-division output implementation device according to Embodiment 2 of the present invention;

[0043] Figure 10 This is a timing diagram of an audio analog-to-digital converter chip array data time-division output implementation device according to Embodiment 2 of the present invention;

[0044] Figure 11 This is a unit output timing diagram of any analog-to-digital converter chip in an audio analog-to-digital converter chip array data time-division output implementation device according to Embodiment 2 of the present invention;

[0045] Figure 12 This is a flowchart of a method for implementing time-division output of audio analog-to-digital converter chip array data according to Embodiment 3 of the present invention;

[0046] Figure 13 This is a flowchart of a method for implementing time-division output of audio analog-to-digital converter chip array data according to Embodiment 3 of the present invention. Detailed Implementation

[0047] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0048] Example 1

[0049] like Figure 4 As shown, this embodiment provides a time-division multiplexing output device for an audio analog-to-digital converter (ADC) chip array. The device includes multiple parallel-connected audio ADC chips, Chip1 to ChipN. Each audio ADC chip includes a control module 1 and a switching module 2.

[0050] Control module 1 includes a field time slot control unit 11 and a first logic operation unit 12. The field time slot control unit 11 is used to generate a field time slot indication signal ADCDAT_wordslot_oe based on the field time slot value. The first logic operation unit 12 is used to perform logic operations on the bit clock signal BCLK and the field time slot indication signal ADCDAT_wordslot_oe to obtain a first control signal S1. The first control signal S1 is used to control the operation of switch module 2.

[0051] like Figure 5 As shown, in one embodiment, the first logic operation unit 12 includes a NOT gate, a delay unit, and an AND gate. Taking the audio analog-to-digital converter chip Chip1 as an example: the NOT gate is used to perform a logical inversion operation on the bit clock signal BCLK to generate the bit clock inversion signal invertBCLK. The delay unit is used to perform a delay operation on the bit clock inversion signal invertBCLK based on the delay configuration value to obtain the bit slot indication signal ADCDAT_bitslot_oe. The AND gate is used to perform an AND logical operation on the bit slot indication signal ADCDAT_bitslot_oe and the word slot indication signal ADCDAT_wordslot_oe to obtain the first control signal S1.

[0052] Furthermore, the delay time of the delay unit is greater than or equal to the maximum output data delay of the audio analog-to-digital converter (ADC) chips in the audio ADC chip array and less than 1 / 2 bit duration. It is understood that the output data delay of each chip in the audio ADC chip array may be the same or different. For example, the output data delay of ADC chip Chip1 is 10ns, and the output data delay of ADC chip Chip2 is 13ns. This embodiment controls the delay time of the delay unit to be greater than or equal to 13ns and less than 1 / 2 bit duration to avoid the problem of multiple drives occurring at the junction of two adjacent time slots in the output data of different ADC chips.

[0053] Furthermore, the field time slot control unit 11 includes a time slot counter, which is used to mark the current time slot position count value. Further, the time slot counter marks the current time slot position count value based on the left and right channel clock signals LRCK and a word length indication value, wherein the left and right channel clock signals LRCK are used to indicate the timing of data output by each analog-to-digital converter chip, and the word length indication value is used to indicate the word length corresponding to the analog-to-digital conversion result of the audio analog-to-digital converter chip. Optionally, when the number of chips in the analog-to-digital converter chip array is N, the current time slot position count value output by the time slot counter is sequentially 1 to N.

[0054] The field slot control unit 11 compares the current slot position count value with the field slot value to obtain the field slot indication signal ADCDAT_wordslot_oe. It can be understood that the field slot control unit 11 and the delay unit receive configuration information required for the ADC chip to operate from an external main control CPU (not shown). This configuration information includes the field slot value, word length indication value, and delay configuration value. It may also include other configuration information, such as output control signals, chip status control signals, clock control signals, reset control signals, and operational control signals required by the ADC data processing unit.

[0055] Furthermore, different delay configuration values ​​can be generated based on the chip's operating voltage. For example, the audio analog-to-digital converter (ADC) chip operates at 1.8V, so its delay configuration value is relatively large; the audio ADC chip operates at 3.3V, so its delay configuration value is relatively small. After the ADC chip powers on, the delay unit sets the delay time according to the configured delay configuration value, and the audio ADC chip operates according to the configured delay time. It is understood that each chip in the audio ADC chip array has the same configured delay configuration value.

[0056] Different chips are configured with different field time slot values. These field time slot values ​​indicate the corresponding time slot interval of the analog-to-digital converter (ADC) chip that the audio ADC chip array currently needs to drive for data output. For example, the field time slot value configured for ADC chip Chip1 is 1, and the field time slot value configured for ADC chip ChipN is N.

[0057] Furthermore, when the current time slot position count value is equal to the field time slot value, the field time slot indicator signal ADCDAT_wordslot_oe outputs a high level; conversely, when they are not equal, the field time slot indicator signal ADCDAT_wordslot_oe outputs a low level. The function of the field time slot indicator signal ADCDAT_wordslot_oe is to indicate the analog-to-digital converter chip that needs to drive the output data.

[0058] like Figure 5As shown, the switch module 2 can be a tri-state gate circuit. The tri-state gate circuit includes an enable control terminal, an input terminal, and an output terminal. Taking the tri-state gate circuit of the analog-to-digital converter chip Chip1 as an example, the input terminal is used to receive the input signal ADCDAT1, the output terminal is used to send the input signal ADCDAT1, and the enable control terminal is used to control the opening or closing of the tri-state gate circuit based on the first control signal S1. The input signal ADCDAT1 is the analog-to-digital conversion result of the audio analog-to-digital converter chip Chip1.

[0059] In an optional implementation, the enable control terminal receives a first control signal S1. When the first control signal S1 is high, the output terminal of the tri-state gate circuit outputs the analog-to-digital conversion result of the audio analog-to-digital converter chip, that is, the corresponding analog-to-digital converter chip drives the output data; when the first control signal S1 is low, the output terminal of the tri-state gate circuit outputs a high-impedance state, that is, the corresponding analog-to-digital converter chip drives the output high-impedance state.

[0060] like Figure 6 As shown, this embodiment avoids the problem of multiple drives occurring at the junction of two adjacent word slots in the output data of different analog-to-digital converter chips. The effective range of the analog-to-digital conversion results ADCDAT1 to ADCDATN of the analog-to-digital converter chip is changed from one bit slot (equal to one bit clock BCLK cycle) to half a bit slot.

[0061] like Figure 6 As shown, taking analog-to-digital converter (ADC) chips Chip1 and Chip2 with a sampling bit width of 16 bits as examples, by inverting and delaying the bit clock signal BCLK, and then performing an AND operation with the field slot indication signal ADCDAT_wordslot_oe, there is a high-impedance state interval between the output data corresponding to each bit of ADC chip Chip1, and there is a high-impedance state protection interval of half a bit slot between the output data C1D0 corresponding to the 15th bit of ADC chip Chip1 and the output data C2D15 corresponding to the 0th bit of ADC chip Chip2. Since no ADC chip will drive this high-impedance state protection interval, there will be no multi-drive conflict between C1D0 and C2D15.

[0062] like Figure 7As shown, when the current time slot position count is N, and the field time slot value configured in chip ChipN is also N, the field time slot indicator signal ADCDAT_wordslot_oe outputs a high level. When the first control signal S1 is high, the output of the tri-state gate circuit sends the analog-to-digital conversion result of the audio analog-to-digital converter chip ChipM, that is, the audio analog-to-digital converter chip array uses the analog-to-digital conversion result of chip ChipN as the output data ADCDAT; when the first control signal S1 is low, the output of the tri-state gate circuit outputs a high-impedance state, and the output data ADCDAT of the audio analog-to-digital converter chip array is in an idle state.

[0063] Example 2

[0064] like Figure 8 As shown, this embodiment provides a time-division multiplexing output device for an audio analog-to-digital converter (ADC) chip array. The device includes multiple parallel-connected audio ADC chips, Chip1 to ChipN. Each audio ADC chip includes a control module 1 and a switching module 2.

[0065] The control module 1 includes a field time slot control unit 11, a first logic operation unit 12, a word bit flag control unit 13, and a second logic operation unit 14.

[0066] The field slot control unit 11 generates a field slot indication signal ADCDAT_wordslot_oe based on the field slot value. The first logic operation unit 12 performs a logic operation on the bit clock signal BCLK and the field slot indication signal ADCDAT_wordslot_oe to obtain the first control signal S1. The word bit flag control unit 13 generates a valid word length indication signal ADCDAT_wordbit_flag based on the word length indication value and the bit clock signal BCLK. The second logic operation unit 14 is connected to the first logic operation unit 12 and the word bit flag control unit 13. The second logic operation unit 14 performs an OR logic judgment on the first control signal S1 and the valid word length indication signal ADCDAT_wordbit_flag to obtain the second control signal S2. The second control signal S2 is used to control the operation of the switch module 2.

[0067] like Figure 9As shown, in one embodiment, the first logic operation unit 12 includes a NOT gate, a delay unit, and an AND gate. Taking the audio analog-to-digital converter chip Chip1 as an example: the NOT gate is used to perform a logical inversion operation on the bit clock signal BCLK to generate the bit clock inversion signal invertBCLK. The delay unit is used to perform a delay operation on the bit clock inversion signal invertBCLK based on the delay configuration value to obtain the bit slot indication signal ADCDAT_bitslot_oe. The AND gate is used to perform an AND logical operation on the bit slot indication signal ADCDAT_bitslot_oe and the word slot indication signal ADCDAT_wordslot_oe to obtain the first control signal S1.

[0068] Furthermore, the delay time of the delay unit is greater than or equal to the maximum output data delay of the audio analog-to-digital converter (ADC) chips in the audio ADC chip array and less than 1 / 2 bit duration. It is understood that the output data delay of each chip in the audio ADC chip array may be the same or different. For example, the output data delay of ADC chip Chip1 is 10ns, and the output data delay of ADC chip Chip2 is 13ns. This embodiment controls the delay time of the delay unit to be greater than or equal to 13ns and less than 1 / 2 bit duration to avoid the problem of multiple drives occurring at the junction of two adjacent time slots in the output data of different ADC chips.

[0069] Furthermore, the field time slot control unit 11 includes a time slot counter, which is used to mark the current time slot position count value. Further, the time slot counter marks the current time slot position count value based on the left and right channel clock signals LRCK and a word length indication value, wherein the left and right channel clock signals LRCK are used to indicate the timing of data output by each analog-to-digital converter chip, and the word length indication value is used to indicate the word length corresponding to the analog-to-digital conversion result of the audio analog-to-digital converter chip. Optionally, when the number of chips in the analog-to-digital converter chip array is N, the current time slot position count value output by the time slot counter is sequentially 1 to N.

[0070] The field slot control unit 11 compares the current slot position count value with the field slot value to obtain the field slot indication signal ADCDAT_wordslot_oe. It can be understood that the field slot control unit 11 receives configuration information required for the ADC chip to operate from an external main control CPU (not shown). This configuration information includes the field slot value and word length indication value, and may also include other configuration information such as output control signals, chip status control signals, clock control signals, reset control signals, and operational control signals required by the ADC data processing unit.

[0071] Furthermore, different delay configuration values ​​can be generated based on the chip's operating voltage. For example, the audio analog-to-digital converter (ADC) chip operates at 1.8V, so its delay configuration value is relatively large; the audio ADC chip operates at 3.3V, so its delay configuration value is relatively small. After the ADC chip powers on, the delay unit sets the delay time according to the configured delay configuration value, and the audio ADC chip operates according to the configured delay time. It is understood that each chip in the audio ADC chip array has the same configured delay configuration value.

[0072] Different chips are configured with different field time slot values, which indicate the corresponding time slot interval of the analog-to-digital converter (ADC) chip that the audio ADC chip array needs to drive for data output. For example, the field time slot value configured for ADC chip Chip1 is 1, and the field time slot value configured for ADC chip ChipN is N.

[0073] Furthermore, when the current time slot position count value is equal to the field time slot value, the field time slot indicator signal ADCDAT_wordslot_oe outputs a high level; otherwise, the field time slot indicator signal ADCDAT_wordslot_oe outputs a low level.

[0074] The word bit flag control unit 13 includes a bit counter used to mark the current field slot bit position count value. The word bit flag control unit 13 outputs a valid word length indication signal ADCDAT_wordbit_flag based on the current field slot bit position count value and the bit clock signal BCLK.

[0075] like Figure 9 As shown, the switch module 2 can be a tri-state gate circuit. The tri-state gate circuit includes an enable control terminal, an input terminal, and an output terminal. Taking the tri-state gate circuit of the analog-to-digital converter chip Chip1 as an example, the input terminal is used to receive the input signal ADCDAT1, the output terminal is used to send the input signal ADCDAT1, and the enable control terminal is used to control the opening or closing of the tri-state gate circuit based on the second control signal S2. The input signal ADCDAT1 is the analog-to-digital conversion result of the audio analog-to-digital converter chip Chip1.

[0076] In an optional implementation, the enable control terminal receives the second control signal S2. When the second control signal S2 is high, the output terminal of the tri-state gate circuit outputs the analog-to-digital conversion result of the audio analog-to-digital converter chip; when the second control signal S2 is low, the output terminal of the tri-state gate circuit outputs a high-impedance state.

[0077] like Figure 10As shown, the effective range of the analog-to-digital conversion result at the junction of two adjacent word slots of different analog-to-digital conversion chips is changed from one bit slot (equal to one bit clock BCLK cycle) to half a bit slot, thus avoiding the problem of multiple drives at the junction of two adjacent word slots of different analog-to-digital conversion chips.

[0078] like Figure 10 As shown, taking analog-to-digital converter (ADC) chips Chip1 and Chip2 with a sampling bit width of 16 bits as examples, WordLen in the figure represents the sampling word length. For example, the sampling word length WordLen of a 24-bit ADC is equal to 24. By inverting and delaying the bit clock signal BCLK, and performing an AND operation with the field slot indication signal ADCDAT_wordslot_oe, the first control signal S1 is obtained. Then, the first control signal S1 is ORed with the effective word length indication signal ADCDAT_wordbit_flag to obtain the second control signal S2 to control the tri-state gate circuit. There is a high-impedance state protection interval of half a bit slot between the output data C1D0 corresponding to the 15th bit of ADC chip Chip1 and the output data C2D15 corresponding to the 0th bit of ADC chip Chip2. Since no ADC chip will drive this high-impedance state protection interval, there will be no multi-drive conflict between C1D0 and C2D15.

[0079] When the current time slot position count is N, and the field time slot value configured in the ChipM is also N, the field time slot indicator signal ADCDAT_wordslot_oe outputs a high level. For example... Figure 10 As shown, when the bit counter counts the current field slot bit position to 0, the effective word length indicator signal ADCDAT_wordbit_flag jumps to a high level at the rising edge of the bit clock signal BCLK corresponding to the current field slot bit position count being 0; when the bit counter counts the current field slot bit position to the word length indicator value minus 1, the effective word length indicator signal ADCDAT_wordbit_flag jumps to a low level at the falling edge of the bit clock signal BCLK corresponding to the current field slot bit position count being minus 1. For example, for an analog-to-digital converter chip with a sampling bit width of 16 bits, when the bit counter counts the current field slot bit position to 15 bits, the effective word length indicator signal ADCDAT_wordbit_flag jumps to a low level at the falling edge of the bit clock signal BCLK corresponding to the current field slot bit position count being 15 bits.

[0080] like Figure 11As shown, when the second control signal S2 is high, the output of the tri-state gate circuit sends the analog-to-digital conversion result of the audio analog-to-digital converter chip ChipM, that is, the audio analog-to-digital converter chip array uses the analog-to-digital conversion result of the chip ChipM as the output data ADCDAT; when the second control signal S2 is low, the output of the tri-state gate circuit outputs a high-impedance state, and the output data ADCDAT of the audio analog-to-digital converter chip array is in an idle state.

[0081] In summary, since there is no multi-drive problem between transmission bits within the same chip, the audio analog-to-digital converter chip array data time-division output implementation device provided in this embodiment can achieve a high-impedance state protection interval between transmission bits at the junction of different chips, which can avoid the multi-drive problem at the junction of two adjacent word slots of the output data of different chips.

[0082] Example 3

[0083] like Figure 12 As shown, the present invention also provides a method for implementing time-division multiplexing of audio analog-to-digital converter chip array data, the method comprising:

[0084] S101, the field time slot control unit 11 generates a field time slot indication signal ADCDAT_wordslot_oe based on the field time slot value, and the first logic operation unit 12 performs logic operation on the bit clock signal BCLK and the field time slot indication signal ADCDAT_wordslot_oe to obtain the first control signal S1.

[0085] S102, based on the first control signal S1, control the operation of the switch module 2.

[0086] Furthermore, the first control signal S1 is obtained by performing logical operations on the bit clock signal BCLK and the field slot indication signal ADCDAT_wordslot_oe through the first logic operation unit 12, including:

[0087] The bit clock signal BCLK is inverted by a logic NOT gate to generate the bit clock inversion signal invertBCLK. The bit clock inversion signal invertBCLK is then delayed by a delay unit to obtain the bit slot indication signal ADCDAT_bitslot_oe.

[0088] The field slot indication signal ADCDAT_wordslot_oe is obtained by the field slot control unit 11 based on the field slot value and the current slot position count value.

[0089] The first control signal S1 is obtained by performing an AND logic judgment on the bit slot indication signal ADCDAT_bitslot_oe and the field slot indication signal ADCDAT_wordslot_oe through the first logic operation unit 12.

[0090] like Figure 13 As shown, in an optional embodiment, the method for implementing time-division multiplexing of audio analog-to-digital converter chip array data further includes:

[0091] The word bit flag control unit 13 generates a valid word length indicator signal ADCDAT_wordbit_flag based on the word length indicator value and the bit clock signal BCLK.

[0092] The second control signal S2 is obtained by performing an OR logic judgment on the first control signal S1 and the effective word length indication signal ADCDAT_wordbit_flag through the second logic operation unit 14.

[0093] The second control signal S2 controls the operation of the switch module 2.

[0094] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0095] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0096] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0097] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0098] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0099] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An audio digital-to-analog conversion chip array data time-sharing output implementation device, characterized in that, The implementation device includes multiple audio analog-to-digital converter chips connected in parallel. Each audio analog-to-digital converter chip includes a control module and a switching module. The switching module is a three-state gate circuit. The control module includes a field time slot control unit and a first logic operation unit. The field time slot control unit is used to generate a field time slot indication signal based on the field time slot value. The first logic operation unit is used to perform logical operations on the bit clock signal and the field time slot indication signal to obtain a first control signal. The first control signal is used to control the operation of the switch module. The first logic operation unit includes a NOT gate, a delay unit, and an AND gate; The NOT gate is used to perform a logical inversion operation on the bit clock signal to generate a bit clock inversion signal, and the delay unit is used to perform a delay operation on the bit clock inversion signal to obtain a bit slot indication signal. The AND gate is used to perform an AND logic operation on the bit time slot indication signal and the field time slot indication signal to obtain the first control signal.

2. The apparatus of claim 1, wherein, The delay time of the delay unit is greater than or equal to the delay of the largest audio analog-to-digital converter chip output data in the audio analog-to-digital converter chip array and less than 1 / 2 bit duration.

3. The audio analog-to-digital converter chip array data time-division output implementation device according to claim 1, characterized in that, The field time slot control unit includes a time slot counter, which is used to mark the current time slot position count value. The field time slot control unit is used to compare the current time slot position count value with the field time slot value to obtain a field time slot indication signal.

4. The audio analog-to-digital converter chip array data time-division output implementation device according to claim 1, characterized in that, The control module also includes a word bit flag control unit and a second logic operation unit; The word bit flag control unit is used to generate a valid word length indication signal based on the word length indication value and the bit clock signal; The second logic operation unit is connected to the first logic operation unit and the word bit flag control unit. The second logic operation unit is used to perform an OR logic judgment on the first control signal and the effective word length indication signal to obtain the second control signal. The second control signal is used to control the operation of the switch module.

5. The audio analog-to-digital converter chip array data time-division output implementation device according to claim 4, characterized in that, The word bit flag control unit includes a bit counter, which is used to mark the current field slot bit position count value; the word bit flag control unit is used to output a valid word length indication signal based on the marked current field slot bit position count value and the bit clock signal.

6. The audio analog-to-digital converter chip array data time-division output implementation device according to claim 1 or 4, characterized in that, The tri-state gate circuit includes an enable control terminal, an input terminal, and an output terminal; the input terminal is used to receive input signals, the output terminal is used to send input signals, and the enable control terminal is used to control the opening or closing of the tri-state gate circuit based on a first control signal or a second control signal.

7. A method for implementing time-division multiplexing of audio analog-to-digital converter (ADC) chip array data, based on the ADC chip array data time-division multiplexing implementation apparatus as described in any one of claims 1 to 6, characterized in that, The method includes: The field time slot control unit generates a field time slot indication signal based on the field time slot value, and the first logic operation unit performs logic operations on the bit clock signal and the field time slot indication signal to obtain the first control signal. The switching module is controlled to operate based on the first control signal.

8. The method for implementing time-division multiplexing of audio analog-to-digital converter chip array data according to claim 7, characterized in that, The step of performing logical operations on the bit clock signal and the field time slot indication signal through the first logic operation unit to obtain the first control signal includes: The bit clock signal is inverted by a logic NOT gate to generate a bit clock inverted signal, and the bit clock inverted signal is delayed by a delay unit to obtain a bit slot indication signal. The first control signal is obtained by performing an AND logic judgment on the bit slot indication signal and the field slot indication signal through the first logic operation unit.

9. The method for implementing time-division multiplexing of audio analog-to-digital converter chip array data according to claim 7, characterized in that, The method further includes: The word bit flag control unit generates a valid word length indication signal based on the word length indication value and the bit clock signal; The second control signal is obtained by performing an OR logic judgment on the first control signal and the effective word length indication signal through the second logic operation unit. The second control signal controls the operation of the switch module.

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