MCU chip based on RISC-V kernel control and system thereof

Abstract

This invention discloses a RISC-V core-controlled MCU chip and system thereof, relating to the field of embedded systems. It addresses the shortcomings of existing RISC-V core-controlled MCU chips and systems, including poor compatibility, lack of hardware support, and poor security and power consumption. The invention comprises a RISC-V core control module, a compatibility enhancement module, a memory management module, a clock management module, a hardware support extension module, a multi-core processing module, a power optimization module, and a security enhancement module. The invention achieves compatibility and interoperability with external devices and sensors through the compatibility enhancement module and peripheral control system; improves memory utilization and access efficiency through memory virtualization; enhances system data security and protection capabilities through the security enhancement module; and reduces system energy consumption and extends battery life by dynamically adjusting the clock frequencies of the processor and peripherals through a machine learning-based power management algorithm and an adaptive power management model.

Description

Technical Field

[0001] This invention relates to the field of embedded systems, and more specifically to an MCU chip and system based on a RISC-V core control. Background Technology

[0002] In today's rapidly evolving digital age, the Internet of Things (IoT) and embedded systems have become key technologies across various industries. With the expanding applications of smart devices and sensors, the demand for low-power, high-performance microcontroller units (MCUs) is growing. Simultaneously, open instruction set architectures are gaining attention, with the aim of fostering innovation and reducing costs through open design. It is against this backdrop that MCU chips and systems based on the RISC-V core have begun to attract attention.

[0003] Currently, traditional closed-source architectures dominate the embedded field; for example, ARM-based MCUs are widely used in various devices. However, these closed-source architectures often require expensive licensing fees, limiting innovation and customization. Therefore, the open instruction set architecture RISC-V is emerging as a potential alternative. However, the RISC-V ecosystem is currently relatively small, and compatibility issues, unstable software support, lack of hardware support, and security challenges pose significant obstacles to its development.

[0004] MCU chips and systems based on the RISC-V core have several drawbacks. First, compatibility issues limit the direct portability of existing software and tools to the RISC-V platform, increasing development and maintenance costs. Second, due to a lack of hardware support, some specific peripherals and expansion modules may not be compatible. Third, security challenges also need to be addressed to ensure the system's security and reliability under an open instruction set architecture. Furthermore, compared to some mature closed-source architectures, RISC-V faces challenges in power consumption optimization and requires further optimization to meet the needs of low-power devices.

[0005] Therefore, in order to address the shortcomings of existing RISC-V core-controlled MCU chips and systems, such as poor compatibility, lack of hardware support, poor security, and poor power consumption, this invention discloses an RISC-V core-controlled MCU chip and system. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention discloses a RISC-V core-controlled MCU chip and its system. This invention introduces a compatibility enhancement module and a peripheral control system to achieve compatibility and interoperability with external devices and sensors. A standardized universal interface method enables seamless adaptation of the MCU chip to various peripherals and sensors. Hardware support expansion modules and on-chip system integration methods integrate peripheral and communication interfaces, improving the chip's scalability and flexibility. Simultaneously, a storage virtualization method dynamically adjusts the data distribution of flash memory and DRAM, performing intelligent data migration based on memory access patterns and data frequency, improving memory utilization and access efficiency. Furthermore, a security enhancement module is introduced, using a hardware encryption engine and secure boot mechanism to improve system data security and protection capabilities, protecting user data from unauthorized access and tampering. An adaptive power management model dynamically adjusts power management strategies based on chip workload and environmental conditions, achieving power optimization, reducing system energy consumption, and extending battery life. Additionally, a machine learning-based power management algorithm dynamically adjusts the clock frequencies of the processor and peripherals, further reducing power consumption and improving system energy efficiency.

[0007] To achieve the above-mentioned technical effects, the present invention adopts the following technical solution:

[0008] A RISC-V core-controlled MCU chip system, wherein the system includes:

[0009] A RISC-V core control module, which improves instruction throughput and processor performance through superscalar architecture and reduced instruction set;

[0010] The compatibility enhancement module enables compatibility and interoperability with external devices and sensors through a peripheral control system. The peripheral control system achieves seamless adaptation of the MCU chip to various peripherals and sensors through a universal interface standardization method.

[0011] The memory management module dynamically adjusts the data distribution of flash memory and dynamic random access memory (DRAM) through a storage virtualization method; the storage virtualization method uses a deep learning-based memory management algorithm to perform intelligent data migration based on memory access patterns and data popularity.

[0012] A clock management module that dynamically adjusts the clock frequency of the processor and peripherals using a power management algorithm based on machine learning;

[0013] The hardware support expansion module integrates peripheral interfaces and communication interfaces through a system-on-a-chip integration method.

[0014] A multi-core processing module, which improves the system's concurrent processing capability and operating efficiency through parallel computing and shared resource management methods;

[0015] A power optimization module, which dynamically adjusts the power management strategy based on the chip's workload and environmental conditions through an adaptive power management model;

[0016] A security enhancement module improves the system's data security and protection capabilities through a hardware encryption engine and a secure boot mechanism.

[0017] Specifically, the outputs of the RISC-V core control module and the memory management module are connected to the input of the multi-core processing module; the output of the compatibility enhancement module is connected to the input of the hardware support expansion module; the output of the clock management module is connected to the inputs of the RISC-V core control module, the compatibility enhancement module, and the hardware support expansion module; the output of the multi-core processing module is connected to the input of the power optimization module; and the output of the security enhancement module is connected to the inputs of the RISC-V core control module, the compatibility enhancement module, the memory management module, and the multi-core processing module.

[0018] As a further technical solution of the present invention, the RISC-V kernel control module includes a superscalar architecture unit, a reduced instruction set unit, a data path optimization unit, and a data cache unit. The superscalar architecture unit achieves parallel processing through an out-of-order execution method, which improves instruction throughput through a data and control dependency model between instructions. The control dependency model improves instruction execution parallelism through a physical register renaming method. The reduced instruction set unit reduces instruction storage and transmission costs by compressing instruction encoding and decoding formats. The data path optimization unit processes different instructions in parallel through a multi-stage pipeline design method. The data cache unit includes a consistency subunit and a prefetch subunit. The consistency subunit ensures data consistency between multiple cache levels through a cache consistency protocol. The prefetch subunit improves data access efficiency through a data prefetch method, which preloads data into the cache through program memory access and memory access history analysis.

[0019] As a further technical solution of the present invention, the peripheral control system includes a general peripheral interface module, a timing management module, a serial communication interface module, an external memory interface module, and an analog signal interface module; the general peripheral interface module includes an input / output interface unit and a peripheral controller unit; the input / output interface unit achieves flexible connection to external devices through hardware pin multiplexing; the peripheral controller unit achieves compatibility and interoperability with different external devices through integrated peripheral interface protocols; the timing management module includes a timing control unit, a pulse width modulation unit, and a counter unit; the timing control unit achieves control and management of external devices through a timer circuit and a clock source; the pulse width modulation unit achieves pulse width modulation control of external devices through a duty cycle controller; the counter unit achieves counting and measurement of external events through a clock synchronization mechanism; the serial communication interface module uses a universal asynchronous transceiver (UART), a serial peripheral interface (SPI), and a serial communication bus. The I2C interface ensures reliable communication with external devices. The external memory interface module includes a flash memory interface unit and a memory card interface unit. The flash memory interface unit implements read and write operations on the external flash memory through an address decoding circuit and a command control circuit. The memory card interface unit implements read and write operations on the external memory card through a command control circuit and a clock generator. The analog signal interface module includes an analog input unit, an analog output unit, and an analog control unit. The analog input unit converts external analog signals into digital signals through an analog-to-digital converter and a filter, and transmits them to the MCU for processing. The analog output unit converts the digital signals processed by the MCU into analog signals through a digital-to-analog converter and outputs them to external analog devices. The analog control unit controls the working state of the analog signal input and output units through a comparator, a phase-locked loop, a programmable analog front-end, and an online calibration circuit, and realizes the functions of analog signal acquisition, conversion, and control.

[0020] As a further technical solution of the present invention, the deep learning-based memory management algorithm calculates the memory's popularity value using a data popularity calculation formula to assess the memory's importance; the formula expression for the data popularity calculation formula is:

[0021]

[0022] In formula (1), T represents the heat value of the l-th memory block in the j-th module, used to assess the importance of memory l; σ represents the weight of the k-th data type in the j-th module, used to consider the impact of different data types on memory heat; W represents the weight of the s-th data type in the l-th memory block, used to consider the impact of different data types on memory heat; the memory heat prediction formula predicts the future heat of memory; the memory heat prediction formula maps the result to a probability value between 0 and 1 by linearly weighting and summing the correlation between memory blocks; the formula expression of the memory heat prediction formula is:

[0023]

[0024] In formula (2), P represents the predicted heat value of the l-th memory block in the j-th module in the next time period; it is used to represent the future heat status of the memory; ω represents the weight between the l-th memory block and the α-th memory block in the j-th module; it is used to calculate the correlation between the memory blocks; η represents the bias of the l-th memory block in the j-th module, used to adjust the baseline value of the memory heat; the data migration decision formula determines whether the memory needs to be migrated; the data migration decision formula determines whether the memory needs to be migrated by comparing the predicted heat value of the memory with the heat threshold; the formula expression of the data migration decision formula is:

[0025]

[0026] In formula (3), Y represents whether the l-th memory in the j-th module needs to be migrated, which is used to determine whether the memory needs to be migrated; Q represents the heat threshold; b represents the memory weight, which is used to calculate the correlation between the memory.

[0027] As a further technical solution of the present invention, the power management algorithm based on machine learning predicts future load change trends through a load change prediction function; the formula expression of the load change prediction function is:

[0028]

[0029] In formula (4), M represents the predicted value of the future load change trend; N is the intercept, used to represent the benchmark of the load change trend when there are no characteristic parameters; d is the characteristic coefficient, used to measure the influence of each characteristic parameter on the load change trend; t represents the characteristic parameter used for prediction; ∈ represents the error term, used to measure the difference between the actual observed value and the predicted value; the processor clock frequency is dynamically adjusted by the processor clock frequency dynamic adjustment formula; the clock frequency dynamic adjustment formula adjusts the processor clock frequency through the PID controller according to the error between the current load and the target load; the formula expression of the clock frequency dynamic adjustment formula is:

[0030]

[0031] In formula (5), D represents the controller output; u represents the error between the current load and the target load, used to indicate the processor's load status; Indicates processor load; n represents peripheral load; K p K i and K d These represent the proportional, integral, and derivative coefficients of the PID controller, used to adjust the controller's response speed and stability. The peripheral clock frequency is dynamically adjusted using a formula. This formula adjusts the peripheral clock frequency based on the system's load state and target power consumption, using a fuzzy controller. The formula expression for this dynamic adjustment formula is:

[0032]

[0033] In formula (6), R represents the membership degree of input x with respect to the y-th fuzzy rule, which is used to determine the weight of a specific rule; δ and S represent the upper and lower bounds of the membership function of the m-th feature of the y-th rule, which are used to define the rule base of the fuzzy controller.

[0034] As a further technical solution of the present invention, the working steps of the on-chip system integration method in an MCU chip system based on RISC-V core control are as follows:

[0035] Step 1: Functional module analysis;

[0036] Functional analysis of peripheral interfaces and communication interfaces is performed using the hardware description language VHDL, and electrical characteristics and timing aspects are modeled and simulated.

[0037] Step 2: Interface Protocol Design;

[0038] The implementation methods of the physical layer, data link layer, and transport layer of the protocol are determined by the communication protocol specification;

[0039] Step 3: Interface controller design;

[0040] An interface controller circuit is designed using digital logic design methods. The interface controller circuit includes modules for generating, transmitting, and receiving clock, data, and control signals.

[0041] Step 4: Data Cache Management;

[0042] Data caching is managed using a first-in-first-out buffer and a data storage device;

[0043] Step 5: Timing optimization;

[0044] Timing optimization of the entire chip system is performed using timing analysis and clock division methods.

[0045] Step Six: Embedded Software Support;

[0046] Provide an application interface for the interface controller through an embedded software driver;

[0047] Step 7: Verification Test;

[0048] We ensure that the performance and stability of the hardware-supported expansion modules meet the design requirements through functional simulation, timing analysis, synthesis, placement and routing, and physical verification.

[0049] As a further technical solution of the present invention, the adaptive power management model includes a load detection module, an environment detection module, a strategy generation module, and a power control module; the load detection module includes a processor load detection unit and a peripheral device load detection unit; the processor load detection unit detects the processor load in real time using hardware performance counter technology; the peripheral device load detection unit detects the peripheral device load through an interrupt controller and peripheral interface; the environment detection module detects chip temperature, humidity, and other environmental parameters in real time using sensors and analog signal acquisition methods; the strategy generation module includes a dynamic power consumption management unit and a dynamic voltage management unit; based on the information output by the load detection module, the dynamic power consumption management unit calculates the current chip power consumption using statistical analysis methods; based on the output information of the environment detection module and the power consumption management strategy, the dynamic voltage management unit calculates the supply voltage using a voltage regulator and feedback control methods; the power control module controls the output voltage of the power converter using a pulse width modulator.

[0050] As a further technical solution of the present invention, the security enhancement module implements data encryption and decryption functions through a hardware encryption engine; the hardware encryption engine includes a symmetric encryption unit and an asymmetric encryption unit; the symmetric encryption unit encrypts and decrypts data using a symmetric encryption algorithm; the asymmetric encryption unit implements secure data transmission and identity authentication through a public key encryption and private key decryption mechanism; the hardware encryption engine enhances the security of symmetric and asymmetric encryption algorithms through a physical non-rechargeable battery; the physical non-rechargeable battery generates uncopyable physical characteristics to generate keys through transistor parameter variations and circuit noise differences; the security enhancement module ensures the security of the system during startup through a secure boot mechanism; the secure boot mechanism includes a boot verification unit and a secure boot control unit; the boot verification unit ensures that only authorized firmware or software can be loaded and executed through integrity verification and digital signatures; the secure boot control unit manages security policies during startup through a hardware root trust component; the hardware root trust component ensures the security of the system startup process, the protection of stored data, and that critical operations are performed in a secure execution environment through digital signatures, hash verification, and hardware virtualization methods.

[0051] As a further technical solution of the present invention, an MCU chip based on RISC-V core control includes:

[0052] The RISC-V core is used to execute the instruction set and control the operation of the entire system;

[0053] On-chip memory is used to store programs, data, and intermediate results; the on-chip memory includes high-speed static random access memory and flash memory integrated on the chip;

[0054] A general-purpose interface module is used to provide a standardized communication interface with external devices and sensors; the general-purpose interface module includes at least a Universal Serial Bus (I2C / SPI) and a Universal Asynchronous Receiver / Transmitter (UART) interface.

[0055] A peripheral control module is used to control and manage the operation of external devices; the peripheral control module manages the operation of peripherals through control logic circuits and registers.

[0056] An exception handling circuit is used to monitor and handle hardware and software exceptions; the exception handling circuit includes an exception detection circuit, an exception handling unit, and an exception vector table.

[0057] A security protection module is used to provide data encryption and decryption functions; the security protection module improves the security of data transmission and storage through a hardware encryption engine;

[0058] A dynamic voltage regulation circuit is used to optimize power consumption and extend battery life; the dynamic voltage regulation circuit adjusts the chip's operating voltage according to system load requirements through a voltage regulator and a feedback control circuit.

[0059] The peripheral interface module provides an interface for interacting with external devices; the peripheral interface module integrates physical interfaces and control logic through a system-on-a-chip integration method.

[0060] A secure boot module is used to ensure the security and trustworthiness of the system boot process; the secure boot module includes a secure boot ROM, a digital signature verification unit, and a key management unit.

[0061] Positive and beneficial effects:

[0062] This invention introduces a compatibility enhancement module and a peripheral control system to achieve compatibility and interoperability with external devices and sensors. A standardized universal interface method enables seamless adaptation of the MCU chip to various peripherals and sensors. Hardware support expansion modules and on-chip system integration methods integrate peripheral and communication interfaces, improving chip scalability and flexibility. Simultaneously, a storage virtualization method dynamically adjusts the data distribution of flash memory and DRAM, performing intelligent data migration based on memory access patterns and data frequency, improving memory utilization and access efficiency. Furthermore, a security enhancement module is introduced, using a hardware encryption engine and secure boot mechanism to improve system data security and protection capabilities, safeguarding user data from unauthorized access and tampering. An adaptive power management model dynamically adjusts power management strategies based on chip workload and environmental conditions, optimizing power consumption, reducing system energy consumption, and extending battery life. Additionally, a machine learning-based power management algorithm dynamically adjusts the clock frequencies of the processor and peripherals, further reducing power consumption and improving system energy efficiency. Attached image description:

[0063] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0064] Figure 1 This is a framework diagram of an MCU chip system based on RISC-V core control according to the present invention;

[0065] Figure 2 This is a schematic diagram illustrating the principle of the adaptive power management model of the present invention;

[0066] Figure 3This is a schematic diagram illustrating the process steps of the deep learning-based memory management algorithm of the present invention.

[0067] Figure 4 This is a schematic diagram of the peripheral control system of the present invention.

[0068] Figure 5 This is a flowchart illustrating the workflow steps of the on-chip system integration method of the present invention. Detailed Implementation

[0069] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0070] like Figures 1-5 As shown, an MCU chip system based on a RISC-V core control includes:

[0071] A RISC-V core control module, which improves instruction throughput and processor performance through superscalar architecture and reduced instruction set;

[0072] The compatibility enhancement module enables compatibility and interoperability with external devices and sensors through a peripheral control system. The peripheral control system achieves seamless adaptation of the MCU chip to various peripherals and sensors through a universal interface standardization method.

[0073] The memory management module dynamically adjusts the data distribution of flash memory and dynamic random access memory (DRAM) through a storage virtualization method; the storage virtualization method uses a deep learning-based memory management algorithm to perform intelligent data migration based on memory access patterns and data popularity.

[0074] A clock management module that dynamically adjusts the clock frequency of the processor and peripherals using a power management algorithm based on machine learning;

[0075] The hardware support expansion module integrates peripheral interfaces and communication interfaces through a system-on-a-chip integration method.

[0076] A multi-core processing module, which improves the system's concurrent processing capability and operating efficiency through parallel computing and shared resource management methods;

[0077] A power optimization module, which dynamically adjusts the power management strategy based on the chip's workload and environmental conditions through an adaptive power management model;

[0078] A security enhancement module improves the system's data security and protection capabilities through a hardware encryption engine and a secure boot mechanism.

[0079] Specifically, the outputs of the RISC-V core control module and the memory management module are connected to the input of the multi-core processing module; the output of the compatibility enhancement module is connected to the input of the hardware support expansion module; the output of the clock management module is connected to the inputs of the RISC-V core control module, the compatibility enhancement module, and the hardware support expansion module; the output of the multi-core processing module is connected to the input of the power optimization module; and the output of the security enhancement module is connected to the inputs of the RISC-V core control module, the compatibility enhancement module, the memory management module, and the multi-core processing module.

[0080] In the above embodiments, the RISC-V kernel control module includes a superscalar architecture unit, a reduced instruction set unit, a data path optimization unit, and a data cache unit. The superscalar architecture unit achieves parallel processing through out-of-order execution, which improves instruction throughput through a data and control dependency model between instructions. The control dependency model improves instruction execution parallelism through physical register renaming. The reduced instruction set unit reduces instruction storage and transmission costs by compressing instruction encoding / decoding formats. The data path optimization unit processes different instructions in parallel through a multi-stage pipeline design. The data cache unit includes a consistency subunit and a prefetch subunit. The consistency subunit ensures data consistency between multiple cache levels through a cache consistency protocol. The prefetch subunit improves data access efficiency through a data prefetch method, which preloads data into the cache through program memory access and memory access history analysis.

[0081] In a specific embodiment, the RISC-V core control module supports the simultaneous execution of multiple instructions through a superscalar architecture unit, thereby improving processor throughput. The superscalar architecture unit breaks down multiple instructions into multiple micro-operations, executing these micro-operations in parallel to improve instruction execution efficiency. The reduced instruction set unit employs the RISC-V reduced instruction set, minimizing the number of instructions to improve processor efficiency. This reduced instruction set design saves processor logic and area, and makes the processor easier to implement and optimize. The data path optimization unit uses data path optimization techniques to improve processor performance by optimizing the data path. Data path optimization can reduce the length of the data path and lower the clock frequency, thereby improving performance and power efficiency. The data cache unit uses data caching technology to reduce the number of accesses to external memory by caching data internally on the chip. Data caching can improve processor performance, reduce system response time, and reduce power consumption.

[0082] In a RISC-V core-controlled MCU chip system, the processor boasts high performance and efficiency due to its superscalar architecture and reduced instruction set design, enabling rapid execution of various instructions. Furthermore, data path optimization and data caching techniques reduce power consumption and extend battery life. Secondly, internal data caching and data path optimization minimize external memory accesses, thereby improving stability and reliability. Simultaneously, the RISC-V core-controlled MCU chip system offers flexibility, allowing for customization and optimization to meet diverse application needs.

[0083] In the above embodiments, the peripheral control system includes a general peripheral interface module, a timing management module, a serial communication interface module, an external memory interface module, and an analog signal interface module. The general peripheral interface module includes an input / output interface unit and a peripheral controller unit. The input / output interface unit achieves flexible connection to external devices through hardware pin multiplexing. The peripheral controller unit achieves compatibility and interoperability with different external devices through integrated peripheral interface protocols. The timing management module includes a timing control unit, a pulse width modulation unit, and a counter unit. The timing control unit controls and manages external devices through a timer circuit and a clock source. The pulse width modulation unit controls the pulse width of external devices through a duty cycle controller. The counter unit counts and measures external events through a clock synchronization mechanism. The serial communication interface module uses a Universal Asynchronous Receiver / Transmitter (UART), a Serial Peripheral Interface (SPI), and a serial communication bus (I2). C ensures reliable communication with external devices; the external memory interface module includes a flash memory interface unit and a memory card interface unit; the flash memory interface unit realizes reading and writing to the external flash memory through an address decoding circuit and a command control circuit; the memory card interface unit realizes reading and writing to the external memory card through a command control circuit and a clock generator; the analog signal interface module includes an analog input unit, an analog output unit, and an analog control unit; the analog input unit converts external analog signals into digital signals through an analog-to-digital converter and a filter, and transmits them to the MCU for processing; the analog output unit converts the digital signals processed by the MCU into analog signals through a digital-to-analog converter, and outputs them to external analog devices; the analog control unit controls the working state of the analog signal input and output units through a comparator, a phase-locked loop, a programmable analog front-end, and an online calibration circuit, and realizes the functions of analog signal acquisition, conversion, and control.

[0084] In a specific embodiment, the peripheral control system provides an interface for communication and control with various peripherals through a general peripheral interface module. This module supports multiple communication protocols (such as SPI, I2C, UART, etc.) and provides register or memory mapping for data exchange and control with the RISC-V core. A timing management module generates the timing signals and clock signals required by each peripheral. This module can generate appropriate timing signals according to the peripheral's needs, ensuring stable operation. Furthermore, it can coordinate timing conflicts between different peripherals to ensure proper collaboration. A serial communication interface module provides serial communication interfaces, such as UART, SPI, and I2C, for data transmission and communication with external devices. This module converts data sent by the RISC-V core into corresponding serial signals and converts received serial signals into a suitable data format for processing. An external memory interface module interacts with external memory (such as flash memory, SD cards, etc.). It provides read / write control signals and data transmission interfaces for external memory to enable data storage and retrieval operations. Analog signal interface modules are used to process analog signals, such as for analog input / output and analog signal acquisition. These modules include analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), which are used to convert analog signals into digital signals or vice versa.

[0085] In a RISC-V core-based MCU chip system, the general-purpose peripheral interface module flexibly supports various peripherals and communicates with the RISC-V core through a unified interface, enabling the system to have broader application capabilities. Furthermore, the timing management module ensures that the timing requirements of peripherals are met, guaranteeing stable operation and improving the overall system reliability and stability. Secondly, the serial communication interface module provides an efficient data transmission method, enabling reliable data exchange and communication with other devices. Simultaneously, the external memory interface module allows the system to interact with external memory, providing the ability to expand system storage capacity and flexibly adjust as needed. Finally, the analog signal interface module enables the system to process analog signals, meeting the requirements of analog input / output and acquisition, expanding the system's functionality and applicability.

[0086] In the above embodiments, the deep learning-based memory management algorithm calculates the memory's popularity value using a data popularity calculation formula to assess the memory's importance; the formula expression for the data popularity calculation formula is:

[0087]

[0088] In formula (1), T represents the heat value of the l-th memory block in the j-th module, used to assess the importance of memory l; σ represents the weight of the k-th data type in the j-th module, used to consider the impact of different data types on memory heat; W represents the weight of the s-th data type in the l-th memory block, used to consider the impact of different data types on memory heat; the memory heat prediction formula predicts the future heat of memory; the memory heat prediction formula maps the result to a probability value between 0 and 1 by linearly weighting and summing the correlation between memory blocks; the formula expression of the memory heat prediction formula is:

[0089]

[0090] In formula (2), P represents the predicted heat value of the l-th memory block in the j-th module in the next time period; it is used to represent the future heat status of the memory; ω represents the weight between the l-th memory block and the α-th memory block in the j-th module; it is used to calculate the correlation between the memory blocks; η represents the bias of the l-th memory block in the j-th module, used to adjust the baseline value of the memory heat; the data migration decision formula determines whether the memory needs to be migrated; the data migration decision formula determines whether the memory needs to be migrated by comparing the predicted heat value of the memory with the heat threshold; the formula expression of the data migration decision formula is:

[0091]

[0092] In formula (3), Y represents whether the l-th memory in the j-th module needs to be migrated, which is used to determine whether the memory needs to be migrated; Q represents the heat threshold; b represents the memory weight, which is used to calculate the correlation between the memory.

[0093] In a specific embodiment, implementing a deep learning-based memory management algorithm requires the following hardware environment: a memory management module for implementing storage virtualization and data migration functions; a neural network accelerator for accelerating the training and inference processes of the deep learning algorithm; and a memory for storing the model and training data of the deep learning algorithm, as well as runtime data and parameters. In a specific implementation, the specific operation process of the deep learning-based memory management algorithm is as follows:

[0094] U1. Data Acquisition and Preprocessing: Collect memory access patterns and data popularity information of chip workload, and preprocess them to generate training and test set data.

[0095] U2. Model Training: The preprocessed data is trained using a neural network model to obtain a memory management model suitable for the current chip workload.

[0096] U3. Model Export and Deployment: Export the trained memory management model as an executable file and deploy it to the chip.

[0097] U4. Data Migration: During runtime, the memory management module intelligently migrates data to flash memory and DRAM using deep learning algorithms based on the current memory access pattern and data usage, in order to optimize chip performance and power consumption.

[0098] In practical implementation, the test data table for the deep learning-based memory management algorithm is shown in Table 1:

[0099] Table 1. Test data for deep learning-based memory management algorithms.

[0100] 1 Random access high 60% Flash memory, 40% DRAM 20W 2 Sequential access middle 70% DRAM, 30% Flash Memory 15W 3 Random access Low 90% DRAM, 10% Flash Memory 12W 4 Mixed access high 50% Flash, 50% DRAM 18W

[0101] Table 1 shows the memory distribution and power consumption under different memory access modes and data heat. It can be seen that the deep learning-based memory management algorithm can dynamically adjust the memory distribution according to different memory access modes and data heat, thereby optimizing system performance and power consumption.

[0102] In practice, the deep learning-based memory management algorithm collects data access patterns by monitoring memory access patterns and data popularity. Next, feature extraction is performed using deep learning techniques, such as Convolutional Neural Networks (CNNs) or Recurrent Neural Networks (RNNs), on the collected data. Then, the collected data and its corresponding labels are used to train the deep learning model to learn the correlation between different memory access patterns and data popularity. When memory data migration is required, the algorithm predicts the target migration location based on the current memory access pattern and data popularity using the trained deep learning model. Based on the prediction results, the memory management module migrates the data from its original location to the new location and updates the relevant mapping tables and caches.

[0103] In RISC-V core-controlled MCU chip systems, deep learning algorithms can make intelligent decisions based on real-time memory access patterns and data activity, enabling dynamic data migration to adapt to different application scenarios and workloads. Furthermore, deep learning models, trained on large-scale data, can learn more complex data distributions and patterns, improving the accuracy and effectiveness of data migration decisions. Secondly, by rationally adjusting the memory data distribution, frequent data migration and unnecessary energy consumption are avoided, thereby improving the system's energy efficiency. Table 2 shows a comparison of data tests between deep learning-based memory management algorithms and traditional algorithms in a specific implementation.

[0104] Table 2 Comparison of Deep Learning-Based Memory Management Algorithms

[0105] Number of data migrations 100 150 Data access latency 5μs 7μs System energy consumption 50W 60W

[0106] As shown in Table 2, the deep learning-based memory management algorithm has achieved better results in terms of data migration times, data access latency, and system energy consumption, and has higher performance and efficiency compared with traditional algorithms.

[0107] In the above embodiments, the machine learning-based power management algorithm predicts future load change trends using a load change prediction function; the formula for the load change prediction function is:

[0108]

[0109] In formula (4), M represents the predicted value of the future load change trend; N is the intercept, used to represent the benchmark of the load change trend when there are no characteristic parameters; d is the characteristic coefficient, used to measure the influence of each characteristic parameter on the load change trend; t represents the characteristic parameter used for prediction; ∈ represents the error term, used to measure the difference between the actual observed value and the predicted value; the processor clock frequency is dynamically adjusted by the processor clock frequency dynamic adjustment formula; the clock frequency dynamic adjustment formula adjusts the processor clock frequency through the PID controller according to the error between the current load and the target load; the formula expression of the clock frequency dynamic adjustment formula is:

[0110]

[0111] In formula (5), D represents the controller output; u represents the error between the current load and the target load, used to indicate the processor's load status; Indicates processor load; n represents peripheral load; K p K i and K d These represent the proportional, integral, and derivative coefficients of the PID controller, used to adjust the controller's response speed and stability. The peripheral clock frequency is dynamically adjusted using a formula. This formula adjusts the peripheral clock frequency based on the system's load state and target power consumption, using a fuzzy controller. The formula expression for this dynamic adjustment formula is:

[0112]

[0113] In formula (6), R represents the membership degree of input x with respect to the y-th fuzzy rule, which is used to determine the weight of a specific rule; δ and S represent the upper and lower bounds of the membership function of the m-th feature of the y-th rule, which are used to define the rule base of the fuzzy controller.

[0114] In a specific embodiment, the machine learning-based power management algorithm works in the following way:

[0115] Y1. Data Acquisition Phase: Collect power consumption data of the processor and peripherals under different workloads. This data can include power consumption values ​​under different clock frequencies, different task loads, and other relevant environmental conditions.

[0116] Y2. Feature Extraction and Model Training: Features are extracted from the collected power consumption data, and machine learning algorithms (such as neural networks, decision trees, etc.) are used to train the power consumption model. This model can learn the relationship between power consumption and clock frequency, task load, and other environmental factors.

[0117] Y3. Power Consumption Prediction and Frequency Adjustment: A trained model is used to predict power consumption under current workload and environmental conditions. Based on the prediction results, the clock frequencies of the processor and peripherals are dynamically adjusted to optimize power consumption. If the predicted power consumption is high, the clock frequency can be reduced to decrease power consumption; if the predicted power consumption is low, the clock frequency can be increased to improve performance.

[0118] In RISC-V core-controlled MCU chip systems, machine learning-based power management algorithms can effectively reduce system power consumption by dynamically adjusting the clock frequency based on real-time predictions of current workload and environmental conditions. This can extend device battery life or reduce system dependence on power supplies. Furthermore, by dynamically adjusting the clock frequency based on real-time predictions of workload and environmental conditions, system performance can be maximized. Increasing the clock frequency under high load can improve the operating speed and responsiveness of the processor and peripherals. Secondly, machine learning-based power management algorithms can automatically adjust the clock frequency according to different workloads and environmental conditions, making them more adaptable. This flexibility can provide a better user experience and system performance. Table 3 shows a comparison of data between machine learning-based power management algorithms and traditional algorithms in specific implementations.

[0119] Table 3 Data Comparison Table

[0120]

[0121]

[0122] As shown in the table above, when the system is under low load, the traditional algorithm consumes 2.5W, while the machine learning-based algorithm consumes only 2.2W, a reduction of 0.3W, demonstrating significant energy savings. Similarly, when the system is under high load, the machine learning-based algorithm consumes 4.0W, while the traditional algorithm consumes 5.2W, a reduction of 1.2W, reducing reliance on power supplies and extending the equipment's lifespan.

[0123] In a RISC-V core-controlled MCU chip system, the hardware environment for running a machine learning-based power management algorithm includes a processor with machine learning capabilities and related hardware and software support, including training datasets and model training tools. Furthermore, the execution process of the machine learning-based power management algorithm is as follows:

[0124] C1. Collect power consumption and performance data of each module inside the chip to form a training dataset.

[0125] C2. Use machine learning algorithms to train the training dataset to obtain a power management model.

[0126] C3. During chip operation, power consumption and performance data of each module are collected in real time and input into the power management model for prediction and decision-making.

[0127] C4. Based on the prediction results of the power management model, dynamically adjust the clock frequencies of the processor and peripherals to achieve the optimal balance between power consumption and performance. In practice, the test data for the machine learning-based power management algorithm is shown in Table 4.

[0128] Table 4 Test Data Table for Machine Learning-Based Power Management Algorithms

[0129] 162789 CPU 200 150 50 162790 RAM 100 80 20 162791 GPU 300 200 70 162792 CPU 150 120 40 162793 RAM 80 70 15 162794 GPU 200 150 50

[0130] In the table above, the timestamp indicates the time of test data acquisition, and the modules include three modules: CPU, RAM, and GPU. The current clock frequency represents the clock frequency of the current module, the optimal clock frequency represents the optimal clock frequency calculated by the power management algorithm, and power consumption represents the power consumption of the current module. The algorithm's operation and results demonstrate that the machine learning-based power management algorithm can dynamically adjust the clock frequencies of the processor and peripherals based on real-time power consumption and performance data, achieving an optimal balance between power consumption and performance, thereby improving the overall efficiency and performance of the system.

[0131] In the above embodiments, the on-chip system integration method operates in a RISC-V core-controlled MCU chip system as follows:

[0132] Step 1: Functional module analysis;

[0133] Functional analysis of peripheral interfaces and communication interfaces is performed using the hardware description language VHDL, and electrical characteristics and timing aspects are modeled and simulated.

[0134] Step 2: Interface Protocol Design;

[0135] The implementation methods of the physical layer, data link layer, and transport layer of the protocol are determined by the communication protocol specification;

[0136] Step 3: Interface controller design;

[0137] An interface controller circuit is designed using digital logic design methods. The interface controller circuit includes modules for generating, transmitting, and receiving clock, data, and control signals.

[0138] Step 4: Data Cache Management;

[0139] Data caching is managed using a first-in-first-out buffer and a data storage device;

[0140] Step 5: Timing optimization;

[0141] Timing optimization of the entire chip system is performed using timing analysis and clock division methods.

[0142] Step Six: Embedded Software Support;

[0143] Provide an application interface for the interface controller through an embedded software driver;

[0144] Step 7: Verification Test;

[0145] We ensure that the performance and stability of the hardware-supported expansion modules meet the design requirements through functional simulation, timing analysis, synthesis, placement and routing, and physical verification.

[0146] In a specific embodiment, the system-on-chip (SoC) integration method directly integrates hardware modules such as peripheral interface modules and communication interface modules inside the chip, sharing the same on-chip bus with the RISC-V core, and exchanging data and controlling the core through the on-chip bus. Next, the SoC integration method adds corresponding control logic circuits inside the chip to achieve unified control and management of the peripheral and communication interfaces. This includes timing management, data transmission control, interrupt handling, and other functions to ensure the normal operation of the peripherals and their cooperation with the core. Finally, the various hardware modules are connected through the on-chip bus to realize data transmission and communication. The on-chip bus can adopt different architectures, such as the AMBA bus or the AXI bus, to meet the system's bandwidth and latency requirements.

[0147] In a RISC-V core-based MCU chip system, peripheral interfaces and communication interfaces are integrated within the chip using a system-on-chip (SoC) approach. This reduces latency from external connections and signal transmission, improving system response speed and performance. Furthermore, by integrating control logic and a unified on-chip bus architecture, peripheral and communication interfaces can be better managed and controlled, enhancing system stability and reliability. Secondly, integrating peripheral and communication interfaces within the chip reduces reliance on external components, resulting in a more compact chip package and lower system cost and power consumption. Simultaneously, the SoC approach allows for flexible configuration of peripheral and communication interfaces to meet diverse application requirements and functional needs in various scenarios. Finally, the SoC approach facilitates the expansion and addition of new peripheral and communication interfaces to satisfy evolving system requirements.

[0148] In the above embodiments, the adaptive power management model includes a load detection module, an environment detection module, a strategy generation module, and a power control module. The load detection module includes a processor load detection unit and a peripheral device load detection unit. The processor load detection unit detects the processor load in real time using hardware performance counter technology. The peripheral device load detection unit detects the load of peripheral devices through an interrupt controller and peripheral interfaces. The environment detection module detects chip temperature, humidity, and other environmental parameters in real time using sensors and analog signal acquisition methods. The strategy generation module includes a dynamic power consumption management unit and a dynamic voltage management unit. Based on the information output by the load detection module, the dynamic power consumption management unit calculates the current chip power consumption using statistical analysis methods. Based on the output information of the environment detection module and the power consumption management strategy, the dynamic voltage management unit calculates the supply voltage using a voltage regulator and feedback control methods. The power control module controls the output voltage of the power converter using a pulse width modulator.

[0149] In a specific embodiment, the adaptive power management model monitors the current consumption of the chip system in real time through a load detection module. The load detection module collects and analyzes load information to understand the current power consumption status of the system. An environmental detection module monitors the environmental conditions of the chip system, such as temperature and humidity. These environmental factors may affect the chip's performance and power consumption. Based on the data provided by the load detection and environmental detection modules, and pre-defined policy rules, a policy generation module generates corresponding power management policies. These policies may include adjusting voltage frequency, enabling / disabling specific functional modules, etc. The power control module dynamically adjusts and controls the power supply of the chip system according to the power management policies generated by the policy generation module. The power control module can adjust voltage supply, power distribution, etc., to meet the system's performance requirements and power consumption limits.

[0150] In a RISC-V core-based MCU chip system, by monitoring load and environmental conditions in real time, the power supply and power consumption allocation are dynamically adjusted to minimize power consumption while meeting performance requirements, thus achieving energy saving and consumption reduction. Furthermore, the adaptive power management model can dynamically adjust power parameters according to different operating states and environmental conditions, maintaining system stability and reliability under various circumstances. Secondly, through the configuration of the strategy generation module, power management strategies can be customized according to different application requirements and scenarios, improving system scalability and flexibility. Simultaneously, by rationally managing power supply and power consumption allocation, heat generation and loss in the chip system can be reduced, extending system lifespan. Finally, due to the presence of an environmental detection module, the adaptive power management model can automatically adjust power parameters according to changes in environmental conditions to adapt to complex operating environments, improving the system's adaptability under various conditions.

[0151] In the above embodiments, the security enhancement module implements data encryption and decryption functions through a hardware encryption engine; the hardware encryption engine includes a symmetric encryption unit and an asymmetric encryption unit; the symmetric encryption unit encrypts and decrypts data using a symmetric encryption algorithm; the asymmetric encryption unit implements secure data transmission and identity authentication through a public-key encryption and private-key decryption mechanism; the hardware encryption engine enhances the security of symmetric and asymmetric encryption algorithms through a physical non-rechargeable battery; the physical non-rechargeable battery generates uncopyable physical characteristics to generate keys through transistor parameter variations and circuit noise differences; the security enhancement module ensures system security during startup through a secure boot mechanism; the secure boot mechanism includes a boot verification unit and a secure boot control unit; the boot verification unit ensures that only authorized firmware or software can be loaded and executed through integrity verification and digital signatures; the secure boot control unit manages security policies during startup through a hardware root trust component; the hardware root trust component ensures system startup security, data protection, and that critical operations are performed in a secure execution environment through digital signatures, hash verification, and hardware virtualization methods.

[0152] In a specific embodiment, the security enhancement module includes a hardware encryption engine for implementing various encryption algorithms and security protocols. This engine provides fast and efficient data encryption and decryption capabilities, protecting sensitive data in the system. The hardware encryption engine typically supports symmetric encryption algorithms (such as AES), asymmetric encryption algorithms (such as RSA), and hash functions (such as SHA). The security enhancement module ensures system security during the boot process through a secure boot mechanism. It verifies the integrity and authenticity of the firmware or software loaded at boot, preventing the execution of malware or unauthorized code. Secure boot mechanisms typically employ technologies such as digital signatures, hash verification, and secure boot protocols to ensure that only authorized software can run on the system.

[0153] In a RISC-V core-based MCU chip system, a hardware encryption engine allows sensitive data to be encrypted in memory, protecting its confidentiality and integrity. This effectively prevents unauthorized access and data leakage. Furthermore, the secure boot mechanism of the security enhancement module verifies the authenticity of the firmware or software loaded at system startup, preventing the execution of malware or malicious code. This helps prevent system attacks, virus infections, or tampering. Secondly, the overall trustworthiness of the system is enhanced by using the hardware encryption engine and secure boot mechanism. Users can trust the system more because it provides robust data security and protection capabilities. Simultaneously, the security enhancement module prevents unauthorized code execution, thus protecting intellectual property within the system. This is particularly important for chip design companies and software developers, preventing the theft or tampering of their technologies and algorithms. Finally, the use of the security enhancement module enables the system to comply with various security standards and certification requirements, such as the security certification standards of the International Organization for Security Standards (ISO), as well as security specifications and requirements of various industries. This is essential for applications in specific fields, such as finance, healthcare, and the military.

[0154] In the above embodiments, an MCU chip based on RISC-V core control includes:

[0155] The RISC-V core is used to execute the instruction set and control the operation of the entire system;

[0156] On-chip memory is used to store programs, data, and intermediate results; the on-chip memory includes high-speed static random access memory and flash memory integrated on the chip;

[0157] A general-purpose interface module is used to provide a standardized communication interface with external devices and sensors; the general-purpose interface module includes at least a Universal Serial Bus (I2C / SPI) and a Universal Asynchronous Receiver / Transmitter (UART) interface.

[0158] A peripheral control module is used to control and manage the operation of external devices; the peripheral control module manages the operation of peripherals through control logic circuits and registers.

[0159] An exception handling circuit is used to monitor and handle hardware and software exceptions; the exception handling circuit includes an exception detection circuit, an exception handling unit, and an exception vector table.

[0160] A security protection module is used to provide data encryption and decryption functions; the security protection module improves the security of data transmission and storage through a hardware encryption engine;

[0161] A dynamic voltage regulation circuit is used to optimize power consumption and extend battery life; the dynamic voltage regulation circuit adjusts the chip's operating voltage according to system load requirements through a voltage regulator and a feedback control circuit.

[0162] The peripheral interface module provides an interface for interacting with external devices; the peripheral interface module integrates physical interfaces and control logic through a system-on-a-chip integration method.

[0163] A secure boot module is used to ensure the security and trustworthiness of the system boot process; the secure boot module includes a secure boot ROM, a digital signature verification unit, and a key management unit.

[0164] In a specific embodiment, the RISC-V core is the heart of the chip, responsible for executing the instruction set and controlling the operation of the entire system. It employs a Reduced Instruction Set Computing (RISC) architecture, making the instruction set more concise and clear. This reduces instruction complexity and length, improves instruction execution efficiency and speed, and lowers hardware resource requirements. On-chip memory stores programs, data, and intermediate results. It includes high-speed static random access memory and flash memory integrated on the chip. By using high-speed memory to accelerate data and program access, system response speed and performance are improved, and power consumption is reduced. A general-purpose interface module provides standardized communication interfaces with external devices and sensors. It includes at least a Universal Serial Bus (I2C / SPI) and a Universal Asynchronous Receiver / Transmitter (UART) interface. Providing standardized communication interfaces facilitates communication with various external devices and sensors, improving system scalability and compatibility. A peripheral control module controls and manages the operation of external devices. It manages peripheral operations through control logic circuits and registers. A unified peripheral control module facilitates the management and control of various external devices, improving system reliability and stability. An exception handling circuit monitors and handles hardware and software exceptions. It includes an anomaly detection circuit, an anomaly handling unit, and an anomaly vector table. Timely detection and handling of anomalies prevent system crashes and malfunctions, improving system reliability and stability. The security protection module provides data encryption and decryption functions. It enhances the security of data transmission and storage through a hardware encryption engine. Providing data encryption effectively prevents data leakage and security risks, ensuring system security. The dynamic voltage regulation circuit optimizes power consumption and extends battery life. It adjusts the chip's operating voltage according to system load requirements through a voltage regulator and feedback control circuit. Dynamic voltage adjustment prevents chip damage due to over-power supply and extends battery life, improving system reliability and stability. The peripheral interface module provides interfaces for interaction with external devices. It integrates physical interfaces and control logic through on-chip system integration. Providing peripheral interfaces facilitates interaction with various external devices, improving system scalability and compatibility. The secure boot module ensures the security and trustworthiness of the system boot process. It includes a secure boot ROM, digital signature verification, and a key management unit. Providing secure boot functionality effectively prevents unauthorized tampering and attacks, ensuring system security and reliability.

[0165] These modules work together to optimize the functionality and performance of the RISC-V core-controlled MCU chip system. Specifically, the RISC-V core provides instruction-level parallelism, on-chip memory accelerates data and program access, the general-purpose interface module provides standardized communication interfaces, the peripheral control module manages various external devices, the exception handling circuit monitors and handles exceptions, the security protection module enhances the security of data transmission and storage, the dynamic voltage regulation circuit optimizes power consumption and extends battery life, the peripheral interface module provides interfaces for interaction with external devices, and the secure boot module ensures system security and reliability. These positive effects include improved system response speed, enhanced data and system security, improved system scalability and compatibility, reduced power consumption, extended battery life, and improved system reliability and stability, thereby significantly improving the performance and efficiency of the RISC-V core-controlled MCU chip system.

[0166] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these specific embodiments are merely illustrative. Those skilled in the art can omit, substitute, and modify the details of the above methods and systems in various ways without departing from the principles and essence of the present invention. For example, combining the above method steps to perform substantially the same function and achieve substantially the same result according to substantially the same method falls within the scope of the present invention. Therefore, the scope of the present invention is defined only by the appended claims.

Claims

1. A MCU chip system based on RISC-V core control, characterized in that: The system includes: A RISC-V core control module, which improves instruction throughput and processor performance through superscalar architecture and reduced instruction set; The compatibility enhancement module enables compatibility and interoperability with external devices and sensors through a peripheral control system. The peripheral control system achieves seamless adaptation of the MCU chip to various peripherals and sensors through a universal interface standardization method. The memory management module dynamically adjusts the data distribution of flash memory and dynamic random access memory (DRAM) through a storage virtualization method; the storage virtualization method uses a deep learning-based memory management algorithm to perform intelligent data migration based on memory access patterns and data popularity. A clock management module that dynamically adjusts the clock frequency of the processor and peripherals using a power management algorithm based on machine learning; The hardware support expansion module integrates peripheral interfaces and communication interfaces through a system-on-a-chip integration method. A multi-core processing module, which improves the system's concurrent processing capability and operating efficiency through parallel computing and shared resource management methods; A power optimization module, which dynamically adjusts the power management strategy based on the chip's workload and environmental conditions through an adaptive power management model; A security enhancement module improves the system's data security and protection capabilities through a hardware encryption engine and a secure boot mechanism. Specifically, the outputs of the RISC-V core control module and the memory management module are connected to the input of the multi-core processing module; the output of the compatibility enhancement module is connected to the input of the hardware support expansion module; the output of the clock management module is connected to the inputs of the RISC-V core control module, the compatibility enhancement module, and the hardware support expansion module; the output of the multi-core processing module is connected to the input of the power optimization module; and the output of the security enhancement module is connected to the inputs of the RISC-V core control module, the compatibility enhancement module, the memory management module, and the multi-core processing module.

2. The MCU chip system based on RISC-V core control according to claim 1, characterized in that: The RISC-V kernel control module includes a superscalar architecture unit, a reduced instruction set unit, a data path optimization unit, and a data cache unit. The superscalar architecture unit achieves parallel processing through out-of-order execution, which improves instruction throughput through a data and control dependency model between instructions. The control dependency model improves instruction execution parallelism through physical register renaming. The reduced instruction set unit reduces instruction storage and transmission costs by compressing instruction encoding / decoding formats. The data path optimization unit processes different instructions in parallel using a multi-stage pipeline design. The data cache unit includes a consistency subunit and a prefetch subunit. The consistency subunit ensures data consistency between multiple cache levels through a cache consistency protocol. The prefetch subunit improves data access efficiency through a data prefetch method, which preloads data into the cache through program memory access and memory access history analysis.

3. The MCU chip system based on RISC-V core control according to claim 1, characterized in that: The peripheral control system includes a general peripheral interface module, a timing management module, a serial communication interface module, an external memory interface module, and an analog signal interface module. The general peripheral interface module includes an input / output interface unit and a peripheral controller unit. The input / output interface unit achieves flexible connection to external devices through hardware pin multiplexing. The peripheral controller unit achieves compatibility and interoperability with different external devices through integrated peripheral interface protocols. The timing management module includes a timing control unit, a pulse width modulation unit, and a counter unit. The timing control unit controls and manages external devices through timer circuits and clock sources. The pulse width modulation unit controls the pulse width of external devices through a duty cycle controller. The counter unit counts and measures external events through a clock synchronization mechanism. The serial communication interface module ensures communication with external devices through a Universal Asynchronous Receiver / Transmitter (UART), a Serial Peripheral Interface (SPI), and a Serial Communication Bus (I2C). Reliable communication with external devices; the external memory interface module includes a flash memory interface unit and a memory card interface unit; the flash memory interface unit realizes reading and writing to the external flash memory through an address decoding circuit and a command control circuit; the memory card interface unit realizes reading and writing to the external memory card through a command control circuit and a clock generator; the analog signal interface module includes an analog input unit, an analog output unit, and an analog control unit; the analog input unit converts external analog signals into digital signals through an analog-to-digital converter and a filter, and transmits them to the MCU for processing; the analog output unit converts the digital signals processed by the MCU into analog signals through a digital-to-analog converter, and outputs them to external analog devices; the analog control unit controls the working state of the analog signal input and output units through a comparator, a phase-locked loop, a programmable analog front-end, and an online calibration circuit, and realizes the functions of analog signal acquisition, conversion, and control.

4. The MCU chip system based on RISC-V core control according to claim 1, characterized in that: The deep learning-based memory management algorithm calculates the memory's popularity value using a data popularity calculation formula to assess the memory's importance; the formula for the data popularity calculation formula is as follows: （1） In formula (1), T represents the first... In the module, the first The heat value of block memory is used to evaluate memory usage. The importance of; Indicates the first In the module, the first The weight of each data type is used to consider the impact of different data types on memory usage; W represents the weight of the first data type. The first in block memory The weights of different data types are used to consider the impact of different data types on memory heat. The memory popularity prediction formula predicts the future popularity of memory; the memory popularity prediction formula maps the result to a probability value between 0 and 1 by linearly weighting and summing the correlation between memory types. The formula for predicting memory heat is expressed as follows: （2） In formula (2), Indicates the first In the module, the first The predicted popularity of block memory in the next time period is used to indicate the future popularity of the memory. Indicates the first In the module, the first Block memory and the first Weights between block memories are used to calculate the correlation between memories; express In the module, the first The block memory bias is used to adjust the baseline value of memory heat and to determine whether memory needs to be migrated through the data migration decision formula; The data migration decision formula determines whether the memory needs to be migrated by comparing the predicted heat value of the memory with the heat threshold. The formula for the data migration decision is as follows: （3） In formula (3), Y represents the first... In the module, the first Whether block memory needs to be migrated is used to determine whether data migration of the memory is required. 'b' represents the heat threshold; 'b' represents the memory weight, used to calculate the correlation between memories.

5. The MCU chip system based on RISC-V core control according to claim 1, characterized in that: The machine learning-based power management algorithm predicts future load change trends using a load change prediction function; the formula for the load change prediction function is as follows: （4） In formula (4), A predicted value indicating future load change trends; The intercept is used as a benchmark to represent the load variation trend when there are no characteristic parameters. These are characteristic coefficients, used to measure the degree of influence of each characteristic parameter on the load change trend; Represents the feature parameters used for prediction; This represents the error term, used to measure the difference between the actual observed value and the predicted value; the processor clock frequency is dynamically adjusted using a dynamic adjustment formula; this dynamic adjustment formula adjusts the processor clock frequency using a PID controller based on the error between the current and target loads; the formula expression for the dynamic adjustment formula is: （5） In formula (5), Indicates the controller output; It represents the error between the current load and the target load, and is used to indicate the processor's load status; Indicates processor load; Indicates peripheral load; , and These represent the proportional, integral, and derivative coefficients of the PID controller, used to adjust the controller's response speed and stability. The peripheral clock frequency is dynamically adjusted using a formula. This formula adjusts the peripheral clock frequency based on the system's load state and target power consumption, using a fuzzy controller. The formula expression for this dynamic adjustment formula is: （6） In formula (6), Indicates input For the The membership degree of a fuzzy rule is used to determine the weight of a specific rule; and Indicates the first The first rule The membership functions of each feature are defined as upper and lower bounds, which are used to define the rule base of the fuzzy controller.

6. The MCU chip system based on RISC-V core control according to claim 1, characterized in that: The on-chip system integration method operates as follows in a RISC-V core-controlled MCU chip system: Step 1: Functional module analysis; Functional analysis of peripheral interfaces and communication interfaces is performed using the hardware description language VHDL, and electrical characteristics and timing aspects are modeled and simulated. Step 2: Interface Protocol Design; The implementation methods of the physical layer, data link layer, and transport layer of the protocol are determined by the communication protocol specification; Step 3: Interface controller design; An interface controller circuit is designed using digital logic design methods. The interface controller circuit includes modules for generating, transmitting, and receiving clock, data, and control signals. Step 4: Data Cache Management; Data caching is managed using a first-in-first-out buffer and a data storage device; Step 5: Timing optimization; Timing optimization of the entire chip system is performed using timing analysis and clock division methods. Step Six: Embedded Software Support; Provide an application interface for the interface controller through an embedded software driver; Step 7: Verification Test; We ensure that the performance and stability of the hardware-supported expansion modules meet the design requirements through functional simulation, timing analysis, synthesis, placement and routing, and physical verification.

7. The MCU chip system based on RISC-V core control according to claim 1, characterized in that: The adaptive power management model includes a load detection module, an environment detection module, a strategy generation module, and a power control module. The load detection module includes a processor load detection unit and a peripheral device load detection unit. The processor load detection unit detects the processor load in real time using hardware performance counter technology. The peripheral device load detection unit detects the load of peripheral devices through an interrupt controller and peripheral interfaces. The environment detection module detects chip temperature, humidity, and other environmental parameters in real time using sensors and analog signal acquisition methods. The strategy generation module includes a dynamic power consumption management unit and a dynamic voltage management unit. Based on the information output by the load detection module, the dynamic power consumption management unit calculates the current power consumption of the chip using statistical analysis methods; based on the output information of the environmental detection module and the power consumption management strategy, the dynamic voltage management unit calculates the supply voltage using a voltage regulator and feedback control methods; and the power control module controls the output voltage of the power converter using a pulse width modulator.

8. The MCU chip system based on RISC-V core control according to claim 1, characterized in that: The security enhancement module implements data encryption and decryption functions through a hardware encryption engine; the hardware encryption engine includes a symmetric encryption unit and an asymmetric encryption unit; the symmetric encryption unit encrypts and decrypts data using a symmetric encryption algorithm; the asymmetric encryption unit implements secure data transmission and identity authentication through a public key encryption and private key decryption mechanism; the hardware encryption engine enhances the security of symmetric and asymmetric encryption algorithms through a physical non-rechargeable battery; the physical non-rechargeable battery generates uncopyable physical characteristics to generate a key through transistor parameter variations and circuit noise differences; The security enhancement module ensures system security during startup through a secure boot mechanism. This secure boot mechanism includes a boot verification unit and a secure boot control unit. The boot verification unit ensures that only authorized firmware or software can be loaded and executed through integrity verification and digital signatures. The secure boot control unit manages security policies during startup through a hardware root trust component. The hardware root trust component ensures system startup security, data protection, and that critical operations are performed in a secure execution environment through digital signatures, hash verification, and hardware virtualization methods.

9. A MCU chip based on RISC-V core control, characterized in that: An MCU chip system based on a RISC-V core control according to any one of claims 1-8, comprising: The RISC-V core is used to execute the instruction set and control the operation of the entire system; On-chip memory is used to store programs, data, and intermediate results; the on-chip memory includes high-speed static random access memory and flash memory integrated on the chip; A general-purpose interface module is used to provide a standardized communication interface with external devices and sensors; the general-purpose interface module includes at least a Universal Serial Bus (I2C / SPI) and a Universal Asynchronous Receiver / Transmitter (UART) interface. A peripheral control module is used to control and manage the operation of external devices; the peripheral control module manages the operation of peripherals through control logic circuits and registers. An exception handling circuit is used to monitor and handle hardware and software exceptions; the exception handling circuit includes an exception detection circuit, an exception handling unit, and an exception vector table. A security protection module is used to provide data encryption and decryption functions; the security protection module improves the security of data transmission and storage through a hardware encryption engine; A dynamic voltage regulation circuit is used to optimize power consumption and extend battery life; the dynamic voltage regulation circuit adjusts the chip's operating voltage according to system load requirements through a voltage regulator and a feedback control circuit. The peripheral interface module provides an interface for interacting with external devices; the peripheral interface module integrates physical interfaces and control logic through a system-on-a-chip integration method. A secure boot module is used to ensure the security and trustworthiness of the system boot process; the secure boot module includes a secure boot ROM, a digital signature verification unit, and a key management unit.

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