A digital synapse circuit based on superconducting fast single flux quantum logic gates

Abstract

The application provides a digital synapse circuit based on a superconducting fast single-flux quantum logic gate, which comprises a control module, a TFF2 flip-flop sequence in which two output T-type flip-flops are cascaded, a NDRO (non-destructive readout) sequence in which NDROs are cascaded, and a synapse configuration module. The control module is used for receiving a clock signal and a pulse sequence of a presynaptic neuron and controlling generation of a weight sequence. The TFF2 flip-flop sequence receives the pulse sequence and is used for decoding the NDRO sequence of stored weight data. The NDRO sequence in which NDROs are cascaded is used for storing weight data. The synapse configuration module is connected to the set end and the reset end of each NDRO in the NDRO sequence. The first output port of a flip-flop in the flip-flop sequence is connected to a corresponding NDRO in the NDRO sequence. The output port of the last flip-flop in the flip-flop sequence generates a termination signal to the control module. The pulses output by the NDROs in the NDRO sequence are combined to obtain a combined pulse.

Description

Technical Field

[0001] This invention relates to the fields of superconducting rapid single flux quantum (RSFQ) technology and neural network computing. Specifically, this invention designs a digital synaptic circuit based on superconducting RSFQ logic gates. Background Technology

[0002] Artificial neural networks (ANNs) have demonstrated immense application value across numerous fields. As the third generation of neural networks, spiking neural networks (SNNs) are considered truly brain-inspired artificial neural networks, first proposed by researchers at the University of Heidelberg and the University of Bern. Compared to the previous two generations of neural networks, the most significant feature of SNNs is their pulse information processing mechanism, similar to the information processing methods of biological nervous systems based on electrical impulse signals. SNNs encode data information as pulse sequences, a significant difference from traditional artificial neural networks (ANNs) based on floating-point operations. Furthermore, the pulse-driven mechanism in information processing makes SNNs consume less power than traditional artificial neural networks.

[0003] The main structures of a neuron include the cell body, dendrites growing around the cell body to receive stimuli from other neurons, axons that transmit electrical signals, and synapses that connect neurons. Stimuli from the cell body or dendrites are transmitted on the axon as electrical impulses and within the synapse as neurochemical neurotransmitters. Within the synapse, the amount of neurotransmitters and receptors affects the magnitude of the stimulus received by the postsynaptic neuron. Therefore, the strength of connections between neurons varies, and in ANN applications, this connection strength is characterized by weights. Numerous CMOS-based SNN accelerator designs exist, typically using processing units (PEs) as the basic unit, integrating the functions of the neuronal cell body and synapse to perform basic synaptic operations (SOPs). While existing SNNs are slightly inferior to state-of-the-art ANNs in inference accuracy, thanks to the characteristics of sparse computing, CMOS-based SNNs offer better energy efficiency than ANNs. Existing CMOS SNN accelerators can consume energy in the pJ range per SOP, several orders of magnitude lower than traditional ANN accelerators. However, CMOS SNNs also suffer from low throughput and inference efficiency in practical applications, due to the significant amount of additional time slices consumed by SNN pulse encoding. Overall, CMOS SNN accelerators do not offer a significant advantage over advanced ANN accelerators in most cases, limiting their current application scenarios. Finding high-performance, high-throughput, and low-power spiking neuron designs remains a key research focus in the current SNN research field.

[0004] Superconducting high-speed single flux quantum (RSFQ) circuits possess ultra-high speed and ultra-low power consumption characteristics, and are considered one of the most promising alternative technologies to traditional CMOS circuits. RSFQ circuits use Josephson junctions (JJs) as the basic switching element, equivalent to transistors in CMOS. RSFQ circuits transmit information using voltage pulses and store information using single flux quanta, where the single flux quantum Φ0 = ∫V(t)·dt ≈ 2.07 × 10⁻⁶. -15 Wb. RSFQ devices require operation at approximately 4K temperatures, and Josephson junctions offer ps-level switching speeds and <10 -19 The low power consumption of J allows simple devices to operate at frequencies of hundreds of GHz. Under the same process technology, the delay and power consumption of RSFQ circuit logic gates are two orders of magnitude lower than those of CMOS circuits. Unlike CMOS, which uses high and low voltage levels to represent logic 0 / 1, RSFQ circuits use a pulse signal between two clock cycles to represent '1', and the absence of a pulse represents '0'. The main difference between RSFQ and CMOS circuits in design is that almost all logic gates in RSFQ circuits require a clock signal, thus RSFQ circuits can be considered fully gate-level pipelined circuits; and because pulse signals cannot be maintained for long periods, RSFQ circuits require more stringent timing control. Circuit devices based on RSFQ technology have significant advantages in performance and energy efficiency, and have long been used in microprocessor chip design. Meanwhile, superconducting devices exhibit characteristics similar to neurons, such as pulse information processing mechanisms, threshold characteristics, and lossless pulse signal transmission, thus the application of superconducting circuits in SNNs has attracted attention. Figure 1 This section provides a functional description of each superconducting RSFQ logic unit, including TFF2, T1FF, NDRO, Splitter, and Merger. Their symbols, timing, and functions are shown in the figure.

[0005] CMOS-based SNN designs typically require storage circuits, adders, and control modules to achieve synaptic functionality. Weight data is stored in dedicated memory and read out and added to the postsynaptic neuron when a pulse arrives from the presynaptic neuron. Currently, several representative superconducting circuit-based synaptic designs are primarily analog circuit schemes, such as the combination of a superconducting quantum interference device (SQUID) and an RLC circuit. The SQUID circuit receives and transmits the pulse input, which is modulated by a magnetic field generated by an external current; the RLC circuit smooths the pulse to generate the synaptic current output. Schemes based on magnetic Josephson junctions (MJJs) control the weights by changing the critical current of the MJJ through the direction of its internal magnetic order. Synaptic designs based on mutual inductance and switch arrays utilize the number of closed switches to influence the mutual inductance strength, thereby modulating the pulse amplitude.

[0006] While CMOS-based SNN designs have matured, their energy efficiency and speed limitations hinder large-scale applications and their potential to replace traditional ANNs. Superconducting electronic devices, with their ultra-high speed and low power consumption, hold promise for overcoming these bottlenecks. Currently, most synaptic solutions based on superconducting electronic devices are analog circuit designs. SQUID and RLC-based solutions are limited in accuracy and resolution. Because the analog quantities handled by the circuits, such as current, are very small, they are easily affected by thermal noise and quantum fluctuations, leading to reduced inference accuracy. Furthermore, these designs struggle to construct large-scale networks, significantly limiting their practical applications. Solutions based on mutual inductance and switch arrays also face difficulties in parameter setting and manufacturing, and require integration with traditional CMOS circuits for switching and control. Emerging superconducting devices, such as MJJs, also face manufacturing challenges, and their applications remain largely theoretical. Additionally, the magnetic order adjustment of MJJs requires an external magnetic field, increasing cost and difficulty in practical applications. At the same time, the weight resolution represented by MJJ is not ideal, and it can generally only represent two cases: on and off.

[0007] The present invention uses superconducting electronic devices to implement synaptic circuits. The main difficulties to be considered are: (1) Existing analog circuit schemes suffer from low accuracy and resolution and are susceptible to noise, making it difficult to construct large-scale networks and apply them in practice. Digital circuit schemes are expected to solve this problem. (2) Existing synaptic circuit designs face significant difficulties in weight configuration. The new design should meet the requirement of facilitating on-chip weight updates. (3) Storage is a limited resource in superconducting circuit design. The utilization efficiency of storage devices should be improved to reduce the demand for storage circuits. (4) MJJ-based synapses are considered to have great application potential, but the manufacturing problem still cannot be solved. To facilitate actual manufacturing, conventional RSFQ devices should be used to implement synaptic circuits. Summary of the Invention

[0008] To address the aforementioned issues, the synaptic circuit design proposed in this invention considers the following factors: (1) To achieve high-precision and high-resolution synaptic weights, a digital implementation scheme is adopted, using the number of pulses to characterize the weight magnitude, thereby avoiding noise and errors suffered by analog quantities. (2) To achieve convenient weight configuration, a non-volatile NDRO sequence is used to store the weight data. (3) To reduce the consumption of storage circuitry, this design uses a T-flip-flop sequence to decode the weight data, improving the utilization rate of NDRO. (4) All conventional superconducting RSFQ logic gates are used, avoiding manufacturing difficulties. Therefore, the synaptic circuit proposed in this invention mainly consists of a series of T-flip-flops (TFFs) and non-destructive readout (NDRO) units. This synaptic design enables high-precision data storage, facilitates weight configuration, and is beneficial for on-chip learning.

[0009] Specifically, this application proposes a digital synaptic circuit based on a superconducting fast single-flux quantum logic gate, including:

[0010] The control module is used to receive clock signals and pulse sequences from presynaptic neurons, and to control the generation of weight sequences.

[0011] A TFF2 flip-flop sequence consisting of two cascaded output T flip-flops receives the pulse sequence for decoding a non-destructive read sequence of stored weight data;

[0012] An NDRO sequence cascaded from NDRO is used to store weight data;

[0013] The synapse configuration module is connected to the set and reset terminals of each NDRO in the NDRO sequence.

[0014] In this sequence, the first output port of the trigger is connected to the corresponding NDRO in the NDRO sequence, and the output port of the last stage trigger in the sequence generates a termination signal to the control module; the pulses output by each NDRO in the NDRO sequence are combined to obtain a combined pulse.

[0015] The digital synaptic circuit based on superconducting fast single-flux quantum logic gates, wherein the control module includes a first NDRO and a second NDRO;

[0016] The set port of the first NDRO receives the pulse sequence of the presynaptic neuron, the RD port of the first NDRO is connected to the clock signal, the output of the first NDRO sends the pulse sequence for decoding to the trigger sequence, and the reset port of the first NDRO is used to receive the termination signal.

[0017] The set port of the second NDRO receives the pulse sequence of the presynaptic neuron; the RD port of the second NDRO receives the combined pulse output by the NDRO sequence; the reset port of the second NDRO is used to interrupt the generation of the decoding sequence; and the output terminal of the second NDRO outputs the output sequence.

[0018] The digital synaptic circuit based on superconducting fast single-flux quantum logic gates, wherein the RD port of each NDRO in the NDRO sequence is connected to the odd-numbered output port of its corresponding flip-flop, the output port of each NDRO in the NDRO sequence is connected to the input of a combiner, and the output of the combiner outputs the combined pulse.

[0019] The digital synaptic circuit based on superconducting fast single-flux quantum logic gates, wherein the trigger sequence is composed of cascaded two-output T triggers; the odd-numbered output ports of the two-output T triggers are connected to the corresponding NDRO in the NDRO sequence, and the even-numbered output ports of the two-output T triggers are connected to the next stage trigger; the even-numbered output port of the last stage two-output T trigger in the trigger sequence generates a termination signal to the control module.

[0020] The digital synaptic circuit based on superconducting fast single-flux quantum logic gates, wherein the trigger sequence is composed of cascaded two-output T triggers with asynchronous destructive readout function; the even-numbered output ports of the two-output T triggers are connected to the next stage trigger and the even-numbered output ports are connected to the RD port of the corresponding NDRO in the NDRO sequence.

[0021] The digital synaptic circuit based on superconducting fast single-flux quantum logic gates includes a control module called NDRO. The set port of the control module is used to receive the pulse sequence, the reset port of the control module is used to receive the termination signal, and the output terminal of the control module sends the pulse sequence for decoding to the trigger sequence. The RD terminal of the control module is used to receive the clock signal.

[0022] As can be seen from the above solutions, the advantages of the present invention are:

[0023] This invention relates to a digital synaptic circuit based on superconducting RSFQ logic gates. This synaptic circuit primarily consists of a series of T-type flip-flops (TFFs) and non-destructive readout (NDRO) units. Compared to traditional CMOS circuit designs, its speed and energy efficiency are improved by several orders of magnitude. Compared to previous superconducting circuit designs, this design offers significant advantages in accuracy, practicality, configurability, and manufacturability. Attached Figure Description

[0024] Figure 1 A diagram illustrating the functions of each RSFQ logic unit;

[0025] Figure 2 This is a design diagram of a synaptic circuit based on the TFF2 and NDRO sequences;

[0026] Figure 3 The waveform diagram of WRspice simulation based on TFF2 and NDRO sequence synaptic circuits;

[0027] Figure 4 Simulation waveform diagram of synaptic decoding interrupt function;

[0028] Figure 5 This is a design diagram of a synaptic circuit based on the T1FF and NDRO sequences. Detailed Implementation

[0029] To achieve the above-mentioned technical effects, the present invention includes the following key technical points:

[0030] Key Point 1: Synaptic circuit design based on TFF2 and NDRO sequences; This design includes a control module and a core module. NDRO sequences are used to store weight data, and TFF2 sequences are used to decode the weights into pulse sequences. The control module uses two NDRO sequences to implement the start, stop, and interruption of weight decoding.

[0031] Key Point 2: Prominent Circuit Design Based on T1FF and NDRO Sequences; This design is similar to the first design in terms of weight configuration and decoding. The difference is that the control module of this scheme only requires one NDRO to implement. This circuit interrupts the decoding process by reading the state of the T1FF sequence.

[0032] To make the above-mentioned features and effects of the present invention clearer and easier to understand, specific embodiments are described below in conjunction with the accompanying drawings. This specification discloses one or more embodiments incorporating the features of the present invention. The disclosed embodiments are merely illustrative. The scope of protection of the present invention is not limited to the disclosed embodiments, but is defined by the appended claims.

[0033] Figure 2 This is a synaptic design based on the TFF2 and NDRO sequences, comprising a control module, a core module, and a synaptic configuration module. The synaptic configuration module is used to connect to an external weight configuration circuit. The NDRO unit has a set port (S) and a reset port (R) to control whether NDRO stores a 1 or a 0. These two pins can be connected to an external control circuit to achieve weight configuration. Figure 2This paper demonstrates a 4-bit circuit design where the core module uses four NDROs to store weight data. The control module employs two NDROs: the In port connects to the set terminal of the upper NDRO to receive pulse signals from the presynaptic neuron, and the Clock In port receives the clock signal. The control module sends a pulse sequence for decoding to the core module via its outputs (O or Do). The core module's NDRO sequence is driven by the outputs of the TFF2 sequence, performing weight data decoding. Odd-numbered output ports (O1) of the TFF2 are connected to the corresponding NDROs, and even-numbered output ports (O2) are connected to the next TFF2 stage. The O2 port of the last TFF2 stage generates a termination signal to the control module. Because the TFF2 sequences are cascaded, and the number of output pulses is determined by their binary order, the maximum number of pulses decoded by the NDRO sequence is 2^32. 4 -1 = 15. The pulses output by the NDRO sequence are combined into a single output by a combiner. The final output sequence is determined by the NDRO below the control module and sent to the next neuron circuit (i.e., the postsynaptic neuron circuit). The control module also reserves a reset port Rst for interrupting the generation of the decoding sequence, which is connected to the output of the postsynaptic neuron. The purpose of this process is that when the postsynaptic neuron reaches the membrane potential and emits a pulse, the synapse should stop sending pulse sequences to the neuron to prevent the neuron from retaining the original data in the next decoding cycle, which is equivalent to the "refractory period" of biological neurons. This process cannot be achieved by applying a pulse to the reset terminal of the NDRO above the control module, because the old state of the TFF2 sequence will still be retained, thus affecting the next decoding process.

[0034] The decoding process described above involves a TFF2 (2-output T-type flip-flop) element with one input T and two outputs O1 and O2. When the first pulse is input to port T (indicating an odd number of pulses), O1 produces an output; when the second pulse is input to T (indicating an even number of pulses), O2 produces an output, and so on. Each output port of the TFF2 can be considered as an "output on every 2," and the next TFF2 connected in series with it will output on every 4, then on every 8, and so on. Each TFF2 causes the corresponding NDRO to produce an output according to its binary bit order. TFF2s and NDROs with higher bit orders will generate more pulses, thus realizing the decoding process and decoding the binary sequence in NDRO into a decimal pulse count. The storage function of NDRO is reflected in the fact that NDRO is a non-volatile storage element. When its state is 1, applying a pulse to the RD port will cause NDRO to output a pulse, and state 1 will not be cleared.

[0035] Figure 3The WRspice simulation waveform of a 4-bit synaptic circuit is shown, with all four NDRO states of the core module set to '1'. The pulse sequence at the top of the diagram represents the circuit's input clock signal. The In port receives the pulse signal from the presynaptic neuron, and the Do port (the O port of the first NDRO) is used to generate the decoded pulse sequence. The sequence contains a total of 2... n The circuit generates a number of pulses, where n represents the NDRO level in the synaptic circuit, meaning the circuit has n-bit precision. Ports O0 to O3 generate the corresponding number of pulses in binary order, and the Out port outputs the pulse sequence corresponding to the current weight.

[0036] Figure 4 Simulated waveforms are shown demonstrating the interruption of the synaptic decoding process when the postsynaptic neuron reaches a threshold. Directly applying a pulse to the End port (i.e., the R port of the first NDRO) to interrupt the decoding process of the synaptic module is not feasible because the TFF2 sequence may not be in its initial state, which could affect the next stage of decoding. Therefore, in this design, the pulse sequence is truncated at output, while allowing the TFF2 sequence to continue working until the current decoding process is complete. After the TFF2 sequence completes its decoding process, it returns to its initial state without affecting the next stage of decoding.

[0037] 2. Synaptic circuit design based on T1FF and NDRO sequences:

[0038] Figure 5 This paper presents another synaptic circuit design based on T1FF and NDRO sequences. Compared to the previous design, this design uses a T1FF with destructive readout functionality as the module for generating the decoding pulse sequence. In this design, the control module only requires one NDRO unit. The Rst port receives pulses emitted by the postsynaptic neuron to interrupt the decoding process and read out the state saved by the T1FF to prevent it from affecting the next stage of the decoding process. Simultaneously, the last-stage T1FF also generates a pulse signal to terminate the decoding process; if the state of the T1FF sequence is non-zero, it can also restore it to its initial state. This design saves on the consumption of NDRO units, but its disadvantage is that the uniformity of the pulse sequence generated at the Out port is not as good as the previous synaptic scheme. This is because adjacent NDROs execute decoding on the same clock. To avoid the output pulse sequence being too dense, a delay module can be inserted between the output ports O0 and On-1 of the NDRO sequence to disperse the pulse sequence.

[0039] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A digital synaptic circuit based on a superconducting fast single-flux quantum logic gate, characterized in that, include: The control module is used to receive clock signals and pulse sequences from presynaptic neurons, and to control the generation of weight sequences; A TFF2 flip-flop sequence consisting of two cascaded output T flip-flops, which receives the pulse sequence for decoding the non-destructive readout NDRO sequence of stored weight data; An NDRO sequence cascaded from NDRO is used to store weight data; The synapse configuration module is connected to the set and reset terminals of each NDRO in the NDRO sequence. The odd-numbered output ports of the two-output T-type flip-flops are connected to the corresponding NDRO in the NDRO sequence, and the even-numbered output ports of the two-output T-type flip-flops are connected to the next stage flip-flop. The even-numbered output ports of the last stage two-output T-type flip-flops in the flip-flop sequence generate a termination signal to the control module. The pulses output by each NDRO in the NDRO sequence are combined to obtain a combined pulse.

2. The digital synaptic circuit based on superconducting fast single-flux quantum logic gates as described in claim 1, characterized in that, The control module includes a first NDRO and a second NDRO; The set port of the first NDRO receives the pulse sequence of the presynaptic neuron, the RD port of the first NDRO is connected to the clock signal, the output of the first NDRO sends the pulse sequence for decoding to the trigger sequence, and the reset port of the first NDRO is used to receive the termination signal. The set port of the second NDRO receives the pulse sequence of the presynaptic neuron; the RD port of the second NDRO receives the merged pulse output by the NDRO sequence; the reset port of the second NDRO is used to interrupt the generation of the decoding sequence; and the output terminal of the second NDRO outputs the final output sequence.

3. The digital synaptic circuit based on superconducting fast single-flux quantum logic gates as described in claim 1, characterized in that, In the NDRO sequence, the RD port of each NDRO is connected to the odd-numbered output port of its corresponding trigger. The output port of each NDRO in the NDRO sequence is connected to the input of the combiner, and the output of the combiner outputs the combined pulse.

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