Display driving circuit

Abstract

The present application provides a display driving circuit for driving a cholesteric liquid crystal display panel including (m*n) sub-pixels arranged as m rows of sub-pixels and n columns of sub-pixels. The display driving circuit includes first and second data drivers, and first and second scan drivers. The first data driver is coupled to the m rows of sub-pixels respectively and outputs image data to the m rows of sub-pixels. The first scan driver is coupled to the m rows of sub-pixels respectively and scans the m rows of sub-pixels. The second data driver is coupled to the n columns of sub-pixels respectively and outputs image data to the n columns of sub-pixels. The second scan driver is coupled to the n columns of sub-pixels respectively and scans the n columns of sub-pixels. When the cholesteric liquid crystal display panel operates in a reset mode, the m rows of sub-pixels and the n columns of sub-pixels are reset in a time-division and / or zone-division manner.

Description

Technical Field

[0001] This invention relates to display driving, and more particularly to a display driving circuit for driving a cholesteric liquid crystal display panel. Background Technology

[0002] Generally, color cholesteric liquid crystal display panels require a three-layer stacked structure consisting of a red (R) layer, a green (G) layer, and a blue (B) layer. Therefore, as... Figure 1 As shown, the display driving circuit 1 used to drive the cholesterol liquid crystal display panel PL includes a first row driver CD1, a second row driver CD2, a third row driver CD3, a first column driver RD1, a second column driver RD2, and a third column driver RD3.

[0003] The first row driver CD1 and the first column driver RD1 are used to drive the sub-pixel rows and sub-pixel columns corresponding to the red (R) layer of the cholesteric liquid crystal display panel PL, respectively; the second row driver CD2 and the second column driver RD2 are used to drive the sub-pixel rows and sub-pixel columns of the green (G) layer of the cholesteric liquid crystal display panel PL, respectively; and the third row driver CD3 and the third column driver RD3 are used to drive the sub-pixel rows and sub-pixel columns of the blue (B) layer of the cholesteric liquid crystal display panel PL, respectively.

[0004] like Figure 2 and Figure 3 As shown, when a traditional cholesteric liquid crystal display panel (PL) operates in reset mode, a large voltage jump is required to complete the reset of the cholesteric liquid crystal. The red (R), green (G), and blue (B) layers of the cholesteric liquid crystal display panel PL all need to receive the reset voltage RES simultaneously for reset. As a result, the traditional cholesteric liquid crystal display panel PL will generate an excessively large inrush current in reset mode, which urgently needs to be improved. Summary of the Invention

[0005] Therefore, the present invention proposes a display driving circuit to effectively solve the above-mentioned problems encountered by the prior art.

[0006] A preferred embodiment of the present invention is a display driving circuit. In this embodiment, the display driving circuit is used to drive a cholesteric liquid crystal display panel. The cholesteric liquid crystal display panel includes (m*n) sub-pixels. The (m*n) sub-pixels are arranged in m rows and n columns. The display driving circuit includes: a first data driver coupled to the m rows of sub-pixels for outputting image data to the m rows of sub-pixels; a first scan driver coupled to the m rows of sub-pixels for scanning the m rows of sub-pixels; a second data driver coupled to the n columns of sub-pixels for outputting image data to the n columns of sub-pixels; and a second scan driver coupled to the n columns of sub-pixels for scanning the n columns of sub-pixels; wherein, when the cholesteric liquid crystal display panel is operating in reset mode, the m rows of sub-pixels and the n columns of sub-pixels are reset in a time-division and / or partition manner.

[0007] In one embodiment, when the m-row sub-pixels and the n-column sub-pixels are reset in a time-division manner, the reset times of the m-row sub-pixels and the n-column sub-pixels receiving the reset voltage are staggered.

[0008] In one embodiment, a steady-state voltage can be increased after the m-row sub-pixels and n-column sub-pixels have been reset.

[0009] In one embodiment, when the m-row sub-pixels and the n-column sub-pixels are reset in a partitioned manner, the m-row sub-pixels and the n-column sub-pixels receive reset voltages sequentially at different reset times along the vertical or horizontal direction.

[0010] In one embodiment, a steady-state voltage can be increased after the m-row sub-pixels and n-column sub-pixels have been reset.

[0011] In one embodiment, when the m-row sub-pixels and the n-column sub-pixels are reset in a time-division and partitioned manner, the reset times of the m-row sub-pixels and the n-column sub-pixels receiving the reset voltage are staggered, and the m-row sub-pixels and the n-column sub-pixels receive the reset voltage sequentially at different reset times along the vertical or horizontal direction.

[0012] In one embodiment, a steady-state voltage can be increased after the m-row sub-pixels and n-column sub-pixels have been reset.

[0013] In one embodiment, the display driving circuit further includes: a memory, respectively coupled to the first data driver and the second data driver, for storing image data for access by the first data driver and the second data driver; and a control unit, respectively coupled to the memory, the first scan driver and the second scan driver, for controlling the operation of the first scan driver and the second scan driver according to the image data.

[0014] In one embodiment, the display driving circuit further includes: m first multiplexers, each coupled to the m rows of sub-pixels, each first multiplexer also coupled to a control unit, a first data driver and a first scan driver; and n second multiplexers, each coupled to the n columns of sub-pixels, each second multiplexer also coupled to a control unit, a second data driver and a second scan driver.

[0015] In one embodiment, the m rows of sub-pixels include a first row of sub-pixels, a second row of sub-pixels, and a third row of sub-pixels. The first row of sub-pixels, the second row of sub-pixels, and the third row of sub-pixels receive reset voltages at a first reset time, a second reset time, and a third reset time, respectively. The first reset time, the second reset time, and the third reset time do not overlap with each other.

[0016] In one embodiment, the n columns of sub-pixels include a first column of sub-pixels, a second column of sub-pixels, and a third column of sub-pixels. The first column of sub-pixels, the second column of sub-pixels, and the third column of sub-pixels receive reset voltages at a first reset time, a second reset time, and a third reset time, respectively. The first reset time, the second reset time, and the third reset time do not overlap with each other.

[0017] Compared to existing technologies, when the display driving circuit of this invention drives the cholesteric liquid crystal display panel to operate in reset mode, the multi-row sub-pixels and multi-column sub-pixels of the cholesteric liquid crystal display panel are reset in a time-division and / or partition manner. That is, the reset modes are staggered in time and / or space to avoid generating excessive inrush current instantaneously. In addition, when the cholesteric liquid crystal display panel operates in reset mode, it scans sequentially along the horizontal / vertical direction, and a stable phase voltage can be applied after the reset mode ends to stabilize the display image. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a traditional display driver circuit driving a cholesterol liquid crystal display panel.

[0019] Figure 2 This is a timing diagram showing the reset voltage received by the first row of sub-pixels, the second row of sub-pixels, the first column of sub-pixels, and the second column of sub-pixels in a traditional cholesterol liquid crystal display panel, as well as the voltage difference between the sub-pixel column and the sub-pixel row.

[0020] Figure 3 This is a timing diagram showing how a traditional cholesterol liquid crystal display panel simultaneously receives a reset voltage on its red (R) layer, green (G) layer, and blue (B) layer, resulting in an excessively large surge current.

[0021] Figure 4 This is a schematic diagram of a display driving circuit driving a cholesterol liquid crystal display panel in a preferred embodiment of the present invention.

[0022] Figure 5 This is a timing diagram showing that the first row of sub-pixels, the second row of sub-pixels, the first column of sub-pixels, and the second column of sub-pixels in the cholesterol liquid crystal display panel of the present invention receive a stable phase voltage and a voltage difference between the sub-pixel column and the sub-pixel row after receiving a reset voltage.

[0023] Figure 6 This is a timing diagram showing the red (R) layer, green (G) layer, and blue (B) layer of the cholesterol liquid crystal display panel of the present invention receiving reset voltages at different times and then receiving stable phase voltages.

[0024] Figure 7 This is a timing diagram showing the spatial reset of the first row sub-pixels, second row sub-pixels, first column sub-pixels, and second column sub-pixels of the cholesterol liquid crystal display panel of the present invention, when they receive reset voltage or non-reset voltage, and the voltage difference between the sub-pixel column and the sub-pixel row.

[0025] Figure 8 This is a schematic diagram of a cholesterol liquid crystal display panel scanning sequentially in the vertical direction when operating in reset mode.

[0026] Figure 9 This is a schematic diagram of a cholesterol liquid crystal display panel scanning sequentially in the horizontal direction when operating in reset mode.

[0027] Figure 10 This is a timing diagram showing the first row of sub-pixels, the second row of sub-pixels, the first column of sub-pixels, and the second column of sub-pixels in the cholesterol liquid crystal display panel of the present invention receiving a reset voltage or a non-reset voltage for spatial reset, as well as receiving a stable phase voltage and the voltage difference between the sub-pixel column and the sub-pixel row.

[0028] Figure 11 This is a timing diagram showing how the red (R) layer, green (G) layer, and blue (B) layer of the cholesterol liquid crystal display panel of the present invention receive a stable phase voltage after being spatially reset by a reset voltage or a non-reset voltage.

[0029] 1… Display driver circuit

[0030] CD1~CD3… First row drive~Third row drive RD1~RD3… First column driver~Third column driver C1~Cm…m row sub-pixels R1~Rn…n columns of sub-pixels PL… panel RES…Reset Voltage DIF…voltage difference 4… Display driver circuit IM… Memory CPU…control unit PL… panel DD1…First Data Drive DD2…Second Data Drive SD1…First Scan Drive SD2…Second Scan Drive M11~M1m…First Multiplexer M21~M2n…Second Multiplexer C1~Cm…m row sub-pixels R1~Rn…n columns of sub-pixels t0~t15…time R1(R)...The first column of subpixels in the red layer R1(G)...The first column of subpixels in the green layer R1(B)...The first column of subpixels in the blue layer C1(R)...First row of subpixels of the red layer C1(G)...First row of subpixels in the green layer C1(B)...First row of subpixels in the blue layer DIF(R)...Voltage difference of the red layer DIF(G)...Voltage difference of the green layer DIF(B)...Voltage difference of the blue layer CTL… control signal DAT…Image Data VST…Stable phase voltage NRES…Non-reset voltage DIO... Digital Input / Output Signals STB…Digital Video Conversion Signal COL… line ROW…column VRES…vertical direction HRES…Horizontal direction Detailed Implementation

[0031] A preferred embodiment of the present invention is a display driving circuit. In this embodiment, the display driving circuit is used to drive a cholesteric liquid crystal display panel, so that when the cholesteric liquid crystal display panel is operating in reset mode, the multi-row sub-pixels and multi-column sub-pixels of the cholesteric liquid crystal display panel are reset in a time-division and / or partition manner to avoid generating excessive surge current instantaneously, and a stable phase voltage can be added after the reset mode to stabilize the display screen.

[0032] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the display driving circuit 4 driving the cholesteric liquid crystal display panel PL in this embodiment. Figure 4As shown, the cholesterol liquid crystal display panel PL includes (m*n) sub-pixels arranged in m rows of sub-pixels C1~Cm and n columns of sub-pixels R1~Rn. The display driving circuit 4 includes a memory IM, a control unit CPU, a first data driver DD1, a first scan driver SD1, a second data driver DD2, a second scan driver SD2, m first multiplexers M11~M1m, and n second multiplexers M21~M2n.

[0033] The memory IM is coupled to the first data driver DD1 and the second data driver DD2 respectively, and is used to store image data DAT for access by the first data driver DD1 and the second data driver DD2. The control unit CPU is coupled to the memory IM, the first scan driver SD1 and the second scan driver SD2 respectively, and is used to issue control signals CTL according to the image data DAT to control the operation of the first scan driver SD1 and the second scan driver SD2.

[0034] m first multiplexers M11~M1m are respectively coupled to the m rows of sub-pixels C1~Cm. Each first multiplexer M11~M1m is also respectively coupled to the control unit CPU, the first data driver DD1, and the first scan driver SD1. n second multiplexers M21~M2n are respectively coupled to the n columns of sub-pixels R1~Rn. Each second multiplexer M21~M2n is also respectively coupled to the control unit CPU, the second data driver DD2, and the second scan driver SD2.

[0035] The first data driver DD1 is coupled to each of the m rows of sub-pixels C1~Cm, and is used to output image data to the m rows of sub-pixels C1~Cm. The first scan driver SD1 is coupled to each of the m rows of sub-pixels C1~Cm, and is used to scan the m rows of sub-pixels C1~Cm. The second data driver DD2 is coupled to each of the n columns of sub-pixels R1~Rn, and is used to output image data to the n columns of sub-pixels R1~Rn. The second scan driver SD2 is coupled to each of the n columns of sub-pixels R1~Rn, and is used to scan the n columns of sub-pixels R1~Rn.

[0036] It should be noted that when the display driving circuit 4 of the present invention drives the cholesterol liquid crystal display panel PL to operate in the Reset mode, the m-row sub-pixels C1~Cm and the n-column sub-pixels R1~Rn are reset in a time-division and / or partition manner.

[0037] In one embodiment, when the display driving circuit 4 drives the m-row sub-pixels C1~Cm and the n-column sub-pixels R1~Rn of the cholesteric liquid crystal display panel PL to be reset in a time-division multiplexing manner, the reset times of the m-row sub-pixels C1~Cm and the n-column sub-pixels R1~Rn receiving the reset voltage will be staggered, but this is not a limitation. Furthermore, after the m-row sub-pixels C1~Cm and the n-column sub-pixels R1~Rn have completed the reset, a steady-state voltage can be increased to stabilize the display image, but this is not a limitation either.

[0038] In another embodiment, when the display driving circuit 4 drives the m-row sub-pixels C1~Cm and the n-column sub-pixels R1~Rn of the cholesteric liquid crystal display panel PL to be reset in a partitioned manner, the m-row sub-pixels C1~Cm and the n-column sub-pixels R1~Rn receive reset voltages sequentially at different reset times along the vertical or horizontal direction, but this is not a limitation. Furthermore, after the m-row sub-pixels C1~Cm and the n-column sub-pixels R1~Rn have completed their reset, a steady-state voltage can be increased to stabilize the display image, but this is not a limitation either.

[0039] In another embodiment, when the display driving circuit 4 drives the m-row sub-pixels C1~Cm and the n-column sub-pixels R1~Rn of the cholesteric liquid crystal display panel PL to reset in a time-division and partition manner, the reset times of the m-row sub-pixels C1~Cm and the n-column sub-pixels R1~Rn receiving the reset voltage are staggered, and the m-row sub-pixels C1~Cm and the n-column sub-pixels R1~Rn receive the reset voltage sequentially at different reset times along the vertical or horizontal direction, but this is not a limitation. Furthermore, after the m-row sub-pixels C1~Cm and the n-column sub-pixels R1~Rn have completed the reset, a steady-state voltage can be increased to stabilize the display image, but this is not a limitation.

[0040] Please refer to Figure 5 , Figure 5 This is a timing diagram showing the first row sub-pixels C1, the second row sub-pixels C2, the first column sub-pixels R1, and the second column sub-pixels R2 of a cholesterol liquid crystal display panel PL receiving a stabilizing phase voltage VST after receiving a reset voltage RES to stabilize the display image, as well as the voltage difference DIF between sub-pixel columns R1~R2 and sub-pixel rows C1~C2.

[0041] like Figure 5As shown, during the time period from t0 to t1, the first column sub-pixel R1 and the second column sub-pixel R2 respectively receive a reset voltage of -22V RES, and the first row sub-pixel C1 and the second row sub-pixel C2 respectively receive a reset voltage of 22V RES. Therefore, the voltage difference DIF between the first column sub-pixel R1 and the first row sub-pixel C1, between the first column sub-pixel R1 and the second row sub-pixel C2, between the second column sub-pixel R2 and the first row sub-pixel C1, and between the second column sub-pixel R2 and the second row sub-pixel C2 is -44V during the time period from t0 to t1.

[0042] During the period from time t1 to t2, the first column sub-pixel R1 and the second column sub-pixel R2 each receive a reset voltage RES of 22V, and the first row sub-pixel C1 and the second row sub-pixel C2 each receive a reset voltage RES of -22V. Therefore, the voltage difference DIF between the first column sub-pixel R1 and the first row sub-pixel C1, between the first column sub-pixel R1 and the second row sub-pixel C2, between the second column sub-pixel R2 and the first row sub-pixel C1, and between the second column sub-pixel R2 and the second row sub-pixel C2 is 44V during the period from time t1 to t2. The situation during the period from time t2 to t6 can be deduced in the same way, and will not be elaborated further here.

[0043] After the reset is complete, during the period from t6 to t7, the first column sub-pixel R1 and the second column sub-pixel R2 each receive a stable phase voltage VST of 5V, and the first row sub-pixel C1 and the second row sub-pixel C2 each receive a stable phase voltage VST of -5V to stabilize the display. Therefore, the voltage difference DIF between the first column sub-pixel R1 and the first row sub-pixel C1, between the first column sub-pixel R1 and the second row sub-pixel C2, between the second column sub-pixel R2 and the first row sub-pixel C1, and between the second column sub-pixel R2 and the second row sub-pixel C2 is 10V during the period from t6 to t7. The situation during the period from t7 to t12 can be deduced similarly, and will not be elaborated further here.

[0044] Please refer to Figure 6 , Figure 6 This is a timing diagram showing that the first column sub-pixels R1(R), R1(G), R1(B) and the first row sub-pixels C1(R), C1(G), C1(B) of the red (R) layer, green (G) layer and blue (B) layer of the cholesterol liquid crystal display panel PL of the present invention receive a reset voltage RES at different times and then receive a stable phase voltage VST.

[0045] like Figure 6As shown, during the time period from t1 to t2, the first column sub-pixel R1(R) and the first row sub-pixel C1(R) corresponding to the red (R) layer of the cholesterol liquid crystal display panel PL receive reset voltages RES of -22V and 22V respectively, so that the voltage difference DIF(R) between the first column sub-pixel R1(R) and the first row sub-pixel C1(R) is -44V during the time period from t2 to t5.

[0046] During the period from time t2 to t3, the first column sub-pixel R1(G) and the first row sub-pixel C1(G) of the green (G) layer of the cholesterol liquid crystal display panel PL receive reset voltages RES of -22V and 22V respectively, so that the voltage difference DIF(G) between the first column sub-pixel R1(G) and the first row sub-pixel C1(G) is -44V during the period from time t3 to t6.

[0047] During the period from time t3 to t4, the first column sub-pixel R1(B) and the first row sub-pixel C1(B) of the blue (B) layer of the cholesterol liquid crystal display panel PL receive reset voltages RES of -22V and 22V respectively, so that the voltage difference DIF(B) between the first column sub-pixel R1(B) and the first row sub-pixel C1(B) is -44V during the period from time t4 to t7.

[0048] As can be seen from the above: assuming that the time period t1 to t2 during which the first column sub-pixel R1(R) and the first row sub-pixel C1(R) of the red (R) layer corresponding to the cholesterol liquid crystal display panel PL receive the reset voltage RES is defined as the first reset time, the time period t2 to t3 during which the first column sub-pixel R1(G) and the first row sub-pixel C1(G) of the green (G) layer corresponding to the cholesterol liquid crystal display panel PL receive the reset voltage RES is defined as the second reset time, and the time period t3 to t4 during which the first column sub-pixel R1(B) and the first row sub-pixel C1(B) of the blue (B) layer corresponding to the cholesterol liquid crystal display panel PL receive the reset voltage RES is defined as the third reset time, then the first reset time, the second reset time, and the third reset time do not overlap with each other.

[0049] During the period from time t5 to t6, the first column sub-pixel R1(R) and the first row sub-pixel C1(R) corresponding to the red (R) layer of the cholesterol liquid crystal display panel PL receive reset voltages RES of 22V and -22V respectively, so that the voltage difference DIF(R) between the first column sub-pixel R1(R) and the first row sub-pixel C1(R) is 44V during the period from time t6 to t9.

[0050] During the period from time t6 to t7, the first column sub-pixel R1(G) and the first row sub-pixel C1(G) of the green (G) layer of the cholesterol liquid crystal display panel PL receive reset voltages RES of 22V and -22V respectively, so that the voltage difference DIF(G) between the first column sub-pixel R1(G) and the first row sub-pixel C1(G) is 44V during the period from time t7 to t9.

[0051] During the period from time t7 to t8, the first column sub-pixel R1(B) and the first row sub-pixel C1(B) of the blue (B) layer of the cholesterol liquid crystal display panel PL receive reset voltages RES of 22V and -22V respectively, so that the voltage difference DIF(B) between the first column sub-pixel R1(B) and the first row sub-pixel C1(B) is 44V during the period from time t8 to t9.

[0052] During the period from time t9 to t10, the first column sub-pixels R1(R), R1(G), and R1(B) corresponding to the red (R), green (G), and blue (B) layers of the liquid crystal display panel PL, respectively, simultaneously receive a stable phase voltage VST of 5V, and the first row sub-pixels C1(R), C1(G), and C1(B) corresponding to the red (R), green (G), and blue (B) layers of the liquid crystal display panel PL, respectively, simultaneously receive a stable phase voltage VST of -5V. This ensures that during the period from time t10 to t11, the voltage difference DIF(R) between the first column sub-pixel R1(R) and the first row sub-pixel C1(R), the voltage difference DIF(G) between the first column sub-pixel R1(G) and the first row sub-pixel C1(G), and the voltage difference DIF(B) between the first column sub-pixel R1(B) and the first row sub-pixel C1(B) are all 10V, thereby achieving a stable display effect.

[0053] Please refer to Figure 7 , Figure 7 This is a timing diagram showing the spatial reset of the first row sub-pixels C1, the second row sub-pixels C2, the first column sub-pixels R1, and the second column sub-pixels R2 of the cholesterol liquid crystal display panel PL of the present invention, when they receive a reset voltage RES or a non-reset voltage NRES, and the voltage difference DIF between sub-pixel columns R1~R2 and sub-pixel rows C1~C2.

[0054] like Figure 7As shown, during the time period from t0 to t1, the first column sub-pixel R1 and the second column sub-pixel R2 respectively receive a reset voltage of -22V RES, and the first row sub-pixel C1 and the second row sub-pixel C2 respectively receive a reset voltage of 22V RES. Therefore, the voltage difference DIF between the first column sub-pixel R1 and the first row sub-pixel C1, between the first column sub-pixel R1 and the second row sub-pixel C2, between the second column sub-pixel R2 and the first row sub-pixel C1, and between the second column sub-pixel R2 and the second row sub-pixel C2 is -44V during the time period from t0 to t1.

[0055] During the time interval t1 to t2, the first column sub-pixel R1 and the second column sub-pixel R2 each receive a reset voltage RES of 22V, and the first row sub-pixel C1 and the second row sub-pixel C2 each receive a reset voltage RES of -22V. Therefore, the voltage difference DIF between the first column sub-pixel R1 and the first row sub-pixel C1, between the first column sub-pixel R1 and the second row sub-pixel C2, between the second column sub-pixel R2 and the first row sub-pixel C1, and between the second column sub-pixel R2 and the second row sub-pixel C2 is 44V during the time interval t1 to t2.

[0056] During the time interval t2 to t3, the first column sub-pixel R1 and the second column sub-pixel R2 each receive a non-reset voltage NRES of 22V, and the first row sub-pixel C1 and the second row sub-pixel C2 each receive a reset voltage RES of 22V. Therefore, the voltage difference DIF between the first column sub-pixel R1 and the first row sub-pixel C1, between the first column sub-pixel R1 and the second row sub-pixel C2, between the second column sub-pixel R2 and the first row sub-pixel C1, and between the second column sub-pixel R2 and the second row sub-pixel C2 is 0V during the time interval t2 to t3.

[0057] During the period from time t3 to t4, the first column sub-pixel R1 and the second column sub-pixel R2 each receive a non-reset voltage NRES of -22V, and the first row sub-pixel C1 and the second row sub-pixel C2 each receive a reset voltage RES of -22V. Therefore, the voltage difference DIF between the first column sub-pixel R1 and the first row sub-pixel C1, between the first column sub-pixel R1 and the second row sub-pixel C2, between the second column sub-pixel R2 and the first row sub-pixel C1, and between the second column sub-pixel R2 and the second row sub-pixel C2 is 0V during the period from time t3 to t4. The situation during the period from time t4 to t6 is the same as that during the period from time t2 to t4, and will not be described further here.

[0058] Please refer to the following respectively Figure 8 and Figure 9 .like Figure 8 and Figure 9As shown, when the cholesterol liquid crystal display panel is operating in reset mode, it can scan sequentially along the vertical VRES direction or sequentially along the horizontal HRES direction, without any specific limitation. Figure 8 When the multi-row sub-pixels ROW1~ROW960 of the cholesteric liquid crystal display panel are reset in a partitioned manner, the multi-row sub-pixels ROW1~ROW960 can be divided into multiple regions along the vertical direction VRES, for example, marked with diagonal lines or black. The sub-pixels of these multiple regions receive reset voltages sequentially at different reset times, but are not limited to this. When Figure 9 When the multi-row sub-pixels COL1~COL1280 of the cholesterol liquid crystal display panel are reset in a partitioned manner, the multi-row sub-pixels COL1~COL1280 can be divided into multiple regions along the horizontal direction HRES, for example, marked with diagonal lines or black. The sub-pixels of these multiple regions receive the reset voltage sequentially at different reset times, but are not limited to this.

[0059] Please refer to Figure 10 , Figure 10 This is a timing diagram of the first row sub-pixels C1, the second row sub-pixels C2, the first column sub-pixels R1, and the second column sub-pixels R2 of the cholesterol liquid crystal display panel PL of the present invention. After receiving a spatial reset voltage RES or a non-reset voltage NRES, they also receive a stable phase voltage VST and the voltage difference DIF between sub-pixel columns R1~R2 and sub-pixel rows C1~C2.

[0060] like Figure 10 As shown, during the time period from t0 to t1, the first column sub-pixel R1 and the second column sub-pixel R2 respectively receive a reset voltage RES of -22V, and the first row sub-pixel C1 and the second row sub-pixel C2 respectively receive a non-reset voltage NRES of -22V. Then, the voltage difference DIF between the first column sub-pixel R1 and the first row sub-pixel C1, between the first column sub-pixel R1 and the second row sub-pixel C2, between the second column sub-pixel R2 and the first row sub-pixel C1, and between the second column sub-pixel R2 and the second row sub-pixel C2 is 0V during the time period from t0 to t1.

[0061] During the period from time t1 to t2, the first column sub-pixel R1 and the second column sub-pixel R2 each receive a reset voltage RES of 22V, and the first row sub-pixel C1 and the second row sub-pixel C2 each receive a non-reset voltage NRES of 22V. Therefore, the voltage difference DIF between the first column sub-pixel R1 and the first row sub-pixel C1, between the first column sub-pixel R1 and the second row sub-pixel C2, between the second column sub-pixel R2 and the first row sub-pixel C1, and between the second column sub-pixel R2 and the second row sub-pixel C2 is 0V during the period from time t1 to t2. The situation during the period from time t2 to t4 can be deduced similarly, and will not be elaborated upon here.

[0062] During time t4 to t5, the first column sub-pixel R1 and the second column sub-pixel R2 each receive a reset voltage RES of -22V, and the first row sub-pixel C1 and the second row sub-pixel C2 each receive a reset voltage RES of 22V. Therefore, the voltage difference DIF between the first column sub-pixel R1 and the first row sub-pixel C1, between the first column sub-pixel R1 and the second row sub-pixel C2, between the second column sub-pixel R2 and the first row sub-pixel C1, and between the second column sub-pixel R2 and the second row sub-pixel C2 is -44V during time t4 to t5.

[0063] During time t5 to t6, the first column sub-pixel R1 and the second column sub-pixel R2 each receive a reset voltage RES of 22V, and the first row sub-pixel C1 and the second row sub-pixel C2 each receive a reset voltage RES of -22V, so that the voltage difference DIF between the first column sub-pixel R1 and the first row sub-pixel C1, between the first column sub-pixel R1 and the second row sub-pixel C2, between the second column sub-pixel R2 and the first row sub-pixel C1, and between the second column sub-pixel R2 and the second row sub-pixel C2 is 44V during time t5 to t6.

[0064] After the reset mode ends, during the period from time t6 to t7, the first column sub-pixel R1 and the second column sub-pixel R2 respectively receive a stable phase voltage VST of 5V, and the first row sub-pixel C1 and the second row sub-pixel C2 respectively receive a stable phase voltage VST of -5V. This ensures that the voltage difference DIF between the first column sub-pixel R1 and the first row sub-pixel C1, between the first column sub-pixel R1 and the second row sub-pixel C2, between the second column sub-pixel R2 and the first row sub-pixel C1, and between the second column sub-pixel R2 and the second row sub-pixel C2 is 10V during the period from time t6 to t7, thereby achieving a stable display effect.

[0065] During the period from time t7 to t8, the first column sub-pixel R1 and the second column sub-pixel R2 each receive a stable phase voltage VST of -5V, and the first row sub-pixel C1 and the second row sub-pixel C2 each receive a stable phase voltage VST of 5V. This ensures that the voltage difference DIF between the first column sub-pixel R1 and the first row sub-pixel C1, between the first column sub-pixel R1 and the second row sub-pixel C2, between the second column sub-pixel R2 and the first row sub-pixel C1, and between the second column sub-pixel R2 and the second row sub-pixel C2 is -10V during the period from time t7 to t8, thus achieving a stable display effect. The situation during the period from time t8 to t12 can be deduced similarly, and will not be elaborated further here.

[0066] Please refer to Figure 11 , Figure 11This is a schematic diagram showing that the red (R) layer, green (G) layer, and blue (B) layer of the cholesterol liquid crystal display panel PL of the present invention receive a reset voltage RES or a non-reset voltage NRES, and then receive a stable phase voltage VST.

[0067] like Figure 11 As shown, during the period from time t1 to t2, the first column sub-pixel R1(R) and the first row sub-pixel C1(R) corresponding to the red (R) layer of the cholesterol liquid crystal display panel PL receive reset voltages RES of -22V and 22V respectively, resulting in a voltage difference DIF(R) of -44V between the first column sub-pixel R1(R) and the first row sub-pixel C1(R) during the period from time t2 to t5. During the period from time t5 to t8, the first column sub-pixel R1(R) and the first row sub-pixel C1(R) receive a reset voltage RES of -22V and a non-reset voltage NRES of -22V respectively, resulting in a voltage difference DIF(R) of 0V between the first column sub-pixel R1(R) and the first row sub-pixel C1(R).

[0068] During the period from time t2 to t3, the first column sub-pixel R1(G) and the first row sub-pixel C1(G) of the green (G) layer of the cholesteric liquid crystal display panel PL receive reset voltages RES of -22V and 22V respectively, resulting in a voltage difference DIF(G) of -44V between the first column sub-pixel R1(G) and the first row sub-pixel C1(G) during the period from time t3 to t6. During the period from time t6 to t9, the first column sub-pixel R1(G) and the first row sub-pixel C1(G) receive a reset voltage RES of -22V and a non-reset voltage NRES of -22V respectively, resulting in a voltage difference DIF(G) of 0V between the first column sub-pixel R1(G) and the first row sub-pixel C1(G).

[0069] During the period from time t3 to t4, the first column sub-pixel R1(B) and the first row sub-pixel C1(B) of the blue (B) layer of the cholesteric liquid crystal display panel PL receive reset voltages RES of -22V and 22V respectively, resulting in a voltage difference DIF(B) of -44V between the first column sub-pixel R1(B) and the first row sub-pixel C1(B) during the period from time t4 to t7. During the period from time t7 to t10, the first column sub-pixel R1(B) and the first row sub-pixel C1(B) receive a reset voltage RES of -22V and a non-reset voltage NRES of -22V respectively, resulting in a voltage difference DIF(B) of 0V between the first column sub-pixel R1(B) and the first row sub-pixel C1(B).

[0070] As can be seen from the above: assuming that the time period t1 to t2 during which the first column sub-pixel R1(R) and the first row sub-pixel C1(R) of the red (R) layer corresponding to the cholesterol liquid crystal display panel PL receive the reset voltage RES is defined as the first reset time, the time period t2 to t3 during which the first column sub-pixel R1(G) and the first row sub-pixel C1(G) of the green (G) layer corresponding to the cholesterol liquid crystal display panel PL receive the reset voltage RES is defined as the second reset time, and the time period t3 to t4 during which the first column sub-pixel R1(B) and the first row sub-pixel C1(B) of the blue (B) layer corresponding to the cholesterol liquid crystal display panel PL receive the reset voltage RES is defined as the third reset time, then the first reset time, the second reset time, and the third reset time do not overlap with each other.

[0071] During the period from time t8 to t9, the first column sub-pixel R1(R) and the first row sub-pixel C1(R) corresponding to the red (R) layer of the cholesterol liquid crystal display panel PL receive a reset voltage RES of 22V and a non-reset voltage NRES of 22V, respectively, so that the voltage difference DIF(R) between the first column sub-pixel R1(R) and the first row sub-pixel C1(R) is 0V during the period from time t9 to t12. During the period from time t12 to t13, the first column sub-pixel R1(R) and the first row sub-pixel C1(R) receive reset voltages RES of -22V and 22V, respectively, so that the voltage difference DIF(R) between the first column sub-pixel R1(R) and the first row sub-pixel C1(R) is -44V during the period from time t12 to t13.

[0072] During the period from time t9 to t10, the first column sub-pixel R1(G) and the first row sub-pixel C1(G) of the green (G) layer of the cholesteric liquid crystal display panel PL receive a reset voltage RES of 22V and a non-reset voltage NRES of 22V, respectively, so that the voltage difference DIF(G) between the first column sub-pixel R1(G) and the first row sub-pixel C1(G) is 0V during the period from time t10 to t12. During the period from time t12 to t13, the first column sub-pixel R1(G) and the first row sub-pixel C1(G) receive reset voltages RES of -22V and 22V, respectively, so that the voltage difference DIF(G) between the first column sub-pixel R1(G) and the first row sub-pixel C1(G) is -44V during the period from time t12 to t13.

[0073] During the period from time t10 to t11, the first column sub-pixel R1(B) and the first row sub-pixel C1(B) corresponding to the blue (B) layer of the cholesterol liquid crystal display panel PL receive a reset voltage RES of 22V and a non-reset voltage NRES of 22V, respectively, so that the voltage difference DIF(B) between the first column sub-pixel R1(B) and the first row sub-pixel C1(B) is 0V during the period from time t11 to t12. During the period from time t12 to t13, the first column sub-pixel R1(B) and the first row sub-pixel C1(B) receive reset voltages RES of -22V and 22V, respectively, so that the voltage difference DIF(B) between the first column sub-pixel R1(B) and the first row sub-pixel C1(B) is -44V during the period from time t12 to t13.

[0074] During the period from time t13 to t14, the first column sub-pixels R1(R), R1(G), and R1(B) receive a stable phase voltage VST of 5V, and the first row sub-pixels C1(R), C1(G), and C1(B) receive a stable phase voltage VST of -5V. This ensures that the voltage difference DIF between the first column sub-pixels R1(R) and the first row sub-pixels C1(R), between the first column sub-pixels R1(G) and the first row sub-pixels C1(G), and between the first column sub-pixels R1(B) and the first row sub-pixels C1(B) is 10V during the period from time t14 to t15, thereby achieving a stable display effect.

[0075] Compared to existing technologies, when the display driving circuit of this invention drives the cholesteric liquid crystal display panel to operate in reset mode, the multi-row sub-pixels and multi-column sub-pixels of the cholesteric liquid crystal display panel are reset in a time-division and / or partition manner. That is, the reset modes are staggered in time and / or space to avoid generating excessive surge current instantaneously. In addition, when the cholesteric liquid crystal display panel operates in reset mode, it scans sequentially along the horizontal / vertical direction, and a stable phase voltage can be applied after the reset mode ends to stabilize the display image.

Claims

1. A display driving circuit for driving a cholesteric liquid crystal display panel, characterized in that, The cholesterol liquid crystal display panel includes (m*n) sub-pixels, arranged in m rows and n columns. The m rows of sub-pixels include a first row, a second row, and a third row. The n columns of sub-pixels include a first column, a second column, and a third column. The first row and first column of sub-pixels correspond to a red layer of the cholesterol liquid crystal display panel, the second row and second column correspond to a green layer, and the third row and third column correspond to a blue layer. The display driving circuit includes: A first data driver is coupled to each of the m rows of sub-pixels to output image data to the m rows of sub-pixels; A first scan driver is coupled to each of the m rows of sub-pixels for scanning the m rows of sub-pixels; A second data driver, coupled to each of the n columns of sub-pixels, is used to output the image data to the n columns of sub-pixels; and A second scan driver is coupled to each of the n columns of sub-pixels for scanning the n columns of sub-pixels; When the cholesterol liquid crystal display panel operates in a reset mode, the m-row sub-pixels and n-column sub-pixels are reset in a time-division manner. The first row sub-pixels and the first column sub-pixels corresponding to the red layer receive the reset voltage at a first reset time, the second row sub-pixels and the second column sub-pixels corresponding to the green layer receive the reset voltage at a second reset time, and the third row sub-pixels and the third column sub-pixels corresponding to the blue layer receive the reset voltage at a third reset time. The first reset time, the second reset time, and the third reset time do not overlap with each other.

2. The display driving circuit as described in claim 1, characterized in that, A steady-state voltage can be added after the m-row sub-pixels and n-column sub-pixels have been reset.

3. The display driving circuit as described in claim 1, characterized in that, When the m-row sub-pixels and the n-column sub-pixels are reset in a partitioned manner, the m-row sub-pixels and the n-column sub-pixels receive reset voltages sequentially at different reset times along the vertical or horizontal direction.

4. The display driving circuit as described in claim 3, characterized in that, A steady-state voltage can be added after the m-row sub-pixels and n-column sub-pixels have been reset.

5. The display driving circuit as described in claim 1, characterized in that, Also includes: A memory, coupled to the first data driver and the second data driver respectively, is used to store the image data for access by the first data driver and the second data driver; as well as A control unit is coupled to the memory, the first scan driver and the second scan driver respectively, and is used to control the operation of the first scan driver and the second scan driver according to the image data.

6. The display driving circuit as described in claim 5, characterized in that, Also includes: m first multiplexers are respectively coupled to the m rows of sub-pixels, and each first multiplexer is also respectively coupled to the control unit, the first data driver and the first scan driver; as well as n second multiplexers are respectively coupled to the n columns of sub-pixels, and each second multiplexer is also respectively coupled to the control unit, the second data driver and the second scan driver.

Images