A gallium nitride HEMT with integrated protection structure and preparation method thereof

Abstract

The present invention provides a gallium nitride HEMT with an integrated protection structure and a preparation method thereof, wherein the HEMT comprises: a single crystal substrate, a functional device, a protection circuit and a high resistance region; the polished surface of the single crystal substrate has a functional device region and a protection circuit region, the functional device is arranged on the functional device region of the single crystal substrate, the protection circuit is arranged on the protection circuit of the single crystal substrate, and the protection circuit and the single crystal substrate, the protection circuit and the functional device are separated by a part of the high resistance region; the functional device comprises a source S, a gate G1 and a drain D, the protection circuit comprises an electrode S1, a protection module, an electrode G2, another protection module and an electrode G3 connected in sequence; each protection module is composed of a diode and a resistor in parallel, the source S is electrically connected to the electrode S1, and the gate G1 is electrically connected to the electrode G2. The HEMT integrates the functional device and the protection circuit, can release the gate charge to prevent breakdown, and also reduces the turn-off time, reduces the power consumption of the switch, and improves the overall reliability.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor components, and in particular relates to a gallium nitride HEMT with an integrated protection structure and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN) HEMTs (High Electron Mobility Transistors) with integrated protection structures are popular wide-bandgap power semiconductor devices in recent years. Compared with materials such as silicon (Si) and silicon carbide (SiC), gallium nitride (GaN) has better bandgap width, electron mobility, saturated electron velocity, breakdown electric field, and lower temperature coefficient. GaN devices have great potential in high-power, high-frequency applications.

[0003] GaN-based transistors can be categorized as normally-on and normally-off depending on their operating mode. Normally-on devices are unsuitable for power electronics because they can experience overshoot or loss of control during the turn-on process. Normally-off devices, on the other hand, can switch on and off simply through gate drive control and are widely used in power electronics. However, during operation, GaN-based transistors often fail due to sudden increases in applied current or voltage, resulting in gate overheating, damage, and breakdown.

[0004] When GaN-based HEMT devices are integrated into chips, gate overvoltage protection circuits and gate current limiting protection circuits are often added to the chip to prevent failure due to damage and breakdown. However, this configuration increases the chip's peripheral circuit area, resulting in a larger overall chip size, increasing chip manufacturing costs and reducing chip competitiveness. Although technologies exist for integrating gate protection circuits into GaN-based power semiconductor devices, these devices consume high power and have long dead times, affecting operating frequency and reliability. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a gallium nitride HEMT with an integrated protection structure and a preparation method, aiming to solve the problems of high power consumption and low reliability when the gallium nitride HEMT with an integrated protection structure is integrated into the protection circuit in the related art.

[0006] To solve the above technical problems, the present invention provides a gallium nitride HEMT with an integrated protection structure in a first aspect, comprising: a single crystal substrate, a functional device, a protection circuit, and a high resistance region;

[0007] The polished surface of the single crystal substrate comprises a functional device region and a protection circuit region, wherein the functional device is arranged on the functional device region of the single crystal substrate, and the protection circuit is arranged on the protection circuit of the single crystal substrate, and the protection circuit and the single crystal substrate, as well as the protection circuit and the functional device, are separated by a portion of the high resistance region;

[0008] The functional device includes a source S, a gate G1 and a drain D, and the protection circuit includes an electrode S1, a protection module, an electrode G2, another protection module and an electrode G3 connected in sequence; each protection module is composed of a diode and a resistor in parallel, the source S is electrically connected to the electrode S1, and the gate G1 is electrically connected to the electrode G2.

[0009] Furthermore, one of the protection modules includes a first diode and a first resistor separated by a portion of the high resistance region; another protection module includes a second resistor and a second diode separated by a portion of the high resistance region; and the two protection modules are also separated by a portion of the high resistance region;

[0010] The electrode S1 contacts the p-well region of the first diode and the first resistor; the electrode G2 contacts the n-substrate of the first diode, the first resistor, the second resistor and the p-well region of the second diode; the electrode G3 contacts the second resistor and the n-substrate of the second diode.

[0011] Furthermore, the high resistance region includes a first high resistance region, a second high resistance region, a third high resistance region, a fourth high resistance region and a fifth high resistance region;

[0012] The first high resistance region is on the protection circuit region of the single crystal substrate;

[0013] The first diode, the third high-resistance region, the first resistor, the fourth high-resistance region, the second resistor, the fifth high-resistance region, and the second diode are sequentially stacked on the first high-resistance region to form the protection module. The electrode G2 is provided on a side of the protection module close to the functional device. The second high-resistance region is provided between the electrode G2 and the functional device and is connected to the first high-resistance region.

[0014] The electrode G3 is arranged on the side wall of the second resistor, the fifth high resistance region and the second diode away from the functional device, the electrode S1 is partially arranged on the side wall of the first diode, the third high resistance region and the first resistor away from the functional device, and the fourth high resistance region is connected to an insulating wall, which separates the electrode G3 and the electrode S1.

[0015] Furthermore, the first high resistance region, the second high resistance region, the third high resistance region and the fifth high resistance region are ion-implanted GaN high resistance isolation layers with a thickness of 2-4 μm;

[0016] The fourth high resistance region and the insulating wall are aluminum oxide insulating isolation layers with a thickness of 2-4 μm.

[0017] Furthermore, the n-substrate of the first diode and the second diode is a Si-doped n-GaN epitaxial layer, and the Si doping concentration of the Si-doped n-GaN epitaxial layer is 1×10 16 cm -3 ~5×10 16 cm -3 ;

[0018] The p-well regions of the first diode and the second diode are Mg-doped p-GaN epitaxial layers, and the doping concentration of the Mg-doped p-GaN epitaxial layers is 1×10 18 cm -3 ~4×10 18 cm -3 ;

[0019] The thickness of the first diode and the second diode is 1-4 μm.

[0020] Furthermore, the first resistor and the second resistor are Si-doped i-GaN layers with a doping concentration of 1×10 16 cm -3 ~5×10 16 cm -3 ;

[0021] The thickness of the first resistor and the second resistor is 1-4 μm.

[0022] Furthermore, the functional device further includes an n-GaN epitaxial layer disposed on the single crystal substrate, a barrier layer covering the n-GaN epitaxial layer, and a p-GaN epitaxial layer disposed on the barrier layer;

[0023] The gate G1 is disposed on the p-GaN epitaxial layer, and the source S and the drain D are disposed on the barrier layer.

[0024] Furthermore, the n-GaN epitaxial layer is doped with Si at a doping concentration of 1×10 16 cm -3 ~5×10 16 cm -3 The p-GaN epitaxial layer is doped with Mg at a concentration of 1×10 18 cm -3 ~4×10 18 cm-3 .

[0025] Furthermore, the thickness of the n-GaN epitaxial layer is 18-20 μm, the thickness of the barrier layer is 0.01-0.03 μm, and the thickness of the p-GaN epitaxial layer is 2-5 μm.

[0026] A second aspect of the present invention provides a method for preparing a gallium nitride HEMT with an integrated protection structure, comprising the steps of:

[0027] Providing a single crystal substrate, wherein a polished surface of the single crystal substrate has a functional device region and a protection circuit region; ion implantation is performed on the protection circuit region of the single crystal substrate to form a first high resistance region, and an n-GaN epitaxial layer is formed on the single crystal substrate;

[0028] Ion implantation is performed on the n-GaN epitaxial layer along the interface between the functional device region and the protection circuit region to form a second high resistance region, so that the second high resistance region is connected to the first high resistance region; and a portion of the n-GaN epitaxial layer on the side of the functional device region is etched along the thickness direction to form a barrier layer on the surface;

[0029] Etching the n-GaN epitaxial layer on the side of the protection circuit region to form a first electrode groove between the n-GaN epitaxial layer on the side of the protection circuit region and the second high resistance region; ion implantation is performed on the n-GaN epitaxial layer on the side of the protection circuit region to form a p-well region to obtain a first diode;

[0030] forming a third high resistance region and a first resistor in sequence on the first diode; growing a portion of an electrode S1 on a side of the first diode away from the functional device region, so that a surface of the electrode S1 is flush with the first resistor;

[0031] forming a fourth high resistance region, a second resistor and a fifth high resistance region in sequence on the first resistor, wherein the fourth high resistance region covers a portion of the electrode S1;

[0032] forming a second diode on the surface of the fifth high resistance region; forming a p-GaN epitaxial layer in a portion of the barrier layer; and growing an insulating wall on a portion of the fourth high resistance region covering the electrode S1, so that a second electrode groove is formed between the insulating wall and the second resistor, the second diode, and the sidewall of the fifth high resistance region;

[0033] A source S and a drain D are formed on a partial area on the barrier layer, and a gate G1 is formed on the p-GaN epitaxial layer; an electrode G2 is formed in the first electrode groove, an electrode G3 is formed in the second electrode groove, and the electrode S1 is continued to grow so that the electrode G2, the electrode S1 and the electrode G3 all protrude from the surface of at least the second diode.

[0034] Compared with the prior art, the gallium nitride HEMT with integrated protection structure and its preparation method in the present invention have the following advantages:

[0035] First, the protection circuit has a protection module consisting of a diode and a circuit in parallel. A parallel resistor is added between the HEMT's gate G1 and source S, which enables the HEMT to release gate charge more quickly to prevent breakdown, improving device reliability and enabling the device to operate in high-frequency and high-voltage modes.

[0036] Second, a reverse diode is connected in parallel between gate G1 and electrode G of the protection circuit. This allows the HEMT device to quickly discharge gate charge when turned off, shortening the device's turn-off time and significantly reducing the switch's power consumption. This also allows the device's turn-on and turn-off times to differ, providing sufficient dead time in actual circuits to further improve device reliability.

[0037] Third, because the present invention provides the HEMT's functional components and protection circuitry on a single crystal substrate and separates them with a high-resistance region, when the HEMT of the present invention is integrated into a chip, there is no need to connect a protection circuit externally to the chip, significantly reducing the chip's size and manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 2 is a schematic diagram of the overall structure of a gallium nitride HEMT with an integrated protection structure according to an embodiment of the present invention;

[0039] Figure 2 is an equivalent circuit diagram of a gallium nitride HEMT with an integrated protection structure according to an embodiment of the present invention;

[0040] Figure 3 1 is a schematic structural diagram of the method for preparing a HEMT in an embodiment of the present invention after each process of step S1 is completed;

[0041] Figure 4 1 is a schematic structural diagram after completion of each process of step S2 and part of the process of step S3 in the method for preparing a HEMT according to an embodiment of the present invention;

[0042] Figure 5 4 is a schematic structural diagram after the steps of step S4 and part of the steps of step S5 of the method for preparing a HEMT in an embodiment of the present invention are completed;

[0043] Figure 6 1 is a schematic structural diagram of a part of the steps S5 and S6 of the method for preparing a HEMT in an embodiment of the present invention after the steps are completed.

[0044] In the accompanying drawings, the various reference numerals represent: 1. single crystal substrate; 2. functional device; 21. n-GaN epitaxial layer; 22. barrier layer; 23. p-GaN epitaxial layer; 3. protection circuit; 3a. first electrode groove; 3b. second electrode groove; 31. first diode; 32. first resistor; 33. second resistor; 34. second diode; 4. high resistance region; 41. first high resistance region; 42. second high resistance region; 43. third high resistance region; 44. fourth high resistance region; 45. fifth high resistance region; 5. insulating wall. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0046] Example:

[0047] See also Figures 1 and 2 In a first aspect, this embodiment provides a gallium nitride HEMT with an integrated protection structure, comprising: a single crystal substrate 1, a functional device 2, a protection circuit 3, and a high resistance region 4;

[0048] A functional device region and a protection circuit region are provided on the polished surface of the single crystal substrate 1. The functional device 2 is provided on the functional device region of the single crystal substrate 1. The protection circuit 3 is provided on the protection circuit 3 of the single crystal substrate 1. The protection circuit 3 and the single crystal substrate 1, as well as the protection circuit 3 and the functional device 2, are separated by a partial high resistance region 4.

[0049] The functional device 2 includes a source S, a gate G1 and a drain D, and the protection circuit 3 includes an electrode S1, a protection module, an electrode G2, another protection module and an electrode G3 connected in sequence; each protection module is composed of a diode and a resistor in parallel, the source S is electrically connected to the electrode S1, and the gate G1 is electrically connected to the electrode G2.

[0050] The HEMT in this embodiment has the following advantages:

[0051] First, the protection circuit 3 has a protection module composed of a diode and a circuit in parallel. The equivalent circuit diagram of the HEMT is as follows: Figure 2 As shown in Figure 1, a parallel resistor R is added between the gate G1 and the source S of the HEMT, which enables the HEMT to release gate charge faster, preventing breakdown caused by charge accumulation, improving device reliability, and enabling the device to operate in a high-frequency and high-voltage mode.

[0052] Second, the equivalent circuit diagram of HEMT is as follows Figure 2 As shown, a reverse diode is connected in parallel between the gate G1 and the electrode G of the protection circuit 3. Compared with a parallel resistor or capacitor, the parallel reverse diode enables the HEMT device to quickly discharge the gate charge when it is turned off, shortening the device turn-off time and greatly reducing the power consumption of the switch;

[0053] The parallel connection of diodes also makes the turn-on and turn-off times of the device different. In actual bridge circuits, this structure helps to provide sufficient dead time to prevent the upper and lower diodes of the same bridge arm from being turned on at the same time, further improving the reliability of the device.

[0054] Third, because the present invention provides the HEMT functional device 2 and the protection circuit 3 on a single crystal substrate 1 and separates the functional device 2 and the protection circuit 3 by a high-resistance region, when the HEMT of the present invention is integrated into a chip, there is no need to connect the protection circuit 3 externally to the chip, which can significantly reduce the chip size and reduce the chip manufacturing cost.

[0055] Specifically, as an example, the single crystal substrate 1 is a single-side polished n-type highly doped GaN single crystal substrate 1 , and the thickness is preferably 300 μm;

[0056] The drain D, source S and gate G1 can be a stacked electrode of Ti (25nm) / Al (75nm) / Ni (25nm) / Au (75nm). In other embodiments, those skilled in the art can make appropriate replacements for the materials and thicknesses of the drain D, source S and gate G1. For example, Ti / Al can also be used as the electrode material of the drain D and source S.

[0057] The source S and gate G1 of the functional device 2 are electrically connected to the electrodes of the protection circuit 3 via external metal leads, which are not marked in the figure.

[0058] Furthermore, one protection module includes a first diode 31 and a first resistor 32 separated by a partial high resistance region; the other protection module includes a second resistor 33 and a second diode 34 separated by a partial high resistance region; the two protection modules are also separated by a partial high resistance region 4;

[0059] Electrode S1 contacts the p-well region of the first diode 31 and the first resistor 32 ; electrode G2 contacts the n-substrate of the first diode 31 , the first resistor 32 , the second resistor 33 and the p-well region of the second diode 34 ; electrode G3 contacts the n-substrate of the second resistor 33 and the second diode 34 .

[0060] Specifically, the protection module composed of the first diode 31 and the first resistor 32 functions as the overvoltage protection circuit 3 , and the protection module composed of the second diode 34 and the second resistor 33 functions as gate current protection.

[0061] Further, if Figure 1 As shown, the high resistance region 4 includes a first high resistance region 41 , a second high resistance region 42 , a third high resistance region 43 , a fourth high resistance region 44 and a fifth high resistance region 45 ;

[0062] The first high resistance region 41 is on the protection circuit region of the single crystal substrate 1;

[0063] The first diode 31, the third high-resistance region 43, the first resistor 32, the fourth high-resistance region 44, the second resistor 33, the fifth high-resistance region 45, and the second diode 34 are sequentially stacked on the first high-resistance region 41 to form a protection module. An electrode G2 is provided on the side of the protection module close to the functional device 2. The second high-resistance region 42 is provided between the electrode G2 and the functional device 2 and is connected to the first high-resistance region 41.

[0064] The electrode G3 is arranged on the side wall of the second resistor 33, the fifth high resistance region 45 and the second diode 34 away from the functional device 2, and the electrode S1 is partially arranged on the side wall of the first diode 31, the third high resistance region 43 and the first resistor 32 away from the functional device 2. The fourth high resistance region 44 is connected to the insulating wall 5, which separates the electrode G3 and the electrode S1.

[0065] The present invention cleverly integrates the HEMT and the HEMT protection circuit 3 on a single crystal substrate 1 by providing a high resistance region 4 on the device. Figure 1 As shown, the first high resistance region 41 and the second high resistance region 42 are connected to separate the functional device 2 from the protection circuit 3; the fourth high resistance region 44 isolates the first resistor 32 and the second resistor 33; the third high resistance region 43 isolates the first diode 31 and the first resistor 32, and the fifth high resistance region 45 isolates the second diode 34 and the second resistor 33. The protection circuit 3 is prepared by a stacked structure, and metal is grown on the side of the stacked structure to form electrodes connected to the protection circuit 3. The structure is ingenious.

[0066] Further, if Figure 1 As shown, the first high resistance region 41 , the second high resistance region 42 , the third high resistance region 43 and the fifth high resistance region 45 are ion-implanted GaN high resistance isolation layers with a thickness of 2 to 4 μm;

[0067] The fourth high resistance region 44 and the insulating wall 5 are aluminum oxide insulating isolation layers with a thickness of 2-4 μm.

[0068] like Figure 1As shown, since the first high resistance region 41, the second high resistance region 42, the third high resistance region 43 and the fifth high resistance region 45 are respectively adjacent to the n-GaN epitaxial layer 21, the first diode 31 and the second diode 34, it is simpler to prepare the first high resistance region 41, the second high resistance region 42, the third high resistance region 43 and the fifth high resistance region 45 by ion implantation. Specifically, in this embodiment, each high resistance region is obtained by implanting He ions into each n-GaN layer. For detailed steps, please refer to the second part of the embodiments of this specification and will not be repeated here. In other embodiments, the first high resistance region 41, the second high resistance region 42, the third high resistance region 43 and the fifth high resistance region 45 can also be deposited insulating materials.

[0069] The fourth high resistance region 44 and the insulating wall 5 can be made of any material having an insulating isolation function, such as oxide or nitride. The insulating wall 5 in this embodiment is an aluminum oxide insulating isolation layer, which can preferably be replaced by a silicon oxide insulating isolation layer.

[0070] Preferably, the thickness of the first high resistance region 41 , the second high resistance region 42 , the third high resistance region 43 , the fifth high resistance region 45 , the fourth high resistance region 44 and the insulating wall 5 is 3 μm.

[0071] Furthermore, the n-substrate of the first diode 31 and the second diode 34 is a Si-doped n-GaN epitaxial layer 21, and the Si doping concentration of the Si-doped n-GaN epitaxial layer 21 is 1×10 16 cm -3 ~5×10 16 cm -3 ;

[0072] The p-well region of the first diode 31 and the second diode 34 is a Mg-doped p-GaN epitaxial layer 23, and the doping concentration of the Mg-doped p-GaN epitaxial layer 23 is 1×10 18 cm -3 ~4×10 18 cm -3 ;

[0073] The thickness of the first diode 31 and the second diode 34 is 1-4 μm.

[0074] Preferably, the doping concentration of the Si-doped n-GaN epitaxial layer 21 is 2×10 16 cm -3 The doping concentration of the Mg-doped p-GaN epitaxial layer 23 is 2×10 16 cm -3 ; The thickness of the first diode 31 and the second diode 34 is 3μm.

[0075] Furthermore, the first resistor 32 and the second resistor 33 are i-GaN layers doped with Si, with a doping concentration of 1×10 16cm -3 ~5×10 16 cm -3 ;

[0076] The thickness of the first resistor 32 and the second resistor 33 is 1-4 μm.

[0077] Preferably, the doping concentration of the Si-doped i-GaN layer is 2×10 15 cm -3 ; The thickness of the first resistor 32 and the second resistor 33 is 3μm.

[0078] Furthermore, the functional device 2 further includes an n-GaN epitaxial layer 21 disposed on the single crystal substrate 1, a barrier layer 22 covering the n-GaN epitaxial layer 21, and a p-GaN epitaxial layer 23 disposed on the barrier layer 22;

[0079] The gate G1 is disposed on the p-GaN epitaxial layer 23 , and the source S and the drain D are disposed on the barrier layer 22 .

[0080] It should be understood that the structure of the functional device 2 in this embodiment is merely an example of a GaN HEMT with an integrated protection structure. The structure of the protection circuit 3 in this embodiment can be applied to GaN HEMTs with integrated protection structures of various different structures, and is not limited to the functional device 2 in this embodiment.

[0081] Furthermore, the n-GaN epitaxial layer 21 is doped with Si at a doping concentration of 1×10 16 cm -3 ~5×10 16 cm -3 ; The p-GaN epitaxial layer 23 is doped with Mg, and the doping concentration is 1×10 18 cm -3 ~4×10 18 cm -3 .

[0082] Preferably, the Si doping concentration of the n-GaN epitaxial layer 21 is 2×10 16 cm -3 The Mg doping concentration of the p-GaN epitaxial layer 23 is 2×10 16 cm -3 .

[0083] Furthermore, the thickness of the n-GaN epitaxial layer 21 is 18-20 μm, the thickness of the barrier layer 22 is 0.01-0.03 μm, and the thickness of the p-GaN epitaxial layer 23 is 2-5 μm.

[0084] Preferably, the barrier layer 22 is an AlGaN barrier layer with a thickness of 0.02 μm, the thickness of the n-GaN epitaxial layer 21 is 20 μm, and the thickness of the p-GaN epitaxial layer 23 is 3 μm.

[0085] See also Figure 1 and Figures 3 to 6 A second aspect of this embodiment provides a method for preparing a gallium nitride HEMT with an integrated protection structure, comprising the steps of:

[0086] S1: Providing a single crystal substrate 1, wherein a polished surface of the single crystal substrate 1 has a functional device region and a protection circuit region; ion implantation is performed on the protection circuit region of the single crystal substrate 1 to form a first high resistance region 41, and an n-GaN epitaxial layer 21 is formed on the single crystal substrate 1;

[0087] S2: Ion implantation is performed on the n-GaN epitaxial layer 21 along the interface between the functional device region and the protection circuit region to form a second high resistance region 42, so that the second high resistance region 42 is connected to the first high resistance region 41; along the thickness direction, a portion of the n-GaN epitaxial layer 21 on the functional device region side is etched to form a barrier layer 22 on the surface;

[0088] S3: Etching the n-GaN epitaxial layer 21 on the side of the protection circuit region to form a first electrode groove 3a between the n-GaN epitaxial layer 21 on the side of the protection circuit region and the second high resistance region 42; ion implantation is performed on the n-GaN epitaxial layer 21 on the side of the protection circuit region to form a p-well region to obtain a first diode 31;

[0089] S4: forming a third high resistance region 43 and a first resistor 32 on the first diode 31 in sequence; growing a portion of the electrode S1 on the side of the first diode 31 away from the functional device region so that the surface of the electrode S1 is flush with the first resistor 32;

[0090] S5: forming a fourth high resistance region 44, a second resistor 33 and a fifth high resistance region 45 on the first resistor 32 in sequence, wherein the fourth high resistance region 44 covers a portion of the electrode S1;

[0091] S6: forming a second diode 34 on the surface of the fifth high resistance region 45; forming a p-GaN epitaxial layer 23 on a portion of the barrier layer 22; growing an insulating wall 5 on a portion of the fourth high resistance region 44 covering the electrode S1, so that a second electrode groove 3b is formed between the insulating wall 5 and the sidewalls of the second resistor 33, the second diode 34, and the fifth high resistance region 45;

[0092] S7: Form a source S and a drain D on a partial area on the barrier layer 22, and form a gate G1 on the p-GaN epitaxial layer 23; form an electrode G2 in the first electrode groove 3a, and form an electrode G3 in the second electrode groove 3b, and continue to grow the electrode S1 so that the electrodes G2, S1 and G3 all protrude from the surface of the second diode 34 at least.

[0093] Specifically, if Figure 3 As shown, step S1 includes:

[0094] S11: providing a single-side polished n-type highly doped GaN single crystal substrate 1, wherein the polished surface of the single crystal substrate 1 has a functional device region and a protection circuit region;

[0095] S12: Using a photolithography process to form a barrier layer in the functional device area, and implanting He ions into the protection circuit area of ​​the single crystal substrate 1 to form a first high resistance region 41, wherein the thickness of the first high resistance region 41 is 1-3 μm, preferably 2 μm, and the single crystal substrate 1 is an n-type highly doped GaN substrate. In other embodiments, other ion implantations may be used to form the first high resistance region 41;

[0096] S13: A 20 μm thick n-GaN epitaxial layer 21 is grown on the single crystal substrate 1 by chemical vapor deposition (CVD), wherein the n-GaN epitaxial layer 21 is doped with Si at a doping concentration of 1×10 16 cm -3 ~5×10 16 cm -3 , preferably 2×10 16 cm -3 ; Preferably, the n-GaN epitaxial layer 21 is prepared by metal organic chemical vapor deposition (MOCVD).

[0097] Step S2, such as Figure 4 As shown in the first two schematic structure diagrams, it includes:

[0098] S21: Using a photolithography process to form a barrier layer, He ions are implanted on the n-GaN epitaxial layer 21 along the interface between the functional device region and the protection circuit region to form a second high resistance region 42, so that the second high resistance region 42 is connected to the first high resistance region 41, wherein the width of the second high resistance region 42 is 0.3 μm to 0.8 μm, preferably 0.5 μm;

[0099] S21: using a photolithography process to form a barrier layer, etching the n-GaN epitaxial layer 21 on one side of the functional device area to a thickness of 0.02 μm;

[0100] S21: using chemical vapor deposition to deposit a barrier layer 22 with a thickness of 0.02 μm on the surface of the etched n-GaN epitaxial layer 21 ; preferably, using plasma enhanced chemical vapor deposition or atomic layer deposition to deposit the barrier layer 22 , the barrier layer 22 is an AlGaN barrier layer 22 .

[0101] Step S3, such as Figure 4 As shown in the last two schematic structural diagrams, it includes:

[0102] S31: Using a photolithography process to form a barrier layer, etching the edge of the n-GaN epitaxial layer 21 on the side of the protection circuit area, so as to form a first electrode groove 3a between the n-GaN epitaxial layer 21 on the side of the protection circuit area and the second high resistance area 42 ( Figure 4 Not marked yet, see Figure 6 ), and the thickness of the n-GaN epitaxial layer 21 is 6 μm;

[0103] S32: Mg ions are implanted on the n-GaN epitaxial layer 21 on the side of the protection circuit area, and a p-well region is formed on the side away from the functional device area, followed by rapid thermal annealing to obtain a first diode 31, wherein the Mg doping concentration is 1×10 18 cm -3 ~4×10 18 cm -3 , preferably 2×10 16 cm -3 ;

[0104] or,

[0105] S31: A barrier layer is formed by photolithography, and the n-GaN epitaxial layer 21 on one side of the protection circuit area is etched. A new n-GaN epitaxial layer 21 with a thickness of 6 μm is grown on the non-edge of the protection circuit area by chemical vapor deposition, so that a first electrode groove 3 a is formed between the new n-GaN epitaxial layer 21 and the second high resistance region 42. The new n-GaN epitaxial layer 21 is doped with Si at a doping concentration of 1×10 16 cm -3 ~5×10 16 cm -3 , preferably 2×10 16 cm -3 , and preferably growing a new n-GaN epitaxial layer 21 by metal organic chemical vapor deposition;

[0106] S32: Magnesium ions are implanted on the new n-GaN epitaxial layer 21 on the side of the protection circuit area, and a p-well region is formed on the side away from the functional device area, followed by rapid thermal annealing to obtain a first diode 31, wherein the magnesium ion doping concentration is 1×10 18 cm -3 ~4×1018 cm -3 , preferably 2×10 16 cm -3 ;

[0107] Step S4, as Figure 5 As shown in the first three schematic structure diagrams, it includes:

[0108] S41: using a photolithography process to form a blocking layer, and implanting He ions on the first diode 31 to form a third high resistance region 43 with a thickness of 2-4 μm, preferably 3 μm;

[0109] S42: A barrier layer is formed by photolithography, and a first resistor 32 with a thickness of 3 μm is grown on the third high resistance region 43 by metal organic chemical vapor deposition. The first resistor 32 is an i-GaN layer doped with Si, and the doping concentration is 1×10 16 cm -3 ~5×10 16 cm -3 , preferably 1×10 15 cm -3 ;

[0110] S43 : a barrier layer is formed by photolithography, and an electrode S1 with a thickness of 11 to 18 μm is grown outside the first diode 31 away from the functional device region, so that the surface of the electrode S1 is flush with the first resistor 32 .

[0111] Step S5, as Figure 5 The fourth schematic structure diagram and Figure 6 As shown in the first two schematic structure diagrams, it includes:

[0112] S51: A blocking layer is made using a photolithography process, and 2-4 μm of Al2O3 is grown on the surface of the first resistor 32 and the partial electrode S1 connected to the first resistor 32 by chemical vapor deposition to form a fourth high resistance region 44; preferably, Al2O3 with a thickness of 3 μm is grown by plasma enhanced chemical vapor deposition.

[0113] S52: A barrier layer is formed using a photolithography process, and a 6 μm Si-doped i-GaN layer is grown on the first resistor 32 by chemical vapor deposition, with a doping concentration of 1×10 16 cm -3 ~5×10 16 cm -3 ;

[0114] S53: A barrier layer is made using a photolithography process, and He ions are implanted on the Si-doped i-GaN layer to form a fifth high resistance region 45 with a thickness of 2 to 4 μm. The portion below that is not implanted with ions is the second resistor 33 . The thickness of the fifth high resistance region 45 is preferably 3 μm.

[0115] Step S6, as Figure 6 As shown in the last two schematic structure diagrams, it includes:

[0116] S61: A barrier layer is formed by photolithography. A 3 μm thick Si-doped n-GaN layer is grown on the surface of the fifth high resistance region 45 and a portion of the barrier layer 22 by chemical vapor deposition. The doping concentration is 1×10 16 cm -3 ~5×10 16 cm -3 ;

[0117] S62: In the Si-doped n-GaN layer on the fifth high resistance region 45, magnesium ions are implanted toward the side close to the functional device region to prepare a p-well region, and then rapid thermal annealing is performed to obtain a second diode 34. Magnesium ions are implanted into the Si-doped n-GaN layer on the barrier layer 22 to form a p-well region as a whole, thereby obtaining a p-GaN epitaxial layer 23, wherein the magnesium ion doping concentration is 1×10 18 cm -3 ~4×10 18 cm -3 ;

[0118] S63: Al2O3 with a thickness of 9 μm is grown on the surface of the partial area of ​​the fourth high resistance region 44 covering the electrode S1 by chemical vapor deposition to form an insulating wall 5, so that a second electrode groove 3b is formed between the insulating wall 5 and the side walls of the second diode 34, the fourth high resistance region 44 and the fifth high resistance region 45.

[0119] Step S7, as Figure 1 Shown, including:

[0120] S71: A barrier layer is formed using a photolithography process. Metal films of Ti (25 nm) / Al (75 nm) / Ni (25 nm) / Au (75 nm) are deposited on the barrier layer 22 and the p-GaN epitaxial layer 23. A source electrode S and a drain electrode D are formed on the barrier layer 22 using a lift-off process. A gate electrode G1 is formed on the p-GaN epitaxial layer 23. The electrodes are then annealed at 650°C in an N2 environment.

[0121] S72: Use a photolithography process to make a blocking layer, use physical vapor deposition to grow electrode G2 in the first electrode groove 3a, grow electrode G3 in the second electrode groove 3b, continue to grow electrode S1, and then anneal at 650°C in an N2 environment so that electrode G2, electrode S1 and electrode G3 all protrude from the surface of at least the second diode 34.

[0122] It should be known that in the above steps of this embodiment, the n-GaN epitaxial layer 21 is used as the substrate, and p-type impurities are doped into the n-substrate through ion implantation processes multiple times to obtain a p-well region. In addition to the ion implantation process, the p-well region can also be prepared by appropriate process methods, such as alloying method, diffusion method or growth method.

[0123] The barrier layer is made by using the photolithography process in the above steps, so as to cover the portion that does not need to be etched and / or ion implanted in each step with the barrier layer, thereby facilitating the implementation of subsequent etching and ion implantation processes.

[0124] In this embodiment, the functional device 2 and the various layers of the protection circuit 3 on the single crystal substrate 1 are prepared simultaneously, optimizing the complex preparation method. For example, through photolithography and ion implantation, the n-GaN epitaxial layer 21 formed in step S1 can be processed sequentially in the functional device region and the protection circuit region to form the n-GaN epitaxial layer 21 of the functional device 2 and the first diode 31 of the protection circuit 3. For example, in step S6, a Si-doped n-GaN layer is grown simultaneously on the fifth high-resistance region 45 and the barrier layer 22. After the barrier layer is formed through photolithography, ion implantation is performed simultaneously on the unblocked portion to obtain the p-GaN epitaxial layer 23 on the barrier layer 22 and the p-well region on the second diode 34. This simplifies the complex preparation steps and saves costs.

[0125] In addition, it should be understood that the order of the steps in this embodiment is not limited, and the order of some processes can be interchanged. In addition, in the above embodiments, the description of each aspect of the embodiment has different emphases. For details of a part of the embodiment, please refer to the relevant description of other parts of the embodiment.

[0126] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A gallium nitride HEMT with an integrated protection structure, characterized in that: include: Single crystal substrate, functional devices, protection circuits and high resistance regions; The polished surface of the single crystal substrate has a functional device region and a protection circuit region, the functional device is arranged on the functional device region of the single crystal substrate, the protection circuit is arranged on the protection circuit region of the single crystal substrate, and the protection circuit and the single crystal substrate, the protection circuit and the functional device are separated by part of the high resistance region; The functional device includes a source S, a gate G1 and a drain D, and the protection circuit includes an electrode S1, a protection module, an electrode G2, another protection module and an electrode G3 connected in sequence; Each of the protection modules is composed of a diode and a resistor connected in parallel, the source S is electrically connected to the electrode S1, and the gate G1 is electrically connected to the electrode G2; One of the protection modules includes a first diode and a first resistor separated by part of the high resistance region; another protection module includes a second resistor and a second diode separated by part of the high resistance region; the two protection modules are also separated by part of the high resistance region; The electrode S1 contacts the p-well region of the first diode and the first resistor; the electrode G2 contacts the n-substrate of the first diode, the first resistor, the second resistor and the p-well region of the second diode; the electrode G3 contacts the second resistor and the n-substrate of the second diode.

2. The HEMT according to claim 1, characterized in that The high resistance region includes a first high resistance region, a second high resistance region, a third high resistance region, a fourth high resistance region and a fifth high resistance region; The first high resistance region is on the protection circuit region of the single crystal substrate; The first diode, the third high resistance region, the first resistor, the fourth high resistance region, the second resistor, the fifth high resistance region and the second diode are sequentially superimposed on the first high resistance region to form the protection module, the electrode G2 is provided on a side of the protection module close to the functional device, and the second high resistance region is provided between the electrode G2 and the functional device and is connected to the first high resistance region; The electrode G3 is arranged on the side walls of the second resistor, the fifth high resistance region and the second diode away from the functional device, the electrode S1 is partially arranged on the side walls of the first diode, the third high resistance region and the first resistor away from the functional device, the fourth high resistance region is connected to an insulating wall, and the insulating wall separates the electrode G3 and the electrode S1.

3. The gallium nitride HEMT with integrated protection structure according to claim 2, characterized in that: The first high resistance region, the second high resistance region, the third high resistance region and the fifth high resistance region are ion-implanted GaN high resistance isolation layers with a thickness of 2 to 4 μm; The fourth high resistance region and the insulating wall are aluminum oxide insulating isolation layers with a thickness of 2 to 4 μm.

4. The HEMT according to claim 1, wherein: The n-substrate of the first diode and the second diode is a Si-doped n-GaN epitaxial layer, and the Si doping concentration of the Si-doped n-GaN epitaxial layer is 1×10 16 cm -3 ~5×10 16 cm -3 ; The p-well regions of the first diode and the second diode are Mg-doped p-GaN epitaxial layers, and the doping concentration of the Mg-doped p-GaN epitaxial layers is 1×10 18 cm -3 ~4×10 18 cm -3 ; The thickness of the first diode and the second diode is 1-4 μm.

5. The HEMT according to claim 1, wherein: The first resistor and the second resistor are i-GaN layers doped with Si, with a doping concentration of 1×10 16 cm -3 ~5×10 16 cm -3 ; The thickness of the first resistor and the second resistor is 1-4 μm.

6. The HEMT according to claim 1, wherein: The functional device further includes an n-GaN epitaxial layer disposed on the single crystal substrate, a barrier layer covering the n-GaN epitaxial layer, and a p-GaN epitaxial layer disposed on the barrier layer; The gate G1 is disposed on the p-GaN epitaxial layer, and the source S and the drain D are disposed on the barrier layer.

7. The HEMT according to claim 6, characterized in that The n-GaN epitaxial layer is doped with Si at a doping concentration of 1×10 16 cm -3 ~5×10 16 cm -3 The p-GaN epitaxial layer is doped with Mg at a doping concentration of 1×10 18 cm -3 ~4×10 18 cm -3 .

8. The HEMT according to claim 6, characterized in that The thickness of the n-GaN epitaxial layer is 18-20 μm, the thickness of the barrier layer is 0.01-0.03 μm, and the thickness of the p-GaN epitaxial layer is 2-5 μm.

9. A method for preparing a gallium nitride HEMT with an integrated protection structure as claimed in claims 1 to 8, characterized in that: include: Providing a single crystal substrate, wherein a functional device region and a protection circuit region are provided on a polished surface of the single crystal substrate; ion implantation is performed on the protection circuit region of the single crystal substrate to form a first high resistance region, and an n-GaN epitaxial layer is formed on the single crystal substrate; Along the interface between the functional device region and the protection circuit region, ion implantation is performed on the n-GaN epitaxial layer to form a second high resistance region, so that the second high resistance region is connected to the first high resistance region; along the thickness direction, a portion of the n-GaN epitaxial layer on one side of the functional device region is etched, and a barrier layer is formed on the surface; Etching the n-GaN epitaxial layer on the side of the protection circuit region to form a first electrode groove between the n-GaN epitaxial layer on the side of the protection circuit region and the second high resistance region; ion implantation is performed on the n-GaN epitaxial layer on the side of the protection circuit region to form a p-well region to obtain a first diode; A third high resistance region and a first resistor are sequentially formed on the first diode; a partial electrode S1 is grown on a side of the first diode away from the functional device region, so that a surface of the electrode S1 is flush with the first resistor; forming a fourth high resistance region, a second resistor and a fifth high resistance region in sequence on the first resistor, wherein the fourth high resistance region covers a portion of the electrode S1; A second diode is formed on the surface of the fifth high resistance region; a p-GaN epitaxial layer is formed in a partial region of the barrier layer; an insulating wall is grown on a partial region of the fourth high resistance region covering the electrode S1, so that a second electrode groove is formed between the insulating wall and the second resistor, the second diode and the side wall of the fifth high resistance region; A source S and a drain D are formed on a partial area on the barrier layer, and a gate G1 is formed on the p-GaN epitaxial layer; an electrode G2 is formed in the first electrode groove, an electrode G3 is formed in the second electrode groove, and the electrode S1 is continuously grown so that the electrode G2, the electrode S1 and the electrode G3 all protrude from at least the surface of the second diode.

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