A LDMOS device with a graphic RESURF structure and enhanced withstand voltage and a manufacturing method thereof

Abstract

The present invention discloses an LDMOS device with a patterned RESURF structure to enhance withstand voltage and a manufacturing method thereof. The device comprises: a first conductive type surface electric field suppression array located in a second conductive type drift region, comprising a plurality of first conductive type doped regions; a hollow field plate located on a first passivation layer, comprising a first hollow field plate and a second hollow field plate; the second hollow field plate is a plurality of hollow structures, each of which is located on a PN junction formed by each first conductive type doped region and a second conductive type drift region, and adjacent hollow structures are connected; the first conductive type surface electric field suppression array and the hollow field plate constitute a patterned RESURF structure, which makes the electric field more smoothly distributed in the lateral direction, improves the RESURF effect, and improves the withstand voltage of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an LDMOS device with a patterned RESURF structure and enhanced withstand voltage, and a manufacturing method thereof. Background Art

[0002] LDMOS (Laterally Diffused Metal Oxide Semiconductor) devices are lateral power devices with gate, source and drain located on the chip surface. They are compatible with CMOS processes and are therefore widely used in power integrated circuits (power ICs). They mainly realize power conversion, regulation and transmission functions, as well as high-voltage interfaces, simulations, level shifters and protection functions of power management circuits.

[0003] Suppressing the surface electric field is the key to improving the reliability of LDMOS devices. Generally, RESURF (Reduced SURface Field, RESURF) technologies such as field plate technology, buried layer technology or their combination are used to smooth the surface electric field, suppress the electric field peak and improve the device withstand voltage. However, conventional RESURF technology has two disadvantages: (1) the field plate introduces a larger output capacitance, which reduces the switching speed and introduces a larger switching loss; (2) the ability of conventional RESURF technology to suppress the electric field still has a lot of room for improvement. RESURF structures with high surface electric field suppression capabilities can use a smaller drift region length to achieve a higher withstand voltage, thereby reducing the chip area and improving wafer utilization. Summary of the invention

[0004] Technical purpose: In view of the deficiencies in the prior art, the present invention discloses a LDMOS device with a graphic RESURF structure to enhance the withstand voltage and a manufacturing method thereof, which can enhance the withstand voltage of the LDMOS device and save chip area without increasing the length of the drift region.

[0005] Technical solution: In order to achieve the above technical objectives, the present invention adopts the following technical solution.

[0006] A LDMOS device with a patterned RESURF structure and enhanced withstand voltage, comprising:

[0007] Substrate metal electrode;

[0008] A first conductive type substrate located on the substrate metal electrode;

[0009] A first conductivity type epitaxial layer located on a first conductivity type substrate;

[0010] a first conductivity type well region located in the first conductivity type epitaxial layer;

[0011] a first conductivity type source region located in the first conductivity type well region;

[0012] A second conductivity type drift region located in the first conductivity type epitaxial layer, the second conductivity type drift region contacts the first conductivity type well region, and a PN junction is formed at the contact point, which is denoted as PN0;

[0013] A first conductive type surface electric field suppression array located in a second conductive type drift region includes a plurality of first conductive type doped regions arranged in the X direction, i=1,2,3,...,n, n≥1, and a PN junction formed by the first conductive type doped region and the second conductive type drift region is denoted as PNi; wherein the length direction of the device is defined as the X direction, the width direction is the Y direction, and the depth direction is the Z direction;

[0014] a second conductivity type source region located in the first conductivity type well region;

[0015] a second conductivity type drain region located in the second conductivity type drift region;

[0016] A gate dielectric layer spanning a portion of the surface of the second conductive type source region, a surface of the first conductive type well region, a surface of the second conductive type drift region, and a portion of the surface of the second conductive type drain region;

[0017] A second conductive type polysilicon gate located on a portion of the gate dielectric layer;

[0018] A first passivation layer located on the gate dielectric layer and the second conductive type polysilicon gate;

[0019] A hollow field plate located on the first passivation layer, the hollow field plate includes a first hollow field plate connected to a plurality of second hollow field plates arranged in the X direction; the first hollow field plate is located at a portion of the protrusions of the first passivation layer and the sidewall of the first passivation layer, the second hollow field plate corresponds to the first conductive type doping region one by one, and the center of the second hollow field plate is hollowed out and located on the first conductive type doping region, adjacent second hollow field plates are connected, each second hollow field plate includes a plurality of second hollow field plate units arranged in the Y direction, and the second hollow field plate units correspond to the first conductive type doping units one by one; the second hollow field plate coincides with the center of the first conductive type doping region; the first conductive type surface electric field suppression array and the hollow field plate constitute a patterned RESURF structure;

[0020] a second passivation layer located above the first passivation layer and above the hollow field plate;

[0021] A source through hole, a gate through hole, a drain through hole, and a field plate through hole located inside the second passivation layer and the first passivation layer;

[0022] The source metal electrode, gate metal electrode, drain metal electrode and field plate metal electrode are located on the surface of the second passivation layer and inside the source through hole, gate through hole, drain through hole and field plate through hole, and the field plate metal electrode is interconnected with the gate metal electrode.

[0023] A method for manufacturing a LDMOS device with a patterned RESURF structure and enhanced withstand voltage, for manufacturing any of the above-mentioned LDMOS devices with a patterned RESURF structure and enhanced withstand voltage, comprising the following steps:

[0024] Step 1, forming a first conductivity type epitaxial layer on a first conductivity type substrate by epitaxial growth;

[0025] Step 2, forming a first conductivity type well region inside the first conductivity type epitaxial layer by an ion implantation process;

[0026] Step 3, forming a first conductivity type source region inside the first conductivity type epitaxial layer and the first conductivity type well region;

[0027] Step 4, forming a second conductivity type drift region inside the first conductivity type epitaxial layer;

[0028] Step 5, forming a first conductive type surface electric field suppression array in the second conductive type drift region, the first conductive type surface electric field suppression array and the second conductive type drift region forming a PN junction; the first conductive type surface electric field suppression array includes a plurality of first conductive type doped regions arranged in the X direction, i=1,2,3,...,n, n≥1, the first conductive type doped region and the second conductive type drift region forming a PN junction, denoted as PNi;

[0029] Step 6, forming a gate dielectric layer on the upper surfaces of the first conductivity type well region, the first conductivity type source region, the second conductivity type drift region, and the first conductivity type surface electric field suppression array;

[0030] Step 7, forming a second conductivity type polysilicon gate on the gate dielectric layer by anisotropic etching processes, wherein the projection length of the second conductivity type polysilicon gate in the X direction covers the junction of the first conductivity type well region and the second conductivity type drift region;

[0031] Step 8, forming a second conductive type source region in the first conductive type well region, and forming a second conductive type drain region in the second conductive type drift region; the second conductive type source region is in contact with the first conductive type source region and is away from the second conductive type drift region; a PN junction depletion layer is formed at the contact surface between the second conductive type drift region and the first conductive type well region, and is recorded as PN0;

[0032] Step 9, forming a first passivation layer on the top and sidewalls of the second conductivity type polysilicon gate and the gate dielectric layer;

[0033] Step 10, forming a hollow field plate by anisotropic etching process, the hollow field plate includes a first hollow field plate connected to a plurality of second hollow field plates arranged in the X direction; the first hollow field plate is located at a portion of the protrusions of the first passivation layer and the side wall of the first passivation layer, the second hollow field plate corresponds to the first conductive type doping region one by one, and the center of the second hollow field plate is hollowed out and located on the first conductive type doping region, adjacent second hollow field plates are connected, each second hollow field plate includes a plurality of second hollow field plate units arranged in the Y direction, and the second hollow field plate units correspond to the first conductive type doping units one by one; the second hollow field plate coincides with the center of the first conductive type doping region; the first conductive type surface electric field suppression array and the hollow field plate constitute a patterned RESURF structure;

[0034] Step 11, depositing a second passivation layer on the first passivation layer and on the hollow field plate by a chemical vapor deposition process;

[0035] Step 12, depositing metal through the source through hole, the gate through hole, the drain through hole, and the field plate through hole and annealing to form a source metal electrode, a gate metal electrode, a drain metal electrode, and a field plate metal electrode, respectively; the field plate metal electrode fills the field plate through hole, and passes through the gap between the adjacent gate metal electrodes to communicate with the source metal electrode;

[0036] Step 13: forming a substrate metal electrode on the bottom layer of the first conductive type substrate.

[0037] Beneficial effects:

[0038] The present invention arranges a matching first conductive type surface electric field suppression array and a hollow field plate in the second conductive type drift region. Firstly, the electric field is distributed more smoothly in the lateral direction, thereby improving the RESURF effect and the withstand voltage of the device. Secondly, the capacitance of the hollow field plate is small, thereby improving the switching characteristics of the device while ensuring the withstand voltage. Thirdly, the structure has a large process window, is insensitive to structural parameters and process parameters, and is simple to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Schematic diagram of a LDMOS device with a graphical RESURF structure to enhance withstand voltage Figure 1 ;

[0040] Figure 2 Schematic diagram of a LDMOS device with a graphical RESURF structure to enhance withstand voltage Figure 2 ;

[0041] Figure 3~Figure 23 A schematic diagram of a manufacturing method of a LDMOS device with a graphical RESURF structure and enhanced withstand voltage;

[0042] Fig.24 A schematic diagram of a hollow field plate structure of another embodiment of an LDMOS device with a patterned RESURF structure to enhance withstand voltage;

[0043] Fig.25 A schematic diagram of a hollow field plate structure of another embodiment of an LDMOS device with a patterned RESURF structure to enhance withstand voltage;

[0044] Explanation of the accompanying drawings: 0, substrate metal electrode; 1, first conductivity type substrate; 2, first conductivity type epitaxial layer; 3, first conductivity type well region; 4, first conductivity type source region; 5, second conductivity type drift region; 6, first conductivity type surface electric field suppression array; 6-i, first conductivity type doped region; 7, gate dielectric layer; 8, second conductivity type polysilicon gate; 9, second conductivity type source region; 10, second conductivity type drain region; 11, first passivation layer; 12, hollow field plate; 12-0, first hollow field plate; 12-i, second hollow field plate; 13, second passivation layer; 13-1, source through hole; 13-2, gate through hole; 13-3, drain through hole; 13-4, field plate through hole; 14-1, source metal electrode; 14-2, gate metal electrode; 14-3, drain metal electrode; 14-4, field plate metal electrode. DETAILED DESCRIPTION

[0045] The following further explains and illustrates a LDMOS device with a patterned RESURF structure and a method for manufacturing the same according to the present invention in conjunction with the accompanying drawings.

[0046] The orientation or positional relationship indicated by the terms "upper" and "lower" etc. is based on the orientation or positional relationship shown in the drawings and is only for the convenience of describing the present invention and simplifying the description. It does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on the invention.

[0047] The terms "first", "second" and "third" are used only for descriptive purposes to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations, nor can they be understood as indicating or implying relative importance.

[0048] As attached Figure 1 and attached Figure 2 As shown, a LDMOS device with a patterned RESURF structure and enhanced withstand voltage, comprising:

[0049] Substrate metal electrode 0;

[0050] A first conductive type substrate 1 located on a substrate metal electrode 0;

[0051] A first conductivity type epitaxial layer 2 located on a first conductivity type substrate 1;

[0052] A first conductivity type well region 3 located in the first conductivity type epitaxial layer 2;

[0053] A first conductivity type source region 4 located in the first conductivity type well region 3;

[0054] A second conductivity type drift region 5 located in the first conductivity type epitaxial layer 2, the second conductivity type drift region 5 is in contact with the first conductivity type well region 3, and a PN junction is formed at the contact point, which is denoted as PN0;

[0055] The first conductive type surface electric field suppression array 6 located in the second conductive type drift region 5 includes a plurality of first conductive type doped regions 6-i arranged in the X direction, i=1,2,3,...,n,n≥1, and n represents the number of first conductive type doped regions; the PN junction formed by the first conductive type doped region 6-i and the second conductive type drift region 5 is denoted as PNi; wherein the length direction of the device is defined as the X direction, the width direction is the Y direction, and the depth direction is the Z direction; adjacent first conductive type doped regions 6-i are not connected, and each first conductive type doped region 6-i includes a plurality of first conductive type doped units that are not connected and arranged in the Y direction;

[0056] A second conductive type source region 9 is located in the first conductive type well region 3, the second conductive type source region 9 is in contact with the first conductive type source region 4 and is far away from the second conductive type drift region 5, and the length between the second conductive type source region 9 and the second conductive type drift region 5 is the channel length LCH, LCH ≥ 0.2 μm;

[0057] A second conductivity type drain region 10 located in the second conductivity type drift region 5, wherein the length between the second conductivity type drain region 10 and PN0 is the drift region length LD, where LD≥1 μm;

[0058] A gate dielectric layer 7 spanning a portion of the second conductivity type source region 9 surface, a first conductivity type well region 3 surface, a second conductivity type drift region 5 surface and a portion of the second conductivity type drain region 10 surface;

[0059] A second conductivity type polysilicon gate 8 located on a portion of the gate dielectric layer 7;

[0060] A first passivation layer 11 located on the gate dielectric layer 7 and the second conductivity type polysilicon gate 8;

[0061] A hollow field plate 12 is located on the first passivation layer 11, and the hollow field plate 12 includes a first hollow field plate 12-0 and a plurality of second hollow field plates 12-i arranged in the X direction, i=1,2,3,...,n,n≥1, and n represents the number of the second hollow field plates, which is the same as the number of the first conductive type doping regions; the first hollow field plate 12-0 is located at a protrusion of a portion of the first passivation layer 11 and a side wall of the first passivation layer 11, and the second hollow field plates 12- i corresponds to the first conductive type doping region 6-i one by one, the center of the second hollow field plate 12-i is hollowed out and located on the first conductive type doping region 6-i, adjacent second hollow field plates 12-i are connected, each second hollow field plate 12-i includes a plurality of unconnected second hollow field plate units arranged in the Y direction, and the second hollow field plate unit corresponds to the first conductive type doping unit one by one; the second hollow field plate coincides with the center of the first conductive type doping region; the first conductive type surface electric field suppression array and the hollow field plate constitute a graphical RESURF structure. The shape of the second hollow field plate 12-i is determined by the shape of the first conductive type doping region 6-i, and the shape of the second hollow field plate unit is determined by the shape of the first conductive type doping unit. If the first conductive type doping region 6-i is a polygon, the second hollow field plate 12-i is a hollow polygon; if the first conductive type doping unit is a polygon, the second hollow field plate unit is a hollow polygon. The shape of the first conductive type doping region 6-i is a polygon, including a triangle, a rectangle, a pentagon, and a hexagon.

[0062] A second passivation layer 13 located above the first passivation layer 11 and above the hollow field plate 12;

[0063] A source through hole 13-1, a gate through hole 13-2, a drain through hole 13-3, and a field plate through hole 13-4 penetrating the second passivation layer 13 and the first passivation layer 11; the source through hole 13-1 is located on the gate dielectric layer 7 corresponding to the projection of the first conductive type source region 4 and part of the second conductive type source region 9 in the Z direction, and the width of the source through hole 13-1 is the same as the width of the device; there are at least two gate through holes 13-2, which are not connected to each other and are located on part of the second conductive type polysilicon gate 8, and the drain through hole 13-3 is located on the gate dielectric layer 7 corresponding to the projection of part of the second conductive type drain region 10 in the Z direction, and the width of the drain through hole 13-3 is the same as the width of the device; the field plate through hole 13-4 also penetrates part of the hollow field plate 12;

[0064] The source metal electrode 14-1, the gate metal electrode 14-2, the drain metal electrode 14-3, and the field plate metal electrode 14-4 are located on the surface of the second passivation layer 13 and inside the source through hole 13-1, the gate through hole 13-2, the drain through hole 13-3, and the field plate through hole 13-4, and the field plate metal electrode 14-4 is interconnected with the gate metal electrode 14-2.

[0065] Among them, the first conductive type surface electric field suppression array 6 and the hollow field plate 12 constitute a graphic RESURF structure; by setting a matching first conductive type surface electric field suppression array and a hollow field plate in the second conductive type drift region, firstly, the electric field is distributed more smoothly in the lateral direction, thereby improving the RESURF effect and the withstand voltage of the device; secondly, the hollow field plate has a small capacitance, thereby improving the switching characteristics of the device while ensuring the withstand voltage; thirdly, the structure has a large process window, is insensitive to structural parameters and process parameters, and is simple to implement.

[0066] In this embodiment, a LDMOS device with enhanced voltage resistance using a graphic RESURF structure is used, wherein the first conductivity type is N-type or P-type, and the second conductivity type is P-type or N-type; the cell arrangement includes strip, hexagon, square and atomic lattice shapes; and applicable semiconductor materials include silicon, silicon carbide, gallium nitride and gallium oxide.

[0067] The hollow field plate 12 may not be provided above the first conductive type doping region 6 - i near the second conductive type drain region 10 , because this region is close to high voltage, and the high voltage is prevented from breaking through the field plate;

[0068] As attached Figure 3 To Attachment Fig.23 As shown, a process flow chart of a method for manufacturing a LDMOS device with a graphical RESURF structure and enhanced withstand voltage of the present invention is provided, and the specific process is as follows:

[0069] Step 1: Figure 3 , Figure 4 As shown, a first conductive type epitaxial layer 2 is formed on a first conductive type substrate 1 by epitaxial growth, the first conductive type substrate 1 is a semiconductor material, including silicon, silicon carbide, gallium nitride, gallium oxide; the first conductive type is N-type or P-type, and the second conductive type is P-type or N-type;

[0070] Step 2: Figure 5 As shown, on the surface of the wafer prepared in step 1, the ion implantation mask layer is patterned by a photolithography process, and then a first conductive type well region 3 is formed inside the first conductive type epitaxial layer 2 by an ion implantation process. The doping concentration of the first conductive type well region 3 is 1e16cm -3 ~1e18cm -3 , the length of the first conductive type well region 3 is not less than 1 μm, and the depth is not less than 1 μm;

[0071] Step 3: Figure 6As shown, on the surface of the wafer prepared in step 2, the ion implantation mask layer is patterned by a photolithography process, and then a first conductive type source region 4 is formed inside the first conductive type epitaxial layer 2 and the first conductive type well region 3 by an ion implantation process. The doping concentration of the first conductive type source region 4 is 1e19cm -3 ~5e20cm -3 ; Wherein, the first conductive type source region 4 penetrates the first conductive type well region 3 and extends into the first conductive type epitaxial layer 2, the depth of the first conductive type source region 4 is greater than the depth of the first conductive type well region 3, the depth of the first conductive type source region 4 is not less than 2μm, the length of the first conductive type source region 4 is less than the length of the first conductive type well region 3, and the length of the first conductive type source region 4 ranges from 0.2μm to 0.8μm;

[0072] Step 4: Figure 7 As shown, on the surface of the wafer prepared in step 3, the ion implantation mask layer is patterned by a photolithography process, and then a second conductive type drift region 5 is formed inside the first conductive type epitaxial layer 2 by an ion implantation process. The doping concentration of the second conductive type drift region 5 is 1e16m -3 ~5e17cm -3 ; Wherein, the second conductive type drift region 5 is far away from the first conductive type source region 4 and contacts the first conductive type well region 3. The depth of the second conductive type drift region 5 is less than the depth of the first conductive type well region 3 and is ≥0.5 μm. Its length is determined by the device withstand voltage index. The recommended value is shown in Table 1.

[0073] Table 1 Recommended values ​​for the length of the second conductivity type drift region

[0074]

[0075] Step 5: Figure 8 and Fig. 9 As shown, Figure 8 This is a three-dimensional diagram of the device in step 5. Fig. 9 is a top view; on the surface of the wafer prepared in step 4, the ion implantation mask layer is patterned by a photolithography process, and then a first conductive type surface electric field suppression array 6 is formed in the second conductive type drift region 5 by an ion implantation process, and the first conductive type surface electric field suppression array 6 forms a PN junction with the second conductive type drift region 5; the first conductive type surface electric field suppression array 6 includes a plurality of first conductive type doped regions 6-i arranged in the X direction, i=1,2,3,...,n, n≥1, the first conductive type doped region 6-i forms a PN junction with the second conductive type drift region 5, which is recorded as PNi; the doping concentration of the first conductive type doped region 6-i is 1e17m -3 ~1e19cm -3, the doping concentration of the first conductive type doping region 6-i is higher than the doping concentration of the second conductive type drift region 5; Figure 8 As shown, the length direction of the device is defined as the X direction, the width direction is the Y direction, and the depth direction is the Z direction; adjacent first conductive type doping regions 6-i are not connected, and each first conductive type doping region 6-i includes a plurality of first conductive type doping units that are not connected and arranged in the Y direction; each first conductive type doping region 6-i has a length X1 ≥ 0.2 μm in the X direction, a width Y1 ≥ 0.2 μm in the Y direction, and a depth Z1 ≥ 0.2 μm in the Z direction; on the XY plane, a spacing dx ≥ 0.2 μm between two adjacent first conductive type doping regions 6-i, and a spacing dy ≥ 0.2 μm between adjacent first conductive type doping units in each first conductive type doping region 6-i; the number of first conductive type doping regions 6-i in the Y direction, that is, the number of first conductive type doping units is not less than 1; Figure 8 In the figure, as a schematic and to prevent too many marks from affecting readability, only one PN junction formed by the first conductive type doping region 6-i and the second conductive type drift region 5 is marked with PNi, and the marks PNi of the remaining PN junctions formed by the first conductive type doping region 6-i and the second conductive type drift region 5 are omitted;

[0076] Step 6: Fig.10 As shown, on the surface of the wafer prepared in step 5, a gate dielectric layer 7 is formed by a chemical vapor deposition process, an oxidation process, or a composite process of a chemical vapor deposition process and an oxidation process, such as first performing chemical vapor deposition and then performing oxidation, or first performing oxidation and then performing chemical vapor deposition, and the thickness thereof is in the range of 10nm to 100nm; the gate dielectric layer 7 covers the upper surfaces of the first conductive type well region 3, the first conductive type source region 4, the second conductive type drift region 5, and the first conductive type surface electric field suppression array 6;

[0077] Step 7: Fig.11 As shown, on the surface of the wafer prepared in step 6, a layer of polysilicon is grown by chemical vapor deposition process; a second conductive type doped polysilicon is formed by large-area ion implantation process, and the doping concentration is 1e20m -3 ~5e20cm -3 ; The etching mask layer is patterned by a photolithography process, and then a second conductive type polysilicon gate 8 is formed by anisotropic etching processes; the second conductive type polysilicon gate 8 is located on the gate dielectric layer 7, and the projection length in the X direction covers the junction of the first conductive type well region 3 and the second conductive type drift region 5;

[0078] Step 8: Fig.12As shown, on the surface of the wafer prepared in step 7, the ion implantation mask layer is patterned by a photolithography process, and then a second conductive type source region 9 is formed in the first conductive type well region 3 by an ion implantation process, and its length range is 0.2μm~1μm, and its depth range is 0.1μm~0.3μm, and a second conductive type drain region 10 is formed in the second conductive type drift region 5, and its length range is 0.2μm~1μm, and its depth range is 0.1μm~0.3μm, the second conductive type source region 9 is in contact with the first conductive type source region 4 and is away from the second conductive type drift region 5; the second conductive type drain region 10 is away from the first conductive type surface electric field suppression array 6; the doping concentration of the second conductive type source region 9 and the second conductive type drain region 10 is 1e19m -3 ~5e20cm -3 ;

[0079] It is defined that the contact surface between the second conductive type drift region 5 and the first conductive type well region 3 forms a PN junction depletion layer, which is recorded as PN0; the distance between the second conductive type source region 9 and PN0 is the channel length LCH, and the channel length LCH is not less than 0.2 μm; the distance between the second conductive type drain region 10 and PN0 is the drift region length LD, and the drift region length LD is not less than 1 μm;

[0080] Step 9: Fig.13 As shown, on the surface of the wafer prepared in step 8, a first passivation layer 11 is formed by a chemical vapor deposition process, an oxidation process, or a composite process of a chemical vapor deposition process and an oxidation process, such as first performing chemical vapor deposition and then oxidation, or first performing oxidation and then chemical vapor deposition, and the thickness thereof is in the range of 50nm to 500nm; the first passivation layer 11 is located on the top and sidewalls of the second conductive type polysilicon gate 8 and the gate dielectric layer 7;

[0081] Step 10: Figure 14-17 As shown, on the surface of the wafer prepared in step 9, a field plate is first formed by a chemical vapor deposition process, an evaporation process, or a sputtering process, and the thickness ranges from 50nm to 500nm; when the chemical vapor deposition process is adopted, the field plate is composed of polycrystalline silicon with a doping concentration of 1e15m -3 ~5e20cm -3; When the evaporation process or the sputtering process is adopted, the field plate is composed of one or more combinations of metals such as Ti, Al, Ni, Pt, Ag, etc.; then the etching mask layer is patterned by the photolithography process, and then a part of the field plate is removed by the anisotropic etching process to form a hollow field plate 12; the first hollow field plate 12-0 is located at the protrusion of part of the first passivation layer 11 and the side wall of the first passivation layer 11, the second hollow field plate 12-i corresponds to the first conductive type doping region 6-i one by one, and the center of the second hollow field plate 12-i is hollowed out and located at the first Above the conductive type doping region 6-i, adjacent second hollow field plates 12-i are connected, each second hollow field plate 12-i includes a plurality of unconnected second hollow field plate units arranged in the Y direction, and the second hollow field plate units correspond to the first conductive type doping units one by one; the second hollow field plate coincides with the center of the first conductive type doping region; the hollow field plate 12 includes a connected first hollow field plate 12-0 and a plurality of second hollow field plates 12-i arranged in the X direction, i=1,2,3,...,n,n≥1; the first hollow field plate 12-0 is located at the protrusion of part of the first passivation layer 11 and the side wall of the first passivation layer 11, the protrusion of the first passivation layer 11 refers to the first passivation layer 11 located on the top of the second conductive type polysilicon gate 8; the side wall of the first passivation layer 11 refers to the first passivation layer 11 close to the first conductive type surface electric field suppression array 6 and connected to the protrusion of the first passivation layer 11; the second hollow field plate 12-i corresponds to the first conductive type doped region 6-i one by one, and the center of the second hollow field plate 12-i is hollowed out and located on the first conductive type doped region 6-i, and the adjacent second hollow field plate 12-i is located on the first conductive type doped region 6-i. The plates 12-i are connected, and each second hollow field plate 12-i includes a plurality of unconnected second hollow field plate units arranged in the Y direction, and the second hollow field plate units correspond one-to-one to the first conductive type doping units; the second hollow field plate coincides with the center of the first conductive type doping region; that is, for the first conductive type doping region 6-i, it is adjacent to the first conductive type doping region 6-i+1, and the second hollow field plate 12-i corresponding to the first conductive type doping region 6-i is adjacent to the second hollow field plate 12-i+1, and the two are connected through a narrow field plate film.

[0082] Fig.14 is the top view of the device. Fig.15 yes Fig.14 The cross section along A-A', Fig.16 A schematic diagram showing the hollow field plate 12 alone is shown. Fig.17 It is a partial schematic diagram of the second hollow field plate and the first conductive type doping region, showing the design parameters of the hollow field plate. The design rules of the design parameters are as follows:

[0083] (1) Each second hollow field plate corresponds to a first conductivity type doped region 6 - i, and the centers of the two coincide;

[0084] (2) Each second hollow field plate has a hollow shape. If the first conductivity type doped region 6-i is rectangular, the second hollow field plate has a hollow structure in the shape of a double-square frame. The outer side length X3 of the second hollow field plate 12-i is ≥ 0.4 μm. Compared with the length X2 of the first conductivity type doped region 6-i, X3 - X2 ≥ 0.1 μm. The outer side width Y3 of the second hollow field plate 12-i is ≥ 0.4 μm. Compared with the width Y2 of the first conductivity type doped region 6-i, Y3 - Y2 ≥ 0.1 μm. The inner side length X1 of the second hollow field plate 12-i is ≥ 0.1 μm. Compared with the length X2 of the first conductivity type doped region 6-i, X2 - X1 ≥ 0.1 μm. The inner side width Y1 of the second hollow field plate 12-i is ≥ 0.1 μm. Compared with the width Y2 of the first conductivity type doped region 6-i, Y2 - Y1 ≥ 0.1 μm. In the X-Y plane, the distance d2 between two adjacent second hollow field plates 12-i is ≥ 0.1 μm. In each second hollow field plate 12-i, the distance d3 between adjacent second hollow field plate units is ≥ 0.1 μm.

[0085] (3) Optionally, no hollow field plate 12 may be provided above the first conductivity type doped region 6-i close to the second conductivity type drain region 10 because it is close to high voltage here to prevent the field plate from being broken down by high voltage.

[0086] Step 11, as Figure 18-Figure 20 shown, Fig. 20 is the top view of the device, Fig.19 is Fig. 20 the cross-sectional view at B-B'. On the surface of the wafer prepared in Step 9, a second passivation layer 13 is deposited by chemical vapor deposition. The second passivation layer 13 is located above the first passivation layer 11 and above the hollow field plate 12, as Fig.18 shown; then the second passivation layer 13 and the first passivation layer 11 are etched by an etching process to form a source via 13-1, a gate via 13-2, a drain via 13-3, and a field plate via 13-4, as Figure 19-20As shown; wherein, the source through hole 13-1 is located on the gate dielectric layer 7 corresponding to the projection of the first conductive type source region 4 and part of the second conductive type source region 9 in the Z direction, and the width of the source through hole 13-1 is the same as the width of the device; the gate through hole 13-2 is located on part of the second conductive type polysilicon gate 8, there are several gate through holes 13-2, and adjacent gate through holes 13-2 are not connected. In this embodiment, the number of gate through holes 13-2 is not less than two; the drain through hole 13-3 is located on the gate dielectric layer 7 corresponding to the projection of part of the second conductive type drain region 10 in the Z direction; the width of the drain through hole 13-3 is the same as the width of the device; the field plate through hole 13-4 is located on part of the hollow field plate 12, specifically, the field plate through hole 13-4 is located on part of the first hollow field plate at the protrusion of the first passivation layer 11, and the size of the field plate through hole 13-4 is a conventional size in the art, and generally the length and width are not less than 0.5μm;

[0087] In this embodiment, the second passivation layer 13 is silicon oxide, or nitride, or a composite of silicon oxide and nitride;

[0088] Step 12: Figure 21-22 As shown, Fig. 22 is a top view of the device. Fig.21 yes Fig. 22 Cross-sectional view at CC'; metal is deposited and annealed through the source through hole 13-1, the gate through hole 13-2, the drain through hole 13-3, and the field plate through hole 13-4 to form a source metal electrode 14-1, a gate metal electrode 14-2, a drain metal electrode 14-3, and a field plate metal electrode 14-4 respectively; wherein the source metal electrode 14-1 fills the source through hole 13-1 and covers part of the top of the second passivation layer 13, and the gate metal electrode 14-2 fills the gate through hole 13-1 and covers part of the top of the second passivation layer 13; The drain metal electrode 14-3 fills the drain through hole 13-3 and covers a portion of the top of the second passivation layer 13, the field plate metal electrode 14-4 fills the field plate through hole 13-4, and passes through the gap between the adjacent gate metal electrode 14-2 to communicate with the source metal electrode 14-1; the source metal electrode layout is connected to the field plate metal electrode layout in the photolithography layout, so as to realize the electrical short circuit between the gate and the field plate of the LDMOS device;

[0089] Step 13: Fig.23 As shown, on the bottom layer of the first conductive type substrate 1 of the wafer prepared in step 11, an ohmic metal is deposited by a sputtering process or an evaporation process and annealed to form a substrate metal electrode 0.

[0090] The electrode materials of the source metal electrode 14-1, the gate metal electrode 14-2, the drain metal electrode 14-3, the field plate metal electrode 14-4, and the substrate metal electrode 0 are one or more combinations of Ti, Al, Ni, Pt, and Ag metals, or other metals, depending on actual conditions.

[0091] Fig.24 A top view of a device structure in which the first conductive type doping region is hexagonal in shape is provided in another embodiment of the present invention. Fig.24 It can be seen that the shape of the second hollow field plate 12 - i changes to a hollow hexagon accordingly, and each second hollow field plate includes a plurality of unconnected second hollow field plate units arranged in the Y direction.

[0092] Fig.25 A top view of a device structure in which the first conductive type doping region is hexagonal in shape is provided in another embodiment of the present invention. Fig.25 As can be seen from the figure, the shape of the second hollow field plate 12-i changes to a hollow hexagon, which is similar to Fig.24 The difference in the example is that Fig.25 Each second hollow field plate includes a plurality of connected second hollow field plate units arranged in the Y direction, that is, when adjacent second hollow field plate units are photolithographically and etched, a certain width of field plate material is retained, the width of which is ≥0.2μm, and the length of which is the spacing between adjacent second hollow field plate units.

[0093] The working principle of the present invention is:

[0094] Case 1: When the field plate and the first conductive type surface electric field suppression array proposed in the present invention do not exist, the electric field lines emitted in the lateral direction, i.e., the X direction, when the high voltage is applied to the drain terminate at the PN junction depletion layer formed by the second conductive type drift region 5 and the first conductive type well region 3, which is recorded as PN0. Therefore, the PN0 terminates the entire lateral electric field and generates a strong electric field concentration.

[0095] Case 2: When only a solid field plate exists, since the field plate metal electrode 14-4 is connected to the source metal electrode 14-1, the field plate is connected to the source, the source is generally at zero potential, and the drain is applied with high voltage in the lateral direction, that is, the electric field lines in the X direction, a part of the electric field lines are first terminated by the field plate, and the end of the metal field plate close to the drain side terminates more electric field lines due to the proximity to the drain high voltage, and the other part is terminated by PN0, so two electric field spikes are generated on the surface of the second conductive type drift region 5, respectively located at the second conductive type drift region 5 below the end of the field plate close to the drain side and at PN0; compared with case 1, this structure can improve the withstand voltage, but generally speaking, it is not suitable for LDMOS with a withstand voltage of more than 200V;

[0096] Case 3: When there is only a continuous first conductivity type doped region, that is, a continuous first conductivity type doped region is set in the second conductivity type drift region 5; the first conductivity type doped region and the second conductivity type drift region 5 form two PN junctions, which are located at the drain region side and the well region side respectively. These two PN junctions help PN0 share part of the electric field lines, thereby further improving the withstand voltage;

[0097] The above cases 1 to 3 are problems existing in the traditional structure in the prior art;

[0098] Case 4: When only the hollow field plate 12 proposed in the present invention exists, since the hollow field plate 12 is discontinuous, the second conductive type drift region 5 below each discontinuity will introduce an electric field spike, and the electric field lines in the lateral direction, that is, the X direction, applied by the drain are weakened layer by layer at the above-mentioned large number of hollow field plate discontinuities, and the electric field will be more smoothly distributed in the lateral direction, thereby increasing the breakdown voltage; compared with Case 1, the hollow field plate introduces more electric field spikes, which can more significantly weaken the electric field peak at PN0; however, it is necessary to optimize the size of the hollow field plate to prevent the electric field peak at a certain hollow field plate discontinuity from being too high, and try to make the electric field peaks at various locations consistent, so that the RESURF effect is best; in addition, the field plate capacitor formed by the hollow field plate 12 and the second conductive type drift region 5 is part of the output capacitor. Since the field plate is hollow, the hollow field plate 12 and the second conductive type drift region 5, and thus the hollow field plate capacitor is smaller than the conventional solid field plate capacitor;

[0099] Case 5: When only the first conductive type surface electric field suppression array 6 proposed in the present invention exists, since the first conductive type surface electric field suppression array 6 is composed of a plurality of first conductive type doped regions 6-i, which form a plurality of PN junctions with the second conductive type drift region 5, denoted as PNi, the electric field lines emitted in the lateral direction, i.e., the X direction, when the drain applies high voltage are partially terminated by PNi, an electric field spike is generated on each PNi, and finally terminated by PN0, which weakens the electric field concentration effect at PN0, making the electric field more smoothly distributed in the lateral direction, thereby increasing the breakdown voltage; however, it is necessary to optimize the width and spacing of the first conductive type doped regions 6-i in the first conductive type surface electric field suppression array 6 to prevent the electric field peak of a certain PNi from being too high, and to try to make the electric field peaks of each PNi and PN0 consistent, so that the RESURF effect is best;

[0100] Case 6: When the matching first conductive type surface electric field suppression array 6 and hollow field plate 12 proposed by the present invention exist at the same time, firstly, the electric field spikes introduced on the surface of the second conductive type drift region 5 are more dense, which is more effective in suppressing the electric field concentration effect at PN0, making the electric field more smoothly distributed in the lateral direction, and improving the withstand voltage; secondly, since the hollow field plate 12 is located above PNi, the curvature of the PNi depletion layer is changed, making the electric field at PNi smoother, and improving the RESURF effect; thirdly, the first conductive type surface electric field suppression array 6 and the hollow field plate 12 are matched with each other, reducing the design difficulty of each structure, suppressing the sensitivity of the electric field distribution to the size of each structure, and increasing the process window; fourthly, the hollow field plate 12 has a small capacitance, which improves the switching characteristics of the device while ensuring the withstand voltage. The first conductive type surface electric field suppression array and the hollow field plate in the graphic RESURF structure proposed by the present invention are matched with each other and are indispensable.

[0101] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A LDMOS device with a patterned RESURF structure to enhance withstand voltage, characterized in that: include: Substrate metal electrode; A first conductive type substrate located on the substrate metal electrode; A first conductivity type epitaxial layer located on a first conductivity type substrate; a first conductivity type well region located in the first conductivity type epitaxial layer; a first conductivity type source region located in the first conductivity type well region; A second conductivity type drift region located in the first conductivity type epitaxial layer, the second conductivity type drift region contacts the first conductivity type well region, and a PN junction is formed at the contact point, which is denoted as PN0; A first conductivity type surface electric field suppression array located in a second conductivity type drift region includes i first conductivity type doped regions arranged in the X direction, i=1,2,3,‧‧‧‧‧‧n, n≥1, and a PN junction formed by the first conductivity type doped region and the second conductivity type drift region is denoted as PNi; wherein the length direction of the device is defined as the X direction, the width direction is the Y direction, and the depth direction is the Z direction; a second conductivity type source region located in the first conductivity type well region; a second conductivity type drain region located in the second conductivity type drift region; A gate dielectric layer spanning a portion of the surface of the second conductive type source region, a surface of the first conductive type well region, a surface of the second conductive type drift region, and a portion of the surface of the second conductive type drain region; A second conductive type polysilicon gate located on a portion of the gate dielectric layer; A first passivation layer located on the gate dielectric layer and the second conductive type polysilicon gate; A hollow field plate located on the first passivation layer, the hollow field plate includes a first hollow field plate connected to a plurality of second hollow field plates arranged in the X direction; the first hollow field plate is located at a portion of the protrusions of the first passivation layer and the sidewall of the first passivation layer, the second hollow field plate corresponds to the first conductive type doping region one by one, and the center of the second hollow field plate is hollowed out and located on the first conductive type doping region, adjacent second hollow field plates are connected, each second hollow field plate includes a plurality of second hollow field plate units arranged in the Y direction, and the second hollow field plate units correspond to the first conductive type doping units one by one; the second hollow field plate coincides with the center of the first conductive type doping region; the first conductive type surface electric field suppression array and the hollow field plate constitute a patterned RESURF structure; a second passivation layer located above the first passivation layer and above the hollow field plate; A source through hole, a gate through hole, a drain through hole, and a field plate through hole located inside the second passivation layer and the first passivation layer; The source metal electrode, gate metal electrode, drain metal electrode and field plate metal electrode are located on the surface of the second passivation layer and inside the source through hole, gate through hole, drain through hole and field plate through hole, and the field plate metal electrode is interconnected with the gate metal electrode.

2. The LDMOS device with a patterned RESURF structure and enhanced withstand voltage according to claim 1, characterized in that: Each first conductive type doping region has a length X1≥0.2μm in the X direction, a width Y1≥0.2μm in the Y direction, and a depth Z1≥0.2μm in the Z direction. In the XY plane, a distance between two adjacent first conductive type doping regions has an adjacent length difference dx≥0.2μm and an adjacent width difference dy≥0.2μm.

3. The LDMOS device with a patterned RESURF structure and enhanced withstand voltage according to claim 1, characterized in that: Adjacent first conductive type doping regions are not connected, and each first conductive type doping region includes a number of unconnected first conductive type doping units arranged in the Y direction; adjacent second hollow field plates are connected, and each second hollow field plate includes a number of second hollow field plate units arranged in the Y direction, the second hollow field plate units correspond one-to-one to the first conductive type doping units, and the several second hollow field plate units of each second hollow field plate are connected or not connected.

4. The LDMOS device with a patterned RESURF structure and enhanced withstand voltage according to claim 1, characterized in that: The outer side length X3 of the second hollow field plate is ≥0.4μm, compared with the length X2 of the first conductive type doping region, X3-X2 is ≥0.1μm; the outer side length width Y3 of the second hollow field plate is ≥0.4μm, compared with the width Y2 of the first conductive type doping region, Y3-Y2 is ≥0.1μm; the inner side length X1 of the second hollow field plate is ≥0.1μm, compared with the length X2 of the first conductive type doping region, X2-X1 is ≥0.1μm, the inner side length width Y1 of the second hollow field plate is ≥0.1μm, compared with the width Y2 of the first conductive type doping region, Y2-Y1 is ≥0.1μm, in the XY plane, the spacing d2 between two adjacent second hollow field plates is ≥0.1μm, and in each second hollow field plate, the spacing d3 between adjacent second hollow field plate units is ≥0.1μm.

5. The LDMOS device with a patterned RESURF structure and enhanced withstand voltage according to claim 1, characterized in that: No hollow field plate is disposed above the first conductivity type doped region close to the second conductivity type drain region.

6. The LDMOS device with a patterned RESURF structure and enhanced withstand voltage according to claim 1, characterized in that: The length distance between the second conductive type source region and the second conductive type drift region is the channel length LCH, LCH≥0.2 μm; the length distance between the second conductive type drain region and PN0 is the drift region length LD, LD≥1 μm.

7. The LDMOS device with a patterned RESURF structure and enhanced withstand voltage according to claim 1, characterized in that: The shape of the first conductive type doping region is a polygon, including a triangle, a rectangle, a pentagon, and a hexagon.

8. The LDMOS device with a patterned RESURF structure and enhanced withstand voltage according to claim 1, characterized in that: The shape of the hollow field plate is determined by the shape of the first conductive type doping region.

9. The LDMOS device with a patterned RESURF structure and enhanced withstand voltage according to claim 1, characterized in that: The source through hole is located on the gate dielectric layer corresponding to the projection of the first conductive type source region and part of the second conductive type source region in the Z direction; the gate through hole is located on part of the second conductive type polysilicon gate, there are several gate through holes, and adjacent gate through holes are not connected; the drain through hole is located on the gate dielectric layer corresponding to the projection of part of the second conductive type drain region in the Z direction; the field plate through hole is located on part of the hollow field plate.

10. A method for manufacturing a LDMOS device with a patterned RESURF structure and enhanced withstand voltage, for manufacturing a LDMOS device with a patterned RESURF structure and enhanced withstand voltage as claimed in any one of claims 1 to 9, characterized in that: The following steps are involved: Step 1, forming a first conductivity type epitaxial layer on a first conductivity type substrate by epitaxial growth; Step 2, forming a first conductivity type well region inside the first conductivity type epitaxial layer by an ion implantation process; Step 3, forming a first conductivity type source region inside the first conductivity type epitaxial layer and the first conductivity type well region; Step 4, forming a second conductivity type drift region inside the first conductivity type epitaxial layer; Step 5, forming a first conductivity type surface electric field suppression array in the second conductivity type drift region, the first conductivity type surface electric field suppression array and the second conductivity type drift region form a PN junction; the first conductivity type surface electric field suppression array includes i first conductivity type doped regions arranged in the X direction, i=1,2,3,‧‧‧‧‧‧n, n≥1, the first conductivity type doped region and the second conductivity type drift region form a PN junction, recorded as PNi; Step 6, forming a gate dielectric layer on the upper surfaces of the first conductivity type well region, the first conductivity type source region, the second conductivity type drift region, and the first conductivity type surface electric field suppression array; Step 7, forming a second conductivity type polysilicon gate on the gate dielectric layer by anisotropic etching processes, wherein the projection length of the second conductivity type polysilicon gate in the X direction covers the junction of the first conductivity type well region and the second conductivity type drift region; Step 8, forming a second conductive type source region in the first conductive type well region, and forming a second conductive type drain region in the second conductive type drift region; the second conductive type source region is in contact with the first conductive type source region and is away from the second conductive type drift region; a PN junction depletion layer is formed at the contact surface between the second conductive type drift region and the first conductive type well region, and is recorded as PN0; Step 9, forming a first passivation layer on the top and sidewalls of the second conductivity type polysilicon gate and the gate dielectric layer; Step 10: forming a hollow field plate by anisotropic etching process, wherein the hollow field plate includes a first hollow field plate connected to a plurality of second hollow field plates arranged in the X direction; The first hollow field plate is located at a portion of the protrusion of the first passivation layer and the side wall of the first passivation layer, the second hollow field plate corresponds to the first conductive type doping region one by one, and the center of the second hollow field plate is hollowed out and located on the first conductive type doping region, adjacent second hollow field plates are connected, each second hollow field plate includes a plurality of second hollow field plate units arranged in the Y direction, and the second hollow field plate units correspond to the first conductive type doping units one by one; the second hollow field plate coincides with the center of the first conductive type doping region; The first conductive type surface electric field suppression array and the hollow field plate constitute a patterned RESURF structure; Step 11, depositing a second passivation layer on the first passivation layer and on the hollow field plate by a chemical vapor deposition process; Step 12, depositing metal through the source through hole, the gate through hole, the drain through hole, and the field plate through hole and annealing to form a source metal electrode, a gate metal electrode, a drain metal electrode, and a field plate metal electrode, respectively; the field plate metal electrode fills the field plate through hole, and passes through the gap between the adjacent gate metal electrodes to communicate with the source metal electrode; Step 13: forming a substrate metal electrode on the bottom layer of the first conductive type substrate.

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