Method for determining link deterministic delay, electronic device and computer storage medium

Abstract

This disclosure provides a method for determining the deterministic delay of a link, applied at a receiving end, comprising: performing frequency division and frequency multiplication on an initial frame boundary according to a preset frequency division multiple and a preset frequency multiplication multiple to obtain a frequency multiplication frame boundary; wherein, the frequency multiplication frame boundary is used to write data received from the link into the buffer of the link, or to read data received from the buffer in the link; and determining the deterministic delay of the link according to the estimated absolute delay of the link and the frequency multiplication frame boundary. This method allows for a flexible value of the deterministic delay, solving the problems of limited deterministic delay values, wasted delay due to a small absolute delay but a large deterministic delay, and high circuit design complexity due to a large absolute delay but a small deterministic delay, thus reducing the complexity of circuit design. This disclosure also provides a receiving end, an electronic device, and a computer storage medium.

Description

Technical Field

[0001] This invention relates to the field of communication technology, specifically to a method for determining link deterministic delay, an electronic device, and a computer storage medium. Background Technology

[0002] The rapid development of wireless communication technology, especially with the large-scale commercialization of 5G (5th Generation Mobile Communication Technology) and the rapid pre-research of 6G (6th Generation Mobile Communication Technology), has led to increasingly precise requirements for the synchronization and latency of data transmission links in wireless communication devices (or components). For example, 5G wireless communication devices have strict quantitative requirements for the absolute latency of a single channel and the relative latency between multiple channels in terms of antenna channel data transmission. In reality, different operating scenarios or different periods of operation after startup of wireless communication devices (or components) will cause changes in data transmission latency. In order to achieve the predetermined latency requirements, wireless communication devices (or components) need to adopt a lot of additional technologies during the design process, which greatly increases the complexity of design and implementation and extends the design and iteration cycle of products.

[0003] Currently, the JESD204C interface technology has significant advantages in obtaining deterministic latency of data links, but it also has many drawbacks, such as limited latency values, wasted latency, and insufficient latency. Therefore, a more mature method for obtaining deterministic latency of data links is urgently needed. Summary of the Invention

[0004] This disclosure addresses the aforementioned deficiencies in the prior art by providing a method for determining link deterministic delay, an electronic device, and a computer storage medium.

[0005] In a first aspect, embodiments of this disclosure provide a method for determining link deterministic delay, applied at a receiving end, the method comprising:

[0006] Based on a preset frequency division factor and a preset frequency multiplication factor, the initial frame boundary is subjected to frequency division and frequency multiplication processing to obtain a frequency multiplication frame boundary; wherein, the frequency multiplication frame boundary is used to write data received from the link into the buffer of the link, or to read data received from the link from the buffer;

[0007] The deterministic delay of the link is determined based on the estimated absolute link delay and the frequency multiplication frame boundary.

[0008] In some embodiments, the initial frame boundary is an initial in-path frame boundary or an initial aligned frame boundary, the frequency-doubled frame boundary is a frequency-doubled in-path frame boundary or a frequency-doubled aligned frame boundary, the initial in-path frame boundary corresponds to the frequency-doubled frame boundary, the initial aligned frame boundary corresponds to the frequency-doubled aligned frame boundary, and the period of the frequency-doubled in-path frame boundary is the same as the period of the frequency-doubled aligned frame boundary.

[0009] The frequency-multiplied frame boundary is used to write data received from the link into the link's buffer;

[0010] The frequency-doubled aligned frame boundary is used to read data received in the link from the cache.

[0011] In some embodiments, determining the link deterministic delay based on the estimated absolute link delay and the frequency doubling frame boundary includes:

[0012] The period of the frequency doubling frame boundary is N times the period of the link deterministic delay, where N is a positive integer;

[0013] The value of N is determined based on the estimated absolute link delay and the frequency multiplication frame boundary.

[0014] In some embodiments, determining the value of N based on the estimated link absolute delay and the frequency multiplication frame boundary includes:

[0015] If the estimated absolute link delay is less than the frequency multiplier frame boundary, then N is determined to be 1.

[0016] In some embodiments, determining the value of N based on the estimated link absolute delay and the frequency multiplication frame boundary includes:

[0017] If the estimated absolute link delay is not less than the frequency doubling frame boundary, the value conditions are determined based on the estimated absolute link delay, the frequency doubling frame boundary, and the link uncertainty parameters.

[0018] The smallest positive integer that satisfies the given value condition is determined as the value of N.

[0019] In some embodiments, the value selection conditions are determined based on the estimated link absolute delay, the frequency doubling frame boundary, and the link uncertainty parameters, including:

[0020] Based on the estimated link absolute delay and link uncertainty parameters, the minimum link absolute delay and the maximum link absolute delay are determined.

[0021] The value selection conditions are determined based on the minimum link absolute delay, the maximum link absolute delay, and the frequency multiplication frame boundary.

[0022] In some embodiments, the value condition is: (N-1) times the period of the frequency doubling frame boundary is less than the minimum link absolute delay, and N times the period of the frequency doubling frame boundary is greater than the maximum link absolute delay.

[0023] In some embodiments, the method further includes the step of obtaining the initial in-line frame boundary and the initial aligned frame boundary:

[0024] Data is received from the link, and the received data is decoded to obtain the initial trailing frame boundary;

[0025] Receive a reference signal and determine the initial alignment frame boundary based on the reference reference signal and the lemc interval agreed upon in advance with the transmitter.

[0026] Secondly, embodiments of this disclosure provide a receiving end, the receiving end comprising:

[0027] The first processing module is used to perform frequency division and frequency multiplication processing on the initial frame boundary according to a preset frequency division multiple and a preset frequency multiplication multiple to obtain a frequency multiplication frame boundary; wherein, the frequency multiplication frame boundary is used to write data received from the link into the buffer of the link, or to read data received from the link from the buffer;

[0028] The second processing module is used to determine the deterministic delay of the link based on the estimated absolute delay of the link and the frequency doubling frame boundary.

[0029] Thirdly, embodiments of this disclosure provide an electronic device, including:

[0030] One or more processors;

[0031] A storage device on which one or more programs are stored;

[0032] When the one or more programs are executed by the one or more processors, the one or more processors implement the link deterministic delay determination method as described above.

[0033] Fourthly, embodiments of this disclosure provide a computer storage medium storing a computer program thereon, which, when executed, implements the method for determining link deterministic delay as described above.

[0034] With a fixed period for the initial frame boundary, the initial frame boundary is first divided and then multiplied according to a preset division factor and a preset multiplication factor. By adjusting the ratio of the preset division factor to the preset multiplication factor, a flexible, arbitrarily sized multiplied frame boundary can be obtained. This multiplied frame boundary serves as a new frame boundary for writing / reading data, no longer limited to a fixed frame structure period. The multiplied frame boundary can be larger or smaller than the initial frame boundary, and the relationship between the multiplied and initial frame boundaries is not limited to a specific integer multiple. Furthermore, after obtaining a multiplied frame boundary of arbitrary size, the deterministic link delay can be determined based on the estimated absolute link delay and the multiplied frame boundary, thus obtaining a flexible, deterministic link delay. It solves the problem of limited values ​​for deterministic delay; when the absolute delay of the link is small but the deterministic delay is large, the deterministic delay can be reduced without changing the circuit design, thus solving the problem of wasted delay caused by a small absolute delay but a large deterministic delay; when the absolute delay of the link is large but the deterministic delay is small, it is not necessary to shorten the traces by changing the circuit design to reduce the absolute delay of the link to make it smaller than the deterministic delay. Instead, the deterministic delay can be increased without changing the circuit design, thus solving the problem of high circuit design complexity caused by a large absolute delay but a small deterministic delay, and reducing the complexity of the circuit design.

[0035] Furthermore, for certain devices or equipment, they need to operate in different application scenarios. Even if the frame structure period is the same, the processing clock period used in different application scenarios may be inconsistent, which will lead to inconsistent latency when the device or equipment is working in these application scenarios. By adopting the link deterministic latency determination method provided in the embodiments of this disclosure, the frequency multiplication frame boundary used for data read and write operations in each application scenario is different, but the deterministic latency obtained in each application scenario can be kept consistent, which further reduces the design complexity of the device or equipment and improves the compatibility of the device or equipment. Attached Figure Description

[0036] Figure 1 This is a flowchart illustrating the link deterministic delay determination method provided in the embodiments of this disclosure. Figure 1 ;

[0037] Figure 2 This is a flowchart illustrating the link deterministic delay determination method provided in the embodiments of this disclosure. Figure 2 ;

[0038] Figure 3 This is a flowchart illustrating the link deterministic delay determination method provided in the embodiments of this disclosure. Figure 3 ;

[0039] Figure 4This is a flowchart illustrating the link deterministic delay determination method provided in the embodiments of this disclosure. Figure 4 ;

[0040] Figure 5 This is a flowchart illustrating the link deterministic delay determination method provided in the embodiments of this disclosure. Figure 5 ;

[0041] Figure 6 This is a flowchart illustrating the link deterministic delay determination method provided in the embodiments of this disclosure. Figure 6 ;

[0042] Figure 7 This is a flowchart illustrating the link deterministic delay determination method provided in the embodiments of this disclosure. Figure 7 ;

[0043] Figure 8 This is a schematic diagram of the principle provided in the embodiments of this disclosure;

[0044] Figure 9 This is a schematic diagram showing that the period of RX_mul_lemc is less than the period of RX_lemc, as provided in this embodiment of the disclosure.

[0045] Figure 10 This is a schematic diagram showing that the period of RX_mul_lemc is greater than the period of RX_lemc, as provided in the embodiments of this disclosure. Detailed Implementation

[0046] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0047] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the said feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded.

[0049] The embodiments described herein can be described with reference to plan views and / or cross-sectional views using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations can be modified according to manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to those shown in the drawings, but include modifications to configurations formed based on manufacturing processes. Therefore, the areas illustrated in the drawings are schematic in nature, and the shapes of the areas shown in the figures illustrate specific shapes of areas of an element, but are not intended to be limiting.

[0050] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0051] In a JESD204 system, there may be multiple data processing units distributed across different clock domains without a defined delay relationship. This results in varying link delays after each power-on or re-establishment of the connection. The JESD204B interface technology provides a mechanism for deterministic interface delay. Deterministic delay on the link refers to the delay from the start of frame-based data input at the TX device (transmitter) to the time when the RX device (receiver) receives and outputs the frame data; this delay remains consistent after each power-on or re-establishment of the connection.

[0052] Currently, the JESD204C interface technology has a significant advantage in obtaining deterministic latency for data links. The JESD204C interface technology is an essential technology for achieving high-speed serial transmission of communication data. The JESD204C interface standard describes the key technologies of the physical layer, link layer, and transport layer in detail. Driven by the JESD organization, the JESD204C protocol is continuously evolving towards JESD204C.1 and JESD204_USR (USR: ultra-short reach) interface standards, and has significant potential for future development and expansion.

[0053] According to the method described in the JESD204C protocol, the data transmitting side and the data receiving side use the same reference signal. The data transmitting side generates periodic frame boundaries (TX_lemc: local extend multiblock clock) based on the reference signal (SYSREF signal in the JESD204C protocol), and frames the data (data_in) according to a certain format using TX_lemc and transmits it through the subsequent serial link. The data receiving side receives the data through the serial link and recovers the data-as-a-path frame boundaries (RC_lemc: recovery lemc). The data receiving side generates periodic frame boundaries (RX_lemc: local extend multiblock clock) based on the SYSREF signal. The received data is written to the memory under the control of RC_lemc and read from the memory (data_out) under the control of RX_lemc. According to the above method, when TX_lemc, RC_lemc and RX_lemc are strictly equal, and when the absolute delay of data from the sender to the receiver is required to be less than the above lemc period, the transmission from data_in to data_out obtains a link deterministic delay: one lemc period.

[0054] However, the JESD204C interface technology also has many drawbacks, such as limited latency values, wasted latency, and insufficient latency. On the one hand, due to the protocol's limitation on frame length, i.e., the limitation on the lemc cycle (locally extended multiple clocks), the deterministic latency obtained by the data link can only be the number of clocks corresponding to the value that the lemc cycle can take. On the other hand, since the absolute latency of data from the sending end to the receiving end is required to be less than the lemc cycle, sometimes in order to reduce the absolute latency of data from the sending end to the receiving end, even if the internal circuit design of the device and the board-level PCB traces are designed to be extremely short, this requirement still cannot be met. In order to use the JESD204C interface technology, it is necessary to increase the lemc cycle. However, increasing the lemc cycle is not supported by all parameters. Furthermore, when the lemc cycle corresponding to a certain parameter is very large, but the actual absolute latency of data from the sending end to the receiving end is very low, it will cause wasted latency.

[0055] In view of this, the present disclosure proposes that, in order to solve the many drawbacks of the JESD204C interface technology, such as limited latency values, wasted latency, and insufficient latency, a method is needed to obtain flexible link deterministic latency. This method would allow the deterministic latency to be no longer limited to one lemc cycle when the lemc period is fixed, and could be greater than or less than one lemc cycle. Furthermore, flexible link deterministic latency can be achieved by flexibly changing the frame boundaries used by the receiver to write data received from the link into the link's buffer and the frame boundaries used by the receiver to read data received from the link's buffer.

[0056] Correspondingly, such as Figure 1 As shown in the figure, this disclosure provides a method for determining link deterministic delay, applied at a receiving end, the method may include the following steps:

[0057] In step S11, the initial frame boundary is subjected to frequency division and frequency multiplication processing according to the preset frequency division multiple and the preset frequency multiplication multiple to obtain the frequency multiplication frame boundary; wherein, the frequency multiplication frame boundary is used to write the data received from the link into the link's buffer, or to read the data received from the link from the buffer;

[0058] In step S12, the deterministic delay of the link is determined based on the estimated absolute link delay and the frequency doubling frame boundary.

[0059] The deterministic delay of a link can correspond to multiple links (sometimes referred to as a lane below). The initial frame boundary can be a frame boundary originally used to write data received from the link into the buffer of that link (e.g., the associated frame boundary RC_lemc recovered by the receiver from the data received in the link, used to write data into the buffer of that link), or a frame boundary originally used to read data received in the link from the buffer of that link (e.g., the periodic frame boundary RX_lemc generated by the receiver based on the SYSREF signal, used to read data received in the link from the buffer of that link). When the initial frame boundary is a frame boundary used for write operations, the resulting frequency-doubled frame boundary is also an associated frame boundary used for write operations; when the initial frame boundary is a frame boundary used for read operations, the resulting frequency-doubled frame boundary is also an aligned frame boundary used for read operations. After obtaining the frequency-doubled frame boundary, it is used as the new frame boundary for data read and write operations.

[0060] It should be noted that the initial frame boundary and the frequency doubling frame boundary can both be two different types of frame boundaries. However, the frame boundary used to write data received from the lane into the buffer of that lane and the frame boundary used to read data received from the lane from the buffer of that lane have the same period. Therefore, in the method of obtaining link deterministic delay, processing either type of initial frame boundary can determine the link deterministic delay.

[0061] The absolute latency of the link refers to the time it takes for data to be sent from the sending end to the receiving end and then recovered. It is the sum of three parts: the processing latency on the sending side, the routing latency between the sending end and the receiving end, and the processing latency on the receiving end. It is predictable and will not be described in detail in the embodiments disclosed herein.

[0062] As can be seen, with a fixed period for the initial frame boundary, by first performing frequency division and then frequency multiplication on the initial frame boundary according to a preset division factor and a preset multiplication factor, and by adjusting the ratio of the preset division factor to the preset multiplication factor, a flexible, arbitrarily sized multiplied frame boundary can be obtained. This multiplied frame boundary can then be used as a new frame boundary for writing / reading data, no longer limited to a fixed frame structure period. The multiplied frame boundary can be larger or smaller than the initial frame boundary, and the relationship between the multiplied and initial frame boundaries is not limited to a specific integer multiple. Furthermore, after obtaining a multiplied frame boundary of arbitrary size, the deterministic link delay can be determined based on the estimated absolute link delay and the multiplied frame boundary, thus obtaining a flexible, deterministic link delay. It solves the problem of limited values ​​for deterministic delay; when the absolute delay of the link is small but the deterministic delay is large, the deterministic delay can be reduced without changing the circuit design, thus solving the problem of wasted delay caused by a small absolute delay but a large deterministic delay; when the absolute delay of the link is large but the deterministic delay is small, it is not necessary to shorten the traces by changing the circuit design to reduce the absolute delay of the link to make it smaller than the deterministic delay. Instead, the deterministic delay can be increased without changing the circuit design, thus solving the problem of high circuit design complexity caused by a large absolute delay but a small deterministic delay, and reducing the complexity of the circuit design.

[0063] Furthermore, for certain devices or equipment, they need to operate in different application scenarios. Even if the frame structure period is the same, the processing clock period used in different application scenarios may be inconsistent, which will lead to inconsistent latency when the device or equipment is working in these application scenarios. By adopting the link deterministic latency determination method provided in the embodiments of this disclosure, the frequency multiplication frame boundary used for data read and write operations in each application scenario is different, but the deterministic latency obtained in each application scenario can be kept consistent, which further reduces the design complexity of the device or equipment and improves the compatibility of the device or equipment.

[0064] It should be noted that any data transmission system with a specific frame structure can obtain deterministic delay using the deterministic delay determination method provided in the embodiments of this disclosure. It is not limited to data transmission systems with the LEMC frame structure specified in the JESD204C protocol mentioned above. For example, it can also be a data transmission system with the LMFC (Local Multi Frame Clock) frame structure, which is specified in the JESD204B protocol.

[0065] The following explanation uses the LEMC frame structure as an example. In one specific implementation, the initial frame boundary can be either a path-aligned frame boundary (RC_lemc) used for data writing operations, or an aligned frame boundary (RX_lemc) used for data reading operations. When the initial frame boundary is RC_lemc, the frequency-doubled frame boundary can be represented as RC_mul_lemc; when the initial frame boundary is RX_lemc, the frequency-doubled frame boundary can be represented as RX_mul_lemc. The period of RC_lemc is consistent with the period of RX_lemc, and the period of RC_mul_lemc is consistent with the period of RX_mul_lemc.

[0066] Accordingly, in some embodiments, the initial frame boundary is an initial in-path frame boundary or an initial aligned frame boundary, the frequency doubling frame boundary is a frequency doubling in-path frame boundary or a frequency doubling aligned frame boundary, the initial in-path frame boundary corresponds to the frequency doubling frame boundary, the initial aligned frame boundary corresponds to the frequency doubling aligned frame boundary, and the period of the frequency doubling in-path frame boundary is the same as the period of the frequency doubling aligned frame boundary; the frequency doubling in-path frame boundary is used to write data received from the link into the link's buffer; the frequency doubling aligned frame boundary is used to read data received from the buffer in the link.

[0067] The absolute link delay is predictable and needs to be less than the deterministic link delay. A flexible deterministic delay can be obtained based on the frequency multiplication frame boundary by using the absolute link delay as an auxiliary reference. Accordingly, in some embodiments, such as... Figure 2As shown, determining the deterministic link delay (i.e., step S12) based on the estimated absolute link delay and the frequency multiplication frame boundary may include the following steps:

[0068] In step S21, N times the period of the frequency doubling frame boundary is taken as the period of the link deterministic delay, where N is a positive integer;

[0069] In step S22, the value of N is determined based on the estimated absolute link delay and the frequency multiplication frame boundary.

[0070] Taking the frequency doubling frame boundary as RX_mul_lemc as an example, the deterministic delay of the link can be expressed as N*RX_mul_lemc, where N is a positive integer. The value of N is further determined based on the estimated absolute delay of the link and the frequency doubling frame boundary.

[0071] In some embodiments, such as Figure 3 As shown, determining the value of N based on the estimated link absolute delay and the frequency multiplication frame boundary (i.e., step S122) may include the following steps:

[0072] In step S31, if the estimated absolute link delay is less than the frequency doubling frame boundary, the value of N is determined to be 1.

[0073] The estimated absolute link delay is denoted as T_d. Taking the frequency multiplication frame boundary as RX_mul_lemc as an example, when T_d is less than RX_mul_lemc, the deterministic delay can be RX_mul_lemc, that is, N takes the value of 1.

[0074] In some embodiments, such as Figure 4 As shown, determining the value of N based on the estimated link absolute delay and the frequency multiplication frame boundary (i.e., step S122) may include the following steps:

[0075] In step S41, if the estimated absolute link delay is not less than the frequency doubling frame boundary, the value conditions are determined based on the estimated absolute link delay, the frequency doubling frame boundary, and the link uncertainty parameters.

[0076] In step S42, the smallest positive integer that satisfies the value condition is determined as the value of N.

[0077] The estimated link absolute delay is denoted as T_d. Taking the frequency doubling frame boundary as RX_mul_lemc as an example, if T_d is not less than RX_mul_lemc, RX_mul_lemc cannot be directly used as the link deterministic delay. At this time, it is necessary to further determine the value of N based on the estimated link absolute delay, the frequency doubling frame boundary, and the link uncertainty parameters, so that the link absolute delay is less than the link deterministic delay and all lanes can obtain the same deterministic delay.

[0078] In this disclosure, the term "link uncertainty parameter" refers to a parameter that changes due to environmental factors. For example, parameters that change due to environmental factors such as voltage and temperature. The "link uncertainty parameter" can be determined based on actual environmental factors and specific tests. Alternatively, it can be expressed according to relevant measurement standards (e.g., "Evaluation and Expression of Measurement Uncertainty").

[0079] Accordingly, in some embodiments, such as Figure 5 As shown, the determination of value conditions (i.e., as described in step S41) based on the estimated link absolute delay, frequency doubling frame boundary, and link uncertainty parameters may include the following steps:

[0080] In step S51, the minimum link absolute delay and the maximum link absolute delay are determined based on the estimated link absolute delay and the link uncertainty parameters.

[0081] In step S52, the value conditions are determined based on the minimum link absolute delay, the maximum link absolute delay, and the frequency multiplication frame boundary.

[0082] The estimated link absolute delay is denoted as T_d. Based on T_d and the link uncertainty parameters, the minimum lane absolute delay T_d_min and the maximum lane absolute delay T_d_max among all lanes are determined. Taking the frequency multiplication frame boundary RX_mul_lemc as an example, the deterministic delay can be determined based on T_d_min, T_d_max and RX_mul_lemc.

[0083] Accordingly, in some embodiments, the condition for taking the value can be: (N-1) times the period of the frequency doubling frame boundary is less than the minimum link absolute delay, and N times the period of the frequency doubling frame boundary is greater than the maximum link absolute delay.

[0084] The condition for the value can be expressed as: T_d_min>(N-1)*RX_mul_lemc, and N*RX_mul_lemc>T_d_max.

[0085] As mentioned above, since the deterministic link delay is determined based on the estimated absolute link delay and the frequency multiplication frame boundary in this embodiment, an arbitrary-size deterministic link delay can be obtained after obtaining an arbitrary-size frequency multiplication frame boundary (i.e., the period of the frequency multiplication frame boundary is of arbitrary length). The reason why an arbitrary-size frequency multiplication frame boundary can be obtained is that the preset frequency division multiple and the preset frequency multiplication multiple are not limited.

[0086] Let the preset division factor be denoted as d, and the preset multiplication factor be denoted as m. Taking the initial frame boundary as RX_lemc, the division frame boundary as RX_div_lemc, and the multiplication frame boundary as RX_mul_lemc as an example, let the period of RX_lemc be denoted as t0, and the period of RX_mul_lemc as t1. The least common multiple of t0 and t1 is denoted as c = LCM(t0, t1). Taking the period of RX_div_lemc as c, the division factor for RX_lemc is d = c / t0, and the multiplication factor for RX_div_lemc is m = c / t1. The multiplied RX_mul_lemc is obtained, and the period of RX_mul_lemc is d / m times the period of RX_lemc. It can be seen that the period of RX_mul_lemc can be smaller or larger than the period of RX_lemc. The relationship between RX_mul_lemc and RX_lemc is arbitrary and no longer limited to a certain integer multiple relationship. Even if the period of RX_lemc is a fixed lemc period, the period of RX_mul_lemc can be made to take any value by changing the values ​​of d and m.

[0087] When the initial frame boundary is RC_lemc or RX_lemc, before step S11 above, the receiver recovers RC_lemc based on the data received in the lane and generates RX_lemc based on the received reference signal, i.e., the SYSREF signal. Correspondingly, in some embodiments, such as... Figure 6 As shown, the method also includes the steps of obtaining the initial in-path frame boundary and the initial alignment frame boundary:

[0088] In step S61, data is received from the link and the received data is decoded to obtain the initial trailing frame boundary;

[0089] In step S62, a reference signal is received, and the initial alignment frame boundary is determined based on the reference signal and the lemc interval agreed upon with the transmitter in advance.

[0090] like Figure 7 As shown below, a specific embodiment will be used to describe the contents of steps S61, S62, and S11 in detail.

[0091] In step S71, data is received and RC_lemc is recovered according to the sending end protocol.

[0092] The content of step S71 is actually the same as that of step S61.

[0093] When data is transmitted through a serial link, the sending and receiving ends pre-agree on the frame format. For example, the JESD204C protocol specifies a frame structure based on multiple bytes. The sending end marks the frame boundaries and transmits them through the link. The frame boundary is denoted as TX_lemc. The generation method of TX_lemc is similar to that of RX_lemc, also generated by the sending end based on the received SYSREF signal. The receiving end, according to the pre-agreed protocol with the sending end, performs a series of decoding operations on the received data stream to obtain the initial frame boundary RC_lemc. The period of RC_lemc is the same as that of TX_lemc.

[0094] In step S72, RC_lemc is divided by a factor of d according to a preset division factor d to obtain RC_div_lemc.

[0095] The period of RC_div_lemc is d times the period of RC_lemc.

[0096] In step S73, RC_div_lemc is multiplied by m according to the preset multiplication factor m to obtain RC_mul_lemc.

[0097] Wherein, the period of RC_div_lemc is m times the period of RC_mul_lemc, and the period of RC_mul_lemc is d / m times the period of RC_lemc.

[0098] In step S74, the SYSREF signal is received, and RX_lemc is generated according to the lemc interval of the sending end protocol.

[0099] In particular, the content of step S74 is actually the same as that of step S62, and there is no fixed execution order between steps S71-S73 and steps S74-S76.

[0100] The receiver and transmitter pre-agree on the lemc interval based on the actual application scenario. For example, in the JESD204C protocol, the lemc interval is pre-defined according to a specific parameter configuration for the application scenario. The receiver receives the SYSREF signal and uses it as a reference starting point to generate a periodic signal RX_lemc with the lemc interval as the periodic interval.

[0101] In step S75, RX_lemc is divided by a factor of d according to a preset division factor d to obtain RX_div_lemc.

[0102] The period of RX_div_lemc is d times the period of RX_lemc.

[0103] In step S76, RX_div_lemc is multiplied by m according to the preset multiplication factor m to obtain RX_mul_lemc.

[0104] Wherein, the period of RX_div_lemc is m times the period of RX_mul_lemc, and the period of RX_mul_lemc is d / m times the period of RX_lemc.

[0105] In step S77, each link sequentially writes link data to the memory under the control of RC_mul_lemc, and the write address is cleared to zero when the first RC_mul_lemc is valid; each link sequentially reads data from the memory under the control of RX_mul_lemc, and the read address is cleared to zero each time RX_mul_lemc is valid.

[0106] Specifically, each link has a dedicated memory for caching data received from that link. When the first RC_mul_lemc is received, write enable is enabled, the write address is cleared to zero, and then the write address is incremented sequentially to write the link data into the memory. Data can only be read after the data is written. When the first RX_mul_lemc is received, read enable is enabled, the read address is cleared to zero, and then the read address is incremented sequentially to read the data from the memory.

[0107] The following combination Figure 8 , Figure 9 and Figure 10 Taking an example, we will briefly describe the method for determining link deterministic delay provided in the embodiments of this disclosure.

[0108] like Figure 8As shown, the transmitting and receiving ends share the same reference signal. Both the TX_lemc of the transmitting end and the RX_lemc of the receiving end are generated based on this reference signal. In JESD204C, the reference signal is the SYSREF signal. Taking a specific data_n as an example, data_n specifically refers to the data corresponding to the boundary of the RC_mul_lemc obtained after processing RC_lemc. data_n is transmitted at the boundary of a certain TX_lemc. For a certain lane, data_n will appear at the time of the solved RC_mul_lemc. data_n is written into memory and awaits being read. The time when data_n is read is at RX_mul_lemc. Because different lanes have different data transmission delays, the arrival time of data_n may also be different for different lanes. For a certain lane, if data_n arrives earlier, it will remain in memory for a longer time. For another lane, if data_n arrives later, it will remain in memory for a shorter time. However, data_n from all lanes will be read simultaneously. In this way, data_n from all lanes is sent from TX_lemc and synchronously received by RX_mul_lemc, with the same deterministic delay of N*RX_mul_lemc (N is a positive integer), in the unit of working clock cycles.

[0109] like Figure 9 As shown, this is a schematic diagram where the period of RX_mul_lemc is less than the period of RX_lemc. First, RX_lemc is divided by 3 to obtain RX_div_lemc. Then, the obtained RX_div_lemc is multiplied by 4 to obtain RX_mul_lemc. Finally, the period of RX_mul_lemc is 3 / 4 of the period of RX_lemc, where T represents the period of RX_lemc.

[0110] like Figure 10 As shown, this is a schematic diagram where the period of RX_mul_lemc is greater than the period of RX_lemc. First, RX_lemc is divided by 3 to obtain RX_div_lemc. Then, the obtained RX_div_lemc is multiplied by 2 to obtain RX_mul_lemc. Finally, the period of RX_mul_lemc is 3 / 2 of the period of RX_lemc, where T represents the period of RX_lemc.

[0111] Furthermore, embodiments of this disclosure also provide an electronic device that may include:

[0112] One or more processors;

[0113] A storage device on which one or more programs are stored;

[0114] When one or more programs are executed by one or more processors, the one or more processors implement the determination method for link deterministic delay as described above.

[0115] Furthermore, this disclosure also provides a computer storage medium storing a computer program thereon, wherein when the program is executed, it implements the link deterministic delay determination method as described above.

[0116] It will be understood by those skilled in the art that all or some of the steps in the methods disclosed above, and the functional modules / units in the apparatus, can be implemented as software, firmware, hardware, and suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0117] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A method for determining the deterministic delay of a link, wherein, The method includes: Based on a preset frequency division factor and a preset frequency multiplication factor, the initial frame boundary is subjected to frequency division and frequency multiplication processing to obtain a frequency multiplication frame boundary; wherein, the frequency multiplication frame boundary is used to write data received from the link into the buffer of the link, or to read data received from the link from the buffer; The deterministic delay of the link is determined based on the estimated absolute link delay and the frequency multiplication frame boundary.

2. The method according to claim 1, wherein, The initial frame boundary is either the initial in-path frame boundary or the initial aligned frame boundary, and the frequency-doubled frame boundary is either the frequency-doubled in-path frame boundary or the frequency-doubled aligned frame boundary. The initial in-path frame boundary corresponds to the frequency-doubled in-path frame boundary, and the initial aligned frame boundary corresponds to the frequency-doubled aligned frame boundary. The period of the frequency-doubled in-path frame boundary is the same as the period of the frequency-doubled aligned frame boundary. The frequency-multiplied frame boundary is used to write data received from the link into the link's buffer; The frequency-doubled aligned frame boundary is used to read data received in the link from the cache.

3. The method according to claim 2, wherein, The step of determining the deterministic link delay based on the estimated absolute link delay and the frequency multiplication frame boundary includes: The period of the frequency doubling frame boundary is N times the period of the link deterministic delay, where N is a positive integer; The value of N is determined based on the estimated absolute link delay and the frequency multiplication frame boundary.

4. The method according to claim 3, wherein, The step of determining the value of N based on the estimated link absolute delay and the frequency multiplication frame boundary includes: If the estimated absolute link delay is less than the frequency multiplier frame boundary, then N is determined to be 1.

5. The method according to claim 3, wherein, The step of determining the value of N based on the estimated link absolute delay and the frequency multiplication frame boundary includes: If the estimated absolute link delay is not less than the frequency doubling frame boundary, the value of N is determined based on the estimated absolute link delay, the frequency doubling frame boundary, and the link uncertainty parameter. The smallest positive integer that satisfies the given value condition is determined as the value of N.

6. The method according to claim 5, wherein, The step of determining the value conditions based on the estimated link absolute delay, the frequency multiplication frame boundary, and the link uncertainty parameters includes: Based on the estimated link absolute delay and link uncertainty parameters, the minimum link absolute delay and the maximum link absolute delay are determined. The value selection conditions are determined based on the minimum link absolute delay, the maximum link absolute delay, and the frequency multiplication frame boundary.

7. The method according to claim 6, wherein, The condition for N is that (N-1) times the period of the frequency doubling frame boundary is less than the minimum link absolute delay, and N times the period of the frequency doubling frame boundary is greater than the maximum link absolute delay.

8. The method according to any one of claims 2-7, further comprising: Data is received from the link, and the received data is decoded to obtain the initial trailing frame boundary; Receive a reference signal and determine the initial alignment frame boundary based on the reference reference signal and the lemc interval agreed upon in advance with the transmitter.

9. An electronic device, comprising: One or more processors; A storage device on which one or more programs are stored; When the one or more programs are executed by the one or more processors, the one or more processors implement the method for determining link deterministic delay as described in any one of claims 1-8.

10. A computer storage medium having a computer program stored thereon, wherein, When the program is executed, it implements the method for determining link deterministic delay as described in any one of claims 1-8.

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