Xor and graph quantum circuit synthesis method for optimizing CNOT operation

Abstract

The application discloses an exclusive or and diagram quantum circuit synthesis method for optimizing CNOT operation, comprising the following steps: S100, creating an AND gate node or an XOR gate node for a logical and item or a logical exclusive or item in an exclusive or and expression of a Boolean function f, and obtaining an XAG representing the Boolean function f; S200, traversing each node in the XAG, and respectively constructing a mapping relationship between an AND gate node, an XOR gate node and a Clifford+T gate cascade according to a type of the node, whether an edge between the node and 0 branch sub-nodes and 1 branch sub-nodes of the node is a complementary edge, and whether the sub-nodes are shared; and adding the Clifford+T gate cascade mapped by the corresponding type node to a circuit according to a circuit line label based on the mapping relationship; and finally obtaining a Clifford+T quantum circuit for the optimized CNOT operation constructed for the Boolean function f. The method has the advantages that the CNOT operation is optimized without increasing the number of qubits, the number of CNOT gates and the depth of CNOT gates of the Clifford+T quantum circuit obtained from the XAG are reduced, and therefore, efficient and high-fidelity quantum calculation is realized.

Description

Technical Field

[0001] This invention relates to the field of quantum circuit synthesis and design technology, and in particular to a method for optimizing CNOT operations using XOR AND graph quantum circuit synthesis. Background Technology

[0002] Quantum circuits, composed of quantum gates acting on qubits, are a common model for realizing quantum computing. Due to the fragility of qubits, current quantum technologies only support single-qubit and two-qubit quantum gates. On the one hand, under current quantum technologies, two-qubit gates, i.e., controllable-inverse-negative (CNOT) gates, have higher implementation complexity and more execution cycles compared to single-qubit gates. On the other hand, due to the interaction between the quantum system and its environment, correlation errors between qubits caused by specific quantum hardware make CNOT gates the main source of errors in current quantum circuits. This necessitates optimizing CNOT operations in quantum circuits, reducing the number and depth of CNOT gates, to achieve efficient and high-fidelity quantum computing.

[0003] Arithmetic functions are widely used in quantum computing, quantum encryption, and security. Xor-And Graphs (XAGs), as function structures or circuit representation models, can represent arithmetic functions in a relatively compact way. Furthermore, XAGs are often used to reduce the multiplicative complexity of functions. [1] Compared to using other functions to represent models, using XAG as a representation model for synthesizing quantum circuits has significant advantages. [2] .

[0004] A commonly used general quantum gate library is the Clifford+T gate library, which consists of Clifford gates and T gates. Clifford gates include single-qubit gates (H gates, NOT gates, etc.) and two-qubit gates (CNOT gates). T gates include T0 or T1 gates. Gates. XAG quantum circuit synthesis methods typically use XAG representation functions to map the AND and XOR gate nodes in the XAG to cascaded Clifford+T gates, thus obtaining a Clifford+T quantum circuit. However, current XAG quantum circuit synthesis methods focus more on reducing the number of T gates and the T-gate depth by increasing the number of CNOT gates or qubits, without optimizing for CNOT operations. Qubits are a relatively scarce quantum resource, and increasing the number of qubits is detrimental to the physical implementation of quantum circuits. Increasing the number of CNOT gates is detrimental to achieving efficient and high-fidelity quantum computing. Therefore, when using XAG representation functions to synthesize Clifford+T quantum circuits, it is necessary to optimize CNOT operations without increasing the number of qubits.

[0005] In summary, to achieve efficient and high-fidelity quantum computing, when using XAG to synthesize Clifford+T quantum circuits, it is necessary to find a quantum circuit synthesis method that optimizes CNOT operations, reducing the number of CNOT gates and the CNOT gate depth without increasing the number of qubits.

[0006] References:

[0007] [1]. E. Testa, M. Soeken, L. Amarù and GDMicheli. Reducing the multiplicative complexity in logic networks for cryptography and security applications. In 2019 56th ACM / IEEE Design Automation Conference (DAC). 2019, Las Vegas, NV, USA, 1–6.

[0008] [2].G.Meuli, M.Soeken and G.De Micheli.Xor-and-inverter graphs forquantum compilation.Npj Quantum Information 8.2022,7:1-11. Summary of the Invention

[0009] The purpose of this invention is to provide an optimized method for synthesizing XOR AND graph quantum circuits for CNOT operations, thereby solving the aforementioned problems existing in the prior art.

[0010] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0011] A method for synthesizing XOR AND graph quantum circuits to optimize CNOT operations includes the following steps:

[0012] S100. Using XAG to represent Boolean functions:

[0013] For a Boolean function f, given an XOR expression consisting of logical AND terms and logical XOR terms, the XAG representing the Boolean function f is obtained by creating AND gate nodes or XOR gate nodes for the logical AND terms or logical XOR terms in the XOR expression.

[0014] S200, Clifford+T quantum circuits constructed using XAG as a Boolean function and optimized with CNOT operations:

[0015] Traverse each node in the XAG, and construct mapping relationships between AND gate nodes and Clifford+T gate cascades, and between XOR gate nodes and Clifford+T gate cascades, based on the node type, whether the edges between a node and its 0-branch and 1-branch child nodes are supplementary edges, and whether the child nodes are shared. Based on the mapping relationships, add the Clifford+T gate cascades mapped to the corresponding types of nodes to the circuit according to the circuit line labels. Finally, obtain the Clifford+T quantum circuit constructed for the Boolean function f by the optimized CNOT operation.

[0016] Preferably, step S100 specifically includes the following:

[0017] S101. Create an AND gate node or an XOR gate node for a logical AND term or logical XOR term in the XOR expression of the Boolean function f. If the number of literals in the logical AND term or logical XOR term is greater than 2, first decompose it into several logical AND terms or logical XOR terms with a literal number of 2. Then create an AND gate node or an XOR gate node for the logical AND term or logical XOR term with a literal number of 2, and use the node function of the obtained node to replace the 2 literals in the logical AND term or logical XOR term respectively.

[0018] S102. Recursively execute step S101 until there is only one single text item in the XOR expression of the Boolean function f; if this text item is a negation operation, then add an outgoing edge as a supplementary edge to the node corresponding to the text item in the XAG; finally, obtain the XAG representing the Boolean function f.

[0019] Preferably, in step S101, creating an AND gate node or an XOR gate node for a logical AND term or logical XOR term with a word count of 2 specifically includes the following:

[0020] S1011. If the literal in a logical AND or logical XOR term is a variable x u If ∈X, then first create a variable node for the variable in XAG; if a variable node v already exists in XAG... i Then the node v is shared. i No new node needs to be created for this variable; otherwise, a variable node v should be created for this variable. i ;

[0021] If the literal in a logical AND or XOR term is not a variable, then there must exist a node v in the XAG containing that literal. j Share this node v j No new node needs to be created for this text;

[0022] Then use the node function f(v) i ) and f(v jReplace two characters in the logical AND or logical XOR term;

[0023] S1012. Create AND gate nodes or XOR gate nodes in the XAG for the logical AND or XOR terms after text replacement; if the node v for the logical AND or XOR term already exists in the XAG. k Then the node v is shared. k No new node needs to be created; otherwise, a node v is created in the XAG for the logical AND / OR XOR term. k At the same time, create node v respectively k With node v i and node v k With node v j The edge e(v) between i ,v k ) and e(v j ,v k ); when the literal terms in the logical AND or logical XOR term are related to the node function f(v i ) or f(v j Perform the negation operation, that is... or When, then edge e(v) i ,v k ) or e(v j ,v k () represents the edge filling;

[0024] Then use the node function f(v) k Replace the logical AND term or logical XOR term in the XOR expression of the Boolean function f.

[0025] Preferably, step S200 specifically includes the following:

[0026] S201. Add n circuit lines to the circuit, and use the input variables x1, x2, ..., x1 respectively. n Label the n circuit lines, and use each circuit line to store the state of a variable;

[0027] S202. Perform a depth-first traversal of the nodes in the XAG to obtain an ordered set of nodes V = {v1, v2, ..., v...} d}, where d is the number of nodes in the XAG;

[0028] S203, Let k = 1;

[0029] S204, Based on node v k The type of ∈V is determined by the mapping relationship between AND gate nodes and Clifford+T gate concatenations, and the mapping relationship between XOR gate nodes and Clifford+T gate concatenations, which determines the type of node v. kThe mapping is a cascade of Clifford+T gates obtained by optimizing the CNOT operation;

[0030] S205. Let k = k + 1; if k ≤ d, jump to step S204, otherwise jump to step S206;

[0031] S206. The circuit synthesis process is complete, resulting in a Clifford+T quantum circuit constructed from Boolean function f using optimized CNOT operations.

[0032] Preferably, step S204 specifically includes the following:

[0033] S2041, if v k It represents the variable x u For a variable node (1≤u≤n), then v k The corresponding circuit is labeled x u The circuit lines;

[0034] S2042, if v k It is an AND gate node or an XOR gate node. Assume node v in the XAG... k The child nodes with 0 branches and the child nodes with 1 branches are v i and v j (1≤i≤d, 1≤j≤d, and i≠k∧j≠k∧i≠j), the circuit is labeled as follows. and The circuit lines respectively store the node function f(v) i ) and f(v j The calculation results;

[0035] Based on node v k Its 0-branch child node v i and 1 branch child node v j Determine whether the edges between nodes are supplementary edges and whether child nodes are shared, and construct mapping relationships between AND gate nodes and Clifford+T gate concatenations, and between XOR gate nodes and Clifford+T gate concatenations, respectively; and based on the corresponding mapping relationships, assign AND gate node v k or XOR gate node v k The mapped Clifford+T gate cascades are added to the circuit according to the circuit line labels; for storing the node function f(v) k Add circuit line labels to the circuit lines in the calculation results.

[0036] Preferably, step S2042 specifically includes the following:

[0037] S20421, If ​​node v kTo represent an AND gate, first add a circuit line with the input state being the quantum ground state |0> to store the node function f(v). k )=f(v i )f(v j The calculation results are then used to determine the AND gate node v based on the mapping relationship between the AND gate node and the Clifford+T gate concatenation. k This is mapped to the corresponding Clifford+T gate cascade, which means adding the Clifford+T gate cascade to the circuit according to the circuit line labels, and labeling the added circuit lines as follows:

[0038] S20422, If node v k If we denote an XOR gate, then based on the mapping relationship between the XOR gate node and the cascaded Clifford+T gates, we can define the XOR gate node v... k The mapping is to the corresponding Clifford+T gate cascade, that is, to add the Clifford+T gate cascade to the circuit according to the circuit line label; depending on the specific situation in the mapping relationship, the circuit line with the input state of quantum ground state |0> or the circuit labeled as The circuit lines or circuits labeled as Circuit storage node function The calculation results were used to label the circuit line as follows.

[0039] Preferably, step S2042 further includes,

[0040] S20423, when v k When it is the root node of an XAG, if node v k If there is one outgoing edge that serves as a supplementary edge, then it is labeled as follows in the circuit: Add a NOT gate to the circuit line and relabel the circuit line with f; otherwise, label it as... The circuit line is relabeled as f, indicating that the circuit line outputs the calculation result of the Boolean function f.

[0041] Preferably, the mapping relationship between the AND gate node and the Clifford+T gate cascade includes,

[0042] AND gate node case I: e(v) i ,v k ) and e(v j ,v k None of them are edge padding. The corresponding AND gate node is the first type of Clifford+T gate cascade, expressed as follows:

[0043]

[0044] AND gate node case II: e(v) i ,v k ) is the edge supplement, e(v) j ,v k This is not edge padding; it corresponds to the second type of Clifford + T gate cascade for AND gate nodes, expressed as follows:

[0045]

[0046] AND gate node case III: e(v) i ,v k ) is not for edge filling, e(v) j ,v k () represents the filler edge, corresponding to the third type of Clifford+T gate cascade for AND gate nodes, expressed as follows:

[0047]

[0048] AND gate node case IV: e(v) i ,v k ) and e(v j ,v k All of these are filler edges, corresponding to the fourth type of Clifford+T gate cascade for AND gate nodes, expressed as follows:

[0049]

[0050] Among them, e(v i ,v k ) and e(v j ,v k ) are nodes v k Its 0 branch node v i and 1 branch child node v j The edge between; For newly added circuit lines with the input state being the quantum ground state |0>; and These are respectively acting on the circuit lines H-door, T-door and Door; To act on the circuit line and The CNOT gate, in which the circuit lines and These represent the control circuit line and the target circuit line, respectively. It acts on the circuit line and The CNOT gate, in which the circuit lines and These represent the control circuit line and the target circuit line, respectively. This indicates a cascading of doors.

[0051] Preferably, the mapping relationship between the XOR gate node and the Clifford+T gate cascade includes,

[0052] XOR gate node case I: e(v i ,v k ) and e(v j ,v k None of them are edge completions, and the zero-branch child node v i and 1 branch child node v j They are all shared;

[0053] XOR gate node case II: e(v i ,v k ) and e(v j ,v k All are supplementary edges, and the zero-branch child node v i and 1 branch child node v j They are all shared;

[0054] Both XOR gate node case I and XOR gate node case II correspond to the first type of Clifford+T gate cascade for XOR gate nodes, expressed as follows:

[0055]

[0056] XOR gate node case III: e(v i ,v k ) is to fill in the edge, e(v) j ,v k It is not an edge patching, and the zero-branch child node v i and 1 branch child node v j They are all shared;

[0057] XOR gate node case IV: e(v i ,v k ) is not the side-filling part, e(v) j ,v k ) is an edge supplement, and 0 branches to child node v. i and 1 branch child node v j They are all shared;

[0058] Both XOR gate node cases III and IV correspond to the second type of Clifford+T gate cascade for XOR gate nodes, expressed as follows:

[0059]

[0060] XOR gate node case V: e(v) i ,v k ) and e(vj ,v k None of them are edge completions, and the zero-branch child node v i Not shared;

[0061] XOR gate node case VI: e(v i ,v k ) and e(v j ,v k All are supplementary edges, and the zero-branch child node v i Not shared;

[0062] Both XOR gate node cases V and VI correspond to the third type of Clifford+T gate cascade for XOR gate nodes, expressed as follows:

[0063]

[0064] XOR gate node case VII: e(v i ,v k ) is to fill in the edge, e(v) j ,v k It is not an edge patching, and the zero-branch child node v i Not shared;

[0065] XOR gate node case VIII: e(v i ,v k ) is not the side-filling part, e(v) j ,v k ) is an edge supplement, and 0 branches to child node v. i Not shared;

[0066] Both XOR gate node cases VII and VIII correspond to the fourth type of Clifford+T gate cascade, expressed as follows:

[0067]

[0068] XOR gate node case IX: e(v) i ,v k ) and e(v j ,v k None of them are edge completions, and the zero-branch child node v i Shared, 1-branch child node v j Not shared;

[0069] XOR gate node case X: e(v) i ,v k ) and e(v j ,v k All are supplementary edges, and the zero-branch child node v i Shared, 1-branch child node vj Not shared;

[0070] Both XOR gate node cases IX and XOR gate node cases X correspond to the fifth type of Clifford+T gate cascade, expressed as follows:

[0071]

[0072] XOR gate node case XI: e(v i ,v k ) is to fill in the edge, e(v) j ,v k It is not an edge patching, and the zero-branch child node v i Shared, 1-branch child node v j Not shared;

[0073] XOR gate node case XII: e(v i ,v k ) is not the side-filling part, e(v) j ,v k ) is an edge supplement, and 0 branches to child node v. i Shared, 1-branch child node v j Not shared;

[0074] Both XOR gate node cases XI and XOR gate node cases XII correspond to the sixth type of Clifford+T gate cascade for XOR gate nodes, expressed as follows:

[0075]

[0076] Among them, e(v i ,v k ) and e(v j ,v k ) are nodes v k Its 0-branch child node v i and 1 branch child node v j The edge between; For newly added circuit lines with the input state being the quantum ground state |0>; To act on the circuit line and The CNOT gate, in which the circuit lines and These represent the control circuit line and the target circuit line, respectively. For action on circuit lines and The CNOT gate, in which, and These represent the control circuit line and the target circuit line, respectively. For action on circuit lines The NOT gate; It acts on the circuit line The NOT gate; This indicates a cascading of doors.

[0077] Preferably, in step S20422, the node functions are stored using corresponding circuit lines according to the specific circumstances in the mapping relationship. The calculation results, and used The circuit line is specifically labeled as follows:

[0078] For XOR gate node cases I to IV, before adding the Clifford+T gate cascade in the circuit, a circuit line with the quantum ground state |0> as the input state needs to be added first to store the node function. The calculation results, and used Label the circuit line;

[0079] For XOR gate node cases V to VIII, use the circuit notation as shown. Circuit storage node function The calculation results were used to relabel the circuit lines as follows.

[0080] For XOR gate node cases IX to XII, use the circuit notation as shown. Circuit storage node function The calculation results were used to relabel the circuit lines as follows.

[0081] The beneficial effects of this invention are: it solves the problem that the Clifford+T quantum circuits obtained by the current XAG quantum circuit synthesis method have a large number of CNOT gates and a high CNOT gate depth. It optimizes CNOT operations without increasing the number of qubits, thereby reducing the number of CNOT gates and the CNOT gate depth of the Clifford+T quantum circuits obtained by XAG, thus achieving efficient and high-fidelity quantum computing. Attached Figure Description

[0082] Figure 1 This is a flowchart of the method of the present invention in Embodiment 1;

[0083] Figure 2 This is a circuit description of the cascaded Clifford+T gates mapped to the AND gate nodes in Example 1, where (a) represents the first type of cascaded Clifford+T gates for the AND gate nodes, (b) represents the second type of cascaded Clifford+T gates for the AND gate nodes, (c) represents the third type of cascaded Clifford+T gates for the AND gate nodes, and (d) represents the fourth type of cascaded Clifford+T gates for the AND gate nodes.

[0084] Figure 3 This is a circuit description of the Clifford+T gate cascades mapped to XOR gate nodes in Embodiment 1, where (a) represents the first type of Clifford+T gate cascade for XOR gate nodes, (b) represents the second type of Clifford+T gate cascade for XOR gate nodes, (c) represents the third type of Clifford+T gate cascade for XOR gate nodes, (d) represents the fourth type of Clifford+T gate cascade for XOR gate nodes, (e) represents the fifth type of Clifford+T gate cascade for XOR gate nodes, and (f) represents the sixth type of Clifford+T gate cascade for XOR gate nodes.

[0085] Figure 4 This is a schematic diagram of the XAG structure created in Example 2;

[0086] Figure 5 This is a schematic diagram of the Clifford+T quantum circuit structure synthesized using the method of the present invention in Example 2. Detailed Implementation

[0087] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0088] Example 1

[0089] In this embodiment, an XOR AND graph (XAG) quantum circuit synthesis method for optimizing CNOT operations is provided. The method mainly includes two parts: using XAG to represent Boolean functions and constructing a Clifford+T quantum circuit based on XAG as Boolean functions after optimizing CNOT operations.

[0090] Before describing the method of the present invention in detail, some basic concepts of XOR AND graph (XAG) will be introduced to facilitate understanding of the present invention.

[0091] An XAG can represent a Boolean function f with n variables, where the n variables form a set X = {x1, x2, ..., xn}. n XAG is a directed acyclic graph G = (V, E).

[0092] V = {v} k |1≤k≤d} is the set of nodes, v k 'v' is a node, and 'd' is the number of nodes in the XAG. Node v k It can represent the variable x iVariable nodes ∈X can also be AND gate nodes or XOR gate nodes representing logical AND gates or logical XOR gates. In XAG, variable nodes have no child nodes, while each AND gate node or XOR gate node has two child nodes: a 0-branch child node and a 1-branch child node. If node v k If a node is a child node of multiple nodes, then it is called node v. k Shared, i.e., node v k It is a shared node.

[0093] E={e i The set of edges is |1≤i≤|E|. If node v j (1≤j≤d∧j≠k) is the node v k If a node is a child node, then there exists a path in the XAG consisting of node v. j To node v k A directed edge is represented by a line segment with an arrowhead, and this edge is also represented by e(v). j ,v k Description. e(v) j ,v k ) are nodes v respectively j and node v k The outgoing and incoming edges. Node v k Edges between nodes with 0 branches are represented by dashed lines, while edges between nodes with 1 branch are represented by solid lines.

[0094] The node vk can be associated with the function f(v) that performs the operation. k Related to ), it is called f(v) k ) represents a node function. For example, node v k For x u For nodes with variables (1≤u≤n), then f(v) k )=x u When node v k When representing an AND gate or an XOR gate, f(v) k Perform a logical AND-OR or logical XOR operation on node v, taking its 0-branch child node and 1-branch child node as input. k If node v is the root node of the XAG, then node v k There exists an outgoing edge representing the output of function f. If this outgoing edge is a supplementary edge, then Otherwise f = f(v) k ).

[0095] The two parts of the method of the present invention will be described in detail below:

[0096] I. Using XAG to represent Boolean functions:

[0097] For a Boolean function f, given an XOR expression consisting of logical AND terms and logical XOR terms, the XAG representing the Boolean function f is obtained by creating AND gate nodes or XOR gate nodes for the logical AND terms or logical XOR terms in the XOR expression.

[0098] After a given function f has an XOR expression consisting of logical AND terms and logical XOR terms, an XAG is created by performing the following steps:

[0099] 1.1 Create AND gate nodes or XOR gate nodes for a logical AND or logical XOR term in the XOR expression of the Boolean function f. If the number of literals in the logical AND or logical XOR term is greater than 2, decompose it into several logical AND or logical XOR terms with a number of 2 literals each (those with fewer than 2 literals are treated as a single literal term). Then, create AND gate nodes or XOR gate nodes for the logical AND or logical XOR terms with a number of 2 literals each, and use the node functions of the resulting nodes to replace the two literals in the logical AND or logical XOR term respectively.

[0100] 1.11. If the literal in a logical AND or XOR term is a variable x u If ∈X, then first create a variable node for the variable in XAG; if a variable node v already exists in XAG... i Then the node v is shared. i No new node needs to be created for this variable; otherwise, a variable node v should be created for this variable. i ;

[0101] If the literal in a logical AND or XOR term is not a variable, then there must exist a node v in the XAG containing that literal. j The node v can be shared. j No new node needs to be created for this text.

[0102] Then use the node function f(v) i ) and f(v j Replace two literals in the logical AND or logical XOR term.

[0103] 1.12. Create AND gate nodes or XOR gate nodes in the XAG for the logical AND or XOR terms after text replacement. If a node v for the logical AND or XOR term already exists in the XAG. k Then the shared node v k No new node needs to be created; otherwise, a node v is created in the XAG for the logical AND / OR XOR term. k At the same time, create node v respectively k With node v i and node v k With node v j The edge e(v) betweeni ,v k ) and e(v j ,v k ); when the literal terms in the logical AND or logical XOR term are related to the node function f(v i ) or f(v j Perform the negation operation, that is... or When, then edge e(v) i ,v k ) or e(v j ,v k () represents the edge filling;

[0104] Then use the node function f(v) k Replace the logical AND term or logical XOR term in the XOR expression of the Boolean function f.

[0105] Specifically, create AND gate nodes or XOR gate nodes in the XAG for the logical AND or XOR terms after text replacement:

[0106] (1) For logical AND terms: according to logical AND term l i l j The two characters l i and l j The corresponding node v i and node v j Create an AND gate node v k and node v i and node v j Each as node v k The 0th and 1st branch child nodes are used to create node v. k With node v i and node v k With node v j The edge e(v) between i ,v k ) and e(v j ,v k When this logic is inverted by the literal terms in the item, the corresponding node function is also inverted, and the corresponding edge becomes a supplementary edge; using the node function f(v k Replace the logical AND term l in the expression of function f. i l j .

[0107] (2) For logical XOR terms: based on logical XOR terms The two characters l i and l j The corresponding node v i and node v j Create XOR gate node v k and node vi and node v j Each as node v k The 0th and 1st branch child nodes are used to create node v. k With node v i and node v k With node v j The edge e(v) between i ,v k ) and e(v i ,v k Using the node function f(v) k Replace the logical XOR term in the expression of function f.

[0108] 1.2 Recursively execute step 1.1 until there is only one single text item in the XOR expression of the Boolean function f; if this text item is a negation operation, then add an outgoing edge as a supplementary edge to the node corresponding to this text item in the XAG.

[0109] 1.3 After completing the above steps, you will obtain the XAG representing the Boolean function f.

[0110] II. Constructing a Clifford+T quantum circuit based on XAG as a Boolean function with optimized CNOT operations:

[0111] Traverse each node in the XAG, and construct mapping relationships between AND gate nodes and Clifford+T gate cascades, and between XOR gate nodes and Clifford+T gate cascades, based on the node type, whether the edges between a node and its 0-branch and 1-branch child nodes are supplementary edges, and whether the child nodes are shared. Based on the mapping relationships, add the Clifford+T gate cascades mapped to the corresponding types of nodes to the circuit according to the circuit line labels. Finally, obtain the Clifford+T quantum circuit constructed for the Boolean function f by the optimized CNOT operation.

[0112] In this embodiment, one circuit line represents one qubit, used to store the state of a variable or the calculation result of a node function. The following are the steps for constructing a Clifford+T quantum circuit for function f using an XAG with d nodes, obtained through optimized CNOT operations. This process involves cascading optimized CNOT Clifford+T gates (obtained through cascading) for the AND or XOR gate nodes in the XAG to construct the optimized CNOT Clifford+T quantum circuit for function f.

[0113] This section specifically includes the following steps.

[0114] 2.1 Add n circuit lines to the circuit, and use the input variables x1, x2, ..., x1 respectively. n Label the n circuit lines, and use each circuit line to store the state of a variable;

[0115] 2.2. Perform a depth-first traversal of the nodes in the XAG to obtain an ordered set of nodes V = {v1, v2, ..., v...} d}, where d is the number of nodes in the XAG;

[0116] 2.3. Let k = 1;

[0117] 2.4. Based on node v k The type ∈V, based on the mapping relationship between AND gate nodes and Clifford+T gate concatenations, and the mapping relationship between XOR gate nodes and Clifford+T gate concatenations, will v k The mapping is a cascade of Clifford+T gates obtained by optimizing the CNOT operation;

[0118] This step specifically includes the following situations:

[0119] 2.4.1 If v k It represents the variable x u For a variable node (1≤u≤n), then v k The corresponding circuit is labeled x u The circuit lines;

[0120] 2.4.2, If v k It is an AND gate node or an XOR gate node, based on node v k Its 0-branch child node v i and 1 branch child node v j To determine whether the edges between nodes are supplementary edges and whether child nodes are shared, construct mapping relationships between AND gate nodes and Clifford+T gate concatenations (see Table 1) and between XOR gate nodes and Clifford+T gate concatenations (see Table 2), respectively; and based on the corresponding mapping relationships, assign AND gate node v k or XOR gate node v k The mapped Clifford+T gate cascades are added to the circuit according to the circuit line labels; for storing the node function f(v) k (where the node function of the AND gate node is f(v)) k )=f(v i )f(v j The node function of the XOR gate node is... Add circuit line labels to the circuit lines in the calculation results. (wherein, it is assumed that node v in XAG) kThe child nodes with 0 branches and the child nodes with 1 branches are v i and v j (1≤i≤d, 1≤j≤d, and i≠k∧j≠k∧i≠j), the circuit is labeled as follows. and The circuit lines respectively store the node function f(v) i ) and f(v j (Calculation results). Specifically:

[0121] (1) If node v k To represent an AND gate, first add a circuit line with the input state being the quantum ground state |0> to store the node function f(v). k )=f(v i )f(v j The calculation results are then used to determine the mapping relationship between AND gate nodes and Clifford+T gate cascades (see Table 1; the circuit diagrams corresponding to each Clifford+T gate cascade are attached). Figure 2 ), and the AND gate node v k This is mapped to the corresponding Clifford+T gate cascade, which means adding the Clifford+T gate cascade to the circuit according to the circuit line labels, and labeling the added circuit lines as follows:

[0122] Table 1 AND gate node v k Mapped Clifford+T gate cascade

[0123]

[0124] Table 1 shows the Clifford+T gate concatenations constructed for AND gate nodes in this invention. These Clifford+T gate concatenations are AND gate nodes v obtained by optimizing the CNOT operation. k The Clifford+T gates are cascaded. In four cases of Clifford+T gate cascading, the number of CNOT gates is 3, and the CNOT gate depth is also 3.

[0125] The meanings of the relevant parameters in the symbol descriptions in Table 1 are as follows: e(v i ,v k ) and e(v j ,v k ) are nodes v k Its 0 branch node v i and 1 branch child node v j The edge between; For newly added circuit lines with the input state being the quantum ground state |0>; and These are respectively acting on the circuit lines H-door, T-door and Door; To act on the circuit line and The CNOT gate, in which the circuit lines and These represent the control circuit line and the target circuit line, respectively. It acts on the circuit line and The CNOT gate, in which the circuit lines and These represent the control circuit line and the target circuit line, respectively. This indicates a cascading of doors.

[0126] (2) If node v k To represent an XOR gate, the mapping relationship between XOR gate nodes and cascaded Clifford+T gates is shown in Table 2 (see Appendix for circuit diagrams corresponding to each cascaded Clifford+T gate). Figure 3 ), and the XOR gate node v k The mapping is to the corresponding Clifford+T gate cascade, that is, to add the Clifford+T gate cascade to the circuit according to the circuit line label. For cases I to IV, before adding the Clifford+T gate cascade to the circuit, a circuit line with the input state of quantum ground state |0> needs to be added to the circuit first to store the node function. The calculation results were used to label the circuit line as follows. For cases V to VIII, use the circuit labeled as follows: Circuit storage node function The calculation results were used to relabel the circuit lines as follows. (i.e., circuit lines) Need to be re-labeled For cases IX to XII, use the circuit labeled as follows. Circuit storage node function The calculation results were used to relabel the circuit lines as follows. (i.e., circuit lines) It needs to be re-labeled as ).

[0127] Table 2 XOR gate node v k Mapped Clifford+T gate cascade

[0128]

[0129]

[0130] Table 2 shows the Clifford+T gate concatenation constructed for the XOR gate nodes in this invention. This Clifford+T gate concatenation is an XOR gate node v obtained by optimizing the CNOT operation. k The Clifford+T gates are cascaded. "--" indicates that the node can be a shared node or a non-shared node. In cases I and II, the number of CNOT gates and the CNOT gate depth are both 2. In the other 10 cases, the number of CNOT gates and the CNOT gate depth are both 1.

[0131] The meanings of the relevant parameters in the symbol descriptions in Table 2 are as follows: e(v i ,v k ) and e(v j ,v k ) are nodes v k Its 0 branch node v i and 1 branch child node v j The edge between; For newly added circuit lines with the input state being the quantum ground state |0>; To act on the circuit line and The CNOT gate, in which the circuit lines and These represent the control circuit line and the target circuit line, respectively. To act on the circuit line and The CNOT gate, in which, and These represent the control circuit line and the target circuit line, respectively. To act on the circuit line The NOT gate; It acts on the circuit line The NOT gate; This indicates a cascading of doors.

[0132] 2.4.3, when v k When v is the root node of an XAG, if k If there is one outgoing edge that serves as a supplementary edge, then it is labeled as follows in the circuit: Add a NOT gate to the circuit line and relabel the circuit line with f; otherwise, label it as The circuit line is relabeled as f, indicating that the circuit line outputs the calculation result of the Boolean function f.

[0133] 2.5. Let k = k + 1; if k ≤ d, jump to step 2.4, otherwise jump to step 2.6;

[0134] 2.6 The circuit synthesis process is completed, and the Clifford+T quantum circuit constructed by optimizing CNOT operations for the Boolean function f is obtained.

[0135] Example 2

[0136] In this embodiment, the first output function f of RevLib function C17 is used as an example to illustrate the detailed execution process of the method of the present invention.

[0137] The function has four variables, forming a variable set X = {x1, x2, x3, x4}. Figure 4 It is the XAG of the first output function f of RevLib function C17. Figure 5 The method of this invention is derived from Figure 4 The diagram shows the Clifford+T quantum circuit obtained by optimizing the CNOT operation from XAG.

[0138] I. Using XAG to represent Boolean functions

[0139] This step expands upon the recursion in the "using XAG to represent Boolean functions" step in Example 1 and appropriately combines some steps.

[0140] The XOR expression for function f, consisting of logical AND terms and logical XOR terms, is:

[0141] Logical AND terms in the expression of function f The word count is 2, which is a logical AND term. Create AND gate nodes in the XAG. First, create the following in the XAG for variables x3 and x2: Figure 4 The variables are shown as nodes v1 and v2. The logical AND terms are replaced using node functions f(v1) and f(v2), respectively. Given the characters x3 and x2, we get a logical AND term with 2 characters. Next is the logical AND term. Create in XAG as follows Figure 4 The AND gate is shown, with node v3, and nodes v1 and v2 as child nodes of node v3's 1 and 0 branches respectively, creating edges e(v1,v3) and e(v2,v3). Due to the text item... and Inverting the node functions f(v1) and f(v2) respectively, edges e(v1,v3) and e(v2,v3) are both supplementary edges. Replace the logical AND term in the expression of function f with the node function f(v3). get

[0142] Logical AND terms in the expression of function f The number of characters is 2. The variable x3 already exists in XAG. Figure 4 The variable node v1 shown is shared; no new node needs to be created for variable x3. Create a new node for variable x1 in the XAG as follows: Figure 4 The variable node v4 is shown. The logical AND terms are replaced using node functions f(v4) and f(v1), respectively. Given the characters x1 and x3, we obtain a logical AND term with 2 characters. Next is the logical AND term. Create in XAG as follows Figure 4 The AND gate is shown, with node v5, and nodes v1 and v4 as child nodes of branch 1 and branch 0 of node v5, respectively, creating edges e(v1,v5) and e(v4,v5). Due to the text item... Inverting the node function f(v4) makes edge e(v4,v5) a supplementary edge. Replace the logical AND term in the expression of function f with the node function f(v5). Right now get

[0143] Logical XOR term in the expression of function f The character count is 2, and its creation in XAG is as follows: Figure 4 The XOR gate node v6 is shown, and edges e(v3,v6) and e(v5,v6) are created with nodes v3 and v5 as child nodes of node v6's 1 and 0 branches, respectively. The logical XOR term in the expression of function f is replaced with the node function f(v6). get

[0144] For the logical AND term in the expression of function f The word count is 4, so it is decomposed into two logical AND terms, each with 2 words. and And create AND gate nodes in the XAG for each of these two logical AND terms. Logical AND terms XAG contains, for example, Figure 4 The AND gate node v5 shown can be shared. It represents a logical AND term with a literal count of 2. Create AND gate nodes in the XAG. First, create variable nodes for variables x4 and x2. Variable x2 already exists in the XAG. Figure 4 The variable node v2 shown can be shared. Create a variable x4 in the XAG as follows: Figure 4 The variable node v7 is shown. The node functions f(v2) and f(v7) are used to replace the logical AND terms respectively. Given the characters x2 and x4, we get a logical AND term with 2 characters. Next, logical AND terms Create in XAG as follows Figure 4 The AND gate is shown, with node v8, and nodes v2 and v7 as child nodes of branch 0 and branch 1 of node v8, respectively, creating edges e(v2,v8) and e(v7,v8). Due to the text item... Inverting the node function f(v7) makes edge e(v7,v8) a supplementary edge. Replace the logical AND terms with node functions f(v5) and f(v8) respectively. Sub-logic and terms and Get a logical AND term with 2 literals. Next, create the product terms f(v5)f(v8) in XAG as follows: Figure 4 The AND gate node v9 is shown, and nodes v5 and v8 are created as child nodes of node v9's 0 and 1 branches, respectively, to create edges e(v5,v9) and e(v8,v9). The logical AND terms f(v5)f(v8) in the expression of function f are replaced with the node function f(v9), i.e. get

[0145] Logical XOR term in the expression of function f The number of characters is 2, and it is created in its XAG as follows Figure 4 The XOR gate node v shown 10 And nodes v9 and v6 are respectively designated as nodes v 10 The 0th and 1st branch child nodes create the edge e(v9,v 10 ) and e(v6,v 10 Using the node function f(v) 10 Replace the logical XOR term in the expression of function f. get At this point, the expression for function f contains only one literal term. Due to text items For the node function f(v) 10 Invert the sign, and it is node v in the XAG. 10 Add an outgoing edge as a filler edge. At this point, the XAG of function f is complete, as follows: Figure 4 As shown.

[0146] II. Constructing a Clifford+T quantum circuit based on XAG as a Boolean function with optimized CNOT operations.

[0147] In this embodiment, the loop in the step of "constructing a Clifford+T quantum circuit based on XAG as a Boolean function with optimized CNOT operation" in Embodiment 1 has been expanded, and some steps have been appropriately combined. In addition, because the loop has been expanded, the condition judgment step (i.e., step 2.5 in Embodiment 1) has been omitted.

[0148] Step 1: Add four circuit lines to the circuit, labeling them with the variable symbols from {x1, x2, x3, x4}, as follows: Figure 5 As shown.

[0149] Step 2: Depth-first traversal Figure 4 The XAG shown has 10 nodes. This results in an ordered set of nodes V = {v1, v2, v3, v4, v5, v6, v7, v8, v9, v...}. 10}

[0150] Step 3: Let k = 1.

[0151] Step 4: Based on the node type, using the mapping relationships in Tables 1 and 2 of Example 1, map the corresponding nodes to Clifford+T gate cascades obtained after optimizing CNOT operations:

[0152] Step 4.1 (k=1, k=2): Nodes v1 and v2 represent variables x3 and x2 respectively, and are respectively connected to... Figure 5 The third and second circuit lines correspond to each other. These two circuit lines are labeled x3 and x2, respectively.

[0153] Step 4.2 When a node represents an AND gate or an XOR gate, based on whether the edges between the node and its 0-branch child nodes and 1-branch child nodes are supplementary edges and whether the child nodes are shared, establish the mapping relationships in Tables 1 and 2 of Example 1 respectively. Then, according to the mapping relationships, cascade the Clifford+T gates mapped to the nodes and add them to the circuit according to the circuit line labels:

[0154] Step 4.2.1 (k=3): Node v3 represents an AND gate, with child nodes v2 and v1 for its 0 and 1 branches respectively. The two incoming edges e(v2,v3) and e(v1,v3) are supplementary edges, satisfying the conditions in Case IV of Table 1. Add a circuit line with an input state of quantum ground state |0> to the circuit. Figure 5 The 5th circuit line in the diagram, and according to the circuit line number. Add the Clifford+T gate cascade in Case IV of Table 1 ( Figure 5 (The sub-circuit indicated by G1, enclosed in a dashed box), then use The circuit lines added with labels.

[0155] Step 4.1 (k=4): Node v4 represents variable x1, and... Figure 5 The first circuit line in the circuit is labeled x1.

[0156] Step 4.2.1 (k=5): Node v5 represents an AND gate, with child nodes v4 and v1 for its 0 and 1 branches respectively. The incoming edge e(v4,v5) is a supplementary edge, while the incoming edge e(v1,v5) is not a supplementary edge, satisfying the conditions in Case II of Table 1. Add a circuit line with an input state of quantum ground state |0> to the circuit. Figure 5 The 6th circuit line in the diagram), and according to the circuit line number. Add the Clifford+T gate cascade in Case II of Table 1 ( Figure 5 (The sub-circuit indicated by G2, enclosed in a dashed box), then use The circuit lines added with labels.

[0157] Step 4.2.2 (k=6): Node v6 represents the XOR gate, with branch 0 and branch 1 child nodes v5 and v3 respectively. The two incoming edges e(v5,v6) and e(v3,v6) are not filler edges. Branch 0 child node v5 is a shared node, while branch 1 child node v3 is not a shared node, satisfying the conditions in case IX of Table 2. Add control lines to the circuit as follows: Target line is CNOT gate ( Figure 5 CNOT gate indicated by G3 in China), and the label is The circuit lines are re-labeled as

[0158] Step 4.1 (k=7): Node v7 represents variable x4, and... Figure 5 The fourth circuit line in the circuit is labeled x4.

[0159] Step 4.2.1 (k=8): Node v8 represents an AND gate, with child nodes v2 and v7 for its 0 and 1 branches respectively. The incoming edge e(v2,v8) is not a complement edge, while the incoming edge e(v7,v8) is a complement edge, satisfying the conditions in Case III of Table 1. Add a circuit line with an input state of quantum ground state |0> to the circuit. Figure 5 The 7th circuit line in the circuit, and according to the circuit line number. Add the Clifford+T gate cascade in Case III of Table 1 ( Figure 5 (The sub-circuit indicated by G4, enclosed in a dashed box), then use... The circuit lines added with labels.

[0160] Step 4.2.1 (k=9): Node v9 represents an AND gate, with child nodes v5 and v8 for its 0 and 1 branches respectively. The two incoming edges e(v5,v9) and e(v8,v9) are not filler edges, satisfying the conditions in Case I of Table 1. Add a circuit line with an input state of quantum ground state |0> to the circuit. Figure 5 The 8th circuit line in the circuit, and according to the circuit line number. Add the Clifford+T gate cascade from Case I in Table 1 ( Figure 5 The sub-circuit indicated by G5 (enclosed in a dashed box), then use The circuit lines added with labels.

[0161] Step 4.2.2 (k=10): Node v 10 This represents an XOR gate, with child nodes v9 and v6 in branches 0 and 1 respectively, and two incoming edges e(v9, v...). 10 ) and e(v6,v 10 None of the above are filler edges, and its 0th branch child node v9 is not a shared node, satisfying the conditions in case V of Table 2. Add control lines to the circuit as follows: Target line is CNOT gate ( Figure 5 CNOT gate indicated by G6 in China), and the label is The circuit lines are re-labeled as

[0162] Step 4.2.3 (k=10): Node v 10 It is still the root node of the XAG, and its outgoing edges are supplementary edges, therefore in Figure 5 The circuit is labeled as Add a NOT gate to the circuit line ( Figure 5 The NOT gate indicated by G7 in China, and the label is The circuit lines are relabeled as f.

[0163] Step 6 (k=11): The circuit synthesis process is complete, yielding... Figure 5 As shown, by Figure 4 XAG is a Clifford+T quantum circuit synthesized by function f. Figure 5 The symbols on the right side of the circuit are the final labels of each circuit line. Figure 5 The Clifford+T quantum circuit shown has 8 qubits, 14 CNOT gates, and a CNOT gate depth of 10.

[0164] Example 3

[0165] In this embodiment, the optimization of the Clifford+T quantum circuit is achieved by using the existing method of mapping the AND gate nodes in the XAG to a cascade of Clifford+T gates containing 6 CNOT gates (G.Meuli, M.Soeken, and G.De Micheli. Xor-and-inverter graphs for quantum compilation. Npj Quantum Information 8.2022,7:1-11.) and the method of the present invention, respectively. The optimization results of the two methods are compared to illustrate the effectiveness and superiority of the method of the present invention. The existing method maps the AND gate nodes to a cascade of Clifford+T gates as shown in (8), which is specifically optimized for T operations.

[0166] Since the Clifford+T gate cascades shown in Table 2 of this invention are obtained by mapping the XOR gate nodes in the XAG using optimized CNOT operations, for a fair comparison, both the existing method and the method of this invention construct Clifford+T quantum circuits using the same XAG as Boolean functions. Furthermore, the existing method also uses the method shown in Table 2 of this invention to map the XOR gate nodes in the XAG as Clifford+T gate cascades. Thus, the Clifford+T sub-circuits generated by mapping the XOR gate nodes in the XAG are identical in both the existing method and the method of this invention, and the number of CNOT gates in the Clifford+T sub-circuits is also the same.

[0167] Suppose that the XAG representing the function f has t AND gate nodes, and the number of CNOT gates generated by mapping the XOR gate nodes in the XAG when constructing a Clifford+T quantum circuit from the XAG is p. Existing methods use cascaded Clifford+T gates with 6 CNOT gates to map the AND gate nodes in the XAG, resulting in a Clifford+T quantum circuit with p+6t CNOT gates. The method of this invention uses cascaded Clifford+T gates with 3 CNOT gates to map the AND gate nodes in the XAG, as shown in Table 1 of this invention, resulting in a Clifford+T quantum circuit with p+3t CNOT gates. Therefore, compared to existing methods, the method of this invention reduces the number of CNOT gates in the Clifford+T quantum circuit obtained from the XAG by a proportion that is [missing information]. r = 0 only when there are no AND gate nodes in the XAG, i.e., t = 0. This case is very rare and only occurs in pure check functions. When there are no XOR gate nodes in the XAG, p = 0. In this case, compared with existing methods, the method of the present invention can reduce the number of CNOT gates in the Clifford+T quantum circuit obtained from the XAG by 50%.

[0168] The CNOT gate depth used to map the Clifford+T gate cascades of AND gate nodes is simply referred to as the CNOT gate depth of the AND gate nodes, and the CNOT gate depth used to map the Clifford+T gate cascades of XOR gate nodes is simply referred to as the CNOT gate depth of the XOR gate nodes. Since existing methods also use the method shown in Table 2 of this invention to map the XOR gate nodes in the XAG to Clifford+T gate cascades, the CNOT gate depth of the XOR gate nodes in the existing methods is the same as that in the method of this invention. However, because some CNOT gates in the Clifford+T quantum circuit can be executed in parallel, the CNOT gate depth of the Clifford+T quantum circuit obtained from the XAG is not a simple sum of the CNOT gate depths of the AND gate nodes and the CNOT gate depths of the XOR gate nodes in the XAG. Therefore, it is not easy to compare the CNOT gate depth in the same way as comparing the number of CNOT gates above. However, the CNOT gate depth of the AND gate nodes in the existing methods is 6, while the CNOT gate depth of the AND gate nodes in the method of this invention is 3. Furthermore, generally speaking, the more CNOT gates used to cascade Clifford+T gates for mapping AND gate nodes, the greater the negative impact on the parallel execution of CNOT gates in the Clifford+T quantum circuit obtained from XAG, leading to a higher CNOT gate depth in the Clifford+T quantum circuit. Based on the above analysis, this invention can also reduce the CNOT gate depth in the Clifford+T quantum circuit obtained from XAG.

[0169] To further demonstrate the effectiveness of the method of this invention, Clifford+T quantum circuit synthesis was performed on 10 arithmetic functions in the EPFL benchmark function set using both existing and present invention methods, and the results of the two methods were compared, as shown in Table 3. To ensure a fair comparison, for a given function, both methods constructed the Clifford+T quantum circuit from the same XAG. In Table 3, "Improvement" indicates the percentage reduction in the number of qubits, CNOT gates, and CNOT gate depth obtained by the present invention method compared to existing methods.

[0170] Table 3 compares the results of the method of the present invention with those of existing methods.

[0171]

[0172]

[0173] As shown in Table 3, compared with the results of existing methods, for these 10 arithmetic functions, the method of the present invention can reduce the number of CNOT gates and the CNOT gate depth without increasing the number of qubits. The number of CNOT gates and the CNOT gate depth are reduced by a maximum of 46.94% and 69.69% respectively (function Barrel Shifter), and by an average of 45.31% and 60.61% respectively.

[0174] By adopting the above-disclosed technical solution of this invention, the following beneficial effects are obtained:

[0175] This invention provides an optimized XOR AND graph quantum circuit synthesis method for CNOT operations, which solves the problem that the current XAG quantum circuit synthesis method results in a large number of CNOT gates and a high CNOT gate depth in Clifford+T quantum circuits. It optimizes CNOT operations without increasing the number of qubits, thereby reducing the number of CNOT gates and the CNOT gate depth in Clifford+T quantum circuits obtained from XAG, thus achieving efficient and high-fidelity quantum computing.

[0176] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for synthesizing XOR AND graph quantum circuits to optimize CNOT operations, characterized in that: Includes the following steps, S100. Using XAG to represent Boolean functions: For Boolean functions Given an XOR expression consisting of logical AND terms and logical XOR terms; by creating AND gate nodes or XOR gate nodes for the logical AND terms or logical XOR terms in the XOR expression, we obtain a Boolean function representing the expression. XAG; Step S100 specifically includes the following: S101 is a Boolean function. Create an AND gate node or an XOR gate node for a logical AND or logical XOR term in the XOR expression; if the number of literals in the logical AND or logical XOR term is greater than 2, first decompose it into several logical AND or logical XOR terms with a number of 2 literals; then create an AND gate node or an XOR gate node for the logical AND or logical XOR terms with a number of 2 literals, and use the node function of the obtained node to replace the 2 literals in the logical AND or logical XOR term respectively; S102, Recursively execute step S101 until the Boolean function is reached. The XOR expression contains only a single literal term; if this literal term is negated, then an outgoing edge is added as a filler edge to the node corresponding to that literal term in the XAG; finally, a Boolean function is obtained. XAG; S200, Clifford+T quantum circuits constructed using XAG as a Boolean function and optimized with CNOT operations: Traverse each node in the XAG. Based on the node type and whether the edges between a node and its 0-branch and 1-branch child nodes are supplementary edges, and whether child nodes are shared, construct mapping relationships between AND gate nodes and Clifford+T gate cascades, and between XOR gate nodes and Clifford+T gate cascades, respectively. Then, based on the mapping relationships, add the Clifford+T gate cascades mapped to the corresponding node types to the circuit according to the circuit line labels. The final result is a Boolean function. The Clifford+T quantum circuit constructed by optimizing CNOT operations; The mapping relationship between the AND gate node and the Clifford+T gate cascade includes: AND gate node case I: and None of them are edge padding; they correspond to the first type of Clifford+T gate cascade for AND gate nodes, expressed as follows: ； AND gate node case II: It's for patching the edges. This is not edge patching; it corresponds to the second type of Clifford + T gate cascade for AND gate nodes, expressed as follows: ； AND gate node case III: It's not about patching the edges. This is edge padding, corresponding to the third type of Clifford+T gate cascade for AND gate nodes, expressed as follows: ； AND gate node case IV: and All are edge padding, corresponding to the fourth type of Clifford+T gate cascade for AND gate nodes, expressed as follows: ； in, and Each is a node Its 0 branch node and 1 branch child node The edge between; The newly added input state is the quantum ground state. The circuit lines; , and These are respectively acting on the circuit lines H-gate, T-gate and T-gate † Door; To act on the circuit line and The CNOT gate, in which the circuit lines and These represent the control circuit line and the target circuit line, respectively. It acts on the circuit line and The CNOT gate, in which the circuit lines and These represent the control circuit line and the target circuit line, respectively. This indicates a cascading of doors.

2. The method for synthesizing XOR AND graph quantum circuits for optimizing CNOT operations according to claim 1, characterized in that: In step S101, creating AND gate nodes or XOR gate nodes for logical AND or XOR terms with a word count of 2 specifically includes the following: S1011. If the literals in a logical AND or XOR term are variables. First, create a variable node for the variable in the XAG; if a variable node for that variable already exists in the XAG... Then the node is shared. No new node needs to be created for this variable; otherwise, a variable node should be created for this variable. ; If a literal in a logical AND or XOR term is not a variable, then a node containing that literal must exist in the XAG. Share this node No new node needs to be created for this text; Then use node functions and Replace two characters in the logical AND or logical XOR term; S1012. Create AND gate nodes or XOR gate nodes in the XAG for the logical AND or XOR terms after text replacement; if the logical AND or XOR term node already exists in the XAG. Then the node is shared. No new node needs to be created; otherwise, a node is created in the XAG for the logical AND / OR XOR term. Create nodes at the same time With nodes and nodes With nodes The edge between and When the literal terms in the logical AND or XOR term are related to node functions... or To perform the negation operation, i.e. or At that time, then the side or To fill in the gaps; Then use node functions Replace Boolean function The logical AND term or logical XOR term in the XOR expression.

3. The method for synthesizing XOR AND graph quantum circuits for optimizing CNOT operations according to any one of claims 1 to 2, characterized in that: Step S200 specifically includes the following: S201, Add to the circuit Each circuit line uses input variables. right Each circuit line is labeled, and each circuit line is used to store the state of a variable; S202. Perform a depth-first traversal of the nodes in the XAG to obtain an ordered set of nodes. , The number of nodes in the XAG; S203, Order ; S204, Based on the node The type is based on the mapping relationship between AND gate nodes and Clifford+T gate concatenations, and the mapping relationship between XOR gate nodes and Clifford+T gate concatenations, which will connect the nodes. The mapping is a cascade of Clifford+T gates obtained by optimizing the CNOT operation; S205, Order ;if If the condition is met, proceed to step S204; otherwise, proceed to step S206. S206. The circuit synthesis process is complete, resulting in a Boolean function. The Clifford+T quantum circuit was constructed by optimizing the CNOT operation.

4. The method for synthesizing XOR AND graph quantum circuits for optimizing CNOT operations according to claim 3, characterized in that: Step S204 specifically includes the following: S2041, if It represents a variable ( If the variable node is ), then The corresponding circuit is labeled as The circuit lines; S2042, if It is an AND gate node or an XOR gate node. Assuming a node in an XAG... The child nodes with 0 branches and the child nodes with 1 branches are respectively and ( , ,and The circuit is labeled as follows: and The circuit lines store node functions respectively. and The calculation results; Based on nodes Its 0-branch child node and 1 branch child node Determine whether the edges between nodes are supplementary edges and whether child nodes are shared, and construct mapping relationships between AND gate nodes and Clifford+T gate concatenations, and between XOR gate nodes and Clifford+T gate concatenations, respectively; and based on the corresponding mapping relationships, configure the AND gate nodes... or XOR gate node The mapped Clifford+T gate cascades are added to the circuit according to the circuit line labels; for storing node functions. Add circuit line labels to the circuit lines in the calculation results. .

5. The method for synthesizing XOR AND graph quantum circuits for optimizing CNOT operations according to claim 4, characterized in that: Step S2042 specifically includes the following: S20421, If ​​node To represent an AND gate, first add an input state that is the quantum ground state to the circuit. The circuit lines are used to store node functions. The calculation results are then used to map the AND gate nodes to the Clifford+T gate concatenation based on the mapping relationship between the AND gate nodes and the Clifford+T gate concatenation. This is mapped to the corresponding Clifford+T gate cascade, which means adding the Clifford+T gate cascade to the circuit according to the circuit line labels, and labeling the added circuit lines as follows: ; S20422, If node If we represent an XOR gate, then based on the mapping relationship between the XOR gate node and the cascaded Clifford+T gate, the XOR gate node... The mapping is performed as a corresponding Clifford+T gate cascade, which is then added to the circuit according to the circuit line labels; depending on the specific situation in the mapping relationship, the input state is used as the quantum ground state. The circuit lines or circuits labeled as The circuit lines or circuits labeled as Circuit storage node function The calculation results were used to label the circuit line as follows. .

6. The method for synthesizing XOR AND graph quantum circuits for optimizing CNOT operations according to claim 5, characterized in that: Step S2042 also includes, S20423, when When it is the root node of an XAG, if the node If there is one outgoing edge that serves as a supplementary edge, then it is labeled as follows in the circuit: Add a NOT gate to the circuit line and use Relabel the circuit line; otherwise, label it as... The circuit lines are re-labeled as This indicates that the circuit outputs a Boolean function. The calculation results.

7. The method for synthesizing XOR AND graph quantum circuits for optimizing CNOT operations according to claim 5, characterized in that: The mapping relationship between the XOR gate node and the Clifford+T gate cascade includes: XOR gate node case I: and None of them are edge-filling nodes, and they have 0 branch child nodes. and 1 branch child node They are all shared; XOR gate node case II: and All are edge-filling nodes, and have 0 branch child nodes. and 1 branch child node They are all shared; Both XOR gate node case I and XOR gate node case II correspond to the first type of Clifford+T gate cascade for XOR gate nodes, expressed as follows: ； XOR gate node case III: It is to patch the edge. It is not an edge patching and has 0 branch child nodes. and 1 branch child node They are all shared; XOR gate node case IV: Not patching the edge, It is an edge patching, and has 0 branch child nodes. and 1 branch child node They are all shared; Both XOR gate node cases III and IV correspond to the second type of Clifford+T gate cascade for XOR gate nodes, expressed as follows: ； XOR gate node case V: and None of them are edge-filling nodes, and they have 0 branch child nodes. Not shared; XOR gate node case VI: and All are edge-filling nodes, and have 0 branch child nodes. Not shared; Both XOR gate node cases V and VI correspond to the third type of Clifford+T gate cascade for XOR gate nodes, expressed as follows: ； XOR gate node case VII: It is to patch the edge. It is not an edge patching and has 0 branch child nodes. Not shared; XOR gate node case VIII: Not patching the edge, It is an edge patching, and has 0 branch child nodes. Not shared; Both XOR gate node cases VII and VIII correspond to the fourth type of Clifford+T gate cascade, expressed as follows: ； XOR gate node case IX: and None of them are edge-filling nodes, and they have 0 branch child nodes. Shared, 1 branch child node Not shared; XOR gate node case X: and All are edge-filling nodes, and have 0 branch child nodes. Shared, 1 branch child node Not shared; Both XOR gate node cases IX and XOR gate node cases X correspond to the fifth type of Clifford+T gate cascade, expressed as follows: ； XOR gate node case XI: It is to patch the edge. It is not an edge patching and has 0 branch child nodes. Shared, 1 branch child node Not shared; XOR gate node case XII: Not patching the edge, It is an edge patching, and has 0 branch child nodes. Shared, 1 branch child node Not shared; Both XOR gate node cases XI and XOR gate node cases XII correspond to the sixth type of Clifford+T gate cascade for XOR gate nodes, expressed as follows: ； in, and Each is a node Its 0-branch child node and 1 branch child node The edge between; The newly added input state is the quantum ground state. The circuit lines; To act on the circuit line and The CNOT gate, in which the circuit lines and These represent the control circuit line and the target circuit line, respectively. To act on the circuit line and The CNOT gate, in which, and These represent the control circuit line and the target circuit line, respectively. To act on the circuit line The NOT gate; It acts on the circuit line The NOT gate; This indicates a cascading of doors.

8. The method for synthesizing XOR AND graph quantum circuits for optimizing CNOT operations according to claim 7, characterized in that: In step S20422, the node functions are stored using the corresponding circuit lines according to the specific circumstances in the mapping relationship. The calculation results, and used The circuit line is specifically labeled as follows: For XOR gate node cases I to IV, before adding the Clifford+T gate cascade to the circuit, it is necessary to first add a line to the circuit with the input state being the quantum ground state. The circuit lines are used to store node functions. The calculation results, and used Label the circuit line; For XOR gate node cases V to VIII, use the circuit notation as shown. Circuit storage node function The calculation results were used to relabel the circuit lines as follows. ; For XOR gate node cases IX to XII, use the circuit notation as shown. Circuit storage node function The calculation results were used to relabel the circuit lines as follows. .

Images