A general neural network vector processing apparatus for embedded devices
By combining a RISC-V processor and a vector processing unit, the neural network processing capability of embedded devices has been improved, solving the problem of insufficient versatility of traditional accelerators and enabling efficient processing and flexible computation of large amounts of data.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2024-03-05
- Publication Date
- 2026-07-14
AI Technical Summary
Traditional neural network accelerators designed for embedded devices lack versatility and cannot effectively process large amounts of data. Furthermore, the vector processing unit of the ARM Cortex-M4 has a single function and a fixed vector length, which cannot meet the needs of complex calculations.
Design a general-purpose neural network vector processing device for embedded devices, combining a RISC-V processor and a vector processing unit to support the main computational needs of neural networks, including vector instruction cache and data cache, thereby improving vector processing performance and versatility.
It improves the ability of embedded devices to process large amounts of data, supports the processing of different types of data, and is configurable and efficient, solving the computational bottleneck of traditional neural network accelerators in resource-constrained scenarios.
Smart Images
Figure CN118211622B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of neural network vector processing, and particularly relates to a general neural network vector processing device for embedded devices. Background Technology
[0002] In the era of intelligent interconnection, the concept of "Internet of Everything" has brought broad possibilities for the application of embedded devices, but it has also brought new challenges to the design and development of embedded devices. Currently, embedded devices developed based on mainstream instruction sets are showing signs of inadequacy in the face of the new market environment due to their high difficulty and cost.
[0003] In contrast, RISC-V is an open-source CPU instruction set architecture, characterized by being completely free, having a simple architecture, and allowing for customizable extended instruction sets. It has been widely used in embedded SoC design. In addition to the standard integer instruction set, RISC-V also defines extended instruction sets for different application needs, such as embedded extensions, bit operation extensions, and vector extensions.
[0004] Vector extensions support data-parallel execution within the 32-bit instruction code space. This extension enhances the processor's single-instruction-multiple-data operation by introducing a set of vector registers and vector operation instructions. This allows the same operations to be applied to large batches of data elements, fundamentally changing the data processing capabilities of RISC-V systems while maintaining the conciseness of the instruction code.
[0005] With the increasing adoption of machine learning in applications such as consumer electronics, automotive electronics, and industrial control, technologies like neural networks have experienced a surge in development. The larger the neural network model, the greater the computational demands. Traditional neural network accelerators for embedded devices lack versatility and are limited in resource-constrained scenarios like edge devices. Therefore, implementing vector extensions for frequently used computational types within neural networks shows promising potential.
[0006] The ARM Cortex-M4 is a low-cost, low-power embedded processor with basic vector processing capabilities and some computational performance for neural network algorithms. It is widely used in simple embedded applications in consumer electronics, industrial control, smart homes, and automotive electronics. Its advantages of low power consumption and cost-effectiveness make it an ideal choice for many embedded system designs. It also possesses some computational performance for neural network algorithms.
[0007] The vector processing unit of the ARM Cortex-M4 is relatively simple and has poor configurability, mainly characterized by the following features:
[0008] (1) Limited vector instruction set: The vector processing unit of ARM Cortex-M4 only supports the basic vector instruction set, such as addition, subtraction and logical operations. Its functional units are few and cannot support complex vector calculation tasks.
[0009] (2) Fixed vector length: The vector length of the vector processing unit of ARM Cortex-M4 is fixed, and multiple elements cannot be added or combined with a single instruction, nor can it be configured according to application requirements. The short vector length limits the amount of data processed at one time, reduces the efficiency of parallel computing, and makes it difficult to complete instruction implementation for computationally intensive operation types in neural networks. Summary of the Invention
[0010] To address the aforementioned shortcomings in the existing technology, this invention provides a general neural network vector processing device for embedded devices, which solves the problem that current neural network models are very large, but traditional neural network accelerators for embedded devices lack versatility.
[0011] To achieve the above-mentioned objectives, the technical solution adopted by the present invention is as follows: a general neural network vector processing device for embedded devices, comprising a RISC-V processor, an intermediate cache, and a vector processing unit;
[0012] The RISC-V processor is used to store vector instructions, and based on the original data and RISC-V extended instructions, to generate neural network weights and extract neural network data using a set neural network algorithm, and to complete the set neural network algorithm based on the neural network weights, dot product operation results, integer processing data and floating-point processing data.
[0013] The vector instruction cache is used to cache vector instructions;
[0014] The data cache is used to cache neural network data, dot product operation results, integer processing data, and floating-point processing data.
[0015] The vector processing unit is used to process neural network data according to vector instructions to obtain dot product operation results, integer processing data, and floating-point processing data.
[0016] The beneficial effects of this invention are as follows: This invention solves the problem that traditional scalar processors are insufficient for processing large amounts of data, supports the vector instructions required for the main calculations of neural networks, has more powerful vector processing performance and versatility, and solves the problem that current neural network models are very large, but traditional neural network accelerators for embedded devices are not very versatile.
[0017] Furthermore, the RISC-V processor includes a RISC-V scalar processor core, an instruction memory, and a data memory;
[0018] The RISC-V scalar processor core is used to generate neural network weights and extract neural network data using a set neural network algorithm based on the original data and RISC-V extended instructions, and to complete the set neural network algorithm based on the neural network weights, dot product operation results, integer processing data and floating-point processing data.
[0019] The instruction memory is used to store vector instructions;
[0020] The data storage device is used to store neural network data and dot product operation results.
[0021] The beneficial effect of the above-mentioned further solution is that, while ensuring the normal execution of ordinary scalar instructions, neural network accelerated vector instructions are sent to the vector processing unit for execution, thereby improving processing efficiency.
[0022] Furthermore, the vector processing unit includes a controller, a dual-channel vector processing unit, a dot product unit, and a memory access unit;
[0023] The controller is used to decode vector instructions to obtain dot product control information, operation type, scalar operands, vector configuration information, and memory access operation information.
[0024] The vector dual channel is used to obtain register group occupancy information and, based on the operation type, scalar operands, vector configuration information, memory access operation information, and neural network data, obtain integer processing data and floating-point processing data.
[0025] The dot product unit is used to obtain neural network data from the memory access unit according to the dot product control information, and to perform calculations based on the neural network data and the dot product control information to obtain the dot product operation result.
[0026] The memory access unit is used to transmit the dot product operation result to the data cache, and to read neural network data and store integer processing data and floating-point processing data according to the memory access operation information.
[0027] The beneficial effects of the above-mentioned further solutions are: improving the scalar processor's ability to process large amounts of data, supporting the processing of different types of data, and having configurability and versatility.
[0028] Furthermore, the controller includes a decoding module and an instruction hazard detection module;
[0029] The decoding module is used to decode vector instructions to obtain control signals;
[0030] The instruction hazard detection module is used to obtain instruction execution occupancy information and memory access occupancy information, and to detect the existence and type of hazards by updating the read-write lookup table based on the control signal, instruction execution occupancy information and memory access occupancy information, thereby obtaining dot product control information, operation type, scalar operands, vector configuration information and memory access operation information.
[0031] The beneficial effects of the above-mentioned further solutions are: to realize the control and scheduling of vector acceleration units, and to ensure the correctness and efficiency of data processing.
[0032] Furthermore, the vector dual-channel includes a first channel, a second channel, and a register group;
[0033] The first channel is used to store neural network data into a register group according to the memory access operation information, and to obtain integer processing data and floating-point processing data from the register group and transmit them to the memory access unit through the memory access data queue.
[0034] The register group is used to obtain register group occupancy information, obtain integer data and floating-point data based on neural network data, and obtain the input data queue of the integer arithmetic module and the input data queue of the floating-point arithmetic module based on the priority of read and write requests, integer read and write requests, floating-point read and write requests, integer data and floating-point data, as well as to store integer processing data and floating-point processing data.
[0035] The second channel is used to obtain integer processing data and floating-point processing data based on register group occupancy information, operation type, scalar operands, vector configuration information, the input data queue of the integer operation module, and the input data queue of the floating-point operation module.
[0036] The beneficial effects of the above-mentioned further solutions are: distributing vector acceleration instructions issued by the scalar processor to different instruction pipelines, supporting the processing of different data types, improving the parallelism of instruction execution and hardware utilization; and enabling the processing of operations with different priorities, thereby improving the efficiency of data processing.
[0037] Furthermore, the second channel includes an instruction dispatch module, an arbitration module, an integer arithmetic module, and a floating-point arithmetic module;
[0038] The instruction dispatch module is used to decode the operation type, scalar operands and quantity configuration information to obtain short data fetch instructions, and to parse the execution unit of the short data fetch instructions to obtain short integer operation instructions, short floating-point operation instructions and arbitration instructions.
[0039] The arbitration module is used to detect the existence and type of hazards based on the short arbitration instruction and the register group occupancy information, obtain the priority of the read / write request, and transfer the integer processing data and the floating-point processing data to the register group based on the integer operation module's operation result queue and the floating-point operation module's operation result queue, respectively.
[0040] The integer arithmetic module is used to obtain integer read / write requests according to short integer arithmetic instructions, and to perform addition, subtraction and bit operations on integer data in a pipelined manner according to the input data queue of the integer arithmetic module to obtain integer processing data, and to write the integer processing data into the operation result queue of the integer arithmetic module.
[0041] The floating-point arithmetic module is used to obtain floating-point number read / write requests according to the floating-point arithmetic short instructions, and to perform addition, subtraction and bit operations on floating-point number data in a pipelined manner according to the input data queue of the floating-point arithmetic module to obtain floating-point number processing data, and to write the floating-point number processing data into the operation result queue of the floating-point arithmetic module.
[0042] The beneficial effects of the above-mentioned further solutions are: distributing vector acceleration instructions issued by the scalar processor to different instruction pipelines, supporting the processing of different data types, improving the parallelism of instruction execution and hardware utilization; and enabling the processing of operations with different priorities, thereby improving the efficiency of data processing.
[0043] Furthermore, the memory access unit includes a memory access instruction dispatch module, a control signal buffer queue, a load module, and a store module;
[0044] The control signal cache queue is used to cache memory access operation information;
[0045] The memory access instruction dispatch module is used to decode the memory access operation information to obtain load control instructions and storage control instructions.
[0046] The Load module is used to transmit the dot product operation result to the data cache and obtain the neural network data of the RISC-V processor according to the load control instructions.
[0047] The Store module is used to obtain integer processing data and floating-point processing data according to storage control instructions.
[0048] The beneficial effects of the above-mentioned further solutions are: to achieve efficient storage and retrieval of large amounts of data and to improve the operating efficiency of the vector processing unit. Attached Figure Description
[0049] Figure 1 This is a structural diagram of the present invention.
[0050] Figure 2This is a schematic diagram of the execution flow of the present invention. Detailed Implementation
[0051] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.
[0052] like Figure 1 As shown, in one embodiment of the present invention, a general neural network vector processing device for embedded devices includes a RISC-V processor, an intermediate cache, and a vector processing unit.
[0053] The RISC-V processor is used to store vector instructions, and based on the original data and RISC-V extended instructions, to generate neural network weights and extract neural network data using a set neural network algorithm, and to complete the set neural network algorithm based on the neural network weights, dot product operation results, integer processing data and floating-point processing data.
[0054] The vector instruction cache is used to cache vector instructions;
[0055] The data cache is used to cache neural network data, dot product operation results, integer processing data, and floating-point processing data.
[0056] The vector processing unit is used to process neural network data according to vector instructions to obtain dot product operation results, integer processing data, and floating-point processing data.
[0057] In this embodiment, addressing the shortcomings of traditional scalar processors in handling large volumes of data, this invention proposes a general-purpose neural network vector processing device for embedded devices. This device supports the vector instructions required for the main computations of neural networks, offering superior vector processing performance and versatility. It solves the problem that current neural network models are very large, yet traditional neural network accelerators for embedded devices lack versatility. This invention adds a vector processing unit to a RISC-V processor, improving the parallel data processing capability of neural networks and reducing the computational burden. This invention prunes the entire vector instruction manual, selectively implementing only the computationally intensive operation types required by the neural network.
[0058] In this embodiment, the vector instruction cache is used to cache vector instructions transmitted from the instruction memory in the RISC-V processor and connect to the controller of the vector processing unit to generate control instructions.
[0059] The data cache is used to cache data transmitted from the data memory in the RISC-V processor and is connected to the memory access unit of the vector processing unit for related data caching.
[0060] The RISC-V processor includes a RISC-V scalar processor core, an instruction memory, and a data memory;
[0061] The RISC-V scalar processor core is used to generate neural network weights and extract neural network data using a set neural network algorithm based on the original data and RISC-V extended instructions, and to complete the set neural network algorithm based on the neural network weights, dot product operation results, integer processing data and floating-point processing data.
[0062] The instruction memory is used to store vector instructions;
[0063] The data storage device is used to store neural network data and dot product operation results.
[0064] In this embodiment, the RISC-V scalar processor core processes a single instruction or data within a single time period; the RISC-V processor is used to generate neural network weights and extract neural network data using corresponding algorithms based on the original data and RISC-V extended instructions, and to complete further calculations based on integer processing data and floating-point processing data.
[0065] The vector processing unit includes a controller, a dual-channel vector processing unit, a dot product unit, and a memory access unit;
[0066] The controller is used to decode vector instructions to obtain dot product control information, operation type, scalar operands, vector configuration information, and memory access operation information.
[0067] The vector dual channel is used to obtain register group occupancy information and, based on the operation type, scalar operands, vector configuration information, memory access operation information, and neural network data, obtain integer processing data and floating-point processing data.
[0068] The dot product unit is used to obtain neural network data from the memory access unit according to the dot product control information, and to perform calculations based on the neural network data and the dot product control information to obtain the dot product operation result.
[0069] The memory access unit is used to transmit the dot product operation result to the data cache, and to read neural network data and store integer processing data and floating-point processing data according to the memory access operation information.
[0070] In this embodiment, the dot product unit is used to accelerate the dot product operation of the convolutional layer and fully connected layer of the neural network. The dot product control information for each calculation is obtained from the controller, including working enable, data volume, data address, etc. Then, the source data is read through the memory access unit, and the dot product operation result is obtained through multiplication and addition operations. Finally, the result is transmitted to the data memory for storage through the memory access unit.
[0071] In this embodiment, the controller is used to decode vector instructions to obtain some control signals, such as operation type, scalar operands, vector configuration information, memory access operation information, etc., and to perform related operations according to the instruction type; before receiving the next instruction, it can also be used to check whether there is a risk conflict between the currently executed instruction and the next instruction.
[0072] The controller includes a decoding module and an instruction hazard detection module;
[0073] The decoding module is used to decode vector instructions to obtain control signals;
[0074] The instruction hazard detection module is used to obtain instruction execution occupancy information and memory access occupancy information, and to detect the existence and type of hazards by updating the read-write lookup table based on the control signal, instruction execution occupancy information and memory access occupancy information, thereby obtaining dot product control information, operation type, scalar operands, vector configuration information and memory access operation information.
[0075] The vector dual-channel includes a first channel, a second channel, and a register group;
[0076] The first channel is used to store neural network data into a register group according to the memory access operation information, and to obtain integer processing data and floating-point processing data from the register group and transmit them to the memory access unit through the memory access data queue.
[0077] The register group is used to obtain register group occupancy information, obtain integer data and floating-point data based on neural network data, and obtain the input data queue of the integer arithmetic module and the input data queue of the floating-point arithmetic module based on the priority of read and write requests, integer read and write requests, floating-point read and write requests, integer data and floating-point data, as well as to store integer processing data and floating-point processing data.
[0078] The second channel is used to obtain integer processing data and floating-point processing data based on register group occupancy information, operation type, scalar operands, vector configuration information, the input data queue of the integer operation module, and the input data queue of the floating-point operation module.
[0079] The second channel includes an instruction dispatch module, an arbitration module, an integer arithmetic module, and a floating-point arithmetic module;
[0080] The instruction dispatch module is used to decode the operation type, scalar operands and quantity configuration information to obtain short data fetch instructions, and to parse the execution unit of the short data fetch instructions to obtain short integer operation instructions, short floating-point operation instructions and arbitration instructions.
[0081] The arbitration module is used to detect the existence and type of hazards based on the short arbitration instruction and the register group occupancy information, obtain the priority of the read / write request, and transfer the integer processing data and the floating-point processing data to the register group based on the integer operation module's operation result queue and the floating-point operation module's operation result queue, respectively.
[0082] The integer arithmetic module is used to obtain integer read / write requests according to short integer arithmetic instructions, and to perform addition, subtraction and bit operations on integer data in a pipelined manner according to the input data queue of the integer arithmetic module to obtain integer processing data, and to write the integer processing data into the operation result queue of the integer arithmetic module.
[0083] The floating-point arithmetic module is used to obtain floating-point number read / write requests according to the floating-point arithmetic short instructions, and to perform addition, subtraction and bit operations on floating-point number data in a pipelined manner according to the input data queue of the floating-point arithmetic module to obtain floating-point number processing data, and to write the floating-point number processing data into the operation result queue of the floating-point arithmetic module.
[0084] In this embodiment, Figure 1 The register BANK in the context refers to the register group; the arithmetic instruction dispatch module is used to further decode the long instructions decoded by the controller into short data fetch instructions, parse which of the three execution pipelines the execution unit in the control instruction package belongs to (there are three execution pipelines in total: integer arithmetic module, floating-point arithmetic module, and memory access unit), and dispatch control instructions to the subsequent integer arithmetic module, floating-point arithmetic module, and arbitration module.
[0085] The memory access unit includes a memory access instruction dispatch module, a control signal buffer queue, a load module, and a store module;
[0086] The control signal cache queue is used to cache memory access operation information;
[0087] The memory access instruction dispatch module is used to decode the memory access operation information to obtain load control instructions and storage control instructions.
[0088] The Load module is used to transmit the dot product operation result to the data cache and obtain the neural network data of the RISC-V processor according to the load control instructions.
[0089] The Store module is used to obtain integer processing data and floating-point processing data according to storage control instructions.
[0090] like Figure 2 As shown, the execution flow of a general neural network vector processing device for embedded devices provided by the present invention includes the following steps:
[0091] S1, Command Acquisition
[0092] Vector instructions issued from the RISC-V processor's instruction memory are cached in an instruction FIFO. These instructions are then fed into the controller's decoding module for decoding. If there are no instruction dependencies, the decoded instructions are issued to subsequent modules; if there are instruction dependencies, the decoded instructions are temporarily stored.
[0093] S2, Decoding
[0094] The decoding module obtains control signals based on the decoded instruction type, such as the operation type and scalar operands. If a memory access instruction is decoded, the bit width of the vector element to be accessed needs to be determined based on the current vector type register value and the encoding information of the memory access instruction. If a configuration instruction is decoded, the value of the control status register needs to be updated. After decoding, before receiving the next instruction, it should check whether there is a hazard conflict between the currently executing instruction and the next instruction. If no instruction hazard is detected in the instruction hazard detection module, or the number of instructions that can be executed simultaneously has not reached the upper limit, the following judgment will be made: if the floating-point unit is not the control status register and the instruction is valid, the controller's control instruction output is valid; if a ready signal is sent from the next-level memory access unit or vector channel, it indicates that the memory access unit or vector channel can receive the next instruction.
[0095] S3. Decomposition
[0096] After the control commands issued by the controller enter the vector dual-channel system, they are first analyzed by the instruction dispatch module to determine the type of execution unit within the control command packet (there are three execution pipelines: integer arithmetic module, floating-point arithmetic module, and Store unit). The control command packet is then cached in its corresponding FIFO (there are three FIFOs). Next, it is further decoded into control instructions (specific arithmetic operations + register read requests) for the subsequent integer arithmetic module, floating-point arithmetic module, and arbitration module, and then distributed to the subsequent execution units. The specific operations and memory access operations of the instructions are executed separately; the computation unit is only responsible for computation, while the memory access unit handles the interaction with the registers.
[0097] S4, Access Register
[0098] When accessing a register, the control instructions sent by the instruction dispatch module are directly sent to the arbitration module for processing, and then the neural network data is read from the register BANK.
[0099] The arbitration module is specifically responsible for handling register read and write requests. It receives source register read requests from the instruction dispatch module and destination register write requests from the arithmetic unit or load unit, resolves conflicts between these requests, and transfers data to the appropriate unit. The nine input channels consist of six read operation channels from the instruction dispatch module and write operation channels from the integer arithmetic module, floating-point arithmetic module, and storage unit module. The six read operation channels correspond to two source registers from the integer arithmetic module, three source registers from the floating-point arithmetic module, and one source register from the storage unit; the three write operation channels correspond to the destination registers from the integer arithmetic module, floating-point arithmetic module, and storage unit module, respectively. The eight output channels correspond to the eight banks of the register BANK, and each bank can only be accessed by one of the nine read / write request ports at a time.
[0100] The read / write control signals and data of the arbitration module are received by the register BANK. The register module consists of eight independent single-port synchronous SRAMs (Banks), meaning each SRAM can only be read, XORed, and written, with both reads and writes occurring at the sampling time. There are 8 input channels and 6 output channels, with each input channel corresponding to one SRAM. For read requests, the data needs to be assigned a number to indicate which of the six operand queues the data is destined for, ensuring it is placed in the correct location after retrieval. Finally, the data and the assigned number are sent to the operand queues together.
[0101] S5, Execution
[0102] There are three pipelines in total, meaning it can support the parallel execution of three types of instructions (more than three instructions in parallel). One pipeline executes in the integer arithmetic module, one pipeline executes in the floating-point arithmetic module, and one pipeline executes in the memory access unit.
[0103] The neural network data read from the BANK register first passes through the input data queue, and then proceeds to the integer arithmetic module and floating-point arithmetic module to perform the corresponding calculations. The integer arithmetic module performs integer addition, subtraction, and bitwise operations; the floating-point arithmetic module performs floating-point addition, subtraction, multiplication, division, square root, multiplication-addition, and multiplication-subtraction. Both modules use a pipelined approach to compute the neural network data. The calculation results are first written to the result queue and then returned to the arbitration module.
[0104] S6, Write Back
[0105] The neural network operation results are processed by the arbitration module and written back to the register BANK. Then, they are written back to the RISC-V processor's data memory through the Store module of the memory access unit.
[0106] The memory access unit is responsible for moving neural network data from the register bank to memory, or vice versa. First, the memory access control signal from the controller is stored in a control signal buffer queue, which is then in an idle state. When the control signal buffer queue is not empty, it transitions from the idle state to the request state; otherwise, it remains in the idle state. In the request state, it first determines whether it is a Load or Store instruction. If it is a Load instruction, a memory access request can be issued. Three counters are used here: one to record the number of valid memory access request signals sent to memory, one to record the number of valid memory access request signals that memory has responded to, and one to record the number of vector registers whose write operations have been completed by the Load instruction. If it is a Store instruction, it simply places the data into the corresponding memory address in order, provided that the data is in the data result queue and valid, eliminating the step of calculating the destination register address found in the Load operation.
Claims
1. A general-purpose neural network vector processing device for embedded devices, characterized in that, Includes a RISC-V processor, intermediate cache, and vector processing unit; The RISC-V processor is used to store vector instructions, and based on the original data and RISC-V extended instructions, to generate neural network weights and extract neural network data using a set neural network algorithm, and to complete the set neural network algorithm based on the neural network weights, dot product operation results, integer processing data and floating-point processing data. The vector instruction cache is used to cache vector instructions; The data cache is used to cache neural network data, dot product operation results, integer processing data, and floating-point processing data. The vector processing unit is used to process neural network data according to vector instructions to obtain dot product operation results, integer processing data, and floating-point processing data; the vector processing unit includes a controller, a vector dual channel, a dot product unit, and a memory access unit; The controller is used to decode vector instructions to obtain dot product control information, operation type, scalar operands, vector configuration information, and memory access operation information. The vector dual channel is used to obtain register group occupancy information and, based on the operation type, scalar operands, vector configuration information, memory access operation information, and neural network data, obtain integer processing data and floating-point processing data. The dot product unit is used to obtain neural network data from the memory access unit according to the dot product control information, and to perform calculations based on the neural network data and the dot product control information to obtain the dot product operation result. The memory access unit is used to transmit the dot product operation result to the data cache, and to read neural network data and store integer processing data and floating-point processing data according to the memory access operation information.
2. The general neural network vector processing device for embedded devices according to claim 1, characterized in that, The RISC-V processor includes a RISC-V scalar processor core, an instruction memory, and a data memory; The RISC-V scalar processor core is used to generate neural network weights and extract neural network data using a set neural network algorithm based on the original data and RISC-V extended instructions, and to complete the set neural network algorithm based on the neural network weights, dot product operation results, integer processing data and floating-point processing data. The instruction memory is used to store vector instructions; The data storage device is used to store neural network data and dot product operation results.
3. The general neural network vector processing device for embedded devices according to claim 1, characterized in that, The controller includes a decoding module and an instruction hazard detection module; The decoding module is used to decode vector instructions to obtain control signals; The instruction hazard detection module is used to obtain instruction execution occupancy information and memory access occupancy information, and to detect the existence and type of hazards by updating the read-write lookup table based on the control signal, instruction execution occupancy information and memory access occupancy information, thereby obtaining dot product control information, operation type, scalar operands, vector configuration information and memory access operation information.
4. The general neural network vector processing device for embedded devices according to claim 1, characterized in that, The vector dual-channel includes a first channel, a second channel, and a register group; The first channel is used to store neural network data into a register group according to the memory access operation information, and to obtain integer processing data and floating-point processing data from the register group and transmit them to the memory access unit through the memory access data queue. The register group is used to obtain register group occupancy information, obtain integer data and floating-point data based on neural network data, and obtain the input data queue of the integer arithmetic module and the input data queue of the floating-point arithmetic module based on the priority of read and write requests, integer read and write requests, floating-point read and write requests, integer data and floating-point data, as well as to store integer processing data and floating-point processing data. The second channel is used to obtain integer processing data and floating-point processing data based on register group occupancy information, operation type, scalar operands, vector configuration information, the input data queue of the integer operation module, and the input data queue of the floating-point operation module.
5. The general neural network vector processing device for embedded devices according to claim 4, characterized in that, The second channel includes an instruction dispatch module, an arbitration module, an integer arithmetic module, and a floating-point arithmetic module; The instruction dispatch module is used to decode the operation type, scalar operands and quantity configuration information to obtain short data fetch instructions, and to parse the execution unit of the short data fetch instructions to obtain short integer operation instructions, short floating-point operation instructions and arbitration instructions. The arbitration module is used to detect the existence and type of hazards based on the short arbitration instruction and the register group occupancy information, obtain the priority of the read / write request, and transfer the integer processing data and the floating-point processing data to the register group based on the integer operation module's operation result queue and the floating-point operation module's operation result queue, respectively. The integer arithmetic module is used to obtain integer read / write requests according to short integer arithmetic instructions, and to perform addition, subtraction and bit operations on integer data in a pipelined manner according to the input data queue of the integer arithmetic module to obtain integer processing data, and to write the integer processing data into the operation result queue of the integer arithmetic module. The floating-point arithmetic module is used to obtain floating-point number read / write requests according to the floating-point arithmetic short instructions, and to perform addition, subtraction and bit operations on floating-point number data in a pipelined manner according to the input data queue of the floating-point arithmetic module to obtain floating-point number processing data, and to write the floating-point number processing data into the operation result queue of the floating-point arithmetic module.
6. The general neural network vector processing device for embedded devices according to claim 4, characterized in that, The memory access unit includes a memory access instruction dispatch module, a control signal buffer queue, a load module, and a store module; The control signal cache queue is used to cache memory access operation information; The memory access instruction dispatch module is used to decode the memory access operation information to obtain load control instructions and storage control instructions. The Load module is used to transmit the dot product operation result to the data cache and obtain the neural network data of the RISC-V processor according to the load control instructions. The Store module is used to obtain integer processing data and floating-point processing data according to storage control instructions.