A multi-trench 4H-SiC MOSFET device

Abstract

The present invention discloses a multi-groove 4H‑SiC MOSFET device, belonging to the technical field of semiconductor devices. The present invention adopts multi-groove 4H‑SiC to replace part of the buried oxide to reduce the temperature effect, and reasonably designs the number and size of the top grooves of the 4H‑SiC to increase the breakdown voltage of the device. In addition, the present invention reduces the on-resistance by filling multiple grooves with a silicon material whose concentration is greater than that of the drift region. Through the analysis of the temperature effect and breakdown characteristics of the new multi-groove 4H‑SiC MOSFET device, compared with conventional devices, the MOSFET structure provided by the present invention is more suitable for applications under high temperature and high pressure conditions. The present invention provides a new idea for designing high-performance and economical SiC power MOSFETs, injecting new vitality into the development of new power systems.

Description

Technical Field

[0001] The invention relates to a multi-groove 4H-SiC MOSFET device, belonging to the technical field of semiconductor devices. Background Art

[0002] The performance of traditional silicon materials limits the application of silicon devices in high temperature and high pressure environments. Silicon carbide (SiC) semiconductor materials, with their advantages such as high thermal conductivity, high breakdown electric field and high saturated electron drift rate, have shown great potential in high-voltage and high-power power electronics applications.

[0003] As the core of power electronics technology, semiconductor power devices play a vital role in the development of power electronics technology. Among them, lateral double diffused metal-oxide-semiconductor field effect transistors (MOSFETs) have been widely used in radio frequency devices, monolithic integrated electronic power systems, and intelligent power integrated circuits. Compared with other power devices, MOSFETs are compatible with ultra-large-scale integrated circuits and have a relatively simple manufacturing process. However, the main problem of this transistor is its low breakdown voltage and high on-resistance.

[0004] At present, in conventional MOSFET device structures, parasitic capacitance and leakage current are reduced by growing silicon materials on the insulating layer. However, due to the poor thermal conductivity of the buried oxide layer, its maximum lattice temperature increases, so this structure also has the problem of self-heating effect and is not suitable for working under high temperature and high pressure conditions. In order to solve the problem of self-heating effect, insulators with high thermal conductivity are used in the prior art to replace the buried oxide, but this method will cause the device to have a short channel effect, thereby affecting its electrical performance; there is also a method of embedding T-type SiC in the oxide layer to reduce the self-heating effect, but it does not reduce its on-resistance, and the breakdown voltage is not improved. Summary of the invention

[0005] In order to solve the problem that the existing MOSFET device is not suitable for working under high temperature and high voltage conditions, the present invention provides a multi-groove 4H-SiC MOSFET device, comprising a P-type substrate 01, on which a first buried oxide layer 02 and a second buried oxide layer 04, a P-type 4H-SiC layer 03, an N-type Si layer 05, a P-type channel layer 07, an N-type drift layer 08, a high-doping concentration N-type source layer 06 and a source metal layer 10, a high-doping concentration N-type drain layer 09 and a drain metal layer 13, a gate oxide layer 11 and a gate metal layer 12 are sequentially arranged;

[0006] Among them, the first buried oxide layer 02, the P-type 4H-SiC layer 03 and the second buried oxide layer 04 are arranged in sequence above the P-type substrate 01; the high-doping concentration N-type source layer 06 and the P-type channel layer 07 are located above the first buried oxide layer 02, and the high-doping concentration N-type drain layer 09 is located above the second buried oxide layer 04; the N-type drift layer 08 is located between the P-type channel layer 07 and the high-doping concentration N-type drain layer 09; the top of the P-type 4H-SiC layer 03 is multi-grooved, and the N-type drift layer The bottom of 08 is groove-shaped, and the N-type Si layer 05 is embedded between the P-type 4H-SiC layer 03 and the N-type drift layer 08, and is comb-shaped to be used for filling the bottom groove of the N-type drift layer 08 and filling the multiple grooves on the top of the P-type 4H-SiC layer 03; the source metal layer 10 is located above the high-doping concentration N-type source layer 06, and the drain metal layer 13 is located above the high-doping concentration N-type drain layer 09; the gate oxide layer 11 is located above the P-type channel layer 07, and the gate metal layer 12 is located above the gate oxide layer 11.

[0007] Optionally, the material of the N-type drift layer 08 is silicon, the depth and length of the bottom groove thereof are 0.1 μm and 6.5 μm respectively, and the doping concentration thereof is 2×10 16 cm -3 ; The doping concentration of the N-type Si layer 05 is greater than the doping concentration of the N-type drift layer 08.

[0008] Optionally, the doping concentration of the N-type Si layer 05 is 1×10 17 cm -3 .

[0009] Optionally, 7-9 grooves are set on the top of the P-type 4H-SiC layer 03.

[0010] Optionally, the depth of the top trench of the P-type 4H-SiC layer 03 is in the range of 0.10-0.15 μm.

[0011] Optionally, the length of the top trench of the P-type 4H-SiC layer 03 is 0.5 μm, 0.7 μm or 0.8 μm.

[0012] Optionally, the material of the P-type substrate 01 is silicon carbide, and its doping concentration is 1×10 14 cm -3 ; The material of the P-type channel layer 07 is silicon, and its doping concentration is 5×10 17 cm -3 , whose length and thickness are 1μm and 0.5μm respectively.

[0013] Optionally, the doping concentration of the P-type 4H-SiC layer 03 is 1×10 15 cm -3 , its length is 8.5μm, and its thickness is consistent with the buried oxide layers 02 and 04;

[0014] Optionally, the material of the P-type channel layer 07 is silicon, and the doping concentrations thereof are 5×10 17 cm -3 , whose length and thickness are 1μm and 0.5μm respectively.

[0015] Optionally, the materials of the high-doping concentration N-type source layer 06 and the high-doping concentration N-type drain layer 09 are both silicon, and the doping concentrations thereof are both 1×10 19 cm -3 , its length and thickness are consistent with those of the P-type channel layer 07;

[0016] Optionally, the contact property between the source metal layer 10 and the high-doped N-type source layer 06 is ohmic contact; the contact property between the drain metal layer 13 and the high-doped N-type drain layer 09 is ohmic contact; the material of the gate oxide layer 11 is silicon dioxide, and is located between the P-type channel layer 07 and the gate metal layer 12, with a thickness of 50nm, and the contact property between it and the gate metal layer 12 is Schottky contact.

[0017] The present application also provides a semiconductor power device, which includes the above-mentioned multi-trench 4H-SiCMOSFET device.

[0018] The beneficial effects of the present invention are:

[0019] The present invention adopts a P-type 4H-SiC layer with better thermal conductivity to replace part of the buried oxide to reduce the maximum lattice temperature of the device, thereby reducing the impact of the device's self-heating effect, and is more suitable for applications under high temperature conditions; further, the top of the P-type 4H-SiC layer is set to a multi-groove structure, and the number and size of the top grooves are adjusted to generate an additional peak electric field in the N-type drift layer to modulate the surface electric field to make its distribution uniform, thereby increasing the breakdown voltage, and is more suitable for applications under high voltage conditions. Furthermore, the present application uses an N-type Si layer with a doping concentration greater than that of the N-type drift layer to fill the top groove structure of the P-type 4H-SiC layer, thereby reducing the on-resistance and thus reducing the power loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 Schematic diagram of the cross-sectional structure of the multi-trench 4H-SiC MOSFET device in Example 1.

[0022] Figure 2 It is a schematic diagram of the cross-sectional structure of a conventional 4H-SiC MOSFET device in comparative example 1.

[0023] Figure 3 It is a self-heating effect curve diagram of the multi-trench 4H-SiC MOSFET device provided in Example 1 and the conventional device structure.

[0024] Figure 4 It is a breakdown characteristic curve diagram of the multi-trench 4H-SiC MOSFET device provided in Example 1 and a conventional device structure.

[0025] Figure 5 1 is a graph showing output characteristic curves of the multi-trench 4H-SiC MOSFET device provided in Example 1 and a conventional device structure.

[0026] Explanation of the accompanying drawings: 01—P-type substrate; 02—first buried oxide layer; 03—P-type 4H-SiC layer; 04—second buried oxide layer; 05—N-type Si layer; 06—high-doping concentration N-type source layer; 07—P-type channel layer; 08—N-type drift layer; 09—high-doping concentration N-type drain layer; 10—source metal layer; 11—gate oxide layer; 12—gate metal layer; 13—drain metal layer.

[0027] Fig. 6A is a graph showing the relationship between the number of grooves on the top of the P-type 4H-SiC layer and the maximum lattice temperature in Comparative Example 2;

[0028] Figure 6B is a graph showing the relationship between the top trench depth and the maximum lattice temperature of the P-type 4H-SiC layer in comparative example 2;

[0029] Figure 6C This is a graph showing the relationship between the top trench length and the maximum lattice temperature of the P-type 4H-SiC layer in Example 2. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0031] Embodiment 1:

[0032] This embodiment provides a multi-trench 4H-SiC MOSFET device, see Figure 1, comprising: a P-type substrate 01, on which a first buried oxide layer 02 and a second buried oxide layer 04, a P-type 4H-SiC layer 03, an N-type Si layer 05, a P-type channel layer 07, an N-type drift layer 08, a high-doping concentration N-type source layer 06 and a source metal layer 10, a high-doping concentration N-type drain layer 09 and a drain metal layer 13, a gate oxide layer 11 and a gate metal layer 12 are sequentially arranged; wherein the first buried oxide layer 02, the P-type 4H-SiC layer 03 and the second buried oxide layer 04 are sequentially arranged above the P-type substrate 01; the high-doping concentration N-type source layer 06 and the P-type channel layer 07 are located above the first buried oxide layer 02, and the high-doping concentration N-type drain layer 09 is located above the first buried oxide layer 02. The N-type drift layer 08 is located between the P-type channel layer 07 and the high-doping concentration N-type drain layer 09; the top of the P-type 4H-SiC layer 03 is multi-grooved, and the bottom of the N-type drift layer 08 is grooved. The N-type Si layer 05 is embedded between the P-type 4H-SiC layer 03 and the N-type drift layer 08, and is in a comb-tooth shape to be used for filling the bottom grooves of the N-type drift layer 08 and filling the multiple grooves on the top of the P-type 4H-SiC layer 03; the source metal layer 10 is located above the high-doping concentration N-type source layer 06, and the drain metal layer 13 is located above the high-doping concentration N-type drain layer 09; the gate oxide layer 11 is located above the P-type channel layer 07, and the gate metal layer 12 is located above the gate oxide layer 11.

[0033] The material of the N-type drift layer 08 is silicon, and the depth and length of the bottom groove are 0.1 μm and 6.5 μm respectively. The doping concentration is 2×10 16 cm -3 ; The doping concentration of the N-type Si layer 05 is greater than the doping concentration of the N-type drift layer 08. Specifically, the doping concentration of the N-type Si layer 05 is 1×10 17 cm -3 .

[0034] Seven grooves are arranged on the top of the P-type 4H-SiC 03 layer. The depth and length of each groove are 0.1 μm and 0.5 μm respectively, and the interval between adjacent grooves is 0.5 μm.

[0035] In the above structure, since the top of the P-type 4H-SiC layer 03 is a multi-groove structure, that is, a part of the oxide layer is replaced by a P-type 4H-SiC layer 03 with a multi-groove structure, and an N-type Si layer 05 with a higher doping concentration is used to fill the grooves of the 4H-SiC layer, not only the maximum lattice temperature is reduced, but also the electric field distribution of the drift layer is made more uniform, thereby improving the breakdown voltage of the device.

[0036] In addition, the filling of the N-type Si layer 05 reduces the on-resistance of the device, thereby reducing its power loss and improving the overall performance of the device. In the above structure, the material of the P-type substrate 01 is silicon carbide, and its doping concentration is 1×1014 cm -3 ;

[0037] The buried oxide layers 02 and 04 are made of silicon dioxide and are located at the left and right ends above the P-type substrate 01, respectively. The lengths thereof are 3 μm and 1.5 μm, respectively, and the thicknesses thereof are both 0.3 μm.

[0038] The P-type 4H-SiC layer 03 is located between the buried oxide layers 02 and 04, and its doping concentration is 1×10 15 cm -3 , its length is 8.5μm, and its thickness is consistent with the buried oxide layers 02 and 04;

[0039] The material of the P-type channel layer 07 is silicon, and its doping concentration is 5×10 17 cm -3 , whose length and thickness are 1 μm and 0.5 μm respectively;

[0040] The materials of the high-doping concentration N-type source layer 06 and the high-doping concentration N-type drain layer 09 are both silicon, and the doping concentration is 1×10 19 cm -3 , its length and thickness are consistent with those of the P-type channel layer 07;

[0041] The contact property between the source metal layer 10 and the high-doping concentration N-type source layer 06 is an ohmic contact;

[0042] The contact property between the drain metal layer 13 and the high-doping concentration N-type drain layer 09 is an ohmic contact;

[0043] The gate oxide layer 11 is made of silicon dioxide and is located between the P-type channel layer 07 and the gate metal layer 12 . The thickness of the gate oxide layer 11 is 50 nm, and the contact property between the gate oxide layer 11 and the gate metal layer 12 is a Schottky contact.

[0044] Comparative Example 1:

[0045] The cross-section diagram of a conventional 4H-SiC MOSFET device is shown below: Figure 2 As shown, it includes a P-type substrate 01, a buried oxide layer 02 is provided on the P-type substrate 01, a high-doping concentration N-type source layer 06, a P-type channel layer 07, an N-type drift layer 08, and a high-doping concentration N-type drain layer 09 are provided above the buried oxide layer 02 in a horizontal direction, a source metal layer 10 is provided above the high-doping concentration N-type source layer 06, a drain metal layer 13 is provided above the high-doping concentration N-type drain layer 09, and a gate oxide layer 11 is provided between the P-type channel layer 07 and the gate metal layer 12.

[0046] like Figure 2As shown in FIG. 1 , in conventional 4H-SiC MOSFET devices, silicon dioxide with poor thermal conductivity is used as the buried oxide layer 02, which makes the device more affected by the self-heating effect. In addition, there are also problems such as low breakdown voltage and high power loss.

[0047] The multi-groove 4H-SiC MOSFET device provided by the present invention uses a P-type 4H-SiC03 layer with better thermal conductivity to replace part of the buried oxide layer to reduce the maximum lattice temperature, thereby reducing the impact of the device's self-heating effect. In addition, Figure 1 As shown, in the first embodiment of the present invention, 7 grooves are provided on the top of the P-type 4H-SiC layer 03. This multi-groove structure generates an additional peak electric field in the N-type drift layer 08, thereby modulating the surface electric field distribution to make it more uniform to increase the breakdown voltage. In the first embodiment of the present invention, the N-type Si layer 05 with a doping concentration greater than that of the N-type drift layer 08 is used to reduce the on-resistance, thereby reducing the power loss of the device.

[0048] like Figure 3 , which is a self-heating effect curve diagram of the multi-trench 4H-SiC MOSFET device provided in Example 1 of the present invention and the conventional device structure in Comparative Example 1. Figure 3 It can be seen that the maximum lattice temperature of the two structures increases with the increase of the drain voltage, but when the drain voltage is 20V, the maximum lattice temperature of the multi-groove 4H-SiC MOSFET device provided by the present invention is lower than the lattice temperature of the conventional device structure, indicating that the multi-groove 4H-SiC MOSFET device provided by the present invention is less affected by the self-heating effect and is more suitable for applications under high temperature conditions.

[0049] like Figure 4 , which is a breakdown characteristic curve diagram of the multi-trench 4H-SiC MOSFET device provided in Example 1 of the present invention and the conventional device structure in Comparative Example 1. Figure 4 It can be seen that the breakdown voltage of the multi-trench 4H-SiC MOSFET device provided by the present invention is much greater than the breakdown voltage of the conventional device, indicating that it is more suitable for applications under high voltage conditions.

[0050] like Figure 5 , which is a graph showing the output characteristic of the multi-trench 4H-SiC MOSFET device provided in Example 1 of the present invention and the conventional device structure in Comparative Example 1. Figure 5 It can be seen that under the same drain voltage (especially between 0V and 7V), the multi-groove 4H-SiC MOSFET device provided by the present invention has a larger drain current, indicating that its on-resistance is smaller than that of the conventional MOSFET device.

[0051] Comparative Example 2:

[0052] For the grooves on the top of the P-type 4H-SiC layer (03), the present application optimizes the number of grooves and the depth of the grooves. Specifically, for the number of grooves, the present application sets the groove length and depth to be 0.5 μm and 0.1 μm respectively, and sets 4 to 9 grooves for comparison. The results are as follows: Fig. 6A As shown, it can be seen that when the number of grooves is 4, 5, 6, 7, 8 and 9 respectively, the corresponding maximum lattice temperatures are 346.48K, 327.44K, 316.32K, 311.77K, 311.93K and 312.51K respectively. It can be seen that with the increase in the number of grooves, the maximum lattice temperature shows a trend of first decreasing and then increasing, and when 7 grooves are set, the corresponding maximum lattice temperature is the lowest. Therefore, 7-9 grooves can be set in the present application.

[0053] Regarding the groove depth, the present application sets 7 grooves fixedly, and the length of each groove is fixedly set to 0.5 μm, and the depths are set to 0.05 μm, 0.10 μm, 0.15 μm, 0.20 μm and 0.25 μm for comparison. Figure 6B As shown, it can be seen that the corresponding highest lattice temperatures are 313.07K, 311.77K, 312.22K, 313.23K and 312.80K, respectively. From this, it can be seen that the optimal depth range is 0.10-0.15μm.

[0054] Regarding the groove length, the present application sets 7 grooves fixedly, the groove depth is 0.10 μm, and the groove lengths are set to 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm and 0.8 μm respectively. Figure 6C As shown, it can be seen that the corresponding maximum lattice temperatures are 312.72K, 313.08K, 312.75K, 311.77K, 313.23K, 311.85K and 311.83K respectively. Taking all factors into consideration, the length value can be 0.5μm, 0.7μm or 0.8μm. The present invention finds that when the number of grooves is 7, and the depth and length of each groove are 0.1μm and 0.5μm respectively, the maximum lattice temperature of the multi-groove 4H-SiC MOSFET device decreases the most compared with the conventional device, that is, the effect of reducing the influence of the self-heating effect is the best.

[0055] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0056] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-trench 4H-SiC MOSFET device, characterized in that: include: A P-type substrate (01), on which a first buried oxide layer (02) and a second buried oxide layer (04), a P-type 4H-SiC layer (03), an N-type Si layer (05), a P-type channel layer (07), an N-type drift layer (08), a high-doping concentration N-type source layer (06) and a source metal layer (10), a high-doping concentration N-type drain layer (09) and a drain metal layer (13), a gate oxide layer (11) and a gate metal layer (12) are sequentially arranged; The top of the P-type 4H-SiC layer (03) is a multi-groove structure, the bottom of the N-type drift layer (08) is a groove shape, and the N-type Si layer (05) is embedded between the P-type 4H-SiC layer (03) and the N-type drift layer (08) and is in a comb-tooth shape for filling the grooves at the bottom of the N-type drift layer (08) and filling the multi-grooves at the top of the P-type 4H-SiC layer (03); The first buried oxide layer (02), the P-type 4H-SiC layer (03) and the second buried oxide layer (04) are sequentially arranged above the P-type substrate (01); the high-doping concentration N-type source layer (06) and the P-type channel layer (07) are located above the first buried oxide layer (02), and the high-doping concentration N-type drain layer (09) is located above the second buried oxide layer (04); the N-type drift layer (08) is located between the P-type channel layer (07) and the high-doping concentration N-type drain layer (09); the source metal layer (10) is located above the high-doping concentration N-type source layer (06), and the drain metal layer (13) is located above the high-doping concentration N-type drain layer (09); the gate oxide layer (11) is located above the P-type channel layer (07), and the gate metal layer (12) is located above the gate oxide layer (11).

2. The multi-trench 4H-SiC MOSFET device according to claim 1, characterized in that: The doping concentration of the N-type Si layer (05) is greater than the doping concentration of the N-type drift layer (08).

3. The multi-trench 4H-SiC MOSFET device according to claim 2, characterized in that: 7-9 grooves are arranged on the top of the P-type 4H-SiC layer (03).

4. The multi-trench 4H-SiC MOSFET device according to claim 3, characterized in that: The depth of the groove at the top of the P-type 4H-SiC layer (03) is in the range of 0.10-0.15 μm.

5. The multi-trench 4H-SiC MOSFET device according to claim 4, characterized in that: The length of the top groove of the P-type 4H-SiC layer (03) is 0.5 μm, 0.7 μm or 0.8 μm.

6. The multi-trench 4H-SiC MOSFET device according to claim 5, characterized in that: The material of the N-type drift layer (08) is silicon, the depth and length of the bottom trench are 0.1 μm and 6.5 μm respectively, and the doping concentration is 2×10 16 cm -3 .

7. The multi-trench 4H-SiC MOSFET device according to claim 1, characterized in that: The material of the P-type substrate (01) is silicon carbide, and its doping concentration is 1×10 14 cm -3 ; The material of the P-type channel layer (07) is silicon, and its doping concentration is 5×10 17 cm -3 , whose length and thickness are 1μm and 0.5μm respectively.

8. A semiconductor power device, characterized in that: The semiconductor power device comprises the multi-trench 4H-SiC MOSFET device according to any one of claims 1 to 7.

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