Light Emitting Diode

Abstract

The present invention relates to the field of semiconductors and discloses a light emitting diode, comprising a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-electrode and a P-electrode, wherein the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the substrate, and the N-electrode and the P-electrode are insulated from each other; a groove extending to the middle of the N-type semiconductor layer is provided on the P-type semiconductor layer, and the bottom of the groove is a first surface; the P-electrode is located on the P-type semiconductor layer and is electrically connected to the P-type semiconductor layer; an inner groove is also provided in the groove, and the bottom of the inner groove is a second surface, the roughness of the second surface is lower than that of the first surface, and the N-electrode is electrically connected to the N-type semiconductor layer through the second surface of the inner groove.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a light emitting diode. Background Art

[0002] Light Emitting Diode (LED) is a semiconductor diode that can convert electrical energy into light energy. According to the different packaging methods, it can be divided into upright structure, flip-chip structure and vertical structure. Compared with the traditional upright structure chip, the flip-chip structure chip does not need to weld gold wire during the packaging process, can be driven by large current, has low chip thermal resistance and high reliability. Therefore, the flip-chip structure chip has very good applications in general lighting, backlight, flash, and automotive lighting, and is increasingly favored by customers, and its application scope is also constantly expanding.

[0003] The existing flip-chip structure chips are divided into Ag mirror flip-chip structure, DBR (distributed Bragg reflector) flip-chip structure and ODR (omnidirectional reflector) flip-chip structure according to the main reflective layer. Ag mirror flip-chip uses silver film as the reflective layer, which is favored by the industry because of its high reflectivity and high conductivity at different angles. However, Ag metal is highly active, the surface is easily oxidized, and the adhesion between metal and semiconductor is poor, which can easily lead to chip failure. DBR flip-chip structure chips abandon silver film as the reflective layer, and instead use two insulating materials with different refractive indices to alternately stack to form a distributed Bragg reflector as the reflective layer. Although the problem of the silver mirror structure is solved, its reflectivity for light of different incident angles and wavelengths is greatly different, and its application range is limited; later, some people proposed to use the ODR flip-chip structure with metal reflective layer and DBR reflective layer as the reflective layer to improve the reflectivity of the flip chip. However, the problems of the metal reflective layer and DBR reflective layer themselves, as well as the adhesion and stress problems between layers, are all problems that need to be solved urgently. Summary of the invention

[0004] Purpose of the invention: In view of the problems existing in the prior art, the present invention provides a light emitting diode with lower stress, lower voltage, higher brightness and lower cost.

[0005] Technical solution: The present invention provides a light-emitting diode, comprising a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-electrode and a P-electrode, wherein the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the substrate, and the N-electrode and the P-electrode are insulated from each other; a groove extending to the middle of the N-type semiconductor layer is provided on the P-type semiconductor layer, and the bottom of the groove is a first surface; the P-electrode is located on the P-type semiconductor layer and is electrically connected to the P-type semiconductor layer; a first CBL layer, a DBR layer and a second CBL layer are sequentially stacked between the P-type semiconductor layer and the P-electrode; a first through hole exposing the first CBL layer is provided on the DBR layer, and a second through hole exposing the P-type semiconductor layer is provided on the first CBL layer and the second CBL layer, and the first CBL layer and the second CBL layer completely wrap and seal the DBR layer; an inner groove is also provided in the groove, the bottom of the inner groove is a second surface, there is a height difference ΔH1 between the first surface and the second surface, and the N-electrode is electrically connected to the N-type semiconductor layer through the second surface of the inner groove.

[0006] Preferably, the height difference between the first surface and the second surface is 200Å≤△H1≤2000Å; and / or, the first surface and the second surface are connected by a first inclined sidewall, and the inclination angle α of the first inclined sidewall is 5°~60°.

[0007] Preferably, the upper surface of the P-type semiconductor layer is a third surface, the height difference between the first surface and the third surface is 0.5μm≤△H2≤3μm, preferably 1.1μm≤△H2≤1.6μm; and / or, the third surface is connected to the first surface through a second inclined side wall, and the inclination angle β of the second inclined side wall is 20°~60°.

[0008] Preferably, the thickness of the second CBL layer is less than that of the first CBL layer. Specifically, the ratio of the thickness of the first CBL layer to the thickness of the second CBL layer is 5-25.

[0009] Further, the P electrode includes a first connecting electrode and a second connecting electrode, the first connecting electrode is arranged on the second CBL layer and is electrically connected to the P-type semiconductor layer through the second through hole; the second connecting electrode is electrically connected to the P-type semiconductor layer through the first connecting electrode; and / or, the first insulating layer is arranged between the first connecting electrode and the second connecting electrode, the first insulating layer is provided with a third through hole exposing the fourth surface of the first connecting electrode, and is provided with a fourth through hole exposing the second surface, the second connecting electrode is electrically connected to the first connecting electrode through the third through hole, and the N electrode is electrically connected to the N-type semiconductor layer through the fourth through hole.

[0010] Preferably, the third through hole is a porous structure, and the porous structure of the third through hole divides the first insulating layer in the third through hole into a number of independent insulating bulges, and adjacent insulating bulges are isolated from each other to form the third through hole of the porous structure; and / or, the first through hole is a porous structure, and the porous structure of the first through hole divides the DBR layer in the first through hole into a number of independent DBR bulges, and adjacent DBR bulges are isolated from each other to form the first through hole of the porous structure; the second through hole is a porous structure, and the porous structure of the second through hole divides the first CBL layer and the second CBL layer in the second through hole into a number of independent CBL bulges, and adjacent CBL bulges are isolated from each other to form the second through hole of the porous structure.

[0011] Preferably, the first through hole, the second through hole and the insulating bulge are coaxially arranged; and / or, the radius r3 of the insulating bulge is greater than the radius r1 of the first through hole and greater than the radius r2 of the second through hole; and / or, the spacing w1 between adjacent insulating bulges is greater than 5μm. The first through hole, the second through hole and the insulating bulge are coaxially arranged, and the radius of the insulating bulge is designed to be greater than the radius of the first through hole, and the radius of the first through hole is greater than the radius of the second through hole. After such a design, the insulating bulge can just reflect the light passing through the first through hole and the second through hole, improve the reflection effect, and improve the luminous efficiency of the LED. In order to improve the reflection effect, the insulating bulge in the present application can also be designed as a reflection structure, and the reflection structure can be an ordinary reflection layer structure.

[0012] Preferably, the third through hole and the fourth through hole are opened by the following two-stage etching method to obtain the second surface: the first stage: using a mixed gas containing fluorine ions to perform ICP etching on the first insulating layer to expose the first surface of the N-type semiconductor layer; at the same time, the first connecting electrode is exposed; the second stage: using a mixed gas containing chloride ions but not containing fluorine ions to continue etching to obtain the fourth through hole and the inner groove, exposing the second surface; at the same time, the third through hole is obtained to expose the fourth surface. Through the above two-stage distributed etching, the first stage uses CF4, oxygen, Ar, Cl2, BCl3 and other gases for etching, because the first insulating layer is subjected to ICP etching to expose the first surface of the N-type semiconductor layer, and at the same time, the first connecting electrode is exposed; the second stage etching gas is a mixed gas containing Cl ions and containing no F ions. Because the concentration and density of the active chlorine contained are increased, the chemical etching is greatly enhanced, thereby the etching rate is increased, and at the same time, the enhancement of chemical etching will cause the exposed N-type semiconductor layer (containing Ga) to be preferentially etched to obtain the inner groove, and an ion milling effect will occur, so that the second surface of the inner groove is etched more cleanly, which is equivalent to repairing the interface of the exposed N-type semiconductor layer, making the second surface smoother, and the resulting chip voltage is reduced and the brightness is improved.

[0013] Preferably, in the second section, the first metal layer in the first connection electrode is completely etched from top to bottom, the thickness of the second metal layer from top to bottom is S, the surface of the first connection electrode that is not exposed is the fifth surface, then the height difference between the fourth surface and the fifth surface is △T, and 1 / 4*S<△T<4 / 5*S; and / or, the fourth surface and the fifth surface are connected by a third inclined sidewall, and the inclination angle of the third inclined sidewall is θ≤50°. If △T is too small, △H1 is too small, and the etching is insufficient; if △T is too large, △H1 is too large, which easily leads to the N-type semiconductor layer being etched through.

[0014] Preferably, the first insulating layer is composed of an ALD film layer and a silicon nitride / silicon oxide composite laminate stacked in sequence; and / or, the overall thickness of the first insulating layer is greater than or equal to 6KÅ and less than or equal to 15KÅ, wherein the thickness of the silicon nitride is greater than 15% of the thickness of the first insulating layer and less than 50% of the thickness of the first insulating layer. This first insulating layer has a Bragg reflection effect, which can prevent the precipitation of Ag in the PN electrode and protect the entire chip structure.

[0015] Preferably, 12 μm<minimum distance w2 between the N electrode and the first connecting electrode<50 μm; and / or 15 μm<minimum width w3 of the N electrode current channel<50 μm.

[0016] Preferably, the first connection electrode comprises a metal reflective layer formed by a first metal, a metal barrier layer formed by alternating layers of a second metal and a third metal, and a metal protective layer formed by alternating layers of a fourth metal and / or a fifth metal, wherein at least one of the fourth metal and the fifth metal is the same material as the second metal or the third metal, and the thickness of the fourth metal and the fifth metal is greater than the thickness of the second metal layer and the third metal layer. Specifically, the first metal is Ag, the second metal is Ti or Cr, the third metal is Ni or Cr, the fourth metal is Pt or Ni, and the fifth metal is Ti. The second metal is different from the third metal, and the fourth metal is different from the fifth metal; the period of the metal protective layer is 2-10, the thickness of the metal reflective layer is greater than 500Å, and the thickness of the fourth metal layer is greater than the thickness of the fifth metal layer. Among materials such as Ag, Ti, Ni, Cr, and PT, Ag, Ti, and Ni are essential materials. The electrode structure does not contain metal Al and Au, and includes multiple pairs of Ti / Ni stacks, wherein the number of Ti / Ni pairs N1 satisfies 2≤N1≤5, the bottom layer Ag is the thickest, and the Ag thickness is not less than 500Å. The Ni thickness of the last pair of Ti / Ni in the Ti / Ni stack is the thickest, and the thickness is >400Å, wherein the Ni thickness of the entire P electrode is <3KÅ, and the thickness of each Ni layer is <1KÅ. The top layer of the entire P electrode is metal Ti, and the total thickness of the entire P electrode is 4500≤Td<1μm; the thickness of the last pair of Ni / Ti is thicker in order to reserve the third through hole on the first insulating layer mentioned above.

[0017] Beneficial Effects

[0018] Usually, the DBR layer is etched by dry etching. Due to the difference in etching rates of different materials, the sidewalls of the DBR are uneven after etching. If the first connection electrode is directly deposited, the adhesion between the DBR sidewall and the metal layer will deteriorate, which may easily cause metal shedding. However, the present invention deposits a second CBL layer on the DBR layer as a protective layer, and wet etches the first CBL layer and the second CBL layer to obtain a smaller second through hole and form a relatively smooth sidewall, thereby increasing the adhesion between the interface and the first connection electrode deposited subsequently.

[0019] In the present invention, an inner groove with a smoother bottom is provided in the groove extending from the P-type semiconductor layer to the middle of the N-type semiconductor layer, and the N-electrode is electrically connected to the N-type semiconductor layer through the second surface of the inner groove; compared with the prior art in which the N-electrode is electrically connected to the N-type semiconductor through the first surface of the groove, since the roughness of the second surface is reduced, that is, the second surface is smoother and flatter than the first surface, the resistance is reduced, the obtained chip voltage is stable and low, and the brightness of the overall light-emitting diode is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figures 1 to 12b The top view and cross-sectional view show the various stages of the method for manufacturing a light emitting diode in the present invention. DETAILED DESCRIPTION

[0021] The present invention is described in detail below in conjunction with the accompanying drawings.

[0022] Implementation 1:

[0023] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art of the present invention can fully understand the spirit of the present invention. The present invention is not limited to the following embodiments, but can be implemented in other forms. In this specification, there are some identical symbols, which represent elements with the same or similar structure, function, and principle, and can be inferred by those with general knowledge in the industry based on the teachings of this specification. For the sake of brevity of the specification, elements with the same symbols will not be repeated.

[0024] This embodiment provides a light emitting diode such as Figure 12b , including a substrate 101 and an N-type semiconductor layer 102, an active layer 103, a P-type semiconductor layer 104, a transparent conductive layer 105, a first CBL layer 106, a DBR layer 107, a second CBL layer 108, a first connecting electrode 109, a first insulating layer 110, a second connecting electrode 111 and an N-electrode 112, a second insulating layer 113, an N-pad 114 and a P-pad 115 which are sequentially stacked on the substrate 101. The first connection electrode 109 and the second connection electrode 111 constitute a P electrode, and the N electrode 112 is insulated from the P electrode; a groove 1021 extending to the middle of the N-type semiconductor layer 102 is provided on the P-type semiconductor layer 104, and the bottom of the groove 1021 is the first surface 1022; an inner groove 1023 is also provided in the groove 1021, and the bottom of the inner groove 1023 is the second surface 1024, and there is a height difference △H1 between the first surface 1022 and the second surface 1024, and the N electrode 112 is electrically connected to the N-type semiconductor layer 102 through the second surface 1024 of the inner groove 1023. The P electrode is located on the P-type semiconductor layer 104 and is electrically connected to the P-type semiconductor layer 104.

[0025] The DBR layer 107 is provided with a first through hole 1071 exposing the first CBL layer 106, and the first CBL layer 106 and the second CBL layer 108 are provided with a second through hole 1081 exposing the P-type semiconductor layer 104. The first CBL layer 106 and the second CBL layer 108 completely wrap and seal the DBR layer 107; the first connecting electrode 109 of the P electrode is provided on the second CBL layer 108 and is electrically connected to the P-type semiconductor layer 104 through the second through hole 1081; the second connecting electrode 111 is electrically connected to the P-type semiconductor layer 104 through the first connecting electrode 109;

[0026] The first insulating layer 110 is arranged between the first connecting electrode 109 and the second connecting electrode 111. The first insulating layer 110 is provided with a third through hole 1101 exposing the first connecting electrode 109 and a fourth through hole 1102 exposing the second surface 1024. The second connecting electrode 111 is electrically connected to the first connecting electrode 109 through the third through hole 1101, and the N electrode 112 is electrically connected to the N-type semiconductor layer 102 through the fourth through hole 1102.

[0027] The second insulating layer 113 is located on the second connecting electrode 111 and the N electrode 112, and a fifth through hole 1131 exposing the second connecting electrode 111 and a sixth through hole 1132 exposing the N electrode 112 are formed on the second insulating layer 113; an N pad 114 and a P pad 115 isolated from each other are formed on the second insulating layer 113, and the N pad 114 is electrically connected to the N electrode 112 through the fifth through hole 1131, and the P pad 115 is electrically connected to the second connecting electrode 111 through the sixth through hole 1132.

[0028] In one embodiment, the first through hole 1071 is a porous structure, and the porous structure of the first through hole 1071 divides the DBR layer 107 in the first through hole 1071 into a plurality of independent DBR bulges 1072, and adjacent DBR bulges 1072 are isolated from each other to form the first through hole 1071 with a porous structure; the second through hole 1081 is a porous structure, and the porous structure of the second through hole 1081 divides the first CBL layer 106 and the second CBL layer 108 in the second through hole 1081 into a plurality of independent CBL bulges 1082, and adjacent CBL bulges 1082 are isolated from each other to form the second through hole 1081 with a porous structure.

[0029] In another embodiment, the third through hole 1101 is a porous structure, and the porous structure of the third through hole 1101 divides the first insulating layer 110 in the third through hole 1101 into a plurality of independent insulating bulges 1103, and adjacent insulating bulges 1103 are isolated from each other to form the third through hole 1101 with a porous structure, and the spacing w1 between adjacent insulating bulges 1103 is greater than 5 μm. The first through hole 1071, the second through hole 1081 and the third through hole 1101 are concentric circles.

[0030] Figures 1 to 12b The top view and cross-sectional view of each stage of the method for manufacturing a light emitting diode according to an embodiment of the present invention are shown. The method for manufacturing a light emitting diode is described in detail as follows.

[0031] First, refer to Figure 1, a semiconductor stack is formed on the substrate 101. The substrate 101 may be a wafer, and the semiconductor stack formed thereon constitutes a semiconductor wafer. The semiconductor wafer is separated into a plurality of light emitting diodes after a subsequent cutting process, and the following embodiment diagrams and descriptions will be represented by a single light emitting diode.

[0032] In one embodiment of the present invention, the substrate 101 may be formed using a carrier wafer suitable for the growth of semiconductor materials. In addition, the substrate 110 may be formed of a material having excellent thermal conductivity or may be a conductive substrate or an insulating substrate. In addition, the substrate 110 may be formed of a light-transmitting material and may have a mechanical strength that does not cause the entire semiconductor stack 120 to bend and enables it to be effectively divided into separate chips by scribing and breaking processes. For example, the substrate 110 may use a sapphire (Al2O3) substrate, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a zinc oxide (ZnO) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, or a gallium phosphide (GaP) substrate, etc., and in particular, a sapphire (Al2O3) substrate is preferably used. In this embodiment, the substrate 110 is a sapphire having a series of protrusions on the surface, including, for example, protrusions without a fixed slope made by dry etching, or protrusions with a certain slope made by wet etching.

[0033] In one embodiment of the present invention, a semiconductor stack consisting of an N-type semiconductor layer 102, an active layer 103, and a P-type semiconductor layer 104, such as a light-emitting stack, is formed on a substrate 101 by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), physical vapor deposition (PVD), or ion plating, wherein the physical vapor deposition method includes sputtering or evaporation. The N-type semiconductor layer 102, the active layer 103, and the P-type semiconductor layer 104 are sequentially formed on the substrate 101. The N-type semiconductor layer 102, the active layer 103, and the P-type semiconductor layer 104 can be formed of a compound semiconductor of the III-group gallium nitride series, such as GaN, AlN, InGaN, AlGaN, InAlGaN, and at least one of these groups. The N-type semiconductor layer 102 is a layer that provides electrons and can be formed by injecting n-type dopants (for example, Si, Ge, Se, Te, C, etc.). The P-type semiconductor layer 104 is a layer that provides holes and can be formed by injecting p-type dopants (for example, Mg, Zn, Be, Ca, Sr, Ba, etc.). The active layer 103 is a layer that outputs light of a predetermined wavelength by recombining the electrons provided by the N-type semiconductor layer 102 and the holes provided by the P-type semiconductor layer 104. It can be formed by a multi-layer semiconductor film having a single-layer or multi-layer quantum well structure with alternately stacked potential well layers and barrier layers. The active layer 103 will select different material compositions or ratios according to the different wavelengths of the output light. For example, the emission wavelength of the light-emitting diode 1 of the embodiment of the present invention is between 420nm and 580nm. The active layer 103 may be formed to have a pair structure including a well layer and a barrier layer using a Group III to Group V compound semiconductor material (e.g., at least one of InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs (InGaAs) / AlGaAs, or GaP (InGaP) / AlGaP), but the present disclosure is not limited thereto. The well layer may be formed of a material having a smaller energy band gap than that of the barrier layer.

[0034] After the semiconductor stack is formed on the substrate 101, Figure 2a and 2bIn this step, the semiconductor stack is patterned by photolithography and etching to form a MESA step (etching the P-type semiconductor layer 104, the active layer 103, and part of the N-type semiconductor layer 102, and the exposed surface of the N-type semiconductor layer 102 is the first surface 1022 and the ISO walkway area 116 (etching the P-type semiconductor layer 104, the active layer 103, and the N-type semiconductor layer 102 to expose the upper surface of the substrate 101. The ISO walkway area separates and defines a plurality of light-emitting units, and serves as the location of the prepared dividing line in the subsequent cutting process), exposing the first surface 1022 of the N-type semiconductor layer 102. The first surface 1022 is connected to the surface of the P-type semiconductor layer 104, the third surface 1041, through the second inclined sidewall 117, and the inclination angle β of the second inclined sidewall 117 is 20°~60°. A large angle can easily cause the subsequent sidewall insulation layer or metal layer to break, causing leakage risk.

[0035] Next, refer to Figure 3 , and a transparent conductive layer 105 is formed on the P-type semiconductor layer 104. The transparent conductive layer 105 covers the upper surface of the P-type semiconductor layer 104 and is in electrical contact with the P-type semiconductor layer 104. The transparent conductive layer 105 can substantially contact almost the entire upper surface of the P-type semiconductor layer 104. In this structure, when the current is provided to the light-emitting diode, it can be spread in the horizontal direction through the transparent conductive layer 105, and thus can be uniformly provided to the entire P-type semiconductor layer 104. In a preferred embodiment, the thickness of the transparent conductive layer 105 is 70Å~450Å. If the thickness is too thin, it is easy to increase the forward voltage (Vf) of the light-emitting diode, and if it is too thick, its light absorption effect will increase significantly. The material of the transparent conductive layer 105 can be ITO, InO, SnO, CTO, ATO, ZnO, GaP or a combination thereof. The transparent conductive layer 105 can be formed by evaporation or sputtering.

[0036] In another embodiment, the transparent conductive layer 105 is provided with a plurality of openings that expose a portion of the P-type semiconductor layer 104, that is, a honeycomb design or a parallel cross design is adopted. By controlling the size and density of the openings, the area ratio of the semiconductor stack occupied by the transparent conductive layer 105 is greater than 50% and less than 95%. While ensuring that the transparent conductive layer 105 and the P-type semiconductor layer 104 have sufficient ohmic contact, the area of ​​the transparent conductive layer 130 is reduced, and the light absorption effect brought by the ITO material itself is reduced, thereby improving the light extraction efficiency and the brightness of the light-emitting diode. Preferably, the area ratio of the semiconductor stack occupied by the transparent conductive layer 105 is 70 to 90%; for high-power products, considering the current expansion effect, the transparent conductive layer 105 adopts a whole-surface tiling design. Specifically, the openings are distributed in an array, with a diameter of 4 to 20 μm, and the spacing between adjacent openings is 10 to 100 μm. The distance between the edge of the transparent conductive layer 105 and the MESA step is 2 μm to 15 μm. If the distance is too small, leakage may occur easily. If the distance is too large, abnormal edge conduction may occur and the voltage may be too high.

[0037] Next, refer to Figure 4a and 4b , forming a first CBL layer 106 on the transparent conductive layer 105 and the semiconductor stack, wherein the thickness Ta of the first CBL layer 106 is between 3KÅ and 8KÅ, preferably between 4KÅ and 6KÅ. Forming a DBR layer 107 on the first CBL layer 106, wherein the DBR layer 107 is designed to have a reflection spectrum range of 400nm to 600nm to achieve main reflection, and the reflectivity spectrum is greater than 75%; the thickness of the DBR layer 107 is less than 1um, preferably between 3KÅ and 6KÅ; then etching the DBR layer 107 and a portion of the first CBL layer 106 by coating, coating, exposure, and development to form a first through hole 1071 with a radius of r1 exposing the first CBL layer 106, 4um≤r1≤20um, and the minimum distance between two adjacent first through holes 1071 is 15μm<D1<50μm. Specifically, the DBR layer 107 is etched incompletely by using gases such as CF4, BCl3, O2, Ar, etc., and the thickness of the remaining first CBL layer 106 after etching is Tb>0, preferably 1 / 3*Ta≤Tb≤2 / 3*Ta, the etching rate R1 satisfies 10Å / S<R1<25Å / S, the photoresist thickness is <6μm, the upper radio frequency of ICP etching is <1200W, the lower radio frequency is <600W, and the etching angle ∅1 satisfies 25°≤∅1≤50°, preferably 35°≤∅1≤45°.

[0038] Next, refer to Figures 5a to 6, a second CBL layer 108 is formed on the remaining first CBL layer 106 and the DBR layer 107 by evaporating any one or two combinations of materials such as SiN, SiO2, ALD, etc., and the second CBL layer 108 and the uppermost layer of the DBR layer 107 are made of different materials and are formed by different equipment. The first CBL layer 106 and the second CBL layer 108 can be made of the same material or different materials, such as the first CBL layer 106 is silicon oxide and the second CBL layer 108 is silicon nitride, or the first CBL layer 106 is silicon oxide and the second CBL layer 108 is silicon oxide, etc. The thickness of the second CBL layer 108 is 300Å<Tc<2000Å. Through coating, coating, exposure, development and other technologies, a second through hole 1081 with a radius of r2 exposing the P-type semiconductor layer 104 is set on the first CBL layer 106 and the second CBL layer 108 using a wet etching method, 1≤r2≤10um, △r=r1-r2, 2μm<△r<15μm.

[0039] The first CBL layer 106 and the second CBL layer 108 completely wrap and seal the DBR layer 107. The second CBL layer 108 is equivalent to a protective layer, which can cover the side wall of the opening of the DBR layer 107. The first CBL layer 106 and the second CBL layer 108 completely cover the DBR layer 107. The preparation method of at least one of the first CBL layer 106 and the second CBL layer 108 is different from that of the DBR layer 107.

[0040] Next, refer to Figure 7a and 7b , the step of forming the P electrode is performed. The P electrode includes a first connection electrode 109 and a second connection electrode 111. In this step, the first connection electrode 109 is disposed on the second CBL layer 108, and the first connection electrode 109 is electrically connected to the P-type semiconductor layer 104 through the second through hole 1081 and the transparent conductive layer 105.

[0041] The materials of the first connecting electrode 109 include Ag, Ti, Ni, Cr, PT and other materials, among which Ag, Ti and Ni are essential materials. The electrode structure does not contain metal Al and Au. The electrode structure includes multiple pairs of stacked Ti / Ni layers, among which the Ti / Ni pair number N1 satisfies 2≤N1≤5, the bottom layer Ag is the thickest, and the Ag thickness is not less than 500 Å. The last pair of Ni in the TiNi structure is the thickest, with a thickness of >400Å, among which the Ni thickness of the entire first electrode is <3K Å, and the thickness of each Ni layer is <1K Å. The top layer of the entire first connecting electrode is metal Ti, and the total thickness of the entire first connecting electrode is 4500≤Td<1μm, so as to reduce the stress of the first connecting electrode; the last pair of Ni / Ti is thicker in order to reserve the third through hole 1101 on the first insulating layer 110 mentioned above.

[0042] Then, refer to Figures 8a to 9, a first insulating layer 110 is formed on the first connection electrode 109 and the second CBL layer 108, and a third through hole 1101 exposing the first connection electrode 109 and a fourth through hole 1102 exposing the second surface 1024 are opened on the first insulating layer 110, the second connection electrode 111 is electrically connected to the first connection electrode 109 through the third through hole 1101, and the N-electrode 112 is electrically connected to the N-type semiconductor layer 102 through the fourth through hole 1102. Preferably, the third through hole 1101 is a porous structure, and the porous structure of the third through hole 1101 divides the first insulating layer 110 in the third through hole 1101 into a plurality of independent insulating bulges 1103, and adjacent insulating bulges 1103 are isolated from each other to form the third through hole 1101 with a porous structure; the spacing w3 between adjacent insulating bulges 1103 is greater than 5μm, and the insulating bulge 1103 plays a protective role for the first connection electrode 109 of the P electrode in the lower layer. The first through hole 1071 , the second through hole 1081 and the insulating bulge 1103 are concentric circles; the radius r3 of the insulating bulge 1103 is greater than the radius r1 of the first through hole 1071 and greater than the radius r2 of the second through hole 1081 .

[0043] Preferably, the third through hole 1101 and the fourth through hole 1102 are opened by the following two-stage etching method to obtain the second surface 1024:

[0044] The first stage: using a mixed gas containing fluorine ions, such as CF4, oxygen, Ar, Cl2, BCl3 and the like, to perform ICP etching on the first insulating layer 110 to expose the first surface 1022 of the N-type semiconductor layer 102 and, at the same time, expose the first connection electrode 109;

[0045] The second stage: Continue etching using a mixed gas containing chloride ions but not containing fluorine ions to obtain a fourth through hole 1102, exposing a second surface 1024 having a height difference of △H1 with the first surface 1022 of the N-type semiconductor layer 102; at the same time, a third through hole 1101 is obtained, and the first connecting electrode 109 may also be over-etched, so that the fourth surface 1091 of the first connecting electrode 109 exposed by the third through hole 1101 and the fifth surface 1092 of the unexposed first connecting electrode 109 also have a height difference △T. The fourth surface 1091 and the fifth surface 1092 are connected by a third inclined side wall 118, and the inclination angle θ of the third inclined side wall 118 is ≤50°. Because the concentration and density of active chlorine contained in the second etching gas increase, chemical etching is greatly enhanced, thereby increasing the etching rate. At the same time, the enhanced chemical etching causes the exposed N-type semiconductor layer 102 (containing Ga) to be etched preferentially, resulting in an ion milling effect, causing the surface roughness to decrease, which is equivalent to repairing the second surface 1024 of the exposed N-type semiconductor layer 102, making the interface smoother and cleaner, reducing resistance, and obtaining a stable and low chip voltage, with improved brightness.

[0046] In the above-mentioned second etching, the first layer of metal from top to bottom in the first connecting electrode 109 is completely etched away, and the thickness of the second layer of metal from top to bottom is S, then 1 / 4*S<△T<4 / 5*S, if △T is too small, then △H1 is too small, and the etching is insufficient; if △T is too large, then △H1 is too large, which easily causes the N-type semiconductor layer 102 to be etched through.

[0047] At this point, the inner groove 1023 extending from the third surface 1041 of the P-type semiconductor layer 104 to the middle of the N-type semiconductor layer 102 is formed in the groove 1021. The height difference between the first surface 1022 of the groove 1021 and the second surface 1024 of the inner groove 1023 is 200Å≤△H1≤2000Å; preferably △H1<1500Å. The first surface 1022 and the second surface 1024 are connected by the first inclined sidewall 119, and the inclination angle α of the first inclined sidewall 119 is 5°~60°, preferably ≤55°. The height between the first surface 1022 and the third surface 1041 is H1, 1.1μm

[0048] The first insulating layer 110 is composed of ALD film layer 1104 (film layer prepared by atomic deposition method) and silicon nitride / silicon oxide composite laminate 1105 stacked in sequence. Due to the characteristics of Ag metal being active and easy to precipitate, the insulating layer that the P electrode is most directly in contact with is silicon oxide, silicon nitride, ALD, etc. It is particularly recommended that the direct layer be covered with ALD film layer 1104 (atomic layer unit deposition technology "Atomic Layer Deposition (ALD)"), which can achieve step defect-free coverage. At the same time, the breakdown voltage of the film layer of this technology meets the requirement of >8 MV / cm, the O / Al atomic ratio meets the specification of 1.5±0.1, the thickness of the ALD film layer 1104 is between 200Å and 5000Å, and considering the light absorption characteristics of the ALD film layer 1104, the thickness of 500Å to 1500Å is optimal. From a practical point of view, the material in direct contact with the ALD film layer 1104 can be a single layer of silicon oxide, a single layer of silicon nitride material, a single layer of silicon nitride and a single layer of silicon nitride combined film layer, or a silicon nitride / silicon oxide composite stack 1105 structure, and a silicon nitride / silicon oxide composite stack 1105 structure is particularly proposed. The composite stack structure plays the role of a Bragg reflector and can also effectively prevent the precipitation of Ag in the PN electrode. The overall thickness of the first insulating layer 110 is 6KÅ≤Te≤15KÅ, wherein the thickness of silicon nitride is greater than 15% of the thickness of the first insulating layer and less than 50% of the thickness of the first insulating layer, and preferably the thickness of silicon nitride is greater than 20% of the thickness of the first insulating layer and less than 30% of the thickness of the first insulating layer. ​

[0049] The present invention eliminates the problem of plating other more stable metals such as Ti, Pt, Au and TiW on the surface of traditional Ag electrode products after plating the reflective layer, thereby reducing the chip cost. At the same time, the three-layer composite insulation structure of the first insulation layer proposed above can avoid the problem of Ag precipitation.

[0050] Then, refer to Fig.10a and Fig.10b A second connecting electrode 111 and an N-electrode 112 isolated from each other are formed on part of the first insulating layer 110. The second connecting electrode 111 is electrically connected to the first connecting electrode 109 through the third through hole 1101 to form a P-electrode, which is electrically connected to the P-type semiconductor layer 104. The N-electrode 112 is electrically connected to the N-type semiconductor layer 102 through the fourth through hole 1102.

[0051] The materials of the second connection electrode 111 and the N electrode 112 do not contain Au, but are made of Cr, Al, Ti, Ni, Pt and other materials. The electrode thickness is less than 3μm, the angle is less than 60°, the last layer of the electrical connection electrode is metal Cr, and the penultimate layer cannot be metal Ti and metal Al, and can be designed with NiCr / PtCr. 12μm<the minimum distance w1 between the second connection electrode 111 and the N electrode 112<50μm, the purpose of this limitation is to ensure the maximization of the subsequent PN pad; 15μm<the width w2 of the minimum current channel of the N electrode 112<50μm, this limitation is to ensure the minimum congestion area for current flow and avoid current conduction limitation.

[0052] In the present invention, the reflective structure formed by the first insulating layer, the first CBL layer, the DBR layer and the second CBL layer, together with the first connecting electrode, forms a composite reflector, thereby improving the light extraction efficiency of the entire chip.

[0053] Next, refer to Fig.11 A second insulating layer 113 with a thickness of less than 1.5 μm is formed on the second connecting electrode 111 and the N electrode 112 by physical vapor deposition or chemical vapor deposition, and a fifth through hole 1131 exposing the second connecting electrode 111 and a sixth through hole 1132 exposing the N electrode 112 are opened on the second insulating layer 113.

[0054] The material of the second insulating layer 113 includes a non-conductive material, including an organic material or an inorganic material. The organic material includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, polyimide or fluorocarbon polymer. The inorganic material includes silicone, glass or a dielectric material, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), niobium oxide (Nb2O5), hafnium oxide (HfO2), titanium oxide (TiOx), magnesium fluoride (MgF2), aluminum oxide (Al2O3), etc.

[0055] Next, refer to Fig.12a , 12b , negative photoresist is used for photolithography, gluing, etching, flushing, etc., and then one photolithography is used on the second insulating layer 113 to form mutually isolated N pads 114 and P pads 115, the N pad 114 is electrically connected to the N electrode 112 through the sixth through hole 1132, and the P pad 115 is electrically connected to the second connection electrode 111 through the fifth through hole 1131.

[0056] By evaporating the P pad 115 and the N pad 114 after the above-mentioned one-time photolithography, the P pad 115 and the N pad 114 can be made not to contact the side walls of the fifth through hole 1131 and the sixth through hole 1132 on the second insulating layer 113, and the pad will not be placed on the second insulating layer 113. The side wall of the pad is at most in contact with the side wall of the fifth through hole 1131 and the sixth through hole 1132, realizing the electrode edge flattening method, reducing the ups and downs of the pad, avoiding the edge warping, ensuring the flatness of the pad, and ensuring the solid crystal effect. When designing the pad, the grooves where all the N electrodes 112 are located are simultaneously bypassed to avoid obvious depressions in the pad. The pad structure can be an AuSn pad or a bump electrode. The electrode does not contain metal Al, the PT thickness is less than 3KÅ, and includes Cr, PT, Ti, Ni, and Au. The Au thickness is less than 3KÅ, and the Ni thickness is between 4KÅ and 10KÅ. It is evaporated in a heating mode.

[0057] The above embodiments are merely illustrative of the principles and effects of the present application, and are not intended to limit the present application. Anyone with ordinary knowledge in the technical field to which the present application belongs may modify and change the above embodiments without violating the technical principles and spirit of the present application. All equivalent changes and modifications made according to the shapes, structures, features, and spirits described in the claims of the present application shall be included in the claims of the present application.

[0058] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent transformation or modification made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A light emitting diode, comprising an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-electrode and a P-electrode, wherein the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on a substrate, and the N-electrode and the P-electrode are insulated from each other; the P-type semiconductor layer is provided with a groove extending to the middle of the N-type semiconductor layer, and the bottom of the groove is a first surface; the P-electrode is located on the P-type semiconductor layer and is electrically connected to the P-type semiconductor layer; characterized in that: A first CBL layer, a DBR layer, and a second CBL layer are stacked in sequence between the P-type semiconductor layer and the P electrode; a first through hole exposing the first CBL layer is provided on the DBR layer, and second through holes exposing the P-type semiconductor layer are provided on the first CBL layer and the second CBL layer, and the first CBL layer and the second CBL layer completely wrap and seal the DBR layer; An inner groove is further provided in the groove, the bottom of the inner groove is a second surface, a height difference ΔH1 is provided between the first surface and the second surface, and the N electrode is electrically connected to the N-type semiconductor layer through the second surface of the inner groove; The roughness of the second surface is less than that of the first surface, and the height difference is 200Å≤△H1≤2000Å.

2. The light emitting diode according to claim 1, characterized in that: The first surface and the second surface are connected via a first inclined side wall, and an inclination angle α of the first inclined side wall is 5° to 60°.

3. The light emitting diode according to claim 2, characterized in that: The upper surface of the P-type semiconductor layer is a third surface, and a height difference between the first surface and the third surface is 0.5 μm≤△H2≤3 μm; And / or, the third surface is connected to the first surface via a second inclined side wall, and the inclination angle β of the second inclined side wall is 20° to 60°; And / or, the thickness of the second CBL is smaller than the thickness of the first CBL.

4. The light emitting diode according to any one of claims 1 to 3, characterized in that: The P electrode includes a first connection electrode and a second connection electrode, the first connection electrode is disposed on the second CBL layer and is electrically connected to the P-type semiconductor layer through the second through hole; the second connection electrode is electrically connected to the P-type semiconductor layer through the first connection electrode; And / or, a first insulating layer is arranged between the first connecting electrode and the second connecting electrode, a third through hole exposing the fourth surface of the first connecting electrode is provided on the first insulating layer, and a fourth through hole exposing the second surface is provided, the second connecting electrode is electrically connected to the first connecting electrode through the third through hole, and the N electrode is electrically connected to the N-type semiconductor layer through the fourth through hole.

5. The light emitting diode according to claim 4, characterized in that: The third through hole is a porous structure, and the porous structure of the third through hole divides the first insulating layer in the third through hole into a plurality of independent insulating bulges, and adjacent insulating bulges are isolated from each other to form the third through hole of the porous structure; And / or, the first through hole is a porous structure, the porous structure of the first through hole divides the DBR layer in the first through hole into a plurality of independent DBR bulges, and adjacent DBR bulges are isolated from each other to form the first through hole of the porous structure; the second through hole is a porous structure, the porous structure of the second through hole divides the first CBL layer and the second CBL layer in the second through hole into a plurality of independent CBL bulges, and adjacent CBL bulges are isolated from each other to form the second through hole of the porous structure.

6. The light emitting diode according to claim 5, characterized in that: The first through hole, the second through hole and the insulating bulge are coaxially arranged; And / or, the insulating bulge r3>the radius r1 of the first through hole>the radius r2 of the second through hole; And / or, the spacing w1 between adjacent insulating bumps is greater than 5 μm.

7. The light emitting diode according to claim 4, characterized in that: The third through hole and the fourth through hole are opened by the following two-stage etching method to obtain the second surface: The first stage: using a mixed gas containing fluorine ions to perform ICP etching on the first insulating layer to expose the first surface of the N-type semiconductor layer; at the same time, the first connecting electrode is exposed; The second stage: continue etching using a mixed gas containing chloride ions but not containing fluorine ions to obtain the fourth through hole and the inner groove, exposing the second surface; at the same time, obtain a third through hole, exposing the fourth surface.

8. The light emitting diode according to claim 7, characterized in that: In the second section, the first metal layer in the first connecting electrode is completely etched away from top to bottom, the thickness of the second metal layer from top to bottom is S, the surface of the first connecting electrode that is not exposed is the fifth surface, then the height difference between the fourth surface and the fifth surface is △T, and 1 / 4*S<△T<4 / 5*S; And / or, the fourth surface is connected to the fifth surface via a third inclined side wall, and an inclination angle θ of the third inclined side wall is ≤50°.

9. The light emitting diode according to claim 4, characterized in that: The first insulating layer is composed of an ALD film layer and a silicon nitride / silicon oxide composite layer stacked in sequence; And / or, the overall thickness of the first insulating layer is greater than or equal to 6 KÅ and less than or equal to 15 KÅ, wherein the thickness of the silicon nitride is greater than 15% of the thickness of the first insulating layer and less than 50% of the thickness of the first insulating layer.

10. The light emitting diode according to claim 4, characterized in that: 12 μm<the minimum distance w2 between the N electrode and the first connecting electrode<50 μm; And / or, 15 μm<the width w3 of the minimum current channel of the N-electrode<50 μm.

11. The light emitting diode according to claim 4, characterized in that: The first connecting electrode includes a metal reflective layer formed by a first metal, a metal barrier layer in which a second metal and a third metal are alternately stacked, and a metal protective layer formed by a fourth metal and / or a fifth metal, wherein at least one of the fourth metal and the fifth metal is made of the same material as the second metal or the third metal, and the thickness of the fourth metal and the fifth metal are both greater than the thickness of the second metal layer and the third metal layer.

Images