An active clamp flyback topology system and method

Abstract

The embodiment of the application discloses an active clamp flyback topology system and method, the system comprises an AC input end L-N line, a first double-control half-bridge switch, a second double-control half-bridge switch, an isolation transformer, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, an output filter capacitor, the AC input end L-N line is used for receiving an AC input level signal; in the case that the AC input end L-N line is connected to the first double-control half-bridge switch and the second double-control half-bridge switch, and the positive half cycle and the negative half cycle both input the AC input level signal, the isolation transformer is used for isolating the AC input level signal, and the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are used for synchronously rectifying the AC input level signal, and the output filter capacitor is used for filtering and outputting direct current. The application can realize AC-DC conversion of active clamp flyback without a rectifier bridge, and can effectively eliminate the efficiency loss caused by the rectifier bridge.

Description

Technical Field

[0001] This application relates to power supply technology and is applied in fields such as power electronics, and in particular to an active clamp flyback topology system and method. Background Technology

[0002] Currently, conventional active clamp flyback converter circuits are DC-DC circuits. If AC-DC power conversion is required, a rectifier bridge is needed at the input to convert the input AC to DC. The AC-DC circuit works as follows: After the AC level signal is input through the LN line of the AC input terminal, it is first rectified by the rectifier bridge BD1, filtered by the output filter capacitor CE1, and then output as DC. It is then connected to a high-frequency half-bridge composed of MOSFETs Q1 and Q2. By controlling the high and low levels of points A and B, Q1 and Q2 are alternately turned on. Q2 is a switching transistor, and Q1 is a synchronous clamping transistor. The midpoint of the half-bridge is connected to an isolation transformer for isolation transformation, and then rectified by the high-frequency synchronous switching transistor Q3. The output is filtered by the output filter capacitor C3 to output DC, completing the AC-DC conversion. Because of the presence of the input rectifier bridge, losses are inevitable. Typically, the on-state voltage drop of a rectifier bridge is 0.7*2=1.4V. At low input voltages, such as 110V, this can result in power losses of nearly 1% or more, which is one of the bottlenecks to improving efficiency. Therefore, how to reduce the losses caused by the rectifier bridge to the AC-DC circuit is an urgent problem to be solved. Summary of the Invention

[0003] This application provides an active clamp flyback topology system and method that can achieve AC-DC conversion of active clamp flyback without a rectifier bridge, effectively eliminating the efficiency loss caused by the rectifier bridge.

[0004] In a first aspect, embodiments of this application provide an active clamp flyback topology system. The system includes an AC input line (LN line), a first dual-controlled half-bridge switch, a second dual-controlled half-bridge switch, an isolation transformer T1, a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, and an output filter capacitor C3. The AC input line (LN line) is connected to both the first and second dual-controlled half-bridge switches. The first and second dual-controlled half-bridge switches are connected. A point output between the first and second dual-controlled half-bridge switches is connected to the primary winding of the isolation transformer T1. The first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the secondary winding of the isolation transformer T1, and the output filter capacitor C3 are all connected, wherein:

[0005] The AC input terminal LN line is used to receive AC input level signals;

[0006] When the LN line of the AC input terminal is connected to the first dual-controlled half-bridge switch and the second dual-controlled half-bridge switch, and the AC input level signal is input in both the positive and negative half cycles, the isolation transformer T1 is used to isolate and transform the AC input level signal, and the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4 are used to synchronously rectify the AC input level signal, and the output filter capacitor C3 is used to filter the output DC.

[0007] In existing technologies, AC-DC power conversion requires a rectifier bridge at the AC input to convert the AC input to DC. However, the presence of this rectifier bridge inevitably introduces losses. This application addresses this by adding two dual-controlled half-bridge switches (Q1, Q2 and Q3, Q4) synchronized with the positive and negative half-cycles of the input, enabling the topology to adapt to AC input. The specific process is as follows: During the positive and negative half-cycles, the topology receives AC input signals. The LN lines (neutral and live wires) at the AC input terminal are connected to the first and second dual-controlled half-bridge switches, both composed of MOSFETs. The AC input signal is isolated and transformed by an isolation transformer T1, then synchronously rectified by the first switch Q1, second switch Q2, third switch Q3, and fourth switch Q4. Finally, the output DC signal is filtered by the output filter capacitor C3, thus completing the active clamp flyback AC-DC conversion. This application can realize active clamp flyback AC-DC conversion without a rectifier bridge, which can effectively eliminate the efficiency loss caused by the rectifier bridge.

[0008] In one possible implementation, the AC input level signal includes a first AC level signal, a second AC level signal, a third AC level signal, a fourth AC level signal, a fifth AC level signal, and a sixth AC level signal. The first dual-controlled half-bridge switch includes a first synchronous clamping transistor Q5 and a second synchronous clamping transistor Q6. The second dual-controlled half-bridge switch includes a fifth switching transistor Q7 and a sixth switching transistor Q8. The first AC level signal corresponds to the first synchronous clamping transistor Q5, the second AC level signal corresponds to the second synchronous clamping transistor Q6, the third AC level signal corresponds to the fifth switching transistor Q7, the fourth AC level signal corresponds to the sixth switching transistor Q8, the fifth AC level signal corresponds to the first switching transistor Q1, and the sixth AC level signal corresponds to the second switching transistor Q2.

[0009] In this embodiment, the first dual-controlled half-bridge switch includes Q5 and Q6, where Q5 is the first synchronous clamping transistor and Q6 is the second synchronous clamping transistor. The second dual-controlled half-bridge switch includes the fifth switching transistor Q7 and the sixth switching transistor Q8, where Q7 is the fifth switching transistor and Q8 is the sixth switching transistor. After the AC input level signal is input to the circuit through the AC input terminal LN line, it includes a first AC level signal, a second AC level signal, a third AC level signal, a fourth AC level signal, a fifth AC level signal, and a sixth AC level signal. The first AC level signal corresponds to the AC level signal at the first synchronous clamping transistor Q5, the second AC level signal corresponds to the AC level signal at the second synchronous clamping transistor Q6, the third AC level signal corresponds to the AC level signal at the fifth switching transistor Q7, the fourth AC level signal corresponds to the AC level signal at the sixth switching transistor Q8, the fifth AC level signal corresponds to the AC level signal at the first switching transistor Q1, and the sixth AC level signal corresponds to the AC level signal at the second switching transistor Q2. This application achieves active clamp flyback AC-DC conversion by subsequently controlling one or more AC level signals in the AC input level signal and other related steps.

[0010] In another possible implementation, the point between the first dual-controlled half-bridge switch and the second dual-controlled half-bridge switch is the midpoint M between the second synchronous clamping transistor Q6 and the fifth switching transistor Q7.

[0011] In this embodiment, the point between the first dual-controlled half-bridge switch and the second dual-controlled half-bridge switch can specifically be the midpoint M between the second synchronous clamping transistor Q6 and the fifth switching transistor Q7, and the output is connected to the primary winding of the isolation transformer T1 through the midpoint M.

[0012] In another possible implementation, when the AC input level signal is input during the positive half-cycle, the second synchronous clamping transistor Q6, the sixth switch transistor Q8, and the second switch transistor Q2 are continuously turned on during the positive half-cycle, and the first synchronous clamping transistor Q5 is used to absorb the leakage inductance energy of the isolation transformer T1 during the positive half-cycle.

[0013] When the AC input level signal is input during the negative half-cycle, the first synchronous clamping transistor Q5, the fifth switching transistor Q7, and the first switching transistor Q1 are continuously turned on during the negative half-cycle, and the second synchronous clamping transistor Q6 is used to absorb the leakage inductance energy of the isolation transformer T1 during the negative half-cycle.

[0014] In this embodiment, Q5 to Q8 distinguish between switching transistors and synchronous clamping transistors, while Q1 to Q4 do not have such a function or distinction. When an AC level signal is input during the positive half-cycle, Q6 is the second synchronous clamping transistor, Q8 is the sixth switching transistor, and Q2 is the second switching transistor. The second synchronous clamping transistor Q6, the sixth switching transistor Q8, and the second switching transistor Q2 are continuously conducting during the positive half-cycle. When an AC level signal is input during the negative half-cycle, Q5 is the first synchronous clamping transistor, Q7 is the fifth switching transistor, and Q1 is the first switching transistor. The first synchronous clamping transistor Q5, the fifth switching transistor Q7, and the first switching transistor Q1 are continuously conducting during the negative half-cycle. The function of the second synchronous clamping transistor Q6 during the positive half-cycle and the first synchronous clamping transistor Q5 during the negative half-cycle is to cooperate with capacitor C1 to absorb the leakage inductance energy of isolation transformer T1.

[0015] In another possible implementation, the system further includes a digital controller and a driver, which, when the AC input level signal is input during the positive half-cycle, configure the second AC level signal, the fourth AC level signal, and the sixth AC level signal to a high-level state;

[0016] The digital controller and driver are also configured to interleave the first AC level signal and the third AC level signal into high and low level states according to the topology duty cycle requirements;

[0017] The isolation transformer T1 is used to isolate and transform the AC input level signal, the third switch Q3 is used to synchronously rectify the AC input level signal, and the output filter capacitor C3 is used to filter and output the DC of the positive half-cycle.

[0018] In this embodiment, when an AC input level signal is input during the positive half-cycle, the second AC level signal corresponding to the second synchronous clamping transistor Q6, the fourth AC level signal corresponding to the sixth switch transistor Q8, and the sixth AC level signal corresponding to the second switch transistor Q2 are configured to a high level state through a digital controller and a driver. At this time, the second synchronous clamping transistor Q6, the sixth switch transistor Q8, and the second switch transistor Q2 are continuously turned on during the positive half-cycle. Then, according to the topology duty cycle requirements (such as setting the duty cycle to 40%), the first AC level signal and the third AC level signal are controlled to alternate between high and low levels. At this time, the first synchronous clamping transistor Q5 and the fifth switch transistor Q7 are complementaryly turned on. The output at the midpoint M is connected to the isolation transformer T1 for isolation transformation, and then high-frequency synchronous rectification is performed through the secondary third switch transistor Q3. Finally, the DC output during the positive half-cycle is filtered by the output filter capacitor C3, thus completing the AC-DC conversion during the positive half-cycle.

[0019] In yet another possible implementation, when the AC input level signal is input during the negative half-cycle, the digital controller and driver are configured to set the first AC level signal, the third AC level signal and the fifth AC level signal to a high level state.

[0020] The digital controller and driver are also configured to interleave the first AC level signal and the third AC level signal into high and low level states according to the topology duty cycle requirements;

[0021] The isolation transformer T1 is used to isolate and transform the AC input level signal, the fourth switch Q4 is used to synchronously rectify the AC input level signal, and the output filter capacitor C3 is used to filter and output the negative half-cycle DC.

[0022] In this embodiment, when an AC input level signal is input during the negative half-cycle, the digital controller and driver configure the first AC level signal corresponding to the first synchronous clamp transistor Q5, the third AC level signal corresponding to the fifth switch transistor Q7, and the fifth AC level signal corresponding to the first switch transistor Q1 to a high-level state. At this time, the first synchronous clamp transistor Q5, the fifth switch transistor Q7, and the first switch transistor Q1 are continuously conducting during the negative half-cycle. Then, according to the topology duty cycle requirements (e.g., the duty cycle is preset to 40%), the first and third AC level signals are controlled to alternate between high and low levels. During this time, the first synchronous clamp transistor Q5 and the fifth switch transistor Q7 are complementary in conduction. The output at the midpoint M is connected to the isolation transformer T1 for isolation transformation, and then undergoes high-frequency synchronous rectification through the secondary fourth switch transistor Q4. Finally, the output DC signal during the negative half-cycle is filtered by the output filter capacitor C3, thus completing the negative half-cycle AC-DC conversion. This application integrates both positive and negative half-cycle processes to process the AC input and finally outputs DC, completing the AC-DC conversion.

[0023] In another possible implementation, when the second synchronous clamping transistor Q6, the sixth switch transistor Q8, and the second switch transistor Q2 are continuously turned on during the positive half-cycle, or when the first synchronous clamping transistor Q5, the fifth switch transistor Q7, and the first switch transistor Q1 are continuously turned on during the negative half-cycle, the primary voltage waveform flowing through the isolation transformer T1 and the secondary voltage waveform flowing through the third switch transistor Q3 and the fourth switch transistor Q4 are both trapezoidal waves.

[0024] In this embodiment, since the switching power supply output voltage U is at the beginning of operation, i.e., when the energy storage filter capacitor begins to charge, the switching power supply output voltage is... o It changes, but the output voltage U oThe circuit quickly transitions from one initial value to another stable value, and then from another initial value (the previous stable value) to the next stable value. Therefore, when the second synchronous clamping transistor Q6, the sixth switching transistor Q8, and the second switching transistor Q2 are continuously conducting during the positive half-cycle, the primary voltage waveform flowing through the isolation transformer T1 and the secondary voltage waveform flowing through the third switching transistor Q3 are both trapezoidal waves. Similarly, when the first synchronous clamping transistor Q5, the fifth switching transistor Q7, and the first switching transistor Q1 are continuously conducting during the negative half-cycle, the primary voltage waveform flowing through the isolation transformer T1 and the secondary voltage waveform flowing through the fourth switching transistor Q4 are both trapezoidal waves.

[0025] Secondly, embodiments of this application provide an AC input conversion method, which is applied to the system described in the first aspect or any possible implementation of the first aspect.

[0026] Thirdly, embodiments of this application provide a computer-readable storage medium storing instructions that, when executed on at least one processor, implement the method described in the second aspect above.

[0027] Fourthly, this application provides a computer program product comprising computer instructions that, when executed on at least one processor, implement the method described in the second aspect. The computer program product can be a software installation package, which can be downloaded and executed on a computing device when the aforementioned method is required.

[0028] The beneficial effects of the technical methods provided in the second to fourth aspects of this application can be referred to the beneficial effects of the technical solution in the first aspect, and will not be repeated here. Attached Figure Description

[0029] The accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0030] Figure 1 This is a schematic diagram of a topology including a rectifier bridge provided in an embodiment of this application;

[0031] Figure 2 This is a schematic diagram of the architecture of an active clamp flyback topology system provided in an embodiment of this application;

[0032] Figure 3 This is a flowchart illustrating an AC input conversion method provided in an embodiment of this application;

[0033] Figure 4 This is a schematic diagram of the voltage output waveform of an input AC level signal during the positive and negative half-cycles provided in an embodiment of this application. Detailed Implementation

[0034] The embodiments of this application are described below with reference to the accompanying drawings.

[0035] To facilitate understanding, the technical terms involved in the embodiments of this application will be briefly introduced first.

[0036] 1. Active clamp flyback circuit

[0037] Active clamping is a circuit connection method. Single-ended forward topologies using active clamping are currently popular and can also be used in flyback circuits. Active clamping transformer reset technology has many advantages over traditional single-ended reset technology, such as lower stress on the main switch MOS, reduced EMI electromagnetic interference, and a duty cycle greater than 50%. The difference between flyback and forward circuits is that the flyback circuit transfers energy to the load when the switch is turned off (flyback), and the transformer flux changes only in one direction (single-ended). There is no magnetic reset circuit because the process of transferring energy from the secondary side to the load is a demagnetizing process, so no additional demagnetizing winding is needed. Flyback power supplies rely on the energy stored in the inductor (transformer) to release energy to the output capacitor through the secondary side. This means the main oscillator power transistor and the output rectifier transistor do not work synchronously. Without a feedback circuit to strictly control the duty cycle of the preceding stage, and with the output unloaded, the energy in the inductor has nowhere to be released, causing a significant increase in the voltage between the secondary and primary coils (theoretically, the voltage is infinitely high), leading to breakdown (overheating) and damage to the main oscillator power transistor. Under the same maximum magnetic flux density, the range of flux density variation ΔB during continuous operation is smaller than that in discontinuous operation. In a flyback circuit, ΔB is proportional to the voltage across each turn of the primary winding multiplied by the on-state time ton. Given the same input voltage and ton, a larger ΔB means the transformer requires fewer turns or a smaller core. From this perspective, the utilization rate of the transformer core is higher and more efficient when the flyback circuit operates in discontinuous current mode. Therefore, flyback circuits are typically designed to operate in discontinuous current mode. The flyback circuit has the simplest structure and fewest components, resulting in lower cost and wide applicability to various low-power switching power supplies ranging from a few watts to tens of watts.

[0038] Because the flyback circuit operates in discontinuous current mode, the transformer core utilization is high and reasonable, and the flyback circuit has the simplest structure, few components, and low cost. Therefore, the embodiments of this application are used in scenarios with active clamp flyback topologies. Please refer to... Figure 1 , Figure 1 This is a schematic diagram of a topology including a rectifier bridge provided in an embodiment of this application. Figure 1In this circuit, a rectifier bridge is needed at the input to convert the input AC to DC, thereby achieving AC-DC power conversion. The circuit operation is as follows: After receiving the input AC level signal through the LN line of the AC input terminal, the AC level signal is rectified by the rectifier bridge BD1, filtered by the output filter capacitor CE1, and output as DC. Then, it is connected to a high-frequency half-bridge composed of MOSFETs Q1 and Q2. By controlling the high and low levels of points A and B to alternately turn on Q1 and Q2, Q2 is a switching transistor and Q1 is a synchronous clamping transistor. The midpoint of the half-bridge is connected to the isolation transformer T1 for isolation transformation, and then rectified by the high-frequency synchronous switching transistor Q3. The output is filtered by the output filter capacitor C3 to output DC, completing the AC-DC conversion.

[0039] Since the presence of an input rectifier bridge inevitably leads to power loss, resulting in reduced efficiency, the embodiments of this application will subsequently describe a scenario where AC input is converted based on an active clamp flyback topology system that does not require a rectifier bridge.

[0040] Please see Figure 2 , Figure 2 This is a schematic diagram of the architecture of an active clamp flyback topology system provided in an embodiment of this application. The active clamp flyback topology system includes an AC input LN line 201, a first dual-controlled half-bridge switch 202, a second dual-controlled half-bridge switch 203, an isolation transformer T1, a digital controller and driver 204, a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, and an output filter capacitor C3. The first dual-controlled half-bridge switch 202 includes a first synchronous clamping transistor Q5 and a second synchronous clamping transistor Q6, and the second dual-controlled half-bridge switch 203 includes a fifth switch Q7 and a sixth switch Q8. Among them, the AC input terminal LN line 201 is connected to the first double-controlled half-bridge switch 202 and the second double-controlled half-bridge switch 203. The first double-controlled half-bridge switch 202 is connected to the second double-controlled half-bridge switch 203. The midpoint M output of the second synchronous clamping transistor Q6 and the fifth switching transistor Q7 is connected to the primary winding of the isolation transformer T1. The first switching transistor Q1, the second switching transistor Q2, the third switching transistor Q3, the fourth switching transistor Q4, the secondary winding of the isolation transformer T1, and the output filter capacitor C3 are all connected.

[0041] The AC input terminal LN line 201 is used to receive AC input level signals, where N represents the neutral wire and L represents the live wire. The AC input level signals include a first AC level signal (point A), a second AC level signal (point B), a third AC level signal (point C), a fourth AC level signal (point D), a fifth AC level signal (point E), and a sixth AC level signal (point F). The first AC level signal corresponds to the AC level signal at the first synchronous clamping transistor Q5, the second AC level signal corresponds to the AC level signal at the second synchronous clamping transistor Q6, the third AC level signal corresponds to the AC level signal at the fifth switching transistor Q7, the fourth AC level signal corresponds to the AC level signal at the sixth switching transistor Q8, the fifth AC level signal corresponds to the AC level signal at the first switching transistor Q1, and the sixth AC level signal corresponds to the AC level signal at the second switching transistor Q2. In addition, the digital controller and driver 204 are connected to points A to H in the circuit respectively.

[0042] Since the AC input conversion has two operating cycles, positive and negative, during the positive half-cycle, the second synchronous clamp transistor Q6, the sixth switch transistor Q8, and the second switch transistor Q2 are continuously turned on during the positive half-cycle. The digital controller and driver 204 configures the second, fourth, and sixth AC level signals to a high-level state. The digital controller and driver 204 are also used to interleave the first and third AC level signals into high and low-level states according to the topology duty cycle requirements. Correspondingly, during the negative half-cycle, the first synchronous clamp transistor Q5, the fifth switch transistor Q7, and the first switch transistor Q1 are continuously turned on during the negative half-cycle. The digital controller and driver 204 configures the first, third, and fifth AC level signals to a high-level state. The digital controller and driver 204 are also used to interleave the first and third AC level signals into high and low-level states according to the topology duty cycle requirements.

[0043] With the LN line 201 of the AC input terminal connected to the first dual-controlled half-bridge switch 202 and the second dual-controlled half-bridge switch 203, and AC input level signals input during both the positive and negative half cycles, the isolation transformer T1 is used to isolate and transform the AC input level signals, and the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 are used to synchronously rectify the AC input level signals, and the output filter capacitor C3 is used to filter the output DC, thus completing the AC-DC conversion.

[0044] The methods of the embodiments of this application will be described in detail below.

[0045] Please see Figure 3 , Figure 3This is a flowchart illustrating an AC input conversion method provided in an embodiment of this application. Optionally, this method can be applied... Figure 2 The system.

[0046] like Figure 3 The AC input conversion method includes at least steps S301 to S302.

[0047] Step S301: The active clamp flyback topology system receives the AC input level signal through the LN line of the AC input terminal.

[0048] It should be noted that, by Figure 2 It can be seen that the active clamp flyback topology system includes an AC input LN line (N represents the neutral line and L represents the live line), a first dual-controlled half-bridge switch, a second dual-controlled half-bridge switch, an isolation transformer T1, a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, and an output filter capacitor C3. The first dual-controlled half-bridge switch includes a first synchronous clamping transistor Q5 and a second synchronous clamping transistor Q6, and the second dual-controlled half-bridge switch includes a fifth switch Q7 and a sixth switch Q8. When the switching power supply starts working (e.g., with 220V AC input), the active clamp flyback topology system can receive AC level signals through the LN line of the AC input terminal. At this time, the AC input level signals include a first AC level signal (point A), a second AC level signal (point B), a third AC level signal (point C), a fourth AC level signal (point D), a fifth AC level signal (point E), and a sixth AC level signal (point F). Correspondingly, the AC level signal at point A corresponds to the first synchronous clamp transistor Q5, the AC level signal at point B corresponds to the second synchronous clamp transistor Q6, the AC level signal at point C corresponds to the fifth switching transistor Q7, the AC level signal at point D corresponds to the sixth switching transistor Q8, the AC level signal at point E corresponds to the first switching transistor Q1, and the AC level signal at point F corresponds to the second switching transistor Q2. Subsequently, one or more of the above multiple AC level signals can be interleaved with high and low levels and related steps can be performed to realize AC-DC conversion.

[0049] Step S302: With the LN line of the AC input terminal connected to the first dual-controlled half-bridge switch and the second dual-controlled half-bridge switch, and AC input level signals input during both the positive and negative half cycles, the active clamp flyback topology system isolates and transforms the AC input level signals through the isolation transformer T1, synchronously rectifies the AC input level signals through the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4, and outputs DC through the output filter capacitor C3.

[0050] It should be noted that since AC-DC conversion of AC input has two working processes, positive half-cycle and negative half-cycle, the embodiments of this application are divided into two cases: AC input level signal input during the positive half-cycle and AC input level signal input during the negative half-cycle to illustrate AC-DC conversion. The above two cases are described in detail below.

[0051] Specifically, scenario one, Figure 4 This is a schematic diagram of the voltage output waveform of an input AC level signal during the positive and negative half-cycles, as provided in an embodiment of this application. Figure 4 As shown, with the N-line as the reference point, since the energy transfer of a flyback switching power supply must be achieved through an isolation transformer, the switches (MOSFETs or rectifier diodes) on both the primary and secondary sides of the isolation transformer operate in a discontinuous current state. Under the same output power conditions, the peak and RMS current flowing through the switches of a flyback switching power supply are greater than those of forward, bridge, and push-pull switching power supplies. Therefore, to obtain lower output voltage spikes, typical flyback switching power supplies operate in a discontinuous inductor current (transformer energy storage) state. During the positive half-cycle of the AC input signal, this active clamp flyback topology system can configure the second AC level signal (point B) corresponding to the second synchronous clamp transistor Q6, the fourth AC level signal (point D) corresponding to the sixth switch transistor Q8, and the sixth AC level signal (point F) corresponding to the second switch transistor Q2 to a high level state via a digital controller and driver. At this time, the second synchronous clamp transistor Q6, the sixth switch transistor Q8, and the second switch transistor Q2 are continuously conducting during the positive half-cycle. During the positive half-cycle, the first synchronous clamp transistor Q5 is used to absorb the leakage inductance energy of the isolation transformer T1. Then, the second, fourth, and sixth AC level signals are configured to a high level state via the digital controller and driver; and the digital controller and driver... The driver interleaved the first AC level signal (point A) and the third AC level signal (point C) into high and low levels according to the topology duty cycle requirements (the duty cycle value is not limited in this embodiment; the topology duty cycle requirement can be 40%). Then, the AC input level signal is isolated and transformed by isolation transformer T1, and the AC input level signal is synchronously rectified at high frequency by the third switch Q3. Synchronous rectification prevents instability during converter operation and ensures continuous minimum inductance requirements, allowing current to flow in both directions even without a load (because MOSFETs can conduct in both directions). Finally, the output DC of the positive half-cycle is filtered by the output filter capacitor C3, thus completing the positive half-cycle AC-DC conversion. When the switching power supply just starts operating, i.e., when the energy storage filter capacitor begins charging, the switching power supply output voltage U... o It changes, but the output voltage U oIt quickly transitions from one initial value to another stable value, and then from another initial value (the previous stable value) to the next stable value, and so on. Figure 4 As shown in the waveform diagram of the output voltage during the positive half-cycle, when the second synchronous clamping transistor Q6, the sixth switching transistor Q8, and the second switching transistor Q2 are continuously conducting during the positive half-cycle, the primary voltage waveform flowing through the isolation transformer T1 and the secondary voltage waveform flowing through the third switching transistor Q3 are both trapezoidal waves.

[0052] Scenario 2, still as before Figure 4 As shown, with the N line as the reference point, under the condition of input AC input level signal during the negative half-cycle, this active clamp flyback topology system can configure the first AC level signal (point A) corresponding to the first synchronous clamp transistor Q5, the third AC level signal (point C) corresponding to the fifth switch transistor Q7, and the fifth AC level signal (point E) corresponding to the first switch transistor Q1 to a high level state through the digital controller and driver. At this time, the first synchronous clamp transistor Q5, the fifth switch transistor Q7, and the first switch transistor Q1 are continuously turned on during the negative half-cycle. During the negative half-cycle, the second synchronous clamp transistor Q6 is used to absorb the leakage inductance energy of the isolation transformer T1. Then, the first AC level signal is converted to AC level by the digital controller and driver. The first, third, and fifth AC level signals are configured to a high level. The digital controller and driver interleave the first and third AC level signals into high and low levels according to the topology duty cycle requirements. Then, the AC input level signal is isolated and transformed by isolation transformer T1, and the AC input level signal is synchronously rectified at high frequency by the fourth switch Q4. Finally, the output DC of the negative half-cycle is filtered by the output filter capacitor C3, thus completing the negative half-cycle AC-DC conversion. Since the switching power supply output voltage U is initially high when the energy storage filter capacitor begins charging, the switching power supply output voltage is... o It changes, but the output voltage U o It quickly transitions from one initial value to another stable value, and then from another initial value (the previous stable value) to the next stable value, and so on. Figure 4 As shown in the waveform diagram of the output voltage during the negative half-cycle, when the first synchronous clamping transistor Q5, the fifth switching transistor Q7, and the first switching transistor Q1 are continuously conducting during the negative half-cycle, the primary voltage waveform flowing through the isolation transformer T1 and the secondary voltage waveform flowing through the fourth switching transistor Q4 are both trapezoidal waves. This application processes the AC input voltage by combining the positive and negative half-cycles, and finally outputs a DC voltage, thus achieving AC-DC conversion without the need for an input rectifier bridge.

[0053] In existing technologies, AC-DC power conversion requires a rectifier bridge at the AC input to convert the AC input to DC. However, the presence of this rectifier bridge inevitably introduces losses. This application addresses this by adding two dual-controlled half-bridge switches (Q1, Q2 and Q3, Q4) synchronized with the positive and negative half-cycles of the input, enabling the topology to adapt to AC input. The specific process is as follows: During the positive and negative half-cycles, the topology receives AC input signals. The LN lines (neutral and live wires) at the AC input terminal are connected to the first and second dual-controlled half-bridge switches, both composed of MOSFETs. The AC input signal is isolated and transformed by an isolation transformer T1, then synchronously rectified by the first switch Q1, second switch Q2, third switch Q3, and fourth switch Q4. Finally, the output DC signal is filtered by the output filter capacitor C3, thus completing the active clamp flyback AC-DC conversion. This application can realize active clamp flyback AC-DC conversion without a rectifier bridge, which can effectively eliminate the efficiency loss caused by the rectifier bridge.

[0054] This application also provides an electronic device, including the aforementioned active clamp flyback topology system, for example... Figure 2 The system described above.

[0055] This application also provides a computer-readable storage medium storing instructions that, when executed on at least one processor, implement the aforementioned AC input conversion method, for example... Figure 3 The method described.

[0056] This application also provides a computer program product comprising computer instructions that, when executed by a computing device, implement the aforementioned AC input conversion method, for example... Figure 3 The method described.

[0057] In this application, the terms "for example" or "for instance" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "for example" or "for instance" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the use of terms such as "for example" or "for instance" is intended to present the relevant concepts in a specific manner.

[0058] In this application, "at least one" in the embodiments refers to one or more items, and "more than one" refers to two or more items. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can represent: a, b, c, (a and b), (a and c), (b and c), or (a and b and c), where a, b, and c can be single or multiple. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0059] Furthermore, unless otherwise stated, the use of ordinal numbers such as "first" and "second" in the embodiments of this application is for distinguishing multiple objects and is not for limiting the order, sequence, priority, or importance of multiple objects. For example, "first device" and "second device" are only for ease of description and do not indicate that the first device and the second device are different in structure, importance, etc. In some embodiments, the first device and the second device may also be the same device.

[0060] In the above embodiments, the term "when..." can be interpreted, depending on the context, as meaning "if...", "after...", "in response to determining...", or "in response to detecting...". The above descriptions are merely optional embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the concept and principles of this application should be included within the protection scope of this application.

[0061] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0062] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An active clamp flyback topology system, characterized in that, The system includes an AC input line (LN), a first dual-controlled half-bridge switch, a second dual-controlled half-bridge switch, an isolation transformer T1, a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, and an output filter capacitor C3. The AC input line (LN) is connected to the first dual-controlled half-bridge switch and the second dual-controlled half-bridge switch. The first dual-controlled half-bridge switch is connected to the second dual-controlled half-bridge switch. The point output between the first and second dual-controlled half-bridge switches is connected to the primary winding of the isolation transformer T1. The first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the secondary winding of the isolation transformer T1, and the output filter capacitor C3 are all connected. The AC input terminal LN line is used to receive AC input level signals. The AC input level signals include a first AC level signal, a second AC level signal, a third AC level signal, a fourth AC level signal, a fifth AC level signal, and a sixth AC level signal. The first dual-controlled half-bridge switch includes a first synchronous clamping transistor Q5 and a second synchronous clamping transistor Q6. The second dual-controlled half-bridge switch includes a fifth switching transistor Q7 and a sixth switching transistor Q8. The first AC level signal corresponds to the first synchronous clamping transistor Q5, the second AC level signal corresponds to the second synchronous clamping transistor Q6, the third AC level signal corresponds to the fifth switching transistor Q7, the fourth AC level signal corresponds to the sixth switching transistor Q8, the fifth AC level signal corresponds to the first switching transistor Q1, and the sixth AC level signal corresponds to the second switching transistor Q2. When the AC input terminal LN line is connected to the first dual-controlled half-bridge switch and the second dual-controlled half-bridge switch, and the AC input level signal is input in both the positive and negative half-cycles, the isolation transformer T1 is used to isolate and transform the AC input level signal, and the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 are used to synchronously rectify the AC input level signal, and the output filter capacitor C3 is used to filter the output DC. When the AC input level signal is input in the positive half-cycle, the second synchronous clamping transistor Q6, the sixth switch Q8, and the second switch Q2 are continuously turned on in the positive half-cycle, and the first synchronous clamping transistor Q5 is used to absorb the leakage inductance energy of the isolation transformer T1 in the positive half-cycle. When the AC input level signal is input during the negative half-cycle, the first synchronous clamping transistor Q5, the fifth switching transistor Q7, and the first switching transistor Q1 are continuously turned on during the negative half-cycle, and the second synchronous clamping transistor Q6 is used to absorb the leakage inductance energy of the isolation transformer T1 during the negative half-cycle.

2. The system according to claim 1, characterized in that: The point between the first dual-controlled half-bridge switch and the second dual-controlled half-bridge switch is the midpoint M between the second synchronous clamping transistor Q6 and the fifth switching transistor Q7.

3. The system according to claim 1, characterized in that: The system also includes a digital controller and a driver, which are used to configure the second AC level signal, the fourth AC level signal and the sixth AC level signal to a high level state when the AC input level signal is input during the positive half-cycle. The digital controller and driver are also configured to interleave the first AC level signal and the third AC level signal into high and low level states according to the topology duty cycle requirements; The isolation transformer T1 is used to isolate and transform the AC input level signal, the third switch Q3 is used to synchronously rectify the AC input level signal, and the output filter capacitor C3 is used to filter and output the DC of the positive half-cycle.

4. The system according to claim 3, characterized in that: When the AC input level signal is input during the negative half-cycle, the digital controller and driver are configured to set the first AC level signal, the third AC level signal and the fifth AC level signal to a high level state; The digital controller and driver are also configured to interleave the first AC level signal and the third AC level signal into high and low level states according to the topology duty cycle requirements; The isolation transformer T1 is used to isolate and transform the AC input level signal, the fourth switch Q4 is used to synchronously rectify the AC input level signal, and the output filter capacitor C3 is used to filter and output the negative half-cycle DC.

5. The system according to claim 1, characterized in that: When the second synchronizing clamp transistor Q6, the sixth switching transistor Q8, and the second switching transistor Q2 are continuously conducting during the positive half-cycle, or when the first synchronizing clamp transistor Q5, the fifth switching transistor Q7, and the first switching transistor Q1 are continuously conducting during the negative half-cycle, the primary voltage waveform flowing through the isolation transformer T1 and the secondary voltage waveform flowing through the third switching transistor Q3 and the fourth switching transistor Q4 are both trapezoidal waves.

6. A method for converting AC input, characterized in that, An active clamp flyback topology system is applied, comprising an AC input line (LN), a first dual-controlled half-bridge switch, a second dual-controlled half-bridge switch, an isolation transformer T1, a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, and an output filter capacitor C3. The AC input line (LN) is connected to the first dual-controlled half-bridge switch and the second dual-controlled half-bridge switch. The first dual-controlled half-bridge switch is connected to the second dual-controlled half-bridge switch. The point output between the first and second dual-controlled half-bridge switches is connected to the primary winding of the isolation transformer T1. The first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the secondary winding of the isolation transformer T1, and the output filter capacitor C3 are all connected. The method includes: The AC input level signal is received through the LN line of the AC input terminal. The AC input level signal includes a first AC level signal, a second AC level signal, a third AC level signal, a fourth AC level signal, a fifth AC level signal, and a sixth AC level signal. The first dual-controlled half-bridge switch includes a first synchronous clamping transistor Q5 and a second synchronous clamping transistor Q6. The second dual-controlled half-bridge switch includes a fifth switching transistor Q7 and a sixth switching transistor Q8. The first AC level signal corresponds to the first synchronous clamping transistor Q5, the second AC level signal corresponds to the second synchronous clamping transistor Q6, the third AC level signal corresponds to the fifth switching transistor Q7, the fourth AC level signal corresponds to the sixth switching transistor Q8, the fifth AC level signal corresponds to the first switching transistor Q1, and the sixth AC level signal corresponds to the second switching transistor Q2. When the AC input terminal LN line is connected to the first dual-controlled half-bridge switch and the second dual-controlled half-bridge switch, and the AC input level signal is input in both the positive and negative half cycles, the AC input level signal is isolated and transformed by the isolation transformer T1, and the AC input level signal is synchronously rectified by the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4, and the DC output is filtered by the output filter capacitor C3. When the AC input level signal is input during the positive half-cycle, the second synchronous clamping transistor Q6, the sixth switching transistor Q8, and the second switching transistor Q2 are continuously turned on during the positive half-cycle, and the leakage inductance energy of the isolation transformer T1 is absorbed through the first synchronous clamping transistor Q5 during the positive half-cycle. When the AC input level signal is input during the negative half-cycle, the first synchronous clamping transistor Q5, the fifth switching transistor Q7, and the first switching transistor Q1 are continuously turned on during the negative half-cycle, and the leakage inductance energy of the isolation transformer T1 is absorbed through the second synchronous clamping transistor Q6 during the negative half-cycle.

7. An electronic device, characterized in that, The electronic device includes the system as described in any one of claims 1-5.

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