An epitaxial wafer and its preparation method

Abstract

This invention provides an epitaxial wafer and its fabrication method. The epitaxial wafer includes a growth substrate, a mask template, and multiple nanopillars. The mask template is disposed on one side of the growth substrate and includes multiple growth windows, a first mask structure, and a second mask structure. The growth windows penetrate the mask template to the growth substrate. Each nanopillar is disposed within a corresponding growth window and includes a first sub-nanopillar in contact with the growth substrate. The first mask structure surrounds the first sub-nanopillar, and the second mask structure is disposed on the growth substrate and in contact with the first mask structure. The top of the first mask structure is higher than the top of the second mask structure. By adopting this method, the H-passivation effect during the nanopillar growth process can be effectively suppressed, promoting the longitudinal growth of the nanopillars and obtaining nanopillars with a flat c-plane surface.

Description

Technical Field

[0001] This invention belongs to the field of optoelectronic device manufacturing, specifically relating to an epitaxial wafer and its preparation method. Background Technology

[0002] GaN nanopillars have wide applications in optoelectronic devices due to their excellent properties. Their fabrication methods include metal-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE). When growing GaN nanopillars along the c-axis using the MOCVD method, due to the difference in growth rates of each crystal plane, a {10-11} semi-polar plane is usually formed at the edge of the nanopillar. The N-termining atoms on the surface of the semi-polar plane combine with H atoms to form a stable structure, which hinders the continued growth of this plane (i.e., the "H passivation effect"). This results in the formation of a pyramidal tip morphology in the GaN nanopillar, which limits the height of the nanopillar and makes it difficult to grow planar structures on the surface of the nanopillar, thus adversely affecting the fabrication of device structures. Summary of the Invention

[0003] To address the technical problems existing in the prior art, the present invention provides an epitaxial wafer and its preparation method. By setting a first mask structure at the outer edge of the nanopillar growth window, the H passivation effect during the nanopillar growth process can be effectively suppressed, and the longitudinal growth of the nanopillar can be promoted to obtain a nanopillar with a flat c-plane surface, which can be used for subsequent growth of light-emitting device structures with axial quantum well structures.

[0004] To achieve the above-mentioned technical effects, the present invention adopts the following technical solution:

[0005] One objective of this invention is to provide an epitaxial wafer, the epitaxial wafer comprising:

[0006] Growth substrate;

[0007] A mask template is disposed on one side of the growth substrate; the mask template includes multiple growth windows, a first mask structure and a second mask structure, and the growth windows penetrate through the mask template to the growth substrate;

[0008] Multiple nanopillars, each nanopillar disposed within a corresponding growth window, each nanopillar including a first sub-nanopillar in contact with the growth substrate;

[0009] The first mask structure surrounds the first sub-nanopillar, the second mask structure is disposed on the growth substrate and in contact with the first mask structure, and the top of the first mask structure is higher than the top of the second mask structure.

[0010] As a preferred technical solution of the present invention, the second mask structure surrounds the first mask structure, and the first mask structure includes a first substructure and a second substructure stacked together, wherein the lower surface of the first substructure is flush with the upper surface of the second mask structure.

[0011] As a preferred embodiment of the present invention, the second mask structure is disposed on the side of the first mask structure near the growth substrate. The second mask structure includes a third substructure and a fourth substructure. The third substructure is disposed on the side of the first mask structure near the growth substrate, and the fourth substructure is disposed on the growth substrate and contacts the side of the third substructure away from the growth window.

[0012] As a preferred embodiment of the present invention, the nanopillar further includes a second sub-nanopillar, which is disposed on the side of the first sub-nanopillar away from the growth substrate.

[0013] As a preferred embodiment of the present invention, the upper surface of the first sub-nanopillar is flush with the upper surface of the first mask structure; the radial dimension of the second sub-nanopillar is greater than or equal to the radial dimension of the first sub-nanopillar.

[0014] As a preferred embodiment of the present invention, the thickness of the mask template is 50–500 nm, and / or

[0015] The thickness of the second mask structure is 10–100 nm, and / or

[0016] The diameter of the growth window is 200–1000 nm; and / or

[0017] The growth window is circular or hexagonal in shape; and / or

[0018] The growth substrate is a substrate, or the growth substrate includes a substrate and a nitride layer stacked together, and the mask template is disposed on the side of the nitride layer away from the substrate.

[0019] The thickness of the mask template can be 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, or 500nm, etc., and the thickness of the second mask structure can be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm, etc., and the diameter of the growth window can be 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, or 1000nm, etc., but is not limited to the listed values. Other unlisted values ​​within the above ranges are also applicable.

[0020] A second objective of this invention is to provide a method for preparing an epitaxial wafer as provided in one of the objectives, the method comprising:

[0021] The first mask layer is grown on one side of the growth substrate;

[0022] The first mask layer is etched to form the growth window, the first mask structure, and the second mask structure;

[0023] The corresponding nanopillars are grown within each growth window.

[0024] As a preferred embodiment of the present invention, the etching of the first mask layer includes:

[0025] The first mask layer is etched to obtain a second mask layer having the growth window;

[0026] The second mask layer is etched to obtain the first mask structure and the second mask structure.

[0027] As a preferred embodiment of the present invention, the etching of the first mask layer includes:

[0028] Under conditions of SF6 flow rate of 20-60 sccm, O2 flow rate of 10-40 sccm, RF power of 50-200 W, and pressure of 5-10 Pa, a portion of the first mask layer is etched until the growth substrate is exposed.

[0029] Among them, the SF6 flow rate can be 20 sccm, 25 sccm, 30 sccm, 35 sccm, 40 sccm, 45 sccm, 50 sccm, 55 sccm or 60 sccm, etc.; the O2 flow rate can be 10 sccm, 15 sccm, 20 sccm, 25 sccm, 30 sccm, 35 sccm or 40 sccm, etc.; the RF power can be 50W, 60W, 80W, 100W, 120W, 150W, 180W or 200W, etc.; and the pressure can be 5Pa, 6Pa, 7Pa, 8Pa, 9Pa or 10Pa, etc., but is not limited to the listed values. Other unlisted values ​​within the above ranges are also applicable.

[0030] As a preferred embodiment of the present invention, growing the first mask layer on one side of the growth substrate includes:

[0031] Under conditions of pressure of 200–600 mbar, radio frequency power of 30–70 W, SiH4 flow rate of 50–250 sccm, and NH3 flow rate of 10–50 sccm, a first mask layer with a thickness of 50–500 nm is grown on one side of the growth substrate.

[0032] The pressure can be 200 mbar, 250 mbar, 300 mbar, 350 mbar, 400 mbar, 450 mbar, 500 mbar, 550 mbar, or 600 mbar, etc.; the RF power can be 30 W, 35 W, 40 W, 45 W, 50 W, 55 W, 60 W, 65 W, or 70 W, etc.; the SiH4 flow rate can be 50 sccm, 100 sccm, 150 sccm, 200 sccm, or 250 sccm, etc.; the NH3 flow rate can be 10 sccm, 20 sccm, 30 sccm, 40 sccm, or 50 sccm, etc.; and the growth thickness can be 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm, etc., but is not limited to the listed values. Other unlisted values ​​within the above ranges are also applicable.

[0033] Compared with the prior art, the present invention has at least the following beneficial effects:

[0034] (1) The present invention provides an epitaxial wafer with a first mask structure set on the outer edge of the nanopillar growth window, which can effectively suppress the H passivation effect during the nanopillar growth process, promote the longitudinal growth of the nanopillar, and obtain GaN nanopillars with a flat c-plane surface, which can be used for subsequent growth of light-emitting device structures with axial quantum well structures.

[0035] (2) The present invention provides an epitaxial wafer preparation method, which forms a first mask structure on the outer edge of the nanopillar growth window by etching the first mask layer. The process is simple and easy to industrialize. Attached Figure Description

[0036] Figure 1 This is a schematic diagram illustrating the passivation process caused by the combination of H atoms with N atoms in the {10-11} plane during the growth of GaN nanopillars using conventional methods.

[0037] Figure 2 This is a schematic diagram of the structure of the epitaxial wafer provided by the present invention;

[0038] Figure 3 for Figure 2 Another schematic diagram of the nanopillar structure shown in the embodiment;

[0039] Figure 4 for Figure 2The diagram shown in the embodiment illustrates the structure of the mask template.

[0040] Figure 5 for Figure 2 Another structural schematic diagram of the mask template in the illustrated embodiment;

[0041] Figure 6 This is another structural schematic diagram of the epitaxial wafer provided by the present invention;

[0042] Figure 7 This is a schematic diagram of the structure of the epitaxial wafer (before the growth of nanopillars) provided by the present invention;

[0043] Figures 8A-8D A schematic flowchart illustrating the method for preparing an epitaxial wafer provided by the present invention;

[0044] Figure 9 A schematic diagram illustrating the process of suppressing the H passivation effect in the GaN nanopillar growth method provided by this invention;

[0045] In the figure: 1-growth substrate, 11-substrate, 12-nitride layer; 3-mask template, 31-first mask structure, 311-first substructure, 312-second substructure, 32-second mask structure, 321-third substructure, 322-fourth substructure; 4-growth window; 5-nanopillar, 51-first sub-nanopillar, 52-second sub-nanopillar; 6-H atom; 7-quantum well structure. Detailed Implementation

[0046] The present invention will now be described in further detail. However, the examples described below are merely simplified examples of the present invention and do not represent or limit the scope of protection of the present invention. The scope of protection of the present invention is determined by the claims.

[0047] When growing nanopillars using conventional methods, during the growth process on the mask template, H atoms that fall onto the mask template surface migrate along the mask layer surface towards the growth window, reaching the sidewalls of the nanopillars. There, they combine with the terminal N atoms on the {10-11} facets of the nanopillars to form stable structures, such as... Figure 1 As shown, the growth rate of the {10-11} facet is significantly reduced, resulting in a growth rate of the {0001} facet being significantly higher than that of the {10-11} facet. This causes the continuing growth of the nanopillars to form a hexagonal pyramid surface morphology. After this structure is formed, it becomes difficult for the nanopillars to continue growing upwards, limiting the height of the nanopillars. At the same time, it is difficult to grow on the c-facet when growing quantum wells and other structures.

[0048] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of the epitaxial wafer provided by the present invention. The epitaxial wafer includes: a growth substrate 1, a mask template 3, and multiple nanopillars 5.

[0049] The mask template 3 is disposed on one side of the growth substrate 1; the mask template 3 includes multiple growth windows, the growth windows penetrate through the mask template 3 to the growth substrate 1, and the mask template 3 includes a first mask structure and a second mask structure.

[0050] Each nanopillar 5 is disposed within a corresponding growth window, and the nanopillar 5 includes a first sub-nanopillar 51 that contacts the growth substrate 1. A first mask structure surrounds the first sub-nanopillar 51, and a second mask structure is disposed on the growth substrate 1 and in contact with the first mask structure, with the top of the first mask structure being higher than the top of the second mask structure.

[0051] The epitaxial wafer provided by this invention has a first mask structure around the growth window mask template 3. When H atoms fall onto the surface of the mask template 3 and migrate toward the growth window, they will be blocked by the first mask structure and cannot reach the sidewall of the nanopillar 5. This can suppress the H atoms from binding with the N-termining atoms on the {10-11} sidewall of the nanopillar 5. Therefore, it will not affect the longitudinal growth of the nanopillar 5. The nanopillar 5 will still maintain a flat surface on the c-plane during the continued growth process, which is conducive to the growth of structures such as quantum wells in the c-plane direction.

[0052] In one specific embodiment of the present invention, such as Figure 2 As shown, the nanopillar includes a first sub-nanopillar 51 and a second sub-nanopillar 52. The first sub-nanopillar 51 is disposed inside the growth window, and the bottom of the second sub-nanopillar 52 is connected to the top of the first sub-nanopillar 51. The bottom of the second sub-nanopillar 52 is flush with the top of the first mask structure 31. The radial dimension of the second sub-nanopillar 52 is equal to the radial dimension of the first sub-nanopillar 51, as shown. Figure 2 As shown; or, the radial dimension of the second sub-nanopillar 52 is larger than the radial dimension of the first sub-nanopillar 51, as shown. Figure 3 As shown.

[0053] In one specific embodiment of the present invention, the structure of the epitaxial wafer is as follows: Figure 4 As shown, the second mask structure 32 surrounds the first mask structure 31. The first mask structure 31 includes a first substructure 311 and a second substructure 312 stacked together. The lower surface of the first substructure 311 is flush with the upper surface of the second mask structure 32.

[0054] Furthermore, the width of the second mask structure 32 is 200–1500 nm, such as 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, or 1500 nm, but is not limited to the listed values. The width of the second mask structure 32 can be adjusted according to the design requirements of the epitaxial wafer.

[0055] In one specific embodiment of the present invention, the structure of the epitaxial wafer is as follows: Figure 5 As shown, the second mask structure 32 is disposed on the side of the first mask structure 31 near the growth substrate 1. The second mask structure 32 includes a third substructure 321 and a fourth substructure 322. The third substructure 321 is disposed on the side of the first mask structure 31 near the growth substrate 1, and the fourth substructure 322 is disposed on the growth substrate 1 and contacts the side of the third substructure 321 away from the growth window 4.

[0056] Furthermore, the width of the fourth substructure 322 is 200–1500 nm, such as 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, or 1500 nm, but is not limited to the listed values. The width of the fourth substructure 322 can be adjusted according to the design requirements of the epitaxial wafer.

[0057] In one specific embodiment of the present invention, such as Figure 6 As shown, the growth substrate 1 includes a substrate 11 and a nitride layer 12 stacked together, and a mask template 3 is disposed on the side of the nitride layer 12 away from the substrate 11.

[0058] Furthermore, the substrate 11 can be made of sapphire, SiC, Si, GaN, AlN, or diamond, etc. The nitride layer 12 can be made of GaN. Understandably, the thickness of the substrate 11 and the nitride layer 12 can be adjusted according to the needs of the grown nanopillars 5, and no specific limitation is made here.

[0059] In one specific embodiment of the present invention, such as Figure 7 As shown, the thickness of the mask template 3 is h; the shape of the growth window 4 is circular or regular hexagonal, the diameter of the growth window 4 is approximately equal to the diameter of the nanopillar, the diameter of the growth window 4 is a, the spacing of the growth windows 4 is d, a:d=1:(1~1.5); the etching depth is h1, the retention thickness is h2, h=h1+h2, the etching width is d1, the retention mesa width is d2, d=d1+d2, d:d2=1:(0.03~0.05), h:h1=1:(0.1~0.3).

[0060] The present invention also provides a method for preparing the above-mentioned epitaxial wafer, the method comprising the following steps:

[0061] S11: Grow the first mask layer on one side of the growth substrate.

[0062] S12: Etch the first mask layer to form a growth mask, which includes a growth window, a first mask structure, and a second mask structure.

[0063] S13: Grow the corresponding nanopillars within each growth window.

[0064] In one specific embodiment of the present invention, the mask template material can be SiN, and the SiN material can be deposited using plasma-enhanced chemical vapor deposition (PECVD) to form the first mask layer. Specifically, under conditions of a pressure of 200–600 mbar, a radio frequency power of 30–70 W, a SiH4 flow rate of 50–250 sccm, and an NH3 flow rate of 10–50 sccm, a first mask layer with a thickness of 50–500 nm is grown on one side of the growth substrate.

[0065] In one specific embodiment of the present invention, reactive ion etching (RIE) can be used to etch the first mask layer to prepare growth windows. Specifically, under the conditions of SF6 flow rate of 20-60 sccm, O2 flow rate of 10-40 sccm, RF power of 50-200 W, and pressure of 5-10 Pa, a portion of the first mask layer is etched until the growth substrate is exposed, thereby forming multiple growth windows.

[0066] In one specific embodiment of the present invention, inductively coupled plasma etching (ICP) can be used to etch the first mask layer to prepare the growth window. The conditions may include a power of 800-1000W, a pressure of 2-5Pa, a voltage of 150-200V, a chlorine flow rate of 30-50sccm, and an argon flow rate of 5-20sccm.

[0067] In one specific embodiment of the present invention, the etching process may include a first etching process and a second etching process, namely, performing a first etching on a first mask layer to obtain a second mask layer with growth windows; and performing a second etching on the second mask layer to obtain a first mask structure and a second mask structure. The methods and conditions of the second etching process may be the same as or different from those of the first etching process.

[0068] Furthermore, the etching width of the second etching process can be 10–50 nm, and the depth can be 40–400 nm. For example, the width can be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm, and the depth can be 40 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, or 400 nm, etc. However, it is not limited to the values ​​listed above; the depth and width of the second etching process can be adjusted according to the size of the GaN nanopillars to be grown.

[0069] In one specific embodiment of the present invention, the conditions for growing nanopillars using MOCVD can be the same as those for conventional nanopillar growth. For example, the conditions for growing GaN nanopillars with a thickness of 500–5000 nm can be: a temperature of 1000–1150 °C, a pressure of 100–400 mbar, a V / III ratio of 10–1000, and a carrier gas of H2 (or H2 and N2).

[0070] In one specific embodiment of the present invention, the method for growing a nitride layer on the substrate surface can be MOCVD or MBE. For example, the conditions for growing a nitride layer with a thickness of 500-5000 nm and made of GaN can be: a temperature of 950-1150 °C, a pressure of 100-400 mbar, a V / III ratio of 500-5000, and a carrier gas of H2 (or a mixture of H2 and N2).

[0071] To better illustrate the present invention and facilitate understanding of its technical solutions, typical but non-limiting embodiments of the present invention are as follows:

[0072] Example 1

[0073] Please see Figures 8A to 8D This embodiment provides a method for preparing an epitaxial wafer, which includes the following steps:

[0074] S21: Using MOCVD process, a GaN nitride layer 12 with a thickness of 500 nm is grown on the surface of sapphire substrate 11 under the conditions of growth temperature of 950℃, pressure of 100mbar, V / III ratio of 500 and carrier gas of H2 and N2.

[0075] S22: Using the PEVCD process, under conditions of deposition pressure of 200 mbar, RF power of 30 W, SiH4 flow rate of 50 sccm, and NH3 flow rate of 10 sccm, a 50 nm thick SiN mask layer 21 is deposited on the surface of the GaN nitride layer 12. Figure 8A As shown.

[0076] S23: The SiN mask layer 21 is etched using the RIE process to prepare the growth window 4 and the second mask layer 22, as follows: Figure 8B As shown.

[0077] The etching parameters for the RIE process include an SF6 flow rate of 20 sccm, an O2 flow rate of 10 sccm, an RF power of 50W, and a chamber pressure of 5Pa.

[0078] Furthermore, the growth window 4 is circular in shape, with a diameter a = 200 nm and a spacing d = 200 nm, as shown below. Figure 8B As shown.

[0079] S24: The second mask layer 22 is etched under the same conditions as the first etching to obtain the mask template 3, as shown. Figure 8C As shown.

[0080] like Figure 7 As shown, the etching depth (i.e., the height of the first substructure) of this etching process is h1 = 40nm, the retention thickness is h2 = 10nm, the etching width is d1 = 180nm, and the retention mesa width (i.e., the width of the first substructure) is d2 = 10nm.

[0081] S25: Using MOCVD technology, GaN nanopillars with a height of 500 nm were grown at growth window 4 under the conditions of 1000℃, 100mbar, V / III ratio of 10, and carrier gases of H2 and N2. Figure 8D As shown.

[0082] Example 2

[0083] Please see Figures 8A to 8D This embodiment provides a method for preparing an epitaxial wafer, which includes the following steps:

[0084] S31: Using MOCVD process, a GaN nitride layer 12 with a thickness of 5000 nm is grown on the surface of sapphire substrate 11 under the conditions of growth temperature of 1150℃, pressure of 400mbar, V / III ratio of 5000 and carrier gas of H2.

[0085] S32: Using the PEVCD process, under conditions of deposition pressure of 600 mbar, RF power of 70 W, SiH4 flow rate of 250 sccm, and NH3 flow rate of 50 sccm, a 500 nm thick SiN mask layer 21 is deposited on the surface of the GaN nitride layer 12. Figure 8A As shown.

[0086] S33: The SiN mask layer 21 is first etched using RIE to prepare the growth window 4 and the second mask layer 22, as shown. Figure 8B As shown.

[0087] The etching parameters for the RIE process include an SF6 flow rate of 60 sccm, an O2 flow rate of 40 sccm, an RF power of 200W, and a chamber pressure of 10Pa.

[0088] Furthermore, the growth window 4 is circular in shape, with a diameter a = 1000 nm and a spacing d = 1500 nm, as shown below. Figure 8B As shown.

[0089] S34: The second mask layer 22 is etched under the same conditions as the first etching to obtain the mask template 3, as shown. Figure 8C As shown.

[0090] like Figure 7 As shown, the etching depth of this etching process is h1 = 400 nm, the retention thickness is h2 = 100 nm, the etching width is d1 = 1400 nm, and the retention mesa width is d2 = 50 nm.

[0091] S35: Using MOCVD technology, GaN nanopillars with a height of 5000 nm were grown at growth window 4 under the conditions of temperature 1150℃, pressure 400 mbar, V / III ratio 1000, and H2 as carrier gas. Figure 8D As shown.

[0092] Example 3

[0093] Please see Figures 8A to 8D This embodiment provides a method for preparing an epitaxial wafer, which includes the following steps:

[0094] S41: Using MOCVD process, a GaN nitride layer 12 with a thickness of 2500 nm is grown on the surface of sapphire substrate 11 under the conditions of growth temperature of 1000℃, pressure of 250mbar, V / III ratio of 2500, and carrier gas of H2 and N2 mixture.

[0095] S42: Using the PEVCD process, under conditions of deposition pressure of 400 mbar, RF power of 50 W, SiH4 flow rate of 150 sccm, and NH3 flow rate of 30 sccm, a SiN mask layer 21 is deposited on the surface of the GaN nitride layer 12. Figure 8A As shown.

[0096] S43: The SiN mask layer 21 is etched using the RIE process to prepare the growth window 4 and the second mask layer 22, as follows: Figure 8B As shown.

[0097] The etching parameters for the RIE process include an SF6 flow rate of 40 sccm, an O2 flow rate of 25 sccm, an RF power of 150W, and a chamber pressure of 8 Pa.

[0098] Furthermore, the growth window 4 is circular in shape, with a diameter a = 600 nm and a spacing d = 750 nm, as shown below. Figure 8B As shown.

[0099] S44: The second mask layer 22 is etched using the same conditions as the first etching to obtain the mask template 3, as shown. Figure 8C As shown.

[0100] like Figure 7 As shown, the etching process has an etching depth of h1 = 200 nm, a retention thickness of h2 = 50 nm, an etching width of d1 = 750 nm, and a retention mesa width of d2 = 25 nm.

[0101] S45: Using MOCVD technology, GaN nanopillars with a height of 2500 nm were grown at growth window 4 under the conditions of temperature 1100℃, pressure 250 mbar, V / III ratio 500, and carrier gases of H2 and N2. Figure 8D As shown.

[0102] Example 4

[0103] This embodiment provides a method for preparing an epitaxial wafer. Except for the etching depth h1 = 220 nm, the retention thickness h2 = 30 nm, the etching width d1 = 520 nm, and the retention mesa width d2 = 40 nm, the other conditions are the same as in Example 3. The specific fabrication process will not be described in detail here.

[0104] Example 5

[0105] This embodiment provides a method for preparing an epitaxial wafer. Except for the use of ICP etching process to perform the first and second etching on the first mask layer, the other conditions are the same as in Embodiment 3. The specific fabrication process will not be described in detail here.

[0106] Furthermore, the conditions for the ICP etching process include a power of 900W, a pressure of 3Pa, a voltage of 175V, a chlorine flow rate of 40sccm, and an argon flow rate of 10sccm.

[0107] The above embodiment utilizes a selected area epitaxy method to prepare a template for growing GaN nanopillars 5 through a two-step etching process. The etched growth template has growth windows 4 that expose the GaN nitride layer 12 nanopillars. A barrier with a higher height than other mask areas exists around the growth window 4. This barrier separates the GaN nanopillars 5 from the atoms adsorbed on the growth template surface, preventing H atoms 6 from migrating from the growth template surface to the sidewalls of the GaN nanopillars 5 and binding with N atoms. Figure 9 As shown, suppressing the H passivation effect and promoting the longitudinal growth of GaN nanopillars 5 helps to improve the quality of GaN nanopillars 5.

[0108] This indicates that GaN nanopillars 5 can be used in light-emitting diodes (LEDs), which also include quantum well structures 7 (such as...). Figure 9 As shown in the diagram, the structure includes an electron blocking layer, a hole providing layer, and an electrode layer. By using this scheme to fabricate a light-emitting diode, the quality of the light-emitting diode can be improved.

[0109] Comparative Example 1

[0110] Except for the absence of a second etching, i.e., the mask template does not have the first mask structure, the conditions in this comparative example are the same as those in Example 3, and will not be repeated here.

[0111] The test results shown in the table below are obtained by testing the epitaxial wafers prepared in each embodiment and comparative example:

[0112]

[0113] The test results from the various embodiments and comparative examples show that the epitaxial wafers and their preparation methods provided by the present invention can significantly suppress the influence of H passivation effect, promote the longitudinal growth of nanopillars, suppress the generation of {10-11} semi-polar surfaces, and improve the uniformity of the height and diameter of GaN nanopillars.

[0114] The applicant declares that the detailed structural features of the present invention are illustrated through the above embodiments, but the present invention is not limited to the above detailed structural features, that is, it does not mean that the present invention must rely on the above detailed structural features to be implemented. Those skilled in the art should understand that any improvements to the present invention, equivalent substitutions for the components selected in the present invention, additions of auxiliary components, selection of specific methods, etc., all fall within the protection scope and disclosure scope of the present invention.

[0115] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0116] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0117] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. An epitaxial wafer, characterized in that, The epitaxial wafer includes: Growth substrate; A mask template is disposed on one side of the growth substrate; the mask template includes multiple growth windows, a first mask structure and a second mask structure, and the growth windows penetrate through the mask template to the growth substrate; Multiple GaN nanopillars, each GaN nanopillar being disposed within a corresponding growth window, each GaN nanopillar including a first sub-nanopillar in contact with the growth substrate; The first mask structure surrounds the first sub-nanopillar, the second mask structure is disposed on the growth substrate and in contact with the first mask structure, and the top of the first mask structure is higher than the top of the second mask structure.

2. The epitaxial wafer according to claim 1, characterized in that, The second mask structure surrounds the first mask structure, and the first mask structure includes a first substructure and a second substructure stacked together, with the lower surface of the first substructure flush with the upper surface of the second mask structure.

3. The epitaxial wafer according to claim 1, characterized in that, The second mask structure is disposed on the side of the first mask structure near the growth substrate. The second mask structure includes a third substructure and a fourth substructure. The third substructure is disposed on the side of the first mask structure near the growth substrate, and the fourth substructure is disposed on the growth substrate and contacts the side of the third substructure away from the growth window.

4. The epitaxial wafer according to any one of claims 1-3, characterized in that, The GaN nanopillar also includes a second sub-nanopillar, which is disposed on the side of the first sub-nanopillar away from the growth substrate.

5. The epitaxial wafer according to claim 4, characterized in that, The upper surface of the first sub-nanopillar is flush with the upper surface of the first mask structure; the radial dimension of the second sub-nanopillar is greater than or equal to the radial dimension of the first sub-nanopillar.

6. The epitaxial wafer according to claim 3, characterized in that, The thickness of the mask template is 50~500 nm, and / or The thickness of the second mask structure is 10~100 nm, and / or The diameter of the growth window is 200~1000 nm; and / or The growth window is circular or hexagonal in shape; and / or The growth substrate is a substrate, or the growth substrate includes a substrate and a nitride layer stacked together, and the mask template is disposed on the side of the nitride layer away from the substrate.

7. A method for preparing an epitaxial wafer according to any one of claims 1-6, characterized in that, The preparation method includes: A first mask layer is grown on one side of the growth substrate; The first mask layer is etched to form a mask template, the mask template including the growth window, the first mask structure and the second mask structure; The corresponding nanopillars are grown within each growth window.

8. The method for preparing an epitaxial wafer according to claim 7, characterized in that, The etching of the first mask layer includes: The first mask layer is etched to obtain a second mask layer having the growth window; The second mask layer is etched to obtain the first mask structure and the second mask structure.

9. The method for preparing an epitaxial wafer according to claim 7, characterized in that, The etching of the first mask layer includes: Under conditions of SF6 flow rate of 20~60 sccm, O2 flow rate of 10~40 sccm, RF power of 50~200 W, and pressure of 5~10 Pa, a portion of the first mask layer is etched until the growth substrate is exposed.

10. The method for preparing an epitaxial wafer according to claim 7, characterized in that, The process of growing the first mask layer on one side of the growth substrate includes: Under conditions of pressure of 200~600 mbar, radio frequency power of 30~70 W, SiH4 flow rate of 50~250 sccm, and NH3 flow rate of 10~50 sccm, a first mask layer with a thickness of 50~500 nm is grown on one side of the growth substrate.

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