A high-speed sequence triggering method for data stream

Abstract

The application discloses a data stream high-speed sequence triggering method, and belongs to the technical field of information, which comprises the following steps: S1, a sequence triggering identification module comprises four modules, which respectively cover code type rates of less than 200Mbps, 200Mbps-400Mbps, 400Mbps-800Mbps and 800Mbps-1.6Gbps; S2, the four modules output corresponding triggering data through a four-input OR gate; and S3, the sequence triggering identification module outputs corresponding triggering signals through ch0-ch15 channel data, 16-level triggering words and 16-level mask words. The data stream high-speed sequence triggering method can identify sequences with code type rates of less than 200Mbps, and if the code type sequence input by a user is greater than 200Mbps, there will be multiple code type changes in a 5ns clock cycle, and the triggering method of the application can efficiently and correctly identify the code type sequence.

Description

Technical Field

[0001] This invention relates to the field of information technology, specifically to a high-speed data stream sequence triggering method. Background Technology

[0002] The method of observing large amounts of data using digital testing equipment is to set a specific observation start point, end point, or a reference point that is related to the data being analyzed. Once this specific point appears in the data stream, it forms a trigger event. The data storage is controlled based on this event. This process is called triggering. This specific reference point is a data word, or it may be a sequence of words or events. In short, it is a multi-channel logical combination. This data word is called the trigger word. A trigger composed of a sequence of words or events is called a sequence trigger. In short, the trigger word is a data word used to select a data window.

[0003] We will not elaborate on sequence triggering composed of event sequences, but will mainly discuss sequence triggering composed of word sequences. The basis of sequence triggering is word triggering, which is triggered by a specific data word appearing in the data. It is the simplest and most basic triggering method for digital test equipment, and also an important part of complex triggering methods. In the field of chip testing, when testing memory devices, it is often necessary to select the address line or data line in the memory chip's response signal as the trigger word. Sometimes, some control signals are also used together with the address and data to form the trigger word. By capturing data that matches a specific trigger word in the data stream, testers can quickly locate the problem.

[0004] like Figure 1 As shown in the word trigger scheme diagram, taking word triggering of 16 data channels as an example, the user can set the trigger mask word mask_word[15:0] and the trigger word trigger_word[15:0]. When the mask word of the data channel is 1, it means that the user does not care about the data of that data channel. Regardless of whether the sampled data meets the set trigger conditions, the channel will output a trigger signal. When the mask word of the data channel is 0, the channel will output a trigger signal only if the sampled data meets the set trigger conditions. When the word trigger judgment module recognizes that there is a data stream in ch0 to ch15 that matches the trigger word and mask word, it outputs a trigger signal and the system executes the trigger operation.

[0005] The sequence-triggered scheme diagram is as follows: Figure 2 As shown, in sequence triggering, the sampled data in the multiple data channels need to be compared with the multi-level trigger words and mask words set by the user in sequence. Only when the upper level trigger word is satisfied will the lower level trigger word judgment circuit be enabled. The triggering operation will only be executed when signals satisfying the multi-level trigger words appear in the multiple data channels in sequence. Summary of the Invention

[0006] The purpose of this invention is to provide a high-speed data stream sequence triggering method. This method can identify sequences with a code rate below 200 Mbps. If the user-input code sequence exceeds 200 Mbps, multiple code changes will occur within a 5 ns clock cycle. This triggering method can efficiently and correctly identify such a code sequence.

[0007] To achieve the above effects, the present invention provides the following technical solution: a high-speed data stream sequence triggering method, comprising the following steps:

[0008] S1, the sequence trigger recognition module includes 4 main modules, covering code pattern rates ≤200Mbps, 200Mbps-400Mbps, 400Mbps-800Mbps, and 800Mbps-1.6Gbps respectively;

[0009] S2 and the four main modules output corresponding trigger data after passing through a four-input OR gate;

[0010] S3, the sequence trigger recognition module outputs the corresponding trigger signal through the data of channels ch0 to ch15, the 16-level trigger word and the 16-level mask word;

[0011] S4. If any identification module meets the triggering condition, it will output the corresponding trigger signal.

[0012] Furthermore, according to the operation steps in S1, the sequence triggering module circuit of the sequence triggering identification module with a code sequence rate ≤ 200Mbps has 16 data channels. In word triggering, the corresponding trigger word trigger_word[15:0] and mask word mask_word[15:0] can be set. The channel trigger word is set to "1011_0101_1111_0000". When the data stream on the corresponding channel simultaneously meets the trigger word, it will respond to the trigger. The trigger mask word mask_word[15:0] can be set. If mask_word[0] is 1, then the data of channel 0 is not cared about. No matter whether the data of the channel is 0 or 1, the channel will respond to the trigger. The trigger will only be triggered when the trigger word and the mask word are satisfied at the same time.

[0013] Furthermore, according to the operation steps in S1, in the sequence triggering with a code pattern sequence rate ≤ 200 Mbps, the sampled data in the multiple data channels need to be compared with the set multi-level trigger words and mask words in sequence. Only when the upper level trigger word is satisfied will the lower level trigger word judgment circuit be enabled. The triggering operation will be executed when signals satisfying the multi-level trigger words appear in the multiple data channels in sequence. This process is implemented through a state machine in the internal logic. Each level corresponds to a state. Only when the state condition is satisfied will the next state be entered. The trigger signal will be output when all levels satisfy the trigger conditions. Taking a sequence triggering with four levels as an example, assuming that the trigger words are set to ABCD in sequence and no mask word is set, the triggering will only be responded to when the trigger words satisfying A->B->C->D appear in the data stream in sequence.

[0014] Furthermore, according to the operation steps in S1, when the code sequence rate of the sequence trigger recognition module is >200Mbps, there will be multiple code sequences within a single clock cycle.

[0015] Furthermore, according to the operation steps in S1, the 128-bit sampled data ch0_data~ch15_data of the 16 sampling channels are divided into groups of 64 bits each: ch0_data[127:64], ch0_data[63:0], ch1_data[127:64], ch2_data[63:0]….ch15_data ta[127:64], ch15_data[63:0], since the starting time of the code pattern data is unknown in the sampling data, and since the input code pattern rate is 200Mbps~400Mbps, at time n, there are both level one and level two code patterns, or only level one code pattern. The internal logic processes both results simultaneously. The logic implementation of result one is as follows: First, the lower 64 bits of the sampling channel data ch0_data~ch15_data at time n are used for word trigger recognition with level one code pattern. The higher 64 bits of the sampling channel data ch0_data~ch15_data at time n are used for word trigger recognition with level two code pattern. If both trigger words are satisfied, then the sampling data at time n+1 is enabled to be used for word trigger recognition with level three and level four code patterns. If not satisfied, then at time n+1... The data at time n is updated to the new data at time n+1. If the sampled data at time n+1 meets the trigger condition of result 1, then the next level is enabled for word trigger recognition. When the code pattern trigger condition is met sequentially from time n to time n+7, the corresponding trigger data is output. The logic implementation of result 2 is as follows: First, the high 64 bits of the sampled channel data ch0_data to ch15_data at time n are used for word trigger recognition with the first-level code pattern. If the sampled data meets the trigger word condition, then the sampled data at time n+1 is enabled for word trigger recognition with the second-level and third-level code patterns. If not, the data at time n+1 is the latest data at time n. If the sampled data at time n+1 meets the trigger condition of result 2, then the next level is enabled for word trigger recognition. When the code pattern trigger condition is met sequentially from time n to time n+8, the corresponding trigger number is output.

[0016] Furthermore, based on the operation steps in S1, the speed of the sequence trigger judgment is achieved by simultaneously implementing the recognition circuits for the above two code sequence orders in the internal logic of the FPGA. The results of the two recognition circuits are logically ORed through an OR gate, and the corresponding trigger signal is output if one of the sequence orders is satisfied.

[0017] Furthermore, according to the operation steps in S1, the trigger circuit when the input code rate is 400Mbps to 800Mbps first divides the 128-bit sampled data ch0_data to ch15_data from the 16 sampling channels into groups of 32 bits each: ch0_data[31:0], ch0_data[63:32], ch0_data[95:64], ch0_data[127:96], ..., ch15_data[31:0], ch15_data[63:32], ch15_data[95:64], ch15_data[127:96]. Since... The start time of the code pattern data is unknown in the sampling data. Since the input code pattern rate is 400Mbps to 800Mbps, there are four possible outcomes for the code pattern at time n: Outcome 1: Level 1, Level 2, Level 3, and Level 4 code patterns exist; Outcome 2: Level 1, Level 2, and Level 3 code patterns exist; Outcome 3: Level 1 and Level 2 code patterns exist; Outcome 4: Only Level 1 code pattern exists. The internal logic processes all four outcomes simultaneously. The logic for Outcome 1 is as follows: First, the sampling channel data ch0_data~ch15_dat at time n... The lower 32 bits of data 'a' are used for word trigger recognition with the first-level code pattern. The next lower 32 bits of the sampled channel data ch0_data~ch15_data at time n are used for word trigger recognition with the second-level code pattern, the next higher 32 bits with the third-level code pattern, and the higher 32 bits with the fourth-level code pattern. If all four trigger words are satisfied simultaneously, then the sampled data at time n+1 is enabled to perform word trigger recognition with the fifth, sixth, seventh, and eighth-level code patterns. If not, the data at time n+1 is updated to the new data at time n. If the sampled data at time n+1 satisfies the trigger condition of result 1, then the next level is enabled for word trigger recognition. When the code pattern trigger conditions are satisfied sequentially from time n to n+3, the corresponding trigger word is output. The logic for sending data and the second result is as follows: First, the second lowest 32 bits of the sampled channel data ch0_data~ch15_data at time n are used for word trigger recognition with the first-level code pattern; the second highest 32 bits are used for word trigger recognition with the second-level code pattern; and the highest 32 bits are used for word trigger recognition with the third-level code pattern. If the sampled data meets the trigger word condition, then the sampled data at time n+1 is enabled to perform word trigger recognition with the fourth-level, fifth-level, sixth-level, and seventh-level code patterns. If not, then the data at time n+1 is the latest data at time n. If the sampled data at time n+1 meets the trigger condition of result 2, then the next level is enabled for word trigger recognition. When the code pattern trigger conditions are met sequentially from time n to time n+4, the corresponding trigger data is output.

[0018] Furthermore, according to the operation steps in S1, the input code rate is 800 Mbps. The trigger circuit implementation at speeds from s to 1.6Gbps involves first dividing the 128-bit sampled data ch0_data to ch15_data from the 16 sampling channels into groups of 16 bits each: ch0_data[15:0], ch0_data[31:15]...ch0_data[95:80], ch0_data[111:96]; ch15_data[127:112]...ch15_data[15:0], ch15_data[31:15]...ch15_data[111:96], ch15_data[127:112]. Since the starting position of the code pattern data in the sampled data is unknown, and the input code pattern rate is 800Mbps to 1.6Gbps, there are eight possible code pattern results at time n. The logic for result one is as follows: First, the sampled channel data ch0_data to ch15_data at time n are arranged in the order of their sequential appearance, corresponding to the code pattern. The relationship is used to determine word triggers. If all eight trigger words are satisfied simultaneously, the sampled data at time n+1 is enabled to perform word triggering judgment according to the correspondence between the level 9 to level 16 code patterns. If the condition is not met, the data at time n+1 is updated to the new data at time n. If the sampled data at time n+1 satisfies the triggering condition of result 1, the next level is enabled to perform word triggering recognition. When the code pattern triggering conditions are satisfied sequentially from time n to time n+1, the corresponding triggering data is output. The logic for result 2 is as follows: First, the sampled channel data at time n is used to perform word triggering judgment according to the correspondence between the channel data and the code pattern shown in the sequence. If the sampled data satisfies the trigger word condition, the sampled data at time n+1 is enabled to perform word triggering recognition with the level 8 to level 15 code patterns. If the condition is not met, the data at time n+1 is the latest data at time n. If the sampled data at time n+1 satisfies the triggering condition of result 2, the next level is enabled to perform word triggering recognition. When the code pattern triggering conditions are satisfied sequentially from time n to time n+2, the corresponding triggering data is output.

[0019] Furthermore, according to the operation steps in S1, the specific circuits for realizing the result sequence 3 to 8, the recognition circuits for the eight code pattern sequence order are executed in parallel, and the execution result is output after passing through an OR gate. When any level of trigger sequence order is satisfied, a trigger signal is output.

[0020] Furthermore, according to the operation steps in S1, the internal logic simultaneously implements sequence trigger recognition circuits with code pattern rates ≤200Mbps, 200Mbps~400Mbps, 400Mbps~800Mbps, and 800Mbps~1.6Gbps. The results of the four sequence trigger recognition circuits are output after passing through an OR gate, and accurate and fast recognition can be performed when the sequence code pattern rate is <1.6Gbps.

[0021] This invention provides a high-speed data stream sequence triggering method, which has the following advantages: This high-speed data stream sequence triggering method can identify sequences with a code pattern rate of less than 200 Mbps. If the code pattern sequence input by the user is greater than 200 Mbps, there will be multiple code pattern changes within a 5 ns clock cycle. The triggering method of this invention can efficiently and correctly identify the code pattern sequence. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a word triggering scheme for a high-speed data stream sequence triggering method according to the present invention;

[0023] Figure 2 This is a schematic diagram of the sequence triggering scheme of a high-speed data stream sequence triggering method according to the present invention;

[0024] Figure 3 This is a schematic diagram of the architecture of a high-speed data stream sequence triggering method according to the present invention;

[0025] Figure 4 This is a schematic diagram showing the correspondence between the trigger word mask word and the channel in a high-speed data stream sequence triggering method according to the present invention;

[0026] Figure 5 This is a circuit diagram of the word triggering module of a high-speed data stream sequence triggering method according to the present invention;

[0027] Figure 6 This is a four-level sequence triggering identification logic state diagram of a high-speed sequence triggering method for data streams according to the present invention;

[0028] Figure 7 This is a diagram showing the correspondence between channel data and sequence trigger word probability at speeds of 200Mbps to 400Mbps in a high-speed data stream sequence triggering method according to the present invention.

[0029] Figure 8 This is a circuit diagram of a high-speed sequence triggering method for data streams according to the present invention, when the code rate is 200Mb ps to 400Mbps.

[0030] Figure 9 This is a diagram showing the correspondence between channel data and sequence trigger word probability at speeds of 400Mbps to 800Mbps, according to the high-speed sequence triggering method for data streams of the present invention.

[0031] Figure 10 This is a circuit diagram of a high-speed sequence triggering method for data streams according to the present invention, when the code rate is 400Mbps to 800Mbps.

[0032] Figure 11 This is a diagram showing the correspondence between channel data and sequence trigger word probability at speeds of 800Mbps to 1.6Gbps, according to the high-speed sequence triggering method of the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0034] This invention provides a technical solution: Example 1, please refer to... Figure 1-11 A high-speed sequence triggering method for data streams includes the following steps:

[0035] Trigger recognition is based on parallel data with a user clock of 200MHz and a bit width of 128 bits. The above sequence trigger recognition scheme can identify sequences with a code pattern rate of less than 200Mb ps. If the code pattern sequence input by the user is greater than 200Mbps, there will be multiple code pattern changes within a 5ns clock cycle. Therefore, the above scheme cannot correctly identify the code pattern sequence. To solve this problem, the following high-speed sequence trigger recognition scheme is proposed.

[0036] As above Figure 3 As shown, the proposed high-speed sequence triggering scheme supports pattern sequence recognition up to 1.6Gbps. The scheme consists of four main modules, covering four rate ranges: pattern rate ≤200Mbps, 200Mbps-400Mbps, 400Mbps-800Mbps, and 800Mbps-1.6Gbps. The sequence triggering recognition modules in these four rate ranges process the data simultaneously. The processing result is output as corresponding trigger data after passing through a 4-input OR gate. If any recognition module meets the triggering condition, it outputs the corresponding trigger signal. The specific implementation circuit will be described in detail later.

[0037] First, let's explain the circuit design of the sequence trigger module for a code sequence rate ≤ 200Mbps. Taking 16 data channels as an example, in word triggering, the user can set the corresponding trigger word `trigger_word[15:0]` and mask word `mask_word[15:0]`, and their correspondence with the channels is as follows: Figure 4As shown, if the user sets the channel trigger word to "1011_0101_1111_0000", the trigger will only be triggered when the data stream on the corresponding channel simultaneously meets the trigger word. Since the user may not care about the data of some channels, the user can set the trigger mask word mask_word[15:0]. If mask_word[0] is 1, the user does not care about the data of channel 0. Regardless of whether the data of the channel is 0 or 1, the channel will respond to the trigger. The trigger will only be triggered when the trigger word and the mask word are both met.

[0038] as follows Figure 5 The word trigger module circuit diagram is shown. ch0_data~ch15_data represent the sampled data of 16 sampling channels, and ch0_word~ch15_word represent the trigger data of 16 data channels set by the user. The sampled data on each channel is first XORed with the corresponding trigger word. When the channel sampled data matches the trigger word, the result is "1". ch0_mask~ch15_mask represent the trigger mask words for the 16 channels. The XOR result of the channel data and the channel trigger word is ORed with the channel mask word. When the user sets the channel mask word to "1", the channel will output a trigger signal regardless of whether the sampled data meets the user-set trigger data. If the mask word is "0", a trigger signal is only output when the sampled data meets the trigger word. All channel trigger data ultimately passes through an AND gate. Only when all channels meet the trigger word set for their corresponding channels will the word trigger judgment module output the corresponding trigger signal.

[0039] In sequence triggering with a code sequence rate ≤200Mbps, the sampled data in multiple data channels needs to be compared sequentially with the user-defined multi-level trigger words and mask words. The next-level trigger word judgment circuit is only enabled if the previous-level trigger word is satisfied. Triggering is only executed when signals satisfying the multi-level trigger words appear sequentially in the multiple data channels. This process is implemented internally using a state machine, where each level corresponds to a state. The next state is only entered when the condition of the current state is met. A trigger signal is output only when all levels meet the trigger conditions. Taking a four-level sequence triggering as an example, assuming the user sequentially sets the trigger words to ABCD and does not set a mask word, triggering will only occur when the trigger words satisfying A->B->C->D appear sequentially in the data stream. Figure 6 This is a logic state diagram for a four-level sequence trigger recognition when the code sequence rate is ≤200Mbps.

[0040] State definition:

[0041] (1) IDLE: Start state / Idle state

[0042] (2) S1: Code sequence A is identified

[0043] (3) S2: The code pattern sequence AB is identified.

[0044] (4) S3: The code pattern sequence ABC was identified.

[0045] (5) S4: The code pattern sequence ABCD was identified.

[0046] State transition explanation:

[0047] (1) When the state is IDLE, if the code A is detected in the input data stream, the state jumps to state S1. If the code A is not detected in the input data stream, the state remains IDLE.

[0048] (2) When the state is S1, if the code pattern B is detected in the input data stream, the state jumps to S2. If the code pattern B is not detected in the input data stream, the state jumps to IDLE.

[0049] (3) When the state is S2, if the code pattern C is detected in the input data stream, the state jumps to S3. If the code pattern C is not detected in the input data stream, the state jumps to IDLE.

[0050] (4) When the state is S3, if the code pattern D is detected in the input data stream, the state jumps to S4. If the code pattern D is not detected in the input data stream, the state jumps to IDLE.

[0051] (5) When the state is S4, it means that the trigger word set by the user has been correctly identified. In this state, the trigger data is output and the state jumps to IDLE state, waiting for the next sequence trigger identification process to start.

[0052] When the input code sequence rate is >200Mbps, there will be multiple code sequences within a single clock cycle. The above circuit cannot correctly identify the corresponding code sequence. Therefore, the following section will specifically introduce the sequence trigger recognition circuit when the code sequence rate is >200Mbps. First, the recognition circuit when the code sequence rate is between 200Mbps and 400Mbps will be introduced. In order to clearly and intuitively illustrate the specific implementation of this recognition circuit, the following section will provide a detailed introduction with 16 sampling channels and 16 levels of user-defined sequence trigger.

[0053] like Figure 7As shown, the 128-bit sampled data ch0_data~ch15_data from the 16 sampling channels are first divided into groups of 64 bits each: ch0_data[127:64], ch0_data[63:0], ch1_data[127:64], ch2_data[63:0], ..., ch15_data[127:64], ch15_data[63:0]. Since the starting position of the code pattern data in the sampled data is unknown, and since the input code pattern rate is 200Mbps~400Mbps, at time n, there may be both level one and level two code patterns, or only level one code pattern. The internal logic handles both possibilities simultaneously. The logic implementation for possibility one is as follows: First, the lower 64 bits of the sampled channel data ch0_data~ch15_data at time n are used to trigger word recognition with the level one code pattern; the higher 64 bits of the sampled channel data ch0_data~ch15_data at time n are used to trigger word recognition with the level two code pattern. Trigger recognition, specifically word trigger recognition, has been detailed above. If two trigger words are simultaneously satisfied, then the sampled data at time n+1 is enabled to perform word trigger recognition with the level 3 and level 4 code patterns. If not satisfied, the data at time n+1 is updated to the new data at time n. If the sampled data at time n+1 satisfies the trigger condition of possibility 1, then the next level is enabled to perform word trigger recognition. When the code pattern trigger conditions are satisfied sequentially from time n to time n+7, the corresponding trigger data is output. The logic for possibility 2 is as follows: First, the high 64 bits of the sampled channel data ch0_data to ch15_data at time n are used to perform word trigger recognition with the level 1 code pattern. If the sampled data satisfies the trigger word condition, then the sampled data at time n+1 is enabled to perform word trigger recognition with the level 2 and level 3 code patterns. If not satisfied, then the data at time n+1 is the latest data at time n. If the sampled data at time n+1 satisfies the trigger condition of possibility 2, then the next level is enabled to perform word trigger recognition. When the code pattern trigger conditions are satisfied sequentially from time n to time n+8, the corresponding trigger data is output.

[0054] as follows Figure 8 As shown, in order to ensure the speed of sequence trigger judgment, the recognition circuits for the above two code sequence order are implemented simultaneously in the internal logic of the FPGA. The results of the two recognition circuits are logically ORed through an OR gate. If one sequence order is satisfied, the corresponding trigger signal is output.

[0055] The following describes the implementation of the trigger circuit when the input code rate is between 400Mbps and 800Mbps. Figure 9As shown, the 128-bit sampled data ch0_data~ch15_data from the 16 sampling channels are first divided into groups of 32 bits each: ch0_data[31:0], ch0_data[63:32], ch0_data[95:64], ch0_data[127:96], ..., ch15_data[31:0], ch15_data[63:32], ch15_data[95:64], ch15_data[127:96]. Since the starting time of the code pattern data is unknown in the sampled data, and since the input code pattern rate is 400Mbps~800Mbps, code pattern stagnation occurs at time n. In four scenarios, possibility 1: the existence of a level 1, level 2, level 3, and level 4 code type; possibility 2: the existence of a level 1, level 2, and level 3 code type; possibility 3: the existence of a level 1 and level 2 code type; and possibility 4: the existence of only a level 1 code type. The internal logic handles all four possibilities simultaneously. The logic for possibility 1 is as follows: First, the lower 32 bits of the sampled channel data ch0_data~ch15_data at time n are used for word trigger recognition with the level 1 code type. Then, the next lower 32 bits of the sampled channel data ch0_data~ch15_data at time n are used for word trigger recognition with the level 2 code type. The next higher 32 bits... According to the three-level code pattern, word trigger recognition is performed. The high 32 bits of data are used for word trigger recognition with the four-level code pattern. If all four trigger words are satisfied simultaneously, then the sampled data at time n+1 is enabled to perform word trigger recognition with the five-level, six-level, seven-level, and eight-level code patterns. If not satisfied, the data at time n+1 is updated to the new data at time n. If the sampled data at time n+1 satisfies the trigger condition of possibility 1, then the next level is enabled for word trigger recognition. When the code pattern trigger conditions are satisfied sequentially from time n to time n+3, the corresponding trigger data is output. The logic implementation of possibility 2 is as follows: First, the sampled channel data ch0_data~ch15_ at time n... The second lowest 32 bits of data are used for word trigger recognition with the first-level code pattern, the second highest 32 bits with the second-level code pattern, and the highest 32 bits with the third-level code pattern. If the sampled data meets the trigger word condition, then the sampled data at time n+1 is enabled to perform word trigger recognition with the fourth, fifth, sixth, and seventh-level code patterns. If not, the data at time n+1 is the latest data at time n. If the sampled data at time n+1 meets the trigger condition of possibility 2, then the next level is enabled for word trigger recognition. When the code pattern trigger condition is met sequentially from time n to n+4, the corresponding trigger data is output. Following the above description, according to... Figure 9 The correspondence table between channel data and sequence trigger words can be used to implement the specific circuits for possible sequences 3 and 4, which will not be elaborated here.

[0056] as follows Figure 10As shown, in order to ensure the speed of sequence trigger judgment, the recognition circuits for the above four code sequence orders are implemented simultaneously in the internal logic of the FPGA. The results of the four recognition circuits are logically ORed through an OR gate. If any sequence order is satisfied, the corresponding trigger signal is output.

[0057] The following describes the implementation of the trigger circuit when the input code rate is between 800Mbps and 1.6Gbps. Figure 11 As shown, the 128-bit sampled data ch0_data~ch15_data from the 16 sampling channels are first divided into groups of 16 bits each: ch0_data[15:0], ch0_data[31:15]…ch0_data[95:80], ch0_data[111:96]; ch15_data[127:112]…ch15_data[15:0], ch15_data[31:15]…ch15_data[111:96], ch15_data[… [127:112] Since the starting time of the code pattern data is unknown in the sampling data, and since the input code pattern rate is 800Mbps~1.6Gbps, there are eight possible scenarios for the code pattern at time n. The logic implementation of possibility one is as follows: First, the sampling channel data ch0_data~ch15_data at time n are processed according to the channel data and code pattern correspondence shown in sequence 1 in the figure. If all eight trigger words are satisfied simultaneously, then the sampling data at time n+1 is enabled to correspond with the level 9 to level 16 code patterns according to the corresponding relationship. The system performs word trigger judgment. If the condition is not met, the data at time n+1 is updated to the new data at time n. If the sampled data at time n+1 satisfies the trigger condition of possibility 1, then the next level is enabled for word trigger recognition. When the code pattern trigger condition is satisfied sequentially from time n to time n+1, the corresponding trigger data is output. The logic implementation of possibility 2 is as follows: First, the sampled channel data at time n is used to perform word trigger judgment according to the channel data and code pattern correspondence shown in sequence 2 in the figure. If the sampled data satisfies the trigger word condition, then the sampled data at time n+1 is enabled to match the eight-level code pattern. The code pattern is used for word trigger recognition up to level 15. If the condition is not met, the data at time n+1 is the latest data at time n. If the sampled data at time n+1 satisfies the trigger condition of possibility 2, then the next level is enabled for word trigger recognition. When the code pattern trigger condition is satisfied sequentially from time n to time n+2, the corresponding trigger data is output. The specific circuits for possibility sequences 3 to 8 can be implemented as described above, which will not be repeated here. The recognition circuits for the eight code pattern sequences are executed in parallel, and the execution results are output after passing through an OR gate. When any level of trigger sequence is satisfied, a trigger signal is output.

[0058] As can be seen from the high-speed sequence triggering scheme, the internal logic simultaneously implements sequence triggering recognition circuits with code pattern rates ≤200Mbps, 200Mbps~400Mbps, 400Mbps~800Mbps, and 800Mbps~1.6Gbps. The results of these four sequence triggering recognition circuits are output after passing through an OR gate, so that accurate and fast recognition can be performed when the sequence code pattern rate is <1.6Gbps.

[0059] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-speed sequence triggering method for data streams, characterized in that, Includes the following steps: S1, the sequence trigger recognition module includes 4 main modules, covering code pattern rates ≤200Mbps, 200Mbps-400Mbps, 400Mbps-800Mbps, and 800Mbps-1.6Gbps respectively; S2 and the four main modules output corresponding trigger data after passing through a four-input OR gate; S3, the sequence trigger recognition module outputs the corresponding trigger signal through ch0-ch15 channel data, 16-level trigger word and 16-level mask word; S4. If any identification module meets the triggering condition, it will output the corresponding trigger signal. Among them, for the sequence trigger recognition module with a code pattern rate of 200Mbps-400Mbps, the 128-bit sampled data of 16 sampling channels are grouped into groups of 64 bits. The internal logic processes the two results of the code pattern starting from the lower 64 bits and starting from the higher 64 bits at the same time. The two recognition circuits are output through an OR gate. For the sequence trigger recognition module with a code pattern rate of 400Mbps-800Mbps, the 128-bit sampled data is grouped into 32-bit groups, and the four code pattern start position results are processed simultaneously in the internal logic. The four recognition circuits are output through an OR gate. For the sequence trigger recognition module with a code pattern rate of 800Mbps-1.6Gbps, the 128-bit sampled data is grouped into 16-bit groups, and the internal logic processes the start position results of eight different code patterns simultaneously. The eight recognition circuits are output through an OR gate. The sequence triggering identification module circuit with a code sequence rate ≤ 200Mbps has 16 data channels. In the word triggering, the corresponding trigger word trigger_word[15:0] and mask word mask_word[15:0] are set. The channel trigger word is set to "1011_0101_1111_0000". The triggering is only triggered when the data stream on the corresponding channel simultaneously meets the trigger word. The trigger mask word mask_word[15:0] is set. If mask_word[0] is 1, the data of channel 0 is ignored. Regardless of whether the data of the channel is 0 or 1, the channel will respond to the trigger. The triggering is only triggered when the trigger word and the mask word are simultaneously met. In the sequence triggering of the code pattern sequence rate ≤200Mbps, the sampled data in the multiple data channels are compared with the set multi-level trigger words and mask words in turn. Only when the upper level trigger word is satisfied will the lower level trigger word judgment circuit be enabled. The triggering operation will be executed when signals that satisfy the multi-level trigger words appear in the multiple data channels in turn. The internal logic is implemented through a state machine, with each level corresponding to a state. Only when the state condition is satisfied will the next state be entered. The trigger signal will be output when all levels satisfy the trigger conditions. When the code sequence rate of the sequence trigger recognition module is >200Mbps, there will be multiple code sequences within a single clock cycle.

2. The high-speed sequence triggering method for data streams according to claim 1, characterized in that, The process includes the following steps: According to the operation steps in S1, in the sequence triggering with a code sequence rate ≤ 200Mbps, the sampled data in the multiple data channels need to be compared with the set multi-level trigger words and mask words in sequence. Only when the upper level trigger word is satisfied will the lower level trigger word judgment circuit be enabled. When signals satisfying the multi-level trigger words appear in the multiple data channels in sequence, the trigger operation will be executed. This process is implemented through a state machine in the internal logic. Each level corresponds to a state. Only when the state condition is satisfied will the next state be entered. The trigger signal will be output when all levels satisfy the trigger conditions. Taking a sequence triggering with four levels as an example, assuming that the trigger words are set to ABCD in sequence and no mask word is set, the trigger will only be responded to when the trigger words satisfying A->B->C->D appear in the data stream in sequence.

3. The high-speed sequence triggering method for data streams according to claim 1, characterized in that, The steps include: According to the operation steps in S1, when the code sequence rate of the sequence trigger recognition module is >200Mbps, there will be multiple code sequences within a single clock cycle.

4. The high-speed sequence triggering method for data streams according to claim 1, characterized in that, The process includes the following steps: According to the operation steps in S1, the 128-bit sampled data ch0_data~ch15_data of the 16 sampling channels are divided into groups of 64 bits each: ch0_data[127:64], ch0_data[63:0], ch1_data[127:64], ch2_data[63:0]...ch15_data[127:64], ch15_data[63:0]. Since the position of the start time of the code pattern data in the sampled data is unknown, and since the input code pattern rate is 200Mbps~400Mbps, at time n, there may be both level one and level two code patterns, or only level one code pattern. The internal logic processes both results simultaneously. The logic implementation for result one is as follows: First, the lower 64 bits of the sampled channel data ch0_data~ch15_data at time n are used for word trigger recognition with the level one code pattern. The higher 64 bits of the sampled channel data ch0_data~ch15_data at time n are used for word trigger recognition. The first step is to perform word trigger recognition using 4 bits of data and a level 2 code pattern. If both trigger words are satisfied simultaneously, then the sampled data at time n+1 is enabled to perform word trigger recognition using level 3 and level 4 code patterns. If not, the data at time n+1 is updated to the new data at time n. If the sampled data at time n+1 satisfies the trigger condition of result 1, then the next level is enabled for word trigger recognition. When the code pattern trigger conditions are satisfied sequentially from time n to time n+7, the corresponding trigger data is output. The logic for result 2 is as follows: First, the high 64 bits of the sampled channel data ch0_data~ch15_data at time n are performed word trigger recognition using a level 1 code pattern. If the sampled data satisfies the trigger word condition, then the sampled data at time n+1 is enabled to perform word trigger recognition using level 2 and level 3 code patterns. If not, the data at time n+1 is the latest data at time n. If the sampled data at time n+1 satisfies the trigger condition of result 2, then the next level is enabled for word trigger recognition. When the code pattern trigger conditions are satisfied sequentially from time n to time n+8, the corresponding trigger number is output.

5. The high-speed sequence triggering method for data streams according to claim 1, characterized in that, The process includes the following steps: Based on the operation steps in S1, and the speed of sequence trigger judgment, a recognition circuit for two code sequence orders is implemented simultaneously in the internal logic of the FPGA. The results of the two recognition circuits are logically ORed through an OR gate. If one sequence order is satisfied, the corresponding trigger signal is output.

6. The high-speed sequence triggering method for data streams according to claim 1, characterized in that, The process includes the following steps: According to the operation steps in S1, the trigger circuit for input code rate of 400Mbps~800Mbps first divides the 128-bit sampled data ch0_data~ch15_data of the 16 sampling channels into groups of 32 bits each: ch0_data[31:0], ch0_data[63:32], ch0_data[95:64], ch0_data[127:96]...ch15_data[31:0], ch15_data[63:32], ch15_data[95:64], ch15_data[127:96]. Since the code... The starting point of the pattern data is unknown in the sampled data. Since the input pattern rate is 400Mbps~800Mbps, there are four possible patterns at time n: Result 1: Level 1, Level 2, Level 3, and Level 4 patterns exist; Result 2: Level 1, Level 2, and Level 3 patterns exist; Result 3: Level 1 and Level 2 patterns exist; Result 4: Only Level 1 pattern exists. The internal logic processes all four results simultaneously. The logic for Result 1 is as follows: First, the lower 32 bits of the sampled channel data ch0_data~ch15_data at time n are used for word trigger recognition with the Level 1 pattern. Then, the sampled channel data ch0_d at time n... The second lowest 32 bits of data from ata~ch15_data are used for word trigger recognition with the level 2 code pattern, the second highest 32 bits are used for word trigger recognition with the level 3 code pattern, and the highest 32 bits are used for word trigger recognition with the level 4 code pattern. If all four trigger words are satisfied simultaneously, then the sampled data at time n+1 is enabled to be used for word trigger recognition with the level 5, level 6, level 7, and level 8 code patterns. If not, the data at time n+1 is updated to the new data at time n. If the sampled data at time n+1 satisfies the trigger condition of result 1, then the next level is enabled for word trigger recognition. When the code pattern trigger conditions are satisfied sequentially from time n to time n+3, the corresponding trigger data is output. The logic implementation of result 2 is as follows: First, n The second lowest 32 bits of the sampled channel data ch0_data~ch15_data at time n are used for word trigger recognition with the first-level code pattern, the second highest 32 bits are used for word trigger recognition with the second-level code pattern, and the highest 32 bits are used for word trigger recognition with the third-level code pattern. If the sampled data meets the trigger word condition, then the sampled data at time n+1 is enabled to perform word trigger recognition with the fourth-level code pattern, the fifth-level code pattern, the sixth-level code pattern, and the seventh-level code pattern. If it does not meet the condition, then the data at time n+1 is the latest data at time n. If the sampled data at time n+1 meets the trigger condition of result 2, then the next level is enabled to perform word trigger recognition. When the code pattern trigger condition is met sequentially from time n to time n+4, the corresponding trigger data is output.

7. The high-speed sequence triggering method for data streams according to claim 1, characterized in that, The process includes the following steps: Following the operation steps in S1, the trigger circuit is implemented when the input code rate is 800Mbps~1.6Gbps. First, the 128-bit sampled data ch0_data~ch15_data from the 16 sampling channels are grouped into 16-bit groups: ch0_data[15:0], ch0_data[31:15]...ch0_data[95:80], ch0_data[111:96]; ch15_data[127:112]... .ch15_data[15:0], ch15_data[31:15]...ch15_data[111:96], ch15_data[127:112]. Since the starting time of the code pattern data is unknown in the sampling data, and since the input code pattern rate is 800Mbps~1.6Gbps, there are eight possible code pattern results at time n. The logic implementation of result one is as follows: First, the sampling channel data ch0_data~ch15_data at time n. The logic for result two is as follows: First, the channel data at time n is processed according to the correspondence between the channel data and the code pattern shown in the sequence. If all eight trigger words are satisfied simultaneously, the sampled data at time n+1 is enabled to perform word triggering judgment with the code patterns from level 9 to level 16 according to the correspondence. If not satisfied, the data at time n+1 is updated to the new data at time n. If the sampled data at time n+1 satisfies the triggering condition of result 1, the next level is enabled for word triggering recognition. When the code pattern triggering conditions are satisfied sequentially from time n to time n+1, the corresponding triggering data is output. The logic for result two is as follows: First, the channel data at time n is processed according to the correspondence between the channel data and the code pattern shown in the sequence. If the sampled data satisfies the trigger word condition, the sampled data at time n+1 is enabled to perform word triggering recognition with the code patterns from level 8 to level 15. If not satisfied, the data at time n+1 is the latest data at time n. If the sampled data at time n+1 satisfies the triggering condition of result 2, the next level is enabled for word triggering recognition. When the code pattern triggering conditions are satisfied sequentially from time n to time n+2, the corresponding triggering data is output.

8. The high-speed sequence triggering method for data streams according to claim 1, characterized in that, The process includes the following steps: Based on the operation steps in S1, implement the specific circuits for the result sequences 3 to 8. The recognition circuits for the eight code sequence orders are executed in parallel, and the execution results are output after passing through an OR gate. When any level of trigger sequence order is satisfied, a trigger signal is output.

9. The high-speed sequence triggering method for data streams according to claim 1, characterized in that, The process includes the following steps: According to the operation steps in S1, the internal logic simultaneously implements sequence triggering recognition circuits with code pattern rates ≤200Mbps, 200Mbps~400Mbps, 400Mbps~800Mbps, and 800Mbps~1.6Gbps. The results of the four sequence triggering recognition circuits are output after passing through an OR gate. Accurate and fast recognition can be performed when the sequence code pattern rate is <1.6Gbps.

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