A multi-level source driving circuit
Through the multi-level source driving circuit, the 12-bit grayscale generation is achieved using resistor string, capacitor multiplexing and interpolation buffer, which solves the problems of large area and high power consumption of the driving IC in the prior art, and achieves low power consumption and high fine pixels show.
Patent Information
- Application Number
- CN202410359678.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-27
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2044-03-27
AI Technical Summary
The source-level driving method of the existing OLED panel driver IC uses a secondary DAC based on resistor string to generate grayscale, resulting in a large single-channel area of the driver IC, making it difficult to achieve a miniaturized design with low power consumption, resulting in high power consumption and no Benefit for space utilization.
Using a multi-stage source driving circuit, including a primary generation circuit based on resistor string, a secondary generation circuit based on capacitance multiplexing and level, and a three-stage generation circuit based on double-bit interpolation, 12-bit grayscale generation is achieved through a three-stage DAC. , reduce power consumption.
It effectively reduces the power consumption and heat dissipation of the driving circuit, improves the space utilization efficiency, and realizes the grayscale generation of high-fine pixels.
Smart Images
Figure CN118248098B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of power source driving, in particular to a multi-level source driving circuit. Background Art
[0002] The driver IC for OLED is an integrated circuit chip used to control the switching and display mode of the AMOLED panel. As the display resolution and data transmission speed of the panel increase, the requirements for the driver IC are also getting higher and higher.
[0003] The driver IC of AMOLED is divided into: source driver IC and row selection IC. Among them, the source driver IC transmits the control voltage of brightness, grayscale and color to the pixels of the panel row by row through the channel formed by the source and drain ends of the transistor. The current display for OLED is basically based on the generation of grayscale based on the two-level DAC. The structure of this DAC generally uses a resistor string-based method to generate the corresponding first-level grayscale, and the interpolation output of the second level is connected in series to generate the second-level grayscale. The single-channel driving area of the driver IC designed with this source-level driving method is large, and it is not easy to carry out the miniaturization design of the low-power source driver IC; in view of this, we propose a multi-level source driver circuit. Summary of the invention
[0004] The object of the present invention is to provide a multi-level source driving circuit to solve the problems raised in the above background technology.
[0005] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a multi-level source driving circuit, comprising a primary generating circuit based on a resistor string, a secondary generating circuit based on capacitor multiplexing and level, and a tertiary generating circuit based on a double-bit interpolation buffer; and also comprising a power supply module for supplying power to the primary generating circuit, wherein the power supply module comprises a power supply VDD terminal and a GND terminal.
[0006] Optionally, the highest voltage of the first-stage generating circuit is VDD, the lowest voltage is 0, and 15 resistors are connected in series between VDD and 0, and the input DATA[9:6] is used as a switch to select different voltages.
[0007] Optionally, the secondary generation circuit includes five groups of sampling capacitors and five groups of latch circuits, and the secondary generation circuit uses capacitance approximation and level latching to complete the generation of 4-bit / 16 grayscale.
[0008] Optionally, the secondary generation circuit first sends the [6:2]-bit-width DATA to the second-stage DAC of the DAC.
[0009] Optionally, each group of the sampling capacitors includes capacitor 1, capacitor 2 and capacitor 3, and each group of the latch circuits includes transistor 1, transistor 2, transistor 3, transistor 4, transistor 5 and transistor 6. The capacitor 1, capacitor 2 and capacitor 3 are used to generate different voltages and receive the voltage output from the resistor string.
[0010] Optionally, the latch circuit includes capacitor SEL1, capacitor SEL2, capacitor SEL3, capacitor SEL4, capacitor SEL5 and capacitor SEL6, and capacitor SEL3, capacitor SEL4, capacitor SEL5 and capacitor SEL6 are used to select the output voltages of transistor 3, transistor 4, transistor 5 and transistor 6 respectively, and the output voltages include two voltages M3_6_1H and M3_6_1L.
[0011] Optionally, the three-stage generating circuit inputs DATA with a bit width of [1:0] into the third-stage DAC of the DAC, and the three-stage generating circuit includes a bit interpolation buffer, and the bit interpolation buffer includes: a rail-to-rail input stage, a programmable current source, and a summing output unit.
[0012] Optionally, the rail-to-rail input stage includes a VH module and a VL module, the VH module is electrically connected to the M3_6_1H voltage, and the VL module is electrically connected to the M3_6_1L voltage;
[0013] The programmable current source includes terminals D0, D1, D2 and D3, and the programmable current source is compatible with 4-bit grayscale voltage generation;
[0014] The summing output unit outputs a voltage.
[0015] Compared with the prior art, the present invention provides a multi-level source driving circuit, which has the following beneficial effects:
[0016] The multi-level source driving circuit generates high-precision pixel display grayscale based on the three-level DAC source level 12-bit grayscale generation. It can solve the problem that the interpolation output of the second level is connected in series as the second-level grayscale generation method, which leads to a large driving area of the driving IC, resulting in high power consumption of the actual product and is not conducive to space utilization. It can effectively reduce the power consumption and heat dissipation of the driving circuit, and is more environmentally friendly and energy-saving. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 is a schematic diagram of the overall driving circuit of the present invention;
[0018] Figure 2 is a schematic diagram of a power supply module of the present invention;
[0019] Figure 3It is a schematic diagram of the structure of the sampling capacitor and latch circuit of the present invention;
[0020] Figure 4 It is a structural schematic diagram of the three-stage generating circuit of the present invention. DETAILED DESCRIPTION
[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0022] like Figure 1-Figure 4 As shown, the present invention provides a technical solution: a multi-level source driving circuit, including a primary generating circuit based on a resistor string, a secondary generating circuit based on capacitor multiplexing and level, and a tertiary generating circuit based on a double-bit interpolation buffer; and also includes a power supply module for powering the primary generating circuit, the power supply module including a power supply VDD terminal and a GND terminal.
[0023] In this embodiment, the highest voltage of the first-stage generating circuit is VDD, the lowest voltage is 0, and 15 resistors are connected in series between VDD and 0. The pixel grayscale with a width of 10 bits is input, and the input data is DATA[9:0]. Then, the DATA with a width of [9:6] bits can be first sent to the first-stage resistor string of the DAC, and the input DATA[9:6] is used as a switch to select different voltages. The first-stage generating circuit encodes each voltage based on the 4bit / 16 grayscale bits of the resistor string, and the encoding forms are: 0, V1, V2, V3, V4, V5, V6, V7, V8, B9, V10, V11, V12, V13, V14, VDD. Please refer to the following table for details:
[0024]
[0025] The secondary generation circuit includes five sets of sampling capacitors and five sets of latch circuits. The secondary generation circuit uses capacitor approximation and level latching to complete the generation of 4bit / 16 grayscale. The secondary generation circuit first sends the [6:2] bit width DATA to the second stage DAC of the DAC.
[0026] In addition, each group of sampling capacitors includes capacitor 1, capacitor 2 and capacitor 3, and each group of latch circuits includes transistor 1, transistor 2, transistor 3, transistor 4, transistor 5 and transistor 6. Capacitor 1, capacitor 2 and capacitor 3 are used to generate different voltages and receive the voltage output from the resistor string. The latch circuit includes capacitor SEL1, capacitor SEL2, capacitor SEL3, capacitor SEL4, capacitor SEL5 and capacitor SEL6, and capacitor SEL3, capacitor SEL4, capacitor SEL5 and capacitor SEL6 are used to select the output voltage of transistor 3, transistor 4, transistor 5 and transistor 6 respectively, and the output voltage includes two voltages of M3_6_1H and M3_6_1L.
[0027] It is worth noting that the three-stage generation circuit inputs the [1:0] bit width DATA into the third-stage DAC of the DAC. The three-stage generation circuit includes a bit interpolation buffer, which includes: a rail-to-rail input stage, a programmable current source, and a summing output unit. The rail-to-rail input stage includes a VH module and a VL module. The VH module is electrically connected to the M3_6_1H voltage, and the VL module is electrically connected to the M3_6_1L voltage; the programmable current source includes D0, D1, D2, and D3 terminals, and the programmable current source is compatible with 4-bit grayscale voltage generation; the summing output unit outputs the voltage.
[0028] As an implementation method of this embodiment:
[0029] The first-stage input is VOUT1 and VOUT2, and the capacitance of capacitor 1, capacitor 2 and capacitor 3 is 10pf; if capacitor SEL1 and capacitor SEL2 are high, transistor 1 and transistor 2 are turned on at the same time. Due to the voltage division effect of capacitor 1, capacitor 2 and capacitor 3, the voltages of P1 and P4 are:
[0030]
[0031] Then the voltages of P2 and P3 are:
[0032]
[0033] Then the voltages of transistor 3, transistor 4, transistor 5 and transistor 6 are:
[0034] ; The voltage values of these four levels are obtained through the 4-select-2 switch, which are divided into: M3_6_1H and M3_6_1L.
[0035] The voltage values of other levels can be deduced in the same way.
[0036] The above generally describes the present invention in detail, but it is obvious to a person skilled in the art that some modifications or improvements can be made to the present invention. Therefore, modifications or improvements that do not depart from the spirit of the present invention are within the scope of protection of the present invention.
Claims
1. A multi-level source driving circuit, characterized in that: It includes a primary generation circuit based on a resistor string, a secondary generation circuit based on capacitor multiplexing and level, and a tertiary generation circuit based on a double-bit interpolation buffer; it also includes a power supply module for supplying power to the primary generation circuit, the power supply module includes a power supply VDD terminal and a GND terminal; The secondary generation circuit includes five groups of sampling capacitors and five groups of latch circuits. The secondary generation circuit uses capacitor approximation and level latching to complete the generation of 4bit / 16 grayscales. The secondary generation circuit first sends the [6:2]-bit-width DATA to the second-stage DAC of the DAC; Each group of the sampling capacitors includes capacitor 1, capacitor 2 and capacitor 3, each group of the latch circuits includes transistor 1, transistor 2, transistor 3, transistor 4, transistor 5 and transistor 6, and the capacitors 1, capacitor 2 and capacitor 3 are used to generate different voltages to receive the voltage output from the resistor string; The latch circuit includes capacitors SEL1, SEL2, SEL3, SEL4, SEL5 and SEL6, and capacitors SEL3, SEL4, SEL5 and SEL6 are used to select output voltages of transistors 3, 4, 5 and 6 respectively, and the output voltages include two voltages M3_6_1H and M3_6_1L.
2. A multi-level source driving circuit according to claim 1, characterized in that: The highest voltage of the first-stage generating circuit is VDD, the lowest voltage is 0, and 15 resistors are connected in series between VDD and 0. The input DATA[9:6] is used as a switch to select different voltages.
3. A multi-level source driving circuit according to claim 2, characterized in that: The three-stage generating circuit inputs DATA with a bit width of [1:0] into the third-stage DAC of the DAC. The three-stage generating circuit includes a bit interpolation buffer, and the bit interpolation buffer includes: a rail-to-rail input stage, a programmable current source, and a summing output unit.
4. A multi-level source driving circuit according to claim 3, characterized in that: The rail-to-rail input stage includes a VH module and a VL module, the VH module is electrically connected to the M3_6_1H voltage, and the VL module is electrically connected to the M3_6_1L voltage; The programmable current source includes terminals D0, D1, D2 and D3, and the programmable current source is compatible with 4-bit grayscale voltage generation; The summing output unit outputs a voltage.