Back contact solar cell, method of manufacture and cell assembly

Abstract

This application discloses a back-contact solar cell, its fabrication method, and a battery module, belonging to the field of crystalline silicon solar cell technology. The back-contact solar cell includes: a semiconductor substrate having opposing light-receiving and back-lighting surfaces; the back-lighting surface includes a first polar region and a second polar region alternately arranged along a first direction; the light-receiving surface is textured; and the surfaces of the first and second polar regions are polished; a first polar structure is disposed in the first polar region; and a second polar structure is disposed in the second polar region. According to this application, the back-contact solar cell incorporates passivation contact technology on the back side of the semiconductor substrate to form a hybrid back-contact cell. Simultaneously, by making the back-lighting surface of the semiconductor substrate a polished surface, interface defects and carrier recombination in the heterojunction region of the back-lighting surface are reduced, resulting in a solar cell with higher open-circuit voltage and photoelectric conversion efficiency.

Description

Technical Field

[0001] This application belongs to the field of crystalline silicon solar cell technology, and particularly relates to a back-contact solar cell, its preparation method, and its battery module. Background Technology

[0002] As PERC (Passivated Emitter and Rear Cell) battery technology matures and its potential is continuously explored, it is gradually approaching the theoretical limit of its conversion efficiency. The industry has begun to seek the next generation of technology. Currently, the mainstream technologies under development include TOPCon (Tunnel Oxide Passivated Contact) batteries, HJT (Heterojunction) batteries, and IBC (Interdigitated back contact) batteries.

[0003] Unlike traditional double-sided electrode contact batteries, the most significant characteristic of back-contact (BC) batteries is that the metal electrodes are located on the back surface of the battery, with no metal electrodes obstructing the front surface. This improves light utilization and thus results in higher short-circuit current and conversion efficiency. Among various BC technologies, HBC (Hybrid Back Contact) technology boasts the highest photoelectric conversion efficiency. HBC batteries are formed by applying passivation contact technology to the back of the battery using hybrid technology. Currently, the photoelectric conversion efficiency of HBC batteries still needs improvement; therefore, how to enhance the photoelectric conversion efficiency of HBC batteries is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a back-contact solar cell, a fabrication method, and a cell module, which reduces interface defects and carrier recombination in the heterojunction region of the back surface, and has high open-circuit voltage and photoelectric conversion efficiency; moreover, the process is simplified and suitable for large-scale mass production.

[0005] In a first aspect, this application provides a back-contact solar cell, comprising:

[0006] A semiconductor substrate has a light-receiving surface and a back-lighting surface, the back-lighting surface including a first polar region and a second polar region arranged alternately along a first direction, the light-receiving surface is a textured surface, and the surfaces of the first polar region and the second polar region are polished surfaces.

[0007] A first polar structure is disposed in a first polar region. The first polar structure includes a first functional layer and a first electrode structure stacked along the direction away from the semiconductor substrate. The first functional layer includes a first passivation layer and a first doped semiconductor layer stacked along the direction away from the semiconductor substrate. The side surface of the first passivation layer facing the semiconductor substrate is a polished surface.

[0008] The second polar structure is disposed in the second polar region. The second polar structure includes a second functional layer and a second electrode structure stacked along the direction away from the semiconductor substrate. The second functional layer includes a second passivation layer and a second doped semiconductor layer stacked along the direction away from the semiconductor substrate. The side surface of the second passivation layer facing the semiconductor substrate is a polished surface.

[0009] The doping types of the first doped semiconductor layer and the second doped semiconductor layer are opposite.

[0010] According to the back-contact solar cell of this application, a passivation contact technology is combined on the back side of the semiconductor substrate to form a hybrid back-contact cell. At the same time, by making the back surface of the semiconductor substrate into a polished surface, the interface defects and carrier recombination in the heterojunction region of the back surface are reduced, so that the solar cell has a higher open-circuit voltage and photoelectric conversion efficiency.

[0011] According to one embodiment of this application, the second functional layer extends at least partially into the first polar region, and the first orthographic projection of the first functional layer on the semiconductor substrate at least partially overlaps with the second orthographic projection of the second functional layer on the semiconductor substrate;

[0012] The first functional layer and the second functional layer are in direct contact; or...

[0013] An insulating layer is provided between the first functional layer and the second functional layer. The material of the insulating layer includes at least one of phosphosilicate glass or borosilicate glass, silicon oxide, silicon nitride, and silicon oxynitride.

[0014] According to one embodiment of this application, an opening is provided between adjacent first electrode structures and second electrode structures, and the third orthographic projection of the opening on the semiconductor substrate is located in the overlapping area of ​​the first orthographic projection and the second orthographic projection.

[0015] According to one embodiment of this application, the electrode structure includes a conductive layer and an electrode, wherein the conductive layer is located on the side of the doped semiconductor layer away from the passivation layer, and the electrode is located on the side of the conductive layer away from the doped semiconductor layer.

[0016] The conductive layer is made of at least one of zinc oxide, indium oxide and tin oxide, and is doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten and aluminum. The thickness of the conductive layer ranges from 10 nm to 150 nm.

[0017] According to one embodiment of this application, the semiconductor substrate further includes a substrate doping layer, which is located in the first polar region and formed on the side close to the first passivation layer. The doping type of the substrate doping layer is the same as the doping type of the first doped semiconductor layer.

[0018] The thickness of the substrate doped layer ranges from 5 nm to 200 nm.

[0019] According to one embodiment of this application, the distance between the surface of the first polar region and the light-receiving surface is greater than the distance between the surface of the second polar region and the light-receiving surface.

[0020] According to one embodiment of this application, the first passivation layer includes a tunneling oxide with a thickness ranging from 0.5 nm to 2.5 nm, the first doped semiconductor layer includes doped polycrystalline silicon with a thickness ranging from 10 nm to 250 nm, the second passivation layer includes intrinsic amorphous silicon with a thickness ranging from 1 nm to 15 nm, and the second doped semiconductor layer includes doped amorphous silicon and / or microcrystalline silicon with a thickness ranging from 1 nm to 60 nm.

[0021] According to one embodiment of this application, the back-contact solar cell further includes a third functional layer and an anti-reflection layer stacked on the light-receiving surface of the semiconductor substrate and in a direction away from the semiconductor substrate. The third functional layer includes at least one of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped thin-film silicon, silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The anti-reflection layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and transparent conductive oxide.

[0022] Secondly, this application provides a method for fabricating a back-contact solar cell, comprising:

[0023] A semiconductor substrate is provided, the semiconductor substrate having a light-receiving surface and a back-lighting surface opposite to each other, the back-lighting surface including a first polar region and a second polar region alternately arranged along a first direction;

[0024] The surface of the semiconductor substrate is treated to form a textured surface on the light-receiving surface, and a polished surface on the surface of the first polar region and the surface of the second polar region.

[0025] Polar structures are formed in the first polarity region and the second polarity region, respectively;

[0026] The polar structure of the first polar region includes a first functional layer and a first electrode structure stacked along the direction away from the semiconductor substrate. The first functional layer includes a first passivation layer and a first doped semiconductor layer stacked along the direction away from the semiconductor substrate. The surface of the first passivation layer facing the semiconductor substrate is a polished surface. The polar structure of the second polar region includes a second functional layer and a second electrode structure stacked along the direction away from the semiconductor substrate. The second functional layer includes a second passivation layer and a second doped semiconductor layer stacked along the direction away from the semiconductor substrate. The surface of the second passivation layer facing the semiconductor substrate is a polished surface. The doping types of the first doped semiconductor layer and the second doped semiconductor layer are opposite.

[0027] According to the back-contact solar cell fabrication method of this application, a passivation contact technology is combined on the back side of the semiconductor substrate to form a hybrid back-contact cell. At the same time, by making the back surface of the semiconductor substrate into a polished surface, the interface defects and carrier recombination in the heterojunction region of the back surface are reduced, so that the solar cell has a higher open-circuit voltage and photoelectric conversion efficiency. In addition, compared with the existing hybrid back-contact cell process, the fabrication method proposed in this application has a simplified process, which is conducive to large-scale mass production.

[0028] According to one embodiment of this application, the surface treatment of a semiconductor substrate includes:

[0029] Texturing is performed on the light-receiving and back-light-receiving surfaces of the semiconductor substrate;

[0030] A mask is formed on the light-receiving surface of a semiconductor substrate;

[0031] Polish the back surface of the semiconductor substrate;

[0032] Remove the mask.

[0033] According to one embodiment of this application, the remaining thickness of the mask after polishing the back surface of the semiconductor substrate ranges from 10nm to 100nm, and the material of the mask includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0034] According to one embodiment of this application, before processing the surface of the semiconductor substrate, the method further includes:

[0035] The semiconductor substrate is subjected to gettering treatment.

[0036] According to one embodiment of this application, a gettering process is performed on a semiconductor substrate, including:

[0037] Damaged layers on semiconductor substrates are removed by wet etching;

[0038] Gettering treatment of semiconductor substrates is performed by high-temperature phosphorus diffusion;

[0039] The getter layer formed on the semiconductor substrate during the getter process is removed by wet etching.

[0040] According to one embodiment of this application, polar structures are formed in the first polar region and the second polar region, respectively, including:

[0041] A first functional layer is formed on the back surface of a semiconductor substrate;

[0042] The first region corresponding to the second polar region of the semiconductor substrate is etched to remove the first functional layer and the semiconductor substrate of the first thickness within the first region;

[0043] A second functional layer is formed on the back surface of a semiconductor substrate, and the second functional layer covers the first functional layer;

[0044] The second region in the first polar region of the semiconductor substrate is etched to remove the second functional layer and the first functional layer of the second thickness within the second region;

[0045] A conductive layer is formed on the back surface of a semiconductor substrate, and the conductive layer covers the first functional layer and the second functional layer.

[0046] Openings are made in each overlapping region of the first functional layer and the second functional layer, the openings at least cutting off the conductive layer and at most exposing the first functional layer.

[0047] Electrodes that are in contact with the conductive layer are formed in the first region and the second region, respectively.

[0048] According to one embodiment of this application, a wet chemical etching solution is used to remove a first functional layer and a semiconductor substrate of a first thickness in a first region. The wet chemical etching solution includes an alkaline polishing solution.

[0049] According to one embodiment of this application, after forming the second functional layer on the back surface of the semiconductor substrate, the method further includes:

[0050] A third functional layer and an antireflection layer are sequentially formed on the light-receiving surface of a semiconductor substrate.

[0051] Thirdly, this application provides a battery assembly, including a back-contact solar cell according to the aforementioned method, or including a back-contact solar cell prepared according to the aforementioned method.

[0052] The battery module according to this application has a high open-circuit voltage and photoelectric conversion efficiency.

[0053] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0054] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0055] Figure 1 This is one of the cross-sectional structural schematic diagrams of the back-contact solar cell provided in the embodiments of this application;

[0056] Figure 2 This is the second schematic diagram of the cross-sectional structure of the back-contact solar cell provided in the embodiments of this application;

[0057] Figure 3 This is a schematic flowchart of the method for fabricating a back-contact solar cell provided in the embodiments of this application;

[0058] Figure 4 This is one of the cross-sectional structural schematic diagrams of a stage in the preparation method provided in the embodiments of this application;

[0059] Figure 5 This is the second schematic cross-sectional view of a stage in the preparation method provided in the embodiments of this application;

[0060] Figure 6 This is the third cross-sectional structural schematic diagram of a stage in the preparation method provided in the embodiments of this application;

[0061] Figure 7 This is the fourth cross-sectional structural schematic diagram of a stage in the preparation method provided in the embodiments of this application;

[0062] Figure 8 This is the fifth of the cross-sectional structural schematic diagrams of a stage in the preparation method provided in the embodiments of this application;

[0063] Figure 9 This is the sixth of the cross-sectional structural schematic diagrams of a stage in the preparation method provided in the embodiments of this application;

[0064] Figure 10 This is the seventh cross-sectional structural schematic diagram of a stage in the preparation method provided in the embodiments of this application;

[0065] Figure 11 This is the eighth cross-sectional structural diagram of a stage in the preparation method provided in the embodiments of this application.

[0066] Figure label:

[0067] Semiconductor substrate 1, first functional layer 2, first passivation layer 2-1, first doped semiconductor layer 2-2, substrate doped layer 3, insulating layer 4, second functional layer 5, second passivation layer 5-1, second doped semiconductor layer 5-2, third functional layer 6, antireflection layer 7, conductive layer 8, first conductive layer 8-1, second conductive layer 8-2, first electrode 9, second electrode 10, first polar region A, second polar region B, mask M1, first surface S1, second surface S2, third surface S3, first opening G1, second opening G2, third opening G3. Detailed Implementation

[0068] The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings. In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0069] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0070] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0071] In related technologies, the structure of HBC batteries typically features a polished TOPCon region on the back side, while the back heterojunction region and the front side have a textured surface. This design simplifies the manufacturing process. However, because the textured surface has a larger interface area than the polished surface, interface defects and carrier recombination are more severe on the textured surface, resulting in suboptimal passivation of the back heterojunction region and impacting battery efficiency. Furthermore, the current manufacturing process for HBC batteries remains relatively complex, hindering large-scale mass production.

[0072] This application proposes a back-contact solar cell, its fabrication method, and its battery module. By combining passivation contact technology on the back side of a semiconductor substrate, a hybrid back-contact battery is formed. At the same time, by making the back surface of the semiconductor substrate into a polished surface, the interface defects and carrier recombination in the heterojunction region of the back surface are reduced, resulting in a solar cell with higher open-circuit voltage and photoelectric conversion efficiency. In addition, compared with existing hybrid back-contact battery processes, the fabrication method proposed in this application has a simplified process, which is conducive to large-scale mass production.

[0073] Reference Figure 1 , Figure 1 A cross-sectional structure of a back-contact solar cell is shown. One embodiment of this application proposes a back-contact solar cell.

[0074] In this embodiment, the back-contact solar cell includes a semiconductor substrate 1, a first polarity structure, and a second polarity structure. The semiconductor substrate 1 has a light-receiving surface and a backlighting surface opposite to each other. The backlighting surface includes a first polarity region A and a second polarity region B arranged alternately along a first direction D1. The light-receiving surface is textured, and the surfaces of the first polarity region A and the second polarity region B are polished. The first polarity structure is disposed in the first polarity region A. The first polarity structure includes a first functional layer 2 and a first electrode structure stacked along a direction away from the semiconductor substrate 1. The first functional layer 2 includes a first passivation layer 2-1 stacked along a direction away from the semiconductor substrate 1. The first doped semiconductor layer 2-2 and the first passivation layer 2-1 have a polished surface on the side facing the semiconductor substrate 1. A second polar structure is disposed in the second polar region B. The second polar structure includes a second functional layer 5 and a second electrode structure stacked along the direction away from the semiconductor substrate 1. The second functional layer 5 includes a second passivation layer 5-1 and a second doped semiconductor layer 5-2 stacked along the direction away from the semiconductor substrate 1. The surface of the second passivation layer 5-1 facing the semiconductor substrate 1 has a polished surface. The doping type of the first doped semiconductor layer 2-2 and the doping type of the second doped semiconductor layer 5-2 are opposite.

[0075] In some embodiments, the semiconductor substrate 1 may include materials such as single-crystal silicon, germanium, or gallium arsenide. The doping type of the semiconductor substrate 1 may be N-type doping or P-type doping.

[0076] like Figure 1 As shown, in the first direction D1, a first polar region A and a second polar region B are arranged adjacent to each other. A first opening G1 is formed on the back surface of the semiconductor substrate 1, which is used to form the second polar region B. The surface of the first polar region A is designated as the first surface S1, the surface of the second polar region B is designated as the second surface S2, and the light-receiving surface of the semiconductor substrate 1 is designated as the third surface S3.

[0077] In some embodiments, the distance between the first surface S1 and the third surface S3 of the first polar region A is greater than the distance between the second surface S2 and the third surface S3 of the second polar region B. This facilitates the complete removal of the original film layer of the first polar region A when forming the first opening G1.

[0078] The first surface S1 and the second surface S2 are polished surfaces. For example, the first surface S1 and the second surface S2 can be polished surfaces after polishing. The polishing process can be performed using a conventional alkaline polishing solution.

[0079] Because the back surface of the semiconductor substrate 1 is made into a polished surface, the interface area between the back surface of the semiconductor substrate 1 and the polar structure is reduced, thereby reducing the interface defects and carrier recombination in the heterojunction region of the back surface, and improving the open circuit voltage and photoelectric conversion efficiency of the back contact solar cell.

[0080] The third surface S3 has a textured surface. For example, a pyramidal textured surface and / or a textured surface with corrosion pits.

[0081] In some embodiments, the semiconductor substrate 1 further includes a substrate doped layer 3. The substrate doped layer 3 is located in the first polar region A and is formed on the side close to the first passivation layer 2-1. The doping type of the substrate doped layer 3 is the same as the doping type of the first doped semiconductor layer 2-2.

[0082] The surface of the substrate doped layer 3 near the first passivation layer 2-1 is a polished surface. The substrate doped layer 3 is formed by doping a portion of the semiconductor substrate 1. For example, the portion of the semiconductor substrate 1 within the first polar region A is doped with particles such as boron to form a P-type substrate doped layer 3; or, it is doped with particles such as arsenic or phosphorus to form an N-type substrate doped layer 3.

[0083] In some embodiments, the thickness of the substrate doped layer 3 ranges from 5 nm to 200 nm. For example, the thickness of the substrate doped layer 3 can be 5 nm, 50 nm, 100 nm, or 200 nm.

[0084] In some embodiments, the material of the first passivation layer 2-1 may include a tunneling oxide, and the thickness of the first passivation layer 2-1 ranges from 0.5 nm to 2.5 nm. For example, the thickness of the first passivation layer 2-1 may be 0.5 nm, 1.5 nm, or 2.5 nm, etc. This provides a good passivation effect for the first surface S1 while ensuring the majority carrier tunneling effect.

[0085] The surface of the first passivation layer 2-1 closest to the semiconductor substrate 1 is also polished. This reduces the interface area between the first passivation layer 2-1 and the semiconductor substrate 1, thereby reducing the recombination probability of charge carriers at the interface between the first passivation layer 2-1 and the semiconductor substrate 1.

[0086] In some embodiments, the material of the first doped semiconductor layer 2-2 may include doped polycrystalline silicon, and the thickness of the first doped semiconductor layer 2-2 ranges from 10 nm to 250 nm. For example, the thickness of the first doped semiconductor layer 2-2 can be 10 nm, 50 nm, 150 nm, or 250 nm, etc. This provides good field passivation while reducing film thickness and parasitic absorption.

[0087] The doping type of the first doped semiconductor layer 2-2 is the same as or opposite to the doping type of the semiconductor substrate 1. For example, if the semiconductor substrate 1 is N-type doped, the first doped semiconductor layer 2-2 can be either N-type or P-type doped.

[0088] In some embodiments, the second passivation layer 5-1 comprises intrinsic amorphous silicon, and the thickness of the second passivation layer 5-1 ranges from 1 nm to 15 nm. For example, the thickness of the second passivation layer 5-1 can be 1 nm, 10 nm, or 15 nm, etc. This provides a better passivation effect on the second surface S2.

[0089] The surface of the second passivation layer 5-1 closest to the semiconductor substrate 1 is also polished. This reduces the interface area between the second passivation layer 5-1 and the semiconductor substrate 1, thereby reducing the recombination probability of charge carriers at the interface between the second passivation layer 5-1 and the semiconductor substrate 1.

[0090] In some embodiments, the second doped semiconductor layer 5-2 comprises doped amorphous silicon and / or microcrystalline silicon, and the thickness of the second doped semiconductor layer 5-2 ranges from 1 nm to 60 nm. For example, the thickness of the second doped semiconductor layer 5-2 can be 1 nm, 30 nm, or 60 nm, etc. This provides good field passivation while reducing film thickness and parasitic absorption.

[0091] The doping type of the second doped semiconductor layer 5-2 is opposite to that of the first doped semiconductor layer 2-2. For example, if the first doped semiconductor layer 2-2 is N-type doped, then the second doped semiconductor layer 5-2 can be P-type doped.

[0092] In some embodiments, the second functional layer 5 extends at least partially to the first polar region A, and the first orthographic projection of the first functional layer 2 on the semiconductor substrate 1 at least partially overlaps with the second orthographic projection of the second functional layer 5 on the semiconductor substrate 1.

[0093] In the first direction D1, both the second passivation layer 5-1 and the second doped semiconductor layer 5-2 extend towards the first polar regions A on both sides, and respectively partially overlap with the first passivation layer 2-1 and the first doped semiconductor layer 2-2 located in the first polar regions A on both sides. The orthogonal projection of the overlapping portion on the semiconductor substrate 1 is located within the first polar region A. Thus, in the first direction D1, both sides of the first polar region A have overlapping portions.

[0094] like Figure 1 As shown, an insulating layer 4 is provided between the first functional layer 2 and the second functional layer 5. An insulating layer 4 is provided between the second passivation layer 5-1 and the first doped semiconductor layer 2-2 in the overlapping portion of the first functional layer 2 and the second functional layer 5. This reduces leakage current. The insulating layer 4 is made of at least one of the following materials: phosphosilicate glass or borosilicate glass, silicon oxide, silicon nitride, and silicon oxynitride.

[0095] Reference Figure 2 , Figure 2 Another cross-sectional structure of a back-contact solar cell is shown. In some other embodiments, the first functional layer 2 and the second functional layer 5 are in direct contact.

[0096] like Figure 2 As shown, in the overlapping portion of the first functional layer 2 and the second functional layer 5, the second passivation layer 5-1 and the first doped semiconductor layer 2-2 are in direct contact. This improves the passivation quality at the interface between the first polar region A and the second polar region B.

[0097] In some embodiments, the electrode structure includes a conductive layer 8 and an electrode, wherein the conductive layer 8 is located on the side of the doped semiconductor layer away from the passivation layer, and the electrode is located on the side of the conductive layer away from the doped semiconductor layer.

[0098] The first electrode structure can be p-polarized, and the second electrode structure can be n-polarized. Alternatively, the first electrode structure can be n-polarized, and the second electrode structure can be p-polarized. The polarity of the electrode structure depends on the doping type in the functional layer it contacts.

[0099] The first electrode structure includes a first conductive layer 8-1 and a first electrode 9. A second opening G2 is formed on the side of the first doped semiconductor layer 2-2 away from the first passivation layer 2-1. The first conductive layer 8-1 covers the second opening G2 and extends along a first direction D1 to both sides of the second opening G2. The first electrode 9 is located on the side of the first conductive layer 8-1 away from the first doped semiconductor layer 2-2.

[0100] The portion of the first conductive layer 8-1 extending into the second opening G2 may be separated from the first functional layer 2 by a portion of the second functional layer 5. That is, the first conductive layer 8-1 and the first doped semiconductor layer 2-2 are separated by an insulating layer 4, a second passivation layer 5-1, and a second doped semiconductor layer 5-2, or by a second passivation layer 5-1 and a second doped semiconductor layer 5-2.

[0101] The second electrode structure includes a second conductive layer 8-2 and a second electrode 10. The second conductive layer 8-2 is formed on the side of the second doped semiconductor layer 5-2 away from the second passivation layer 5-1 and covers the second polar region B. The second electrode 10 is located on the side of the second conductive layer 8-2 away from the second doped semiconductor layer 5-2.

[0102] In the first direction D1, both sides of the second conductive layer 8-2 can extend at least partially to the first polar region A, and the orthographic projection of the second conductive layer 8-2 on the semiconductor substrate 1 at least partially overlaps with the second orthographic projection of the second functional layer 5 on the semiconductor substrate 1. An insulating layer 4, a second passivation layer 5-1, and a second doped semiconductor layer 5-2 are spaced apart between the second conductive layer 8-2 and the first doped semiconductor layer 2-2, or a second passivation layer 5-1 and a second doped semiconductor layer 5-2 are spaced apart.

[0103] In some embodiments, the first conductive layer 8-1 and the second conductive layer 8-2 comprise transparent conductive oxides. For example, the materials of the first conductive layer 8-1 and the second conductive layer 8-2 include at least one of zinc oxide, indium oxide, and tin oxide.

[0104] The materials of the first electrode 9 and the second electrode 10 can be metallic materials, such as silver or copper.

[0105] In some embodiments, the first conductive layer 8-1 and the second conductive layer 8-2 may be doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten and aluminum.

[0106] In some embodiments, the first conductive layer 8-1 and the second conductive layer 8-2 have the same thickness, ranging from 10 nm to 150 nm. For example, the thickness of the conductive layer 8 can be 10 nm, 50 nm, or 150 nm.

[0107] In some embodiments, a third opening G3 is provided between adjacent first electrode structures and second electrode structures, and the third orthographic projection of the third opening G3 on the semiconductor substrate 1 is located within the overlapping area of ​​the first orthographic projection and the second orthographic projection. The first electrode structure and the second electrode structure are isolated by the third opening G3 to avoid short circuits.

[0108] The third opening G3 is located between each of the first opening G1 and the second opening G2, and the third opening G3 at least separates the first conductive layer 8-1 and the second conductive layer 8-2, and at most exposes the first functional layer 2. Figure 1 or Figure 2 As shown, the third opening G3 separates the first conductive layer 8-1 and the second conductive layer 8-2, and cuts off the second passivation layer 5-1 and the second doped semiconductor layer 5-2, exposing the insulating layer 4 or exposing the first doped semiconductor layer 2-2.

[0109] In some embodiments, the back-contact solar cell further includes a third functional layer 6 and an antireflection layer 7 located on the light-receiving surface of the semiconductor substrate 1. The third functional layer 6 is in contact with the light-receiving surface of the semiconductor substrate 1, and the antireflection layer 7 is located on the side of the third functional layer 6 away from the semiconductor substrate 1 and is in contact with the third functional layer 6. The light-receiving surface of the semiconductor substrate 1 is textured, and the surface of the third functional layer 6 near the semiconductor substrate 1 is also textured.

[0110] The third functional layer 6 includes at least one of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped thin-film silicon, silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The antireflection layer 7 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and transparent conductive oxide.

[0111] Reference Figure 3 , Figure 3 A fabrication process for a back-contact solar cell is shown. An embodiment of this application also proposes a method for fabricating a back-contact solar cell.

[0112] In this embodiment, the method for preparing a back-contact solar cell includes steps 10, 20, and 30.

[0113] Step 10: Provide a semiconductor substrate 1, which has a light-receiving surface and a backlight surface, and the backlight surface includes a first polar region A and a second polar region B arranged alternately along a first direction;

[0114] Step 20: Process the surface of semiconductor substrate 1 to form a textured surface on the light-receiving surface and a polished surface on the surface of the first polar region A and the surface of the second polar region B.

[0115] Step 30: Polar structures are formed in the first polar region A and the second polar region B, respectively.

[0116] In this embodiment, the structure of the back-contact solar cell prepared according to the preparation method can refer to the aforementioned embodiment. The polar structure of the first polar region A includes a first functional layer 2 and a first electrode structure stacked along the direction away from the semiconductor substrate 1. The first functional layer 2 includes a first passivation layer 2-1 and a first doped semiconductor layer 2-2 stacked along the direction away from the semiconductor substrate 1. The surface of the first passivation layer 2-1 facing the semiconductor substrate 1 is a polished surface. The second polar structure is disposed in the second polar region B. The polar structure of the second polar region B includes a second functional layer 5 and a second electrode structure stacked along the direction away from the semiconductor substrate 1. The second functional layer 5 includes a second passivation layer 5-1 and a second doped semiconductor layer 5-2 stacked along the direction away from the semiconductor substrate 1. The surface of the second passivation layer 5-1 facing the semiconductor substrate 1 is a polished surface. The doping type of the first doped semiconductor layer 2-2 and the doping type of the second doped semiconductor layer 5-2 are opposite.

[0117] In step 10, the semiconductor substrate 1 may include materials such as single-crystal silicon, germanium, or gallium arsenide. The doping type of the semiconductor substrate 1 may be N-type doping or P-type doping.

[0118] In this embodiment, the morphology of the light-receiving and back-light-receiving surfaces of the semiconductor substrate 1 is first processed to make the light-receiving surface have a textured structure, such as a pyramidal textured surface and / or an etched pit textured surface, and the back-light-receiving surface have a polished surface, such as a smooth surface after polishing. Then, the various film layer structures are generated on the semiconductor substrate 1 to form a hybrid back-contact solar cell. The fabrication process is simplified, which is beneficial for large-scale mass production.

[0119] As an example, the specific process for processing the surface of the semiconductor substrate 1 in step 20 can be as follows: first, texturing the light-receiving surface and the back-light-receiving surface of the semiconductor substrate 1; then forming a mask M1 on the light-receiving surface of the semiconductor substrate 1; then polishing the back-light-receiving surface of the semiconductor substrate 1; and finally removing the mask M1.

[0120] A semiconductor substrate 1 is immersed in a texturing solution to achieve double-sided texturing of both the light-receiving and back-light-receiving surfaces; then, a mask M1 is prepared on the light-receiving surface to protect the texturing morphology of the light-receiving surface during subsequent polishing. The material of the mask M1 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0121] The semiconductor substrate 1 with the prepared mask M1 is immersed in an alkaline polishing solution to polish the back surface of the semiconductor substrate 1, forming a polished surface morphology. The mask M1 retains a certain thickness after polishing the back surface of the semiconductor substrate 1 to ensure the textured surface morphology of the light-receiving surface of the semiconductor substrate 1. The remaining thickness can range from 10nm to 100nm, such as 10nm, 50nm, or 100nm.

[0122] In some embodiments, the step of removing the mask M1 can be performed in a subsequent step of fabricating the polar structure, i.e., after polishing the back surface of the semiconductor substrate 1, step 30 can be started.

[0123] In some embodiments, before processing the surface of the semiconductor substrate 1, a gettering process may be included. By performing a gettering process on the semiconductor substrate 1, the content of impurity elements in the semiconductor substrate 1 can be reduced, thereby reducing carrier recombination.

[0124] As an example, the process for performing getter treatment on semiconductor substrate 1 may include: first removing the damaged layer of semiconductor substrate 1 by wet etching; then performing getter treatment on semiconductor substrate 1 by high-temperature phosphorus diffusion; and finally removing the getter layer formed on semiconductor substrate 1 during the getter treatment by wet etching. This can effectively reduce the content of impurity elements inside semiconductor substrate 1.

[0125] In some embodiments, the step of forming polar structures in the first polar region A and the second polar region B may include: forming a first functional layer 2 on the back surface of the semiconductor substrate 1; etching a first region corresponding to the second polar region B of the semiconductor substrate 1 to remove the first functional layer 2 and a first thickness of the semiconductor substrate 1 within the first region; forming a second functional layer 5 on the back surface of the semiconductor substrate 1, the second functional layer 5 covering the first functional layer 2; etching a second region in the first polar region A of the semiconductor substrate 1 to remove the second functional layer 5 and the first functional layer 2 of the second thickness within the second region; forming a conductive layer 8 on the back surface of the semiconductor substrate 1, the conductive layer 8 covering the first functional layer 2 and the second functional layer 5; making openings in each overlapping region of the first functional layer 2 and the second functional layer 5, the openings at least cutting off the conductive layer 8 and at most exposing the first functional layer 2; and forming electrodes in contact with the conductive layer 8 in the first region and the second region, respectively.

[0126] Combined with appendix Figure 4-11 , attached Figure 4-11 The cross-sectional structure of the battery at each stage of the fabrication process is shown, specifically illustrating one embodiment of the fabrication method of the back-contact solar cell provided in this application.

[0127] like Figure 4 As shown, Figure 4 The structure of semiconductor substrate 1 after surface treatment is shown. Figure 4 In the process, the light-receiving surface (i.e., the third surface S3) of the semiconductor substrate 1 is textured, the backlight surface of the semiconductor substrate 1 is polished, and the light-receiving surface retains a mask M1.

[0128] like Figure 5As shown, a first functional layer 2 is formed on the back surface of a semiconductor substrate 1. A first passivation layer 2-1 and a first doped semiconductor layer 2-2 are prepared by LPCVD (low-pressure chemical vapor deposition) or PECVD (plasma-enhanced chemical vapor deposition). The material of the first passivation layer 2-1 may include tunneling oxide, with a thickness ranging from 0.5 nm to 2.5 nm, such as 0.5 nm, 1.5 nm, or 2.5 nm. The material of the first doped semiconductor layer 2-2 may include doped polycrystalline silicon, with a thickness ranging from 10 nm to 250 nm, such as 10 nm, 50 nm, 150 nm, or 250 nm. The doping method for the first doped semiconductor layer 2-2 is either to prepare in-situ doped amorphous / polycrystalline silicon followed by high-temperature annealing and crystallization, or to prepare an intrinsic amorphous / polycrystalline silicon layer followed by high-temperature diffusion doping and crystallization.

[0129] In this embodiment, while forming the first functional layer 2, the doping elements in the first doped semiconductor layer 2-2 enter the back surface of the semiconductor substrate 1 through the first passivation layer 2-1 to form the substrate doped layer 3. The doping type of the substrate doped layer 3 is the same as that of the first doped semiconductor layer 2-2. The thickness of the substrate doped layer 3 ranges from 5nm to 200nm, such as 5nm, 50nm, 100nm, or 200nm.

[0130] In this embodiment, after the first functional layer 2 is formed, an insulating layer 4 is prepared on the side of the first functional layer 2 away from the semiconductor substrate 1. The material of the insulating layer 4 includes at least one of phosphosilicate glass or borosilicate glass, silicon oxide, silicon nitride, and silicon oxynitride. The insulating layer 4 is used to protect the remaining portion of the first functional layer 2 when etching the first functional layer 2 corresponding to the second polarity region B.

[0131] like Figure 6 or Figure 7 As shown, etching is performed on the first region corresponding to the second polar region B of the semiconductor substrate 1 to remove the first functional layer 2 and the semiconductor substrate 1 of a first thickness within the first region. The range of the first region is equal to the range of the second polar region B. Etching the first region forms a first opening G1, which exposes the second surface S2. The distance between the first surface S1 and the third surface S3 is greater than the distance between the second surface S2 and the third surface S3. Removing a certain thickness of the semiconductor substrate 1 ensures that no substrate doped layer 3 remains.

[0132] As an example, a portion of the insulating layer 4 can be removed first using laser etching, ink printing, or other methods; then, the first doped semiconductor layer 2-2, the first passivation layer 2-1, and the substrate doped layer 3 can be removed in the area without the insulating layer 4 using wet chemical etching. The wet chemical etching also includes the simultaneous removal of the first functional layer 2 deposited on the front side or around the front edge and the insulating layer 4, exposing the mask M1; and then the mask M1 is removed.

[0133] like Figure 6 As shown, the portion of insulating layer 4 facing the first surface S1 can be retained, thereby forming insulation between the first functional layer 2 and the second functional layer 5 in subsequent processes. Alternatively, as... Figure 7 As shown, the portion of the insulating layer 4 opposite to the first surface S1 can also be removed, thereby improving the passivation at the interface between the first polar region A and the second polar region B. Hereinafter, Figure 6 The structure shown is used as a basis for preparation.

[0134] In some embodiments, the etching solution used in wet chemical etching may include an alkaline polishing solution. This allows for the simultaneous removal of the substrate doped layer 3 and polishing of the second surface S2, creating a polished surface and reducing surface defects.

[0135] like Figure 8 As shown, a second functional layer 5 is formed on the back surface of the semiconductor substrate 1, covering the first functional layer 2. A second passivation layer 5-1 and a second doped semiconductor layer 5-2 are fabricated on the back surface of the semiconductor substrate 1 using LPCVD (low-pressure chemical vapor deposition) or PECVD (plasma-enhanced chemical vapor deposition). The second passivation layer 5-1 comprises intrinsic amorphous silicon with a thickness ranging from 1 nm to 15 nm, such as 1 nm, 10 nm, or 15 nm. The second doped semiconductor layer 5-2 comprises doped amorphous silicon and / or microcrystalline silicon with a thickness ranging from 1 nm to 60 nm, such as 1 nm, 30 nm, or 60 nm. The doping type of the second doped semiconductor layer 5-2 is opposite to that of the first doped semiconductor layer 2-2.

[0136] In some embodiments, after forming the second functional layer 5 on the back surface of the semiconductor substrate 1, the process may further include: sequentially forming a third functional layer 6 and an antireflection layer 7 on the light-receiving surface of the semiconductor substrate 1. The third functional layer 6 and the antireflection layer 7 may also be formed using LPCVD (low-pressure chemical vapor deposition) or PECVD (plasma-enhanced chemical vapor deposition). The third functional layer 6 comprises at least one of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped thin-film silicon, silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The antireflection layer 7 comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and a transparent conductive oxide.

[0137] like Figure 9 As shown, the second region in the first polar region A of the semiconductor substrate 1 is etched to remove the second functional layer 5 and the first functional layer 2 of the second thickness within the second region.

[0138] In this embodiment, the second region is smaller than the first polar region A. This is achieved by removing at least the second doped semiconductor layer 5-2, the second passivation layer 5-1, and the second opening G2 of the insulating layer 4 within the second region. The first doped semiconductor layer 2-2 can be removed to a certain thickness to ensure that no residue of the insulating layer 4 remains in the second region. The second doped semiconductor layer 5-2 and the second passivation layer 5-1 can be removed by laser etching, while the insulating layer 4 and / or the laser oxide layer can be removed by wet chemical etching.

[0139] like Figure 10 As shown, a conductive layer 8 is formed on the back surface of the semiconductor substrate 1. The conductive layer 8 covers the first functional layer 2 and the second functional layer 5. Openings are made in each overlapping area of ​​the first functional layer 2 and the second functional layer 5. The openings at least cut off the conductive layer 8 and at most expose the first functional layer 2.

[0140] The conductive layer 8 can be fabricated using physical vapor deposition (PVD) or chemical vapor deposition (CVD), and can be selected from reactive plasma deposition (RPD), magnetron sputtering, pulsed laser deposition (PLD), vacuum evaporation, atomic layer deposition (ALD), etc. The material of the conductive layer 8 includes at least one of zinc oxide, indium oxide, and tin oxide, and it may be doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten, and aluminum. The thickness of the conductive layer 8 ranges from 10 nm to 150 nm, such as 10 nm, 50 nm, or 150 nm.

[0141] A third opening G3 is formed by etching openings in the overlapping regions of the first functional layer 2 and the second functional layer 5 using laser etching, ink printing, and / or wet chemical etching. The third opening G3 at least truncates the conductive layer 8 and at most exposes the first doped semiconductor layer 2-2. The conductive layer 8 is divided into a first conductive layer 8-1 and a second conductive layer 8-2 by the third opening G3. In the first direction D1, the first conductive layer 8-1 is located above the second opening G2 and extends to both sides, and the second conductive layer 8-2 is located above the first opening G1 and extends to both sides.

[0142] like Figure 11 As shown, electrodes in contact with the conductive layer 8 are formed in the first region and the second region, respectively. The first electrode 9 is located on the side of the conductive layer 8-1 away from the semiconductor substrate 1, and the second electrode 10 is located on the side of the conductive layer 8-2 away from the semiconductor substrate 1. The first electrode 9 and the second electrode 10 can be prepared by methods such as screen printing silver paste, inkjet printing silver paste, or electroplating.

[0143] One embodiment of this application also provides a battery assembly. The battery assembly includes a back-contact solar cell according to the aforementioned method, or includes a back-contact solar cell prepared according to the aforementioned method. The specific structure and principle of the back-contact solar cell, as well as the specific steps of the preparation method, can be referred to the foregoing embodiments, and will not be repeated here.

[0144] According to the battery module of this application, there is less recombination of charge carriers with interface defects in the back contact solar cell, resulting in higher open-circuit voltage and photoelectric conversion efficiency.

[0145] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0146] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for fabricating a back-contact solar cell, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having an opposing light-receiving surface and a back-lighting surface, the back-lighting surface including a first polar region and a second polar region alternately arranged along a first direction; The surface of the semiconductor substrate is treated, including... The light-receiving surface and the back-light-receiving surface of the semiconductor substrate are texturized; A mask is formed on the light-receiving surface of the semiconductor substrate; The backlight surface of the semiconductor substrate is polished, and at the same time, part of the mask is removed; A first functional layer is formed in the first polarity region, including A first functional layer is formed on the back surface of the semiconductor substrate; An insulating layer is formed on the side of the first functional layer away from the semiconductor substrate; Remove the insulating layer located in the first region corresponding to the second polarity region; The first region corresponding to the second polar region of the semiconductor substrate is etched to remove the first functional layer and the semiconductor substrate of the first thickness within the first region, and simultaneously removes the first functional layer and insulating layer deposited on the front side or around the front edge; the first functional layer includes a first passivation layer and a first doped semiconductor layer stacked along the direction away from the semiconductor substrate, and the side surface of the first passivation layer facing the semiconductor substrate is a polished surface; the first passivation layer includes tunneling oxide, and the first doped semiconductor layer includes doped polysilicon; Remove the remaining portion of the mask to form a textured surface on the light-receiving surface, while retaining the insulating layer located in the first polarity region; A second functional layer is formed in the second polarity region; the second functional layer includes a second passivation layer and a second doped semiconductor layer stacked along the direction away from the semiconductor substrate, the side surface of the second passivation layer facing the semiconductor substrate is a polished surface, and the doping type of the first doped semiconductor layer and the doping type of the second doped semiconductor layer are opposite; The second passivation layer comprises intrinsic amorphous silicon, and the second doped semiconductor layer comprises doped amorphous silicon and / or microcrystalline silicon; A second functional layer is formed in the second polarity region, including: A second functional layer is formed on the back surface of the semiconductor substrate, and the second functional layer covers the first functional layer; The second region in the first polar region of the semiconductor substrate is etched to remove the second functional layer, the insulating layer, and the first functional layer of a second thickness within the second region; the range of the second region is smaller than the range of the first polar region. A first polar structure and a second polar structure are respectively formed on the side of the first functional layer away from the semiconductor substrate and on the side of the second functional layer away from the semiconductor substrate.

2. The preparation method according to claim 1, characterized in that, The backlight surface of the semiconductor substrate is polished, and after removing part of the mask, the remaining thickness of the mask is in the range of 10nm-100nm. The material of the mask includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

3. The preparation method according to any one of claims 1-2, characterized in that, Before processing the surface of the semiconductor substrate, the method further includes: The semiconductor substrate is subjected to a gettering process.

4. The preparation method according to claim 3, characterized in that, The gettering process on the semiconductor substrate includes: The damaged layer of the semiconductor substrate is removed by wet etching; The semiconductor substrate is subjected to gettering treatment by high-temperature phosphorus diffusion; The getter layer formed on the semiconductor substrate during the gettering process is removed by wet etching.

5. The preparation method according to any one of claims 1 or 2, characterized in that, The formation of a first polar structure and a second polar structure on the side of the first functional layer away from the semiconductor substrate and the side of the second functional layer away from the semiconductor substrate, respectively, includes: A conductive layer is formed on the back surface of the semiconductor substrate, the conductive layer covering the first functional layer and the second functional layer; Openings are made in each overlapping region of the first functional layer and the second functional layer, the openings at least severing the conductive layer and at most exposing the first functional layer; Electrodes that are in contact with the conductive layer are formed in the first region and the second region, respectively.

6. The preparation method according to claim 1, characterized in that, The first functional layer and the semiconductor substrate of a first thickness in the first region are removed using a wet chemical etching solution, wherein the wet chemical etching solution includes an alkaline polishing solution.

7. The preparation method according to claim 1, characterized in that, After forming the second functional layer on the backlight surface of the semiconductor substrate, the method further includes: A third functional layer and an antireflection layer are sequentially formed on the light-receiving surface of the semiconductor substrate.

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