Semiconductor device and manufacturing method thereof, and electronic device

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof, and an electronic device. The semiconductor device includes a storage unit. The storage unit includes a write transistor and a read transistor. The write transistor includes a write gate extending along a second direction, a write gate dielectric layer surrounding the write gate in sequence, and a write channel layer, and the write channel layer is connected to a write bit line. The read transistor and the write transistor are arranged along a first direction, including a read channel layer, a first gate dielectric layer, a read floating gate, a second gate dielectric layer, and a read control gate. The read channel layer is annular, and the axis of the annular layer extends along the second direction. The first gate dielectric layer and the read floating gate are arranged around the outer side wall of the read channel layer in sequence, and the second gate dielectric layer and the read control gate are located on the outer side wall of the read floating gate in sequence in the third direction. The present invention can facilitate the setting of the read word line on the side of the read transistor, thereby facilitating the reduction of the unit area of ​​the storage unit.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] Based on this, the present application provides a semiconductor device and a manufacturing method thereof, and an electronic device.

[0005] A semiconductor device comprising a memory cell;

[0006] The memory cell comprises: a write transistor and a read transistor;

[0007] The write transistor comprises a write gate extending along the second direction, a write gate dielectric layer and a write channel layer sequentially surrounding the write gate, and the write channel layer is connected to a write bit line;

[0008] The read transistor and the write transistor are arranged in sequence along a first direction, the read transistor includes a read channel layer, a first gate dielectric layer, a read floating gate, a second gate dielectric layer and a read control gate, the read channel layer is annular, the first gate dielectric layer and the read floating gate are arranged in sequence around the outer side wall of the read channel layer, and the second gate dielectric layer and the read control gate are located in sequence on the outer side wall of the read floating gate in a third direction; wherein the read floating gate is connected to the write channel layer, and the read floating gate and the write bit line are arranged at intervals in the first direction, and the first direction, the second direction and the third direction intersect each other.

[0009] In one embodiment, the semiconductor device further includes:

[0010] A substrate, the storage units are stacked on the substrate, the second direction is perpendicular to the substrate, and the first direction and the third direction are parallel to the substrate;

[0011] A stacking layer, located on the substrate and comprising a first dielectric layer and a second dielectric layer alternately stacked;

[0012] A first hole, comprising a first through hole and a plurality of first lateral holes spaced apart from each other, wherein the first through hole penetrates the stacked layer along a second direction, the plurality of first lateral holes spaced apart from each other are recessed from the first through hole toward the plurality of second dielectric layers, the first lateral hole is connected to the first through hole, and the read floating gate, the first gate dielectric layer and the read channel layer are sequentially arranged in the first lateral hole;

[0013] A second hole is sequentially arranged with the first hole along the first direction, comprising a second through hole and a plurality of second lateral holes spaced apart from each other, the first through hole penetrates the stacked layer along the second direction, a plurality of second lateral holes spaced apart from each other are recessed from the second through hole to a plurality of second dielectric layers, the second lateral hole is connected to the second through hole, and the second lateral hole is connected to the first lateral hole, and the write channel layer and the write gate dielectric layer are sequentially arranged in the second lateral holes;

[0014] a write word line, located in the second through hole, and the write gates of the plurality of write transistors stacked in the second direction are part of the write word line;

[0015] a third hole, penetrating the stacked layer along the second direction, and located between two adjacent first holes in the third direction, and the third hole is spaced apart from the first holes;

[0016] A read word line is located in the third hole, the read control gates of the plurality of read transistors stacked in the second direction are a part of the read word line, and the read word line is located between adjacent read transistors in the third direction.

[0017] In one embodiment, the semiconductor device further includes:

[0018] A reference signal line is located in the first through hole, the read channel layer surrounds the outer side wall of the reference signal line, the first gate dielectric layer surrounds the outer side wall of the read channel layer, and the first gate dielectric layer has a first opening in a region away from the write transistor in the first direction, the read floating gate surrounds the outer side wall of the first gate dielectric layer and is insulated from the reference signal line, and the read floating gate has a second opening on a side away from the write transistor in the first direction, and the first opening and the second opening expose the read channel layer;

[0019] A first groove is located on a side of the first hole away from the second hole and extends along a third direction, and the first groove includes a first isolation groove and a plurality of first lateral grooves spaced apart from each other in the second direction, the first isolation groove penetrates the stacked layer along the second direction, the plurality of first lateral grooves spaced apart from each other extend laterally from the first isolation groove, and the first lateral groove exposes the reading channel layer in an area corresponding to the first opening and the second opening;

[0020] The read bit line is located in the first lateral groove and connected to the read channel layer exposed by the first lateral groove.

[0021] In one embodiment, the second gate dielectric layer includes a gate insulating layer located on an inner wall of the third hole, and the gate insulating layer surrounds a side wall of the read word line.

[0022] In one embodiment, the first gate dielectric layer is also located on the sidewall and bottom of the first through hole.

[0023] In one embodiment, the reference signal line includes an extension portion and a protrusion portion, the extension portion is located in the first through hole, and the protrusion portion is located in the first lateral hole.

[0024] In one embodiment,

[0025] The first lateral groove exposes the reading floating gate in the area corresponding to the second opening;

[0026] The semiconductor device further comprises:

[0027] The first isolation structure is located between the first dielectric layers and between the read bit line and the read floating gate, and the first isolation structure shields the read floating gate exposed by the first lateral groove to isolate the read floating gate from the read bit line.

[0028] In one embodiment,

[0029] Two storage units adjacent to each other in a first direction are arranged in mirror symmetry;

[0030] The semiconductor device further includes a second isolation structure, which is located in the first isolation trench and isolates the read bit lines corresponding to two adjacent storage cells.

[0031] In one embodiment, the semiconductor device further includes:

[0032] a second groove, located at a side of the second hole away from the first hole in the first direction and extending along a third direction, the second groove comprising a second isolation groove and a plurality of second lateral grooves spaced apart from each other in the second direction, the second isolation groove penetrating the stacked layer along the second direction, and the plurality of second lateral grooves spaced apart from each other extending laterally from the second isolation groove to the write channel layer;

[0033] a write bit line, located in the second lateral groove;

[0034] The third isolation structure is located in the second isolation groove; the third isolation structure isolates the write bit lines corresponding to two adjacent storage cells.

[0035] In the above-mentioned semiconductor device, while the read transistor and the write transistor are arranged along the first direction, the read word line is formed on one side of the read floating gate in the third direction, and the third direction intersects with the first direction, so that a read control gate can be formed on the side of the read transistor, thereby effectively reducing the unit area of ​​the storage unit.

[0036] A method for manufacturing a semiconductor device, comprising:

[0037] Providing a substrate, and forming a stacked material layer on the substrate, wherein the stacked material layer includes a first dielectric material layer and a second dielectric material layer that are alternately stacked;

[0038] Etching the stacked material layer to form a plurality of first holes, wherein the orthographic projections of the plurality of first holes on the substrate are distributed in a plurality of rows and columns, the row direction is a first direction, and the column direction is a third direction, the first holes include a first through hole and a plurality of mutually spaced first lateral holes, the first through hole penetrates the stacked material layer along a second direction, the plurality of mutually spaced first lateral holes are recessed from the first through hole to the plurality of second dielectric material layers, and the first lateral holes are connected to the first through hole;

[0039] In the first lateral hole, a read floating gate, a first gate dielectric layer and a read channel layer are sequentially formed, wherein the read floating gate and the read channel layer in different layers of the first lateral hole are isolated from each other;

[0040] Between two adjacent first holes in the third direction, the stacked material layer is etched along the second direction to form a third hole, and a read word line is formed in the third hole, wherein the read word line is spaced apart from the read floating gate, the second direction is a direction perpendicular to the substrate, and the third direction is a direction parallel to the substrate;

[0041] Etching the stacked material layer to form a second hole corresponding to each first hole, wherein the first hole and the corresponding second hole are sequentially arranged along a first direction; the second hole comprises a second through hole and a plurality of second lateral holes spaced apart from each other, the second through hole penetrates the stacked material layer along a second direction, the plurality of second lateral holes spaced apart from each other are recessed from the second through hole to the plurality of second dielectric material layers, the second lateral hole is connected to the second through hole, and the second lateral hole is connected to the first lateral hole in a first direction, the first direction being a direction parallel to the substrate and intersecting with the third direction;

[0042] A write channel layer and a write gate dielectric layer are sequentially formed in the second lateral hole, and a write word line is formed in the second through hole. The outer sidewalls of the write channel layer are respectively connected to a read floating gate and a write bit line. The read floating gate and the write bit line are spaced apart.

[0043] In one embodiment, forming a read floating gate, a first gate dielectric layer, and a read channel layer in sequence in the first lateral hole includes:

[0044] Depositing a floating gate material layer, a first gate dielectric material layer and a reading channel layer in sequence in the first lateral hole;

[0045] On a side of the first hole away from the second hole, etching the stacked material layer to form a first groove extending along the third direction, the first groove comprising a first isolation groove and a plurality of mutually spaced first lateral grooves, the first isolation groove penetrating the stacked material layer along the second direction, the plurality of mutually spaced first lateral grooves extending laterally from the first isolation groove to the floating gate material layer in the first hole;

[0046] The floating gate material layer and the first gate dielectric material layer are sequentially etched from the first lateral groove to form a read floating gate with a second opening and the first gate dielectric layer with a first opening.

[0047] In one embodiment, after depositing the floating gate material layer, the first gate dielectric material layer and the reading channel layer in sequence in the first lateral hole, the method further comprises:

[0048] and filling a reference signal line in the first through hole, wherein the reference signal line is insulated from the floating gate material layer and electrically connected to each of the reading channel layers;

[0049] After the floating gate material layer and the first gate dielectric material layer are sequentially etched from the first lateral groove to form a read floating gate having a second opening and the first gate dielectric layer having a first opening, the method comprises:

[0050] forming a read bit line insulated from the read floating gate in the first lateral groove;

[0051] A second isolation structure is formed in the first isolation trench.

[0052] In one embodiment, sequentially depositing a floating gate material layer, a first gate dielectric material layer, and a read channel layer in the first lateral hole includes:

[0053] Depositing a floating gate initial material layer along the first through hole wall and the first lateral hole wall;

[0054] forming a sacrificial layer only in the first lateral holes to expose the floating gate initial material layer on the first dielectric material layer between the first lateral holes;

[0055] Using the sacrificial layer as an etching stop layer, removing the exposed floating gate initial material layer, and the floating gate initial material layer in the first lateral hole forms the floating gate material layer;

[0056] The sacrificial layer is removed, and a first gate dielectric material layer is deposited on the surface of the floating gate material layer and the hole wall of the first through hole;

[0057] The reading channel layers spaced apart from each other are formed in each of the first lateral holes.

[0058] In one embodiment, after forming the read floating gate having the second opening and the first gate dielectric layer having the first opening, the read channel layer protrudes from the first opening and the second opening toward the first isolation trench;

[0059] The read bit line formed in the first lateral groove and insulated from the read floating gate comprises:

[0060] forming a first isolation structure material layer on the inner wall of the first isolation trench and the structure surface exposed in the first lateral trench;

[0061] removing the first isolation structure material layer located on the inner wall of the first isolation groove and the side wall of the reading channel layer to form a first isolation structure extending along the third direction;

[0062] A read bit line is formed in the first lateral trench after the first isolation structure is formed.

[0063] In one embodiment, etching the stacked material layer to form a first groove extending along the third direction on a side of the first hole away from the second hole comprises:

[0064] forming the first isolation groove on a side of the first hole away from the second hole in the first direction;

[0065] The second dielectric material layer is laterally etched from the first isolation trench to form the first lateral trenches symmetrically on both sides of the first isolation trench in the first direction.

[0066] In one embodiment, before forming a read word line in the third hole, the method includes:

[0067] A gate insulating layer is formed on the hole wall of the third hole.

[0068] In one embodiment, after sequentially forming a write channel layer and a write gate dielectric layer in the second lateral hole and forming a write word line in the second through hole, the method further comprises:

[0069] Etching the stacked material layer to form a second groove extending along a third direction on a side of the second hole away from the first hole in the first direction, the second groove comprising a second isolation groove and a plurality of second lateral grooves spaced from each other, the second isolation groove penetrating the stacked material layer along the second direction, and the plurality of second lateral grooves spaced from each other in the second direction extending laterally from the second isolation groove to the writing channel layer;

[0070] forming a write bit line in the second lateral groove;

[0071] A third isolation structure is formed in the second isolation trench.

[0072] An embodiment of the present application provides an electronic device, comprising the semiconductor device described in any of the above embodiments.

[0073] In the manufacturing method of the semiconductor device, a read floating gate, a first gate dielectric layer, and a read channel layer of a read transistor are formed in the first hole. A write transistor is formed in a second hole arranged along a first direction with the first hole. A read word line is formed in a third hole located on one side of the first hole in a third direction. At this time, a read control gate can be formed on the side of the read transistor, thereby effectively reducing the unit area of ​​the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0075] Figure 1 is a flow chart of a method for manufacturing a storage structure provided in an embodiment;

[0076] Figure 2 for Figure 1Flow chart of step S31 in FIG.

[0077] Figure 3-Figure 18 Schematic diagram of the structure obtained in each step of the preparation process of the storage structure provided in one embodiment, and in each figure, (a) is a top view, (b) is a cross-sectional view, and (c) is a cross-sectional view;

[0078] Fig.19 It is a schematic diagram of the three-dimensional structure of a storage structure provided in an embodiment.

[0079] 100-substrate, 200-stacked layer, 210-first dielectric layer, 220-second dielectric layer, 2001-stacked material layer, 2101-first dielectric material layer, 2201-second dielectric material layer, 300-read transistor, 3101-floating gate material layer, 3102-floating gate initial material layer, 3201-first gate dielectric material layer, 310-read floating gate, 320-first gate dielectric layer, 330-read channel layer, 410-read word line, 411-third diffusion barrier layer, 412-third metal layer, 420-reference signal line, 421-first diffusion Barrier layer, 422-first metal layer, 430-read bit line, 431-second diffusion barrier layer, 432-second metal layer, 500-write transistor, 510-write gate dielectric layer, 520-write channel layer, 610-write bit line, 620-write word line, 700-sacrificial layer, 8101-first isolation structure material layer, 810-first isolation structure, 820-second isolation structure, 830-third isolation structure, 11-first through hole, 12-first lateral hole, 13-third hole, 21-first isolation groove, 22-first lateral groove, 30-storage unit. DETAILED DESCRIPTION

[0080] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0081] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0082] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0083] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0084] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0085] The relevant structures of the embodiments of the present invention should not be limited to the specific shapes shown in the drawings of the specification, but include shape deviations due to, for example, manufacturing technology. The shapes shown in the drawings are schematic in nature and do not limit the scope of the present invention.

[0086] In one embodiment, see Figure 1 , a method for manufacturing a semiconductor device is provided, comprising the following steps:

[0087] Step S10, see Figure 3 , providing a substrate 100, and forming a stacked material layer 2001 on the substrate 100, the stacked material layer 2001 including a first dielectric material layer 2101 and a second dielectric material layer 2201 which are alternately stacked.

[0088] Step S20, please continue to refer to Figure 3 , etching the stacked material layer to form a plurality of first holes, wherein the orthographic projections of the plurality of first holes on the substrate are distributed in a plurality of rows and columns (e.g. Figure 3 The first holes are arranged in two rows and two columns, the row direction is the first direction, the column direction is the third direction, the first holes include a first through hole and a plurality of first lateral holes spaced apart from each other, the first through hole penetrates the stacked material layer along the second direction, the plurality of first lateral holes spaced apart from each other are recessed from the first through hole to the plurality of second dielectric material layers, and the first lateral holes are connected to the first through hole;

[0089] The first through hole and the first lateral hole are formed successively, and the aperture of the first through hole in the second direction is consistent. In the actual manufacturing process, the first through hole can be obtained by dry etching.

[0090] The first lateral hole is obtained by laterally etching the second dielectric material layer after forming the first through hole.

[0091] Step S30, see Fig.11 , a reading floating gate, a first gate dielectric layer and a reading channel layer are formed in sequence in the first lateral hole 12, wherein the reading floating gates and the reading channel layers in different layers of the first lateral holes are isolated from each other; the first lateral hole 12 includes side walls parallel to the substrate and side walls perpendicular to the substrate, and the reading floating gate, the first gate dielectric layer and the reading channel layer are all film layers, and the main surfaces of the film layers are deposited on the side walls parallel to the substrate and the side walls perpendicular to the substrate in the first lateral hole 12.

[0092] Step S50, see Fig.16 as well as Fig.17 , between two first holes adjacent to each other in the third direction, the stacked material layer 2001 is etched along the second direction to form a third hole 13, and a read word line 410 is formed in the third hole 13, the read word line 410 is insulated from the read floating gate 310, the second direction is a direction perpendicular to the substrate, and the third direction is a direction parallel to the substrate; the third hole 13 and the first hole include a stacked first dielectric material layer 2101 and a second dielectric material layer 2201.

[0093] Step S60, etching the stacked material layer 2001 to form a second hole arranged along the first direction with the first hole, the second hole including a second through hole and a plurality of second lateral holes spaced apart from each other, the second through hole passing through the stacked material layer along the second direction, the plurality of second lateral holes spaced apart from each other are recessed from the second through hole toward the plurality of second dielectric material layers, the second lateral hole is connected to the second through hole, and the second lateral hole is connected to the first lateral hole in the first direction, the first direction is a direction parallel to the substrate and intersects with the third direction.

[0094] As an example, the first hole and the second hole can be arranged in the form of a periodic cycle ABBA (such as ABBAABBA) in the first direction. A and B represent the first hole and the second hole respectively. The first hole and the second hole are arranged in this way, and every two adjacent AB or BA are included in a storage unit. Of course, the first hole and the second hole can also be arranged in the form of a periodic cycle AB (such as ABABABAB) in the first direction.

[0095] Step S70, see Fig.18 A write channel layer 520 and a write gate dielectric layer 510 are sequentially formed in each second lateral hole, and a write word line 620 is formed in the second through hole. The outer side walls of the write channel layer 520 are respectively connected to the read floating gate 310 and the write bit line 610, and the read floating gate 310 and the write bit line 610 are distributed at intervals.

[0096] In step S10, refer to Figure 3 The substrate 100 may be a single-layer structure or a multi-layer structure.

[0097] For example, the substrate 100 may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for another example, the substrate 100 may also include a substrate such as Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator.

[0098] In some cases, the substrate 100 may also include structures such as logic circuits, which are omitted because they are not closely related to the invention of this solution.

[0099] The first dielectric material layer 2101 and the second dielectric material layer 2201 may be alternately stacked on the substrate 100 by deposition or other processes, thereby forming a stacked material layer 2001. The materials of the first dielectric material layer 2101 and the second dielectric material layer 2201 may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc. The materials of the first dielectric material layer 2101 and the second dielectric material layer 2201 are different. As an example, the material of the first dielectric material layer 2101 may be set to play an isolation role, which may be silicon oxide, and the material of the second dielectric material layer 2201 may play a role as a sacrificial layer, which may be silicon nitride.

[0100] In step S20, please continue to refer to Figure 3 As an example, the stacked material layer 2001 may be first etched along the second direction to form a first through hole 11 penetrating the stacked material layer 2001. Then, the second dielectric material layer 2201 may be laterally etched from the first through hole 11 to form a first lateral hole 12.

[0101] Of course, in other examples, the formation method of the first through hole 11 and the first lateral hole 12 is not limited to this. For example, during the etching process of the stacked material layer 2001, the first dielectric material layer 2101 can be anisotropically etched vertically, while the second dielectric material layer 2201 can be isotropically etched by changing the etching conditions. Therefore, after the etching of the first dielectric material layer 2101 and the second dielectric material layer 2201 is completed, the first through hole 11 penetrating the stacked material layer 2001 along the second direction and the first lateral hole 12 recessed from the first through hole 11 to the second dielectric material layer 2201 are formed.

[0102] In step S30, the material of the read floating gate 310 is a conductive material, such as titanium nitride. The material of the first gate dielectric layer 320 may include but is not limited to oxide or nitride. The material of the read channel layer 330 may include but is not limited to semiconductor materials such as polysilicon and metal oxide.

[0103] The read floating gate 310 and the read channel layer 330 are located in the first lateral hole 12 , and are insulated from the read floating gate 310 and the read channel layer 330 in different layers of the first lateral hole 12 .

[0104] As an example, step S30 may include:

[0105] Step S31, depositing a floating gate material layer, a first gate dielectric material layer and a reading channel layer in sequence in the first lateral hole;

[0106] Step S32, etching the stacked material layer on a side of the first hole away from the second hole to form a first groove extending along a third direction, the first groove comprising a first isolation groove and a plurality of mutually spaced first lateral grooves, the first isolation groove penetrating the stacked material layer along the second direction to expose the stacked first and second dielectric material layers, and transversely etching each second dielectric material layer to obtain a plurality of mutually spaced first lateral grooves, the first lateral grooves exposing the floating gate material layer;

[0107] Step S33 , etching the floating gate material layer and the first gate dielectric material layer in sequence from the first lateral groove to form an opening, specifically, forming a read floating gate with a second opening and a first gate dielectric layer with a first opening.

[0108] See also Fig. 9 In step S31, a floating gate material layer 3101 may be first formed on the hole wall of the first lateral hole 12. Then, a first gate dielectric material layer 3201 may be formed on the surface of the floating gate material layer 3101. Then, a reading channel layer 330 may be formed on the surface of the first gate dielectric material layer 3201.

[0109] After forming the read channel layer 330 in step S31, a reference signal line 420 may be filled in the first through hole 11, so that the reference signal line 420 is electrically connected to each read channel layer 330. The reference signal line 420 is insulated from the floating gate material layer 3101, so as to prevent the reference signal line 420 from being short-circuited with the read floating gate 310 subsequently formed by the floating gate material layer 3101. The material of the reference signal line 420 is a conductive material. The reference signal line 420 may be a single-layer structure or a multi-layer structure.

[0110] The reference signal line 420 may include, for example, a first diffusion barrier layer 421 and a first metal layer 422. The first diffusion barrier layer 421 may block metal diffusion in the first metal layer 422. The material of the first diffusion barrier layer 421 may include, but is not limited to, titanium nitride, etc., and the material of the first metal layer 422 may include, but is not limited to, metal tungsten, etc.

[0111] At this time, a first diffusion barrier layer 421 may be first formed on the surface of the first gate dielectric material layer 3201 located on the hole wall of the first through hole 11 and on the surface of the reading channel layer 330. Then, a first metal material layer filling the first through hole 11 is formed on the surface of the first diffusion barrier layer 421 and above the stacked material layer 2001. Afterwards, the first metal material layer is subjected to chemical mechanical polishing to remove the first metal material layer located above the stacked material layer 2001, thereby forming a first metal layer 422.

[0112] When the reading channel material layer is recessed at the portion opposite to the first lateral hole 12, the reading channel layer 330 formed by the reading channel material layer in the first lateral hole 12 is also recessed at the portion opposite to the first lateral hole 12. At this time, after the reference signal line 420 is formed, the reference signal line 420 includes an extension portion and a protrusion portion, the extension portion is located in the first through hole, the protrusion portion is located in the first lateral hole, and protrudes from the extension portion to the recessed area in the reading channel layer 330. At this time, the contact area between the reference signal line 420 and the reading channel layer 330 can be effectively increased, thereby reducing the contact resistance between the two.

[0113] In step S32, refer to Fig.10 , the stacked material layer 2001 may be first etched on one side of the reference signal line 420 in the first direction to form a first isolation trench 21 penetrating the stacked material layer 2001 and extending along the third direction, wherein the first isolation trench 21 is spaced apart from the floating gate material layer 3101. Then, refer to Fig.11 , the second dielectric material layer 2201 is laterally etched from the first isolation trench 21 to form a first lateral trench 22 .

[0114] In step S33, the floating gate material layer 3101 in the first lateral hole 12 exposed by the first lateral groove 22 is etched to expose the first gate dielectric material layer 3201, and the first gate dielectric material layer 3201 is etched to expose the reading channel layer 330, forming an etched floating gate material layer 3101 and the first gate dielectric material layer 3201, forming a reading floating gate 310 with a second opening and a first gate dielectric layer 320 with a first opening.

[0115] The first gate dielectric layer 320 and the read floating gate 310 are located in the first lateral hole 12, and include side walls extending in a direction perpendicular to the substrate and side walls extending in a direction parallel to the substrate. The side walls surround the first lateral hole 12, and the first opening and the second opening are respectively located on part of the side walls extending in a direction perpendicular to the substrate on the corresponding film layer.

[0116] After step S33, the following steps may also be included:

[0117] Step S41, forming a read bit line insulated from the read floating gate 310 in the first lateral trench 22;

[0118] Step S42 , forming a second isolation structure 820 in the first isolation trench 21 .

[0119] The plurality of memory cells stacked vertically are respectively connected to different read bit lines 430 .

[0120] The read channel layer 330 between the read bit line 430 and the reference signal line 420 may serve as a channel region of the read transistor 300 .

[0121] The second isolation structure 820 is an insulating isolation layer, which can be used to isolate the memory cells in the first direction.

[0122] See also Fig.14 The read bit line 430 may be formed in the first lateral groove 22 extending along the third direction, thereby extending along the third direction. The material of the read bit line 430 is a conductive material, which may be a single-layer structure or a multi-layer structure.

[0123] The read bit line 430 may include a second diffusion barrier layer 431 and a second metal layer 432. The second diffusion barrier layer 431 may block metal diffusion in the second metal layer 432. The material of the second diffusion barrier layer 431 may include but is not limited to titanium nitride, and the material of the second metal layer 432 may include but is not limited to metal tungsten.

[0124] As an example, the material of the read channel layer 330 may include polysilicon, and the material of the read bit line 430 may include a metal material. Before forming the read bit line 430, a metal silicide may be formed on the surface of the read channel layer 330 to reduce the contact resistance between the read channel layer 330 and the read bit line 430.

[0125] In step S50, refer to Fig.16 A third hole 13 is formed on one side of the read floating gate 310 in the third direction and is spaced apart from the read floating gate 310. The read bit line extends along the third direction, the first hole where the reference signal line is located is spaced apart from the third hole in the third direction, and the third hole is closer to the read bit line.

[0126] Then, see Fig.17 A second gate dielectric layer and a read word line 410 are formed in the third hole 13 . Since the third hole 13 and the read floating gate 310 are spaced apart, the read word line 410 formed in the third hole 13 and the read floating gate 310 are spaced apart.

[0127] A read word line material layer may be first formed on the hole wall (side wall and bottom) of the third hole 13 and on the stacked material layer 2001, and then the read word line material layer formed on the stacked material layer 2001 may be removed by a chemical mechanical polishing process on the read word line material layer, thereby forming a read word line 410. The read word line 410 may include a third diffusion barrier layer 411 and a third metal layer 412.

[0128] The read word line 410 and the read floating gate 310 are both disposed on the outer sidewall of the read channel layer 330, and the read floating gate 310 is located between the read word line 410 and the read channel layer 330. The read floating gate stores charges, and the read word line 410 controls the read floating gate at the side of the read floating gate to read the charges.

[0129] The previous steps form a read transistor 300, which includes two gates, one of which is a read floating gate, and the read floating gates of the read transistors 300 of the stacked multiple memory cells are insulated from each other. The other of the two gates is a read control gate, which is a part of the read word line 410. The other gate (read control gate) of the read transistors 300 of the stacked multiple memory cells is a part of the same read word line 410. That is, the read word line 410 may include the read control gates of the multiple read transistors 300 stacked along the second direction. A second gate dielectric layer and a stack material layer are included between the read control gate and the read floating gate 310.

[0130] For example, the second dielectric material layer 2201 between the read word line 410 and the read floating gate 310 may also be used as the second gate dielectric layer of the read transistor 300 .

[0131] Alternatively, a gate insulating layer may be formed on the wall of the third hole 13 first, and then the read word line 410 may be formed. In this case, the gate insulating layer and the second dielectric material layer 2201 between the read word line 410 and the read floating gate 310 may serve as the second gate dielectric layer.

[0132] Based on this, the read transistor 300 includes a read control gate, a second gate dielectric layer, a read floating gate 310 , a first gate dielectric layer 320 and a read channel layer 330 .

[0133] The material of the read word line 410 is a conductive material, which may be a single-layer structure or a multi-layer structure.

[0134] As an example, the read word line 410 may include a third diffusion barrier layer 411 and a third metal layer 412. The third diffusion barrier layer 411 may block metal diffusion in the third metal layer 412. The material of the third diffusion barrier layer 411 may include but is not limited to titanium nitride, etc., and the material of the third metal layer 412 may include but is not limited to metal tungsten, etc.

[0135] In step S60, refer to Fig.18 The stacked material layer 2001 may be first etched along the second direction to form a second through hole, and then the second dielectric material layer 2201 may be etched laterally from the second through hole using the read floating gate 310 as an etching stop layer to form a second lateral hole.

[0136] In step S70, refer to Fig.18, a writing channel layer 520 may be first formed on the second lateral hole wall. The material of the writing channel layer 520 may include, for example, indium gallium zinc oxide (IGZO). It should be noted that the material of the write channel layer 520 can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other metal oxide semiconductor layers, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.

[0137] Then, a write gate dielectric layer 510 is formed on the surface of the write channel layer 520 and the hole wall (including the side wall and the bottom wall) of the second through hole. The material of the write gate dielectric layer 510 may include silicon oxide, silicon nitride, silicon oxynitride, etc. The material of the write gate dielectric layer 510 may be the same as the material of the first dielectric material layer 2101. Of course, the two may also be different.

[0138] Afterwards, a write word line 620 with a single-layer structure or a multi-layer structure may be formed in the second through hole.

[0139] The write word line 620 may include, for example, a fourth diffusion barrier layer and a fourth metal layer. The fourth diffusion barrier layer may block metal diffusion in the fourth metal layer. The material of the fourth diffusion barrier layer may include, but is not limited to, titanium nitride, etc., and the material of the fourth metal layer may include, but is not limited to, metal tungsten, etc.

[0140] At this time, the write transistor 500 may be formed after the read transistor 300 is formed. Of course, the write transistor 500 may also be formed before the read transistor 300 is formed, or formed simultaneously with the read transistor 300, which is not limited here.

[0141] The write transistor 500 includes a write gate, a write gate dielectric layer 510 and a write channel layer 520 which are sequentially arranged around the write gate. The write gates of the plurality of write transistors 500 stacked in the second direction are part of the write word line. The write transistor 500 is a channel-all-around transistor, and the write channel layer 520 surrounds the sidewall of the write word line to form a closed ring shape.

[0142] The write transistor 500 and the read transistor 300 may be included in a 2T0C memory cell 30 , and the charge reading process of the floating gate is effectively controlled by the read word line 410 (read control gate) to realize the reading of storage information 0 and 1.

[0143] In the method of this embodiment, a read floating gate, a first gate dielectric layer, and a read channel layer of a read transistor are formed in the first hole. A write transistor 500 is formed in a second hole arranged along the first direction with the first hole. And a read word line is formed in a third hole located on one side of the first hole in the third direction. At this time, a read control gate can be formed on the side of the read transistor 300, so that the unit area of ​​the memory cell 30 can be effectively reduced. In the embodiment of the present application, each memory cell includes a read transistor and a write transistor arranged in sequence in the first direction; two adjacent memory cells in the first direction are distributed in mirror symmetry. The two memory cells distributed in mirror symmetry are periodically distributed in the first direction, and each memory cell distributed in the first direction is periodically distributed in the third direction. Each layer of memory cells includes the above-mentioned memory cells distributed in the first direction and the third direction. Each layer of memory cells is periodically stacked and distributed in the second direction.

[0144] In one embodiment, see Figure 2 , step S31 comprises:

[0145] Step S311, see Figure 4 , forming a floating gate initial material layer 3102 along the hole wall of the first through hole 11 and the hole wall of the first lateral hole 12;

[0146] Step S312, see Figure 5 , forming a sacrificial layer 700 in the first lateral hole 12;

[0147] Step S313, see Figure 6 , using the sacrificial layer 700 as an etching stop layer, removing the floating gate initial material layer 3102 outside the first lateral hole 12 to form a floating gate material layer 3101;

[0148] Step S314, see Figure 7 , removing the sacrificial layer 700 , and forming a first gate dielectric material layer 3201 on the surface of the floating gate material layer 3101 and the hole wall of the first through hole 11 ;

[0149] Step S315, see Figure 8 , forming a reading channel layer 330 in the first lateral hole 12;

[0150] In step S311, refer to Figure 4, a floating gate initial material layer 3102 with a thickness of 4 nm to 6 nm (eg, 5 nm) can be formed on the wall of the first through hole 11 and the wall of the first lateral hole 12 in one process by atomic layer deposition or the like.

[0151] In step S312, refer to Figure 5 , a sacrificial material layer may be first formed on the surface of the floating gate initial material layer 3102. The sacrificial material layer may fill the first lateral hole 12. For example, a sacrificial material layer with a thickness of 18 nm to 22 nm (eg, 20 nm) may be formed.

[0152] Then, the sacrificial material layer outside the first lateral hole 12 may be removed. For example, a sacrificial material layer with a thickness of 21 nm to 25 nm (such as 23 nm) may be removed to form a sacrificial layer 700 located in the first lateral hole 12. The material of the sacrificial layer 700 may include, but is not limited to, polysilicon.

[0153] It is understandable that the specific thicknesses of the floating gate initial material layer 3102, sacrificial material layer and other film layers in this article can be set according to actual conditions. The above thicknesses are only listed and do not constitute a limitation to the present application.

[0154] In step S313, refer to Figure 6 , using the sacrificial layer 700 as an etching barrier layer, after etching the floating gate initial material layer 3102 , the remaining floating gate initial material layer 3102 forms a floating gate material layer 3101 .

[0155] In step S314, refer to Figure 7 After removing the sacrificial layer 700, the floating gate material layer 3101 in the first lateral hole 12 is exposed. Afterwards, a first gate dielectric material layer 3201 may be formed on the hole wall of the first through hole 11 and on each surface of the floating gate material layer 3101 by an atomic layer deposition process or the like. The thickness of the first gate dielectric material layer 3201 may be, for example, 5 nm to 7 nm (e.g., 6 nm). The material of the first gate dielectric material layer 3201 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0156] As an example, the material of the first gate dielectric material layer 3201 may be the same as the material of the first dielectric material layer 2101 .

[0157] In step S315, refer to Figure 8 , a reading channel material layer may be first formed on the surface of the first gate dielectric material layer 3201 by a deposition process, etc. The thickness of the reading channel material layer may be, for example, 9 nm to 11 nm (eg, 10 nm).

[0158] As an example, the thickness of the reading channel material layer may be controlled so that the reading channel material layer is recessed at a portion opposite to the first lateral hole 12 .

[0159] Then, the reading channel material layer outside the first lateral hole 12 is etched away, while the reading channel material layer inside the first lateral hole 12 is not etched away because it is blocked by the first dielectric material layer 2101. The remaining reading channel material layer inside the first lateral hole 12 forms a reading channel layer 330. The thickness of the etching removal may be 11 nm-13 nm (e.g., 12 nm).

[0160] In this embodiment, the first gate dielectric material layer 3201 is formed simultaneously on the surface of the floating gate material layer 3101 in the first lateral hole 12 and the hole wall of the first through hole 11, so that after the reference signal line 420 is subsequently formed, the reference signal line 420 and the floating gate material layer 3101 can be insulated from each other by the first gate dielectric material layer 3201 located on the side wall of the first through hole 11. At the same time, the first gate dielectric material layer 3201 located on the bottom wall of the first through hole 11 can effectively insulate and isolate the reference signal line 420 from the substrate 100.

[0161] At this time, after the floating gate material layer 3101 is subsequently etched to form the read floating gate 310, and the first gate dielectric material layer 3201 is etched to form the first gate dielectric layer 320, the formed read floating gate 310 and the reference signal line 420 can be effectively insulated by the first gate dielectric layer 320 located on the side wall of the first through hole 11. And the reference signal line 420 can be effectively insulated from the substrate 100 by the first gate dielectric layer 320 located on the bottom wall of the first through hole 11.

[0162] Of course, in other embodiments, the insulation isolation between the read floating gate 310 and the reference signal line 420 can also be achieved by other methods. For example, when forming the read floating gate 310, a sacrificial layer 700 that exposes a portion of the sidewall of the first lateral hole 12 close to the first through hole 11 can be prepared, and then the floating gate initial material layer 3102 is etched using the sacrificial layer 700 as an etching stop layer to form a floating gate material layer 3101, and the floating gate material layer 3101 exposes a portion of the sidewall of the first lateral hole 12 close to the first through hole 11. Afterwards, even if the first gate dielectric material layer 3201 is formed only in the first lateral hole 12, the first gate dielectric material layer 3201 (the first gate dielectric layer 320 formed after the subsequent etching step) on the sidewall of the first lateral hole 12 can also insulate and isolate the read floating gate 310 from the reference signal line 420.

[0163] In one embodiment, see Fig.11 After forming the read floating gate 310 with the second opening and the first gate dielectric layer 320 with the first opening in step S40 , the read channel layer 330 protrudes from the first opening and the second opening toward the first isolation trench 21 .

[0164] At this time, when etching from the first isolation groove 21 to form the first lateral groove 22, after etching the floating gate material layer 3101 and the first gate dielectric material layer 3201 to expose the reading channel layer 330, the floating gate material layer 3101 and the first gate dielectric material layer 3201 can continue to be etched for a period of time, so that the reading channel layer 330 protrudes from the first opening and the second opening toward the direction of the first isolation groove 21.

[0165] Meanwhile, step S41 includes:

[0166] Step S411, see Fig.12 , forming a first isolation structure material layer 8101 on the inner wall of the first isolation trench 21 and the exposed structure surface in the first lateral trench 22;

[0167] Step S412, see Fig.13 , removing the first isolation structure material layer 8101 located on the inner wall of the first isolation trench 21 and the side wall of the reading channel layer 330 to form a first isolation structure 810 extending along the third direction;

[0168] Step S4133, please refer to Fig.14 , a read bit line 430 is formed in the first lateral trench 22 after the first isolation structure 810 is formed.

[0169] In step S411, refer to Fig.12 A first isolation structure material layer 8101 can be formed on the stacked material layer 2001, the inner wall of the first isolation groove 21, and the exposed structure surface in the first lateral groove 22 by processes such as atomic layer deposition.

[0170] At the same time, the read channel layer 330 protrudes from the first opening and the second opening toward the first isolation groove 21. Therefore, in the region between the read channel layer 330 and the first dielectric material layer 2101 above and below it, as the deposition thickness of the first isolation structure material layer 8101 increases, the first isolation structure material layer 8101 formed on the surface of the read channel layer 330 and the first isolation structure material layer 8101 formed on the surface of the first dielectric material layer 2101 can be connected to each other and have a longer length in the first direction. The thickness of the first isolation structure material layer 8101 can be, for example, 4nm-6nm (such as 5nm).

[0171] Then, the first isolation structure material layer 8101 located above the stacked material layer 2001 is removed by chemical mechanical polishing process, etc. At this time, the read floating gate 310 , the first gate dielectric layer 320 and the read channel layer 330 exposed in the first lateral groove 22 are all covered by the first isolation structure material layer 8101 .

[0172] The material of the first isolation structure material layer 8101 may include but is not limited to silicon oxide, silicon nitride, etc. As an example, the material of the first isolation structure material layer 8101 may be the same as the material of the first dielectric material layer 2101, or they may be different.

[0173] In step S412, refer to Fig.13 , the first isolation structure material layer 8101 located on the hole wall of the first isolation groove 21 and the side wall of the reading channel layer 330 can be removed by an isotropic etching process. As described above, the first isolation structure material layer 8101 filled in the area between the reading channel layer 330 and the first dielectric material layer 2101 above and below it has a longer length. Therefore, this part of the first isolation structure material layer 8101 may remain after etching, thereby forming a first isolation structure 810 extending along the third direction.

[0174] As an example, the etching removal thickness of the first isolation structure material layer 8101 may be 5 nm-7 nm (eg, 6 nm).

[0175] In step S413, refer to Fig.14 As an example, the read bit line 430 may include a second diffusion barrier layer 431 and a second metal layer 432 .

[0176] When the reading channel layer 330 is polysilicon, a metal silicide may be first formed on the surface of the reading channel layer 330 exposed in the first lateral groove 22. Then, a second diffusion barrier material layer is formed along the exposed structural surface of the first isolation groove 21 and the first lateral groove 22, and then a second metal material layer is formed on the surface of the second diffusion barrier material layer. Afterwards, the second diffusion barrier material layer and the second metal material layer are etched to remove the second diffusion barrier material layer and the second metal material layer outside the first lateral groove 22, so as to form a second diffusion barrier layer 431 and a second metal layer 432.

[0177] In this embodiment, when the first lateral groove 22 is formed by etching from the first isolation groove 21, the read channel layer 330 is exposed from the first opening and the second opening toward the first isolation groove 21, so that the first isolation structure 810 extending along the third direction can be formed in the region between the read channel layer 330 and the first dielectric material layer 2101 above and below it. At this time, the read floating gate 310 and the read bit line 430 can be effectively insulated and isolated by the first isolation structure 810.

[0178] Of course, in other embodiments, the insulation isolation between the read floating gate 310 and the read bit line 430 can also be achieved by other methods. For example, after forming the read floating gate 310 with the second opening and the first gate dielectric layer 320 with the first opening in step S40, the read channel layer 330 protrudes from the first opening and the second opening toward the first isolation groove 21, and then the read bit line 430 is formed by adjusting the appropriate deposition method and deposition conditions, so that an air gap is formed between the read bit line 430 and the read floating gate 310. Alternatively, in some embodiments, the surface layer between the invalid read floating gates or parasitic read floating gates between the read floating gates 310 of the effective transistors can also be oxidized to achieve insulation isolation between the read floating gates 310 of the effective transistors and the read floating gates 310, and the insulation isolation region is an isolation region formed by the parasitic floating gates through oxidation insulation.

[0179] In one embodiment, step S32 etches the stacked material layer on a side of the first hole away from the second hole to form a first groove extending along a third direction, including:

[0180] Step S321, see Fig.10 , forming a first isolation groove 21 on a side of the first hole away from the second hole in the first direction;

[0181] Step S322, see Fig.11 The second dielectric material layer is laterally etched from the first isolation trench 21 to form first lateral trenches 22 symmetrically on both sides of the first isolation trench 21 in the first direction.

[0182] At this time, two columns of memory cells 30 symmetrically arranged along the first direction may be formed. The read bit lines 430 of the two columns of memory cells 30 may be formed based on the same first isolation trench 21, thereby effectively improving the storage density.

[0183] In one embodiment, see Fig.18 , step S70 sequentially forms a write channel layer and a write gate dielectric layer in the second lateral hole, and after forming a write word line in the second through hole, further comprising:

[0184] Step S81, etching the stacked material layer 2001 to form a second groove extending along a third direction on a side of the second hole away from the first hole in the first direction, the second groove including a second isolation groove and a plurality of second lateral grooves spaced apart from each other, the second isolation groove penetrates the stacked material layer along the second direction, the plurality of second lateral grooves spaced apart from each other extend laterally from the second isolation groove to the write channel layer, the remaining first dielectric material layer 2101 after etching forms a first dielectric layer 210, the remaining second dielectric material layer 2201 forms a second dielectric layer 220, and the second dielectric layer 220 and the first dielectric layer 210 form a stacked layer 200;

[0185] Step S82, forming a write bit line 610 in the second lateral groove;

[0186] Step S83 , forming a third isolation structure 830 in the second isolation trench.

[0187] In step S81, the stacked material layer 2001 may be etched first to form a second isolation trench extending along the third direction, and then the second dielectric material layer 2201 may be etched from the second isolation trench to form a second lateral trench.

[0188] In step S82 , a write bit line 610 with a single-layer structure or a multi-layer structure may be formed in the second lateral groove.

[0189] In step S83, the third isolation structure 830 may be formed by deposition or other processes. The material of the third isolation structure 830 may include silicon oxide, silicon nitride, silicon oxynitride, etc. The material of the third isolation structure 830 may be the same as that of the second dielectric layer 220. Of course, the two may also be different.

[0190] The third isolation structure 830 is made of insulating material, and the third isolation structure 830 and the second isolation structure 820 are respectively located on both sides of the memory cell 30 in the first direction, thereby isolating the memory cell. The third isolation structure 830 and the second isolation structure 820 extend along the third direction, thereby isolating the memory cells in the same column arranged along the third direction between the third isolation structure 830 and the second isolation structure 820 in each layer of memory cells.

[0191] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0192] In one embodiment, a semiconductor device is also provided. Fig.18 as well as Fig.19 , the semiconductor device includes a memory cell 30 .

[0193] The memory cell 30 includes a read transistor 300 and a write transistor 500 sequentially arranged along a first direction.

[0194] The write transistor 500 includes a write gate extending along the second direction, a write gate dielectric layer 510 and a write channel layer 520. The write gate dielectric layer 510 surrounds the write gate. The write channel layer 520 surrounds the write gate dielectric layer 510. The write channel layer 520 is connected to the write bit line 610.

[0195] The material of the write gate is a conductive material, for example, a metal material (such as metal tungsten), etc. The material of the write gate dielectric layer 510 may include but is not limited to oxide or nitride, etc. The write channel layer 520 may include but is not limited to a metal oxide semiconductor layer, such as semiconductor materials such as indium gallium zinc oxide (IGZO). It should be noted that the material of the metal oxide semiconductor layer can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements. The specific details can be adjusted according to the actual situation.

[0196] The read transistor and the write transistor are arranged in sequence along a first direction.

[0197] The read transistor 300 includes a read channel layer 330, a first gate dielectric layer 320, a read floating gate 310, a second gate dielectric layer, and a read control gate, which are arranged in sequence from the inside to the outside. Fig.19 In the perspective view shown, the read channel layer 330 is wrapped by the first gate dielectric layer 320, so Fig.19 The read channel layer 330 is not shown.

[0198] The material of the read channel layer 330 may include but is not limited to semiconductor materials such as polysilicon or metal oxide semiconductor materials. The material of the first gate dielectric layer 320 may include but is not limited to oxides or nitrides, etc., and may be a low-K material or a high-K material. The material of the read floating gate 310 is a conductive material, such as titanium nitride. The material of the second gate dielectric layer may include but is not limited to oxides or nitrides. The material of the read control gate is a conductive material, such as a metal material (such as metal tungsten).

[0199] The read channel layer 330 is annular, and the axis of the annular shape extends along the second direction. The first gate dielectric layer 320 is arranged around the outer side wall of the read channel layer 330. The read floating gate 310 is arranged around the outer side wall of the first gate dielectric layer 320. The second gate dielectric layer is located on the outer side wall of the read floating gate in the third direction. The read control gate is located on the side of the second gate dielectric layer away from the read floating gate in the third direction. The read floating gate 310 is connected to the write channel layer 520 in the first direction and is spaced apart from the write bit line 610. The first direction, the second direction and the third direction intersect each other, for example, the three directions are perpendicular to each other.

[0200] In this embodiment, while the read transistor 300 and the write transistor are arranged along the first direction, the read word line 410 is formed on one side of the read floating gate 310 in the third direction, and the third direction intersects with the first direction, so that a read control gate can be formed on the side of the read transistor 300, thereby effectively reducing the unit area of ​​the storage cell 30.

[0201] In one embodiment, the semiconductor device further includes a substrate 100, a stacked layer 200, a write word line 620, and a read word line 410. The semiconductor device further includes a first hole, a second hole, and a third hole.

[0202] The memory cells are stacked on the substrate 100 . The second direction is perpendicular to the substrate 100 , and the first direction and the third direction are parallel to the substrate 100 .

[0203] The stacked layer 200 is located on the substrate 100, and includes alternately stacked first dielectric layers 210 and second dielectric layers 220. The materials of the first dielectric layer 210 and the second dielectric layer 220 may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride. The materials of the first dielectric layer 210 and the second dielectric layer 220 are different. As an example, the material of the first dielectric layer 210 may be silicon oxide, and the material of the second dielectric layer 220 may be silicon nitride.

[0204] The first hole includes a first through hole 11 and a plurality of mutually spaced first lateral holes 12. The first through hole 11 penetrates the stacked layer 200 along the second direction. The plurality of mutually spaced first lateral holes 12 are recessed from the first through hole 11 to the plurality of second dielectric layers 220. The first lateral hole 12 is connected to the first through hole 11. The read floating gate 310, the first gate dielectric layer 320 and the read channel layer 330 are sequentially disposed in the first lateral hole 12.

[0205] The second hole is arranged with the first hole along the first direction. The second hole includes a second through hole and a plurality of second lateral holes spaced apart from each other. The second through hole includes a through hole that penetrates the stacked layer 200 along the second direction. The plurality of second lateral holes spaced apart from each other are recessed from the second through hole to the plurality of second dielectric layers 220. The second lateral hole is connected to the second through hole. The second lateral hole is connected to the first lateral hole in the first direction. The write channel layer 520 and the write gate dielectric layer 510 are sequentially arranged in the second lateral hole. Therefore, the write channel layer 520 can be connected to the read floating gate 310.

[0206] The write word line 620 is located in the second through hole, and the write gates of the plurality of write transistors 500 stacked in the second direction are part of the write word line.

[0207] The third hole penetrates the stacked layer 200 along the second direction and is located between two adjacent first holes in the third direction. The third hole is spaced apart from the first holes.

[0208] The read word line 410 is located in the third hole. The read control gates of the plurality of read transistors 300 stacked in the second direction are part of the read word line 410. And the read word line 410 is located between adjacent read transistors 300 in the third direction.

[0209] In one embodiment, the semiconductor device further includes a reference signal line 420 and a read bit line 430 , and includes a first trench.

[0210] The reference signal line 420 is located in the first through hole 11, and the read channel layer 330 surrounds the outer side wall of the reference signal line 420. The first gate dielectric layer 320 surrounds the outer side wall of the read channel layer 330. The first gate dielectric layer 320 has a first opening in a region away from the write transistor 500 in the first direction. The read floating gate 310 surrounds the outer side wall of the first gate dielectric layer 320 and is insulated from the reference signal line 420. The read floating gate 310 has a second opening on a side away from the write transistor 500 in the first direction. The first opening and the second opening expose the read channel layer 330.

[0211] The first groove is located on a side of the first hole away from the second hole. The first groove extends along the third direction. The first groove includes a first isolation groove 21 and a plurality of mutually spaced first lateral grooves 22. The first isolation groove 21 penetrates the stacked layer along the second direction. The plurality of mutually spaced first lateral grooves 22 extend laterally from the first isolation groove 21, and the first lateral groove 22 exposes the reading channel layer 330 in the area corresponding to the first opening and the second opening.

[0212] The read bit line 430 is located in the first lateral trench 22 and connected to the read channel layer 330 exposed by the first lateral trench 22 .

[0213] A second isolation structure 820 may be disposed in the first isolation trench 21 .

[0214] In one embodiment, the second gate dielectric layer includes the second dielectric layer 220 between the read word line 410 and the read floating gate 310 and a gate insulating layer located on the inner wall of the third hole. The gate insulating layer surrounds the sidewall of the read word line 410 .

[0215] In other embodiments, the second gate dielectric layer may also only include the second dielectric layer 220 between the read word line 410 and the read floating gate 310. In this case, only the read word line 410 is formed in the third hole, and the second gate dielectric layer does not need to be separately provided, thereby simplifying the process.

[0216] In one embodiment, the first gate dielectric layer 320 is located not only in the first lateral hole 12 , but also on the sidewall and bottom of the first through hole 11 . That is, the first gate dielectric layer 320 extends from the first lateral hole 12 to the sidewall and bottom of the first through hole 11 .

[0217] At this time, the first gate dielectric layer 320 can effectively isolate the reference signal line 420 from the read channel layer 330 on one hand, and can effectively isolate the reference signal line 420 from the substrate 100 below the memory cell 30 on the other hand.

[0218] In one embodiment, the reference signal line 420 includes an extension portion and a protrusion portion. The extension portion is located in the first through hole 11. The protrusion portion is located in the first lateral hole 12 and protrudes from the extension portion into the reading channel layer 330. In this case, the contact area between the reference signal line 420 and the reading channel layer 330 can be effectively increased, thereby reducing the contact resistance between the two.

[0219] In one embodiment, the semiconductor device further includes a first isolation structure 810. The first isolation structure 810 is located between the first dielectric layers 210 and between the read bit line 430 and the read floating gate 310 in the first direction. The first isolation structure 810 covers the end of one side of the read floating gate 310 having the second opening and the end of one side of the first gate dielectric layer 210 having the first opening.

[0220] As an example, the first isolation structure 810 may extend along the third direction.

[0221] The material of the first isolation structure 810 layer may include but is not limited to silicon oxide, silicon nitride, etc. As an example, the material of the first isolation structure 810 layer may be the same as the material of the first dielectric layer 210 , and of course the two may also be different.

[0222] In this embodiment, the read bit line 430 can be effectively insulated and isolated from the read floating gate 310 by the first isolation structure 810 .

[0223] In one embodiment, the semiconductor device further includes a second isolation structure 820. The second isolation structure 820 is located in the first isolation trench 21. Therefore, the second isolation structure 820 extends along the third direction and penetrates the stacked layer 200. Two columns of memory cells 30 are symmetrically arranged on opposite sides of the second isolation structure 820 in the first direction.

[0224] The material of the second isolation structure 820 layer may include but is not limited to silicon oxide, silicon nitride, etc. As an example, the material of the second isolation structure 820 layer may be the same as the material of the second dielectric layer 220, but they may also be different.

[0225] In one embodiment, the semiconductor further includes a second trench, a write bit line 610 , and a third isolation structure 830 .

[0226] The second groove is located on a side of the second hole away from the first hole in the first direction and extends along the third direction. The second groove includes a second isolation groove and a plurality of second lateral grooves spaced apart from each other. The second isolation groove penetrates the stacked layer along the second direction, and the plurality of second lateral grooves spaced apart from each other extend laterally from the second isolation groove to the write channel layer.

[0227] The write bit line 610 is located in the second lateral trench. The third isolation structure 830 is located in the second isolation trench.

[0228] In one embodiment, an electronic device is also provided, comprising one or more semiconductor devices as in the above embodiments. The electronic device includes, for example, data storage devices, copiers, network devices, household appliances, instruments, mobile phones, computers and other devices with data storage functions. The electronic device may include a housing and a circuit board arranged in the housing, a memory or a data read-write circuit integrated on the circuit board. The structure of the memory can refer to the relevant description in some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited in the embodiments of the present disclosure.

[0229] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0230] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: including storage units; The memory cell comprises: a write transistor and a read transistor; The write transistor comprises a write gate extending along the second direction, a write gate dielectric layer and a write channel layer sequentially surrounding the write gate, and the write channel layer is connected to a write bit line; The read transistor and the write transistor are arranged in sequence along a first direction, the read transistor includes a read channel layer, a first gate dielectric layer, a read floating gate, a second gate dielectric layer and a read control gate, the read channel layer is annular, the first gate dielectric layer and the read floating gate are arranged in sequence around the outer side wall of the read channel layer, and the second gate dielectric layer and the read control gate are located in sequence on the outer side wall of the read floating gate in a third direction; wherein the read floating gate is connected to the write channel layer, and the read floating gate and the write bit line are arranged at intervals in the first direction, and the first direction, the second direction and the third direction intersect each other.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: A substrate, the storage units are stacked on the substrate, the second direction is perpendicular to the substrate, and the first direction and the third direction are parallel to the substrate; A stacking layer, located on the substrate and comprising a first dielectric layer and a second dielectric layer alternately stacked; A first hole, comprising a first through hole and a plurality of first lateral holes spaced apart from each other, wherein the first through hole penetrates the stacked layer along a second direction, the plurality of first lateral holes spaced apart from each other are recessed from the first through hole toward the plurality of second dielectric layers, the first lateral hole is connected to the first through hole, and the read floating gate, the first gate dielectric layer and the read channel layer are sequentially arranged in the first lateral hole; A second hole is sequentially arranged with the first hole along the first direction, comprising a second through hole and a plurality of second lateral holes spaced apart from each other, the second through hole penetrates the stacked layer along the second direction, a plurality of second lateral holes spaced apart from each other are recessed from the second through hole to a plurality of second dielectric layers, the second lateral hole is connected to the second through hole, and the second lateral hole is connected to the first lateral hole, and the write channel layer and the write gate dielectric layer are sequentially arranged in the second lateral hole; A write word line is located in the second through hole, and a plurality of the write transistors are stacked along the second direction; and among the plurality of the write transistors stacked along the second direction, the write gate of each of the write transistors is a part of the write word line, and the write gates of different write transistors are different parts of the same write word line; a third hole, penetrating the stacked layer along the second direction, and located between two adjacent first holes in the third direction, and the third hole is spaced apart from the first holes; A read word line is located in the third hole, and a plurality of the read transistors are stacked along the second direction; and among the plurality of the read transistors stacked along the second direction, the read control gate of each of the read transistors is a part of the read word line, and the read control gates of different read transistors are different parts of the same read word line; and the read word line is located between adjacent read transistors in the third direction.

3. The semiconductor device according to claim 2, characterized in that The semiconductor device further comprises: A reference signal line is located in the first through hole, the read channel layer surrounds the outer side wall of the reference signal line, the first gate dielectric layer surrounds the outer side wall of the read channel layer, and the first gate dielectric layer has a first opening in a region away from the write transistor in the first direction, the read floating gate surrounds the outer side wall of the first gate dielectric layer and is insulated from the reference signal line, and the read floating gate has a second opening on a side away from the write transistor in the first direction, and the first opening and the second opening expose the read channel layer; A first groove is located on a side of the first hole away from the second hole and extends along a third direction, and the first groove includes a first isolation groove and a plurality of first lateral grooves spaced apart from each other in the second direction, the first isolation groove penetrates the stacked layer along the second direction, the plurality of first lateral grooves spaced apart from each other extend laterally from the first isolation groove, and the first lateral groove exposes the reading channel layer in an area corresponding to the first opening and the second opening; The read bit line is located in the first lateral groove and connected to the read channel layer exposed by the first lateral groove.

4. The semiconductor device according to claim 2 or 3, characterized in that: The second gate dielectric layer includes a gate insulating layer located on an inner wall of the third hole, and the gate insulating layer surrounds a side wall of the read word line.

5. The semiconductor device according to claim 2 or 3, characterized in that: The first gate dielectric layer is also located on the sidewall and bottom of the first through hole.

6. The semiconductor device according to claim 3, characterized in that The reference signal line includes an extension portion and a protrusion portion, the extension portion is located in the first through hole, and the protrusion portion is located in the first lateral hole.

7. The semiconductor device according to claim 3, characterized in that The first lateral groove exposes the reading floating gate in the area corresponding to the second opening; The semiconductor device further comprises: The first isolation structure is located between the first dielectric layers and between the read bit line and the read floating gate, and the first isolation structure shields the read floating gate exposed by the first lateral groove to isolate the read floating gate from the read bit line.

8. The semiconductor device according to claim 3, characterized in that Two storage units adjacent to each other in a first direction are arranged in mirror symmetry; The semiconductor device further includes a second isolation structure, which is located in the first isolation trench and isolates the read bit lines corresponding to two adjacent storage cells.

9. The semiconductor device according to claim 8, characterized in that The semiconductor device further comprises: a second groove, located at a side of the second hole away from the first hole in the first direction and extending along a third direction, the second groove comprising a second isolation groove and a plurality of second lateral grooves spaced apart from each other in the second direction, the second isolation groove penetrating the stacked layer along the second direction, and the plurality of second lateral grooves spaced apart from each other extending laterally from the second isolation groove to the write channel layer; a write bit line, located in the second lateral groove; The third isolation structure is located in the second isolation groove; the third isolation structure isolates the write bit lines corresponding to two adjacent storage cells.

10. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, and forming a stacked material layer on the substrate, wherein the stacked material layer includes a first dielectric material layer and a second dielectric material layer that are alternately stacked; Etching the stacked material layer to form a plurality of first holes, wherein the orthographic projections of the plurality of first holes on the substrate are distributed in a plurality of rows and columns, the row direction is a first direction, and the column direction is a third direction, the first holes include a first through hole and a plurality of mutually spaced first lateral holes, the first through hole penetrates the stacked material layer along a second direction, the plurality of mutually spaced first lateral holes are recessed from the first through hole to the plurality of second dielectric material layers, and the first lateral holes are connected to the first through hole; In the first lateral hole, a read floating gate, a first gate dielectric layer and a read channel layer are sequentially formed, wherein the read floating gate and the read channel layer in different layers of the first lateral hole are isolated from each other; Between two adjacent first holes in the third direction, the stacked material layer is etched along the second direction to form a third hole, and a read word line is formed in the third hole, wherein the read word line is spaced apart from the read floating gate, the second direction is a direction perpendicular to the substrate, and the third direction is a direction parallel to the substrate; Etching the stacked material layer to form a second hole corresponding to each first hole, wherein the first hole and the corresponding second hole are sequentially arranged along a first direction; the second hole comprises a second through hole and a plurality of second lateral holes spaced apart from each other, the second through hole penetrates the stacked material layer along a second direction, the plurality of second lateral holes spaced apart from each other are recessed from the second through hole to the plurality of second dielectric material layers, the second lateral hole is connected to the second through hole, and the second lateral hole is connected to the first lateral hole in a first direction, the first direction being a direction parallel to the substrate and intersecting with the third direction; A write channel layer and a write gate dielectric layer are sequentially formed in the second lateral hole, and a write word line is formed in the second through hole. The outer sidewalls of the write channel layer are respectively connected to a read floating gate and a write bit line. The read floating gate and the write bit line are spaced apart.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The method sequentially forms a read floating gate, a first gate dielectric layer and a read channel layer in the first lateral hole, including: Depositing a floating gate material layer, a first gate dielectric material layer and a reading channel layer in sequence in the first lateral hole; On a side of the first hole away from the second hole, etching the stacked material layer to form a first groove extending along the third direction, the first groove comprising a first isolation groove and a plurality of mutually spaced first lateral grooves, the first isolation groove penetrating the stacked material layer along the second direction, the plurality of mutually spaced first lateral grooves extending laterally from the first isolation groove to the floating gate material layer in the first hole; The floating gate material layer and the first gate dielectric material layer are sequentially etched from the first lateral groove to form a read floating gate with a second opening and a first gate dielectric layer with a first opening.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: After sequentially depositing a floating gate material layer, a first gate dielectric material layer and a reading channel layer in the first lateral hole, the method further includes: and filling a reference signal line in the first through hole, wherein the reference signal line is insulated from the floating gate material layer and electrically connected to each of the reading channel layers; After the floating gate material layer and the first gate dielectric material layer are sequentially etched from the first lateral groove to form a read floating gate having a second opening and the first gate dielectric layer having a first opening, the method comprises: forming a read bit line insulated from the read floating gate in the first lateral groove; A second isolation structure is formed in the first isolation trench.

13. The method for manufacturing a semiconductor device according to claim 11, wherein: The method of sequentially depositing a floating gate material layer, a first gate dielectric material layer and a reading channel layer in the first lateral hole comprises: Depositing a floating gate initial material layer along the hole wall of the first through hole and the hole wall of the first lateral hole; forming a sacrificial layer only in the first lateral holes to expose the floating gate initial material layer on the first dielectric material layer between the first lateral holes; Using the sacrificial layer as an etching stop layer, removing the exposed floating gate initial material layer, and the floating gate initial material layer in the first lateral hole forms the floating gate material layer; The sacrificial layer is removed, and a first gate dielectric material layer is deposited on the surface of the floating gate material layer and the hole wall of the first through hole; The reading channel layers spaced apart from each other are formed in each of the first lateral holes.

14. The method for manufacturing a semiconductor device according to claim 11, wherein: After forming a read floating gate having a second opening and the first gate dielectric layer having a first opening, the read channel layer protrudes from the first opening and the second opening toward the first isolation groove; The read bit line formed in the first lateral groove and insulated from the read floating gate comprises: forming a first isolation structure material layer on the inner wall of the first isolation trench and the structure surface exposed in the first lateral trench; removing the first isolation structure material layer located on the inner wall of the first isolation groove and the side wall of the reading channel layer to form a first isolation structure extending along the third direction; A read bit line is formed in the first lateral trench after the first isolation structure is formed.

15. The method for manufacturing a semiconductor device according to claim 11, wherein: The step of etching the stacked material layer on a side of the first hole away from the second hole to form a first groove extending along the third direction comprises: forming the first isolation groove on a side of the first hole away from the second hole in the first direction; The second dielectric material layer is laterally etched from the first isolation trench to form the first lateral trenches symmetrically on both sides of the first isolation trench in the first direction.

16. The method for manufacturing a semiconductor device according to claim 10, wherein: Before forming a read word line in the third hole, the method includes: A gate insulating layer is formed in the third hole.

17. The method for manufacturing a semiconductor device according to claim 10, wherein: After sequentially forming a write channel layer and a write gate dielectric layer in the second lateral hole and forming a write word line in the second through hole, the method comprises: Etching the stacked material layer to form a second groove extending along a third direction on a side of the second hole away from the first hole in the first direction, the second groove comprising a second isolation groove and a plurality of second lateral grooves spaced from each other, the second isolation groove penetrating the stacked material layer along the second direction, and the plurality of second lateral grooves spaced from each other in the second direction extending laterally from the second isolation groove to the writing channel layer; forming a write bit line in the second lateral groove; A third isolation structure is formed in the second isolation trench.

18. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 9.

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