A neural network computing acceleration structure based on an on-chip optical network

Abstract

The application relates to the technical field of neural network acceleration and on-chip optical network interconnection, for example to a neural network calculation acceleration structure based on an on-chip optical network. First, through decomposition of a neural network specific operation unit module, according to a neural network module-node mapping scheme, mapping distribution of the operation unit module and on-chip optical network physical nodes is completed, and a neural network calculation acceleration top-layer architecture based on the on-chip optical network is constructed; subsequently, through design of an on-chip optical network optoelectronic hybrid interconnection structure, on-chip optical network bottom-layer physical implementation is completed, and the characteristics of high speed and low consumption interconnection between the on-chip optical network physical nodes are fully utilized. In the running process of the application scheme, on the one hand, the operation nodes are relatively independent, can be fully scheduled for flow processing, parallel calculation is realized, and the overall computing power is improved; on the other hand, the excellent characteristics of the on-chip optical network in transmission delay and transmission power consumption can be fully utilized, power consumption is reduced, bandwidth is improved, and the neural network calculation acceleration effect is improved.

Description

Technical Field

[0001] This application relates to the fields of neural network acceleration and on-chip optical network interconnection technology, for example, to a neural network computing acceleration structure based on on-chip optical networks. Background Technology

[0002] Currently, Network-on-Chip (NoC) technology, which incorporates computer networking technology into system-on-chip (SoC) design, is gradually replacing traditional buses and becoming the most commonly used communication architecture in SoC design due to its superior advantages in scalability and routing flexibility. In particular, the increasingly popular Optical Network-on-Chip (ONoC) technology, which uses optical interconnects to replace traditional electrical connections, offers superior performance in addressing issues such as signal crosstalk, parasitic capacitance, transmission power consumption, and transmission delay.

[0003] In the field of artificial intelligence, neural networks, due to their superior performance in learning ability, feature extraction, big data mining, and nonlinear mapping, have been widely used to solve various problems such as image recognition, autonomous driving, and control optimization. At present, relatively mature commercial devices such as graphics processing units (GPUs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs) provide strong computational support for the development of neural networks.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art:

[0005] As the scale of neural networks increases, these accelerators have gradually shown problems such as communication latency and high energy consumption.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0008] This disclosure provides a neural network computing acceleration structure based on on-chip optical networks to solve the above-mentioned technical problems.

[0009] In some embodiments, the structure includes:

[0010] Neural networks operate in three layers: an instruction layer, a data layer, and an operation layer. The instruction layer determines the neural network features that need acceleration based on acceleration instruction arbitration, controls the transmission and reception of neural network parameter weight information through a control module, and determines the specific neural network kernel operation functions that need acceleration. The data layer transmits and receives neural network data through a memory module. The operation layer contains the neural network operation kernel functions.

[0011] On-chip optical network: It adopts a 2D mesh network topology, is compatible with routing algorithms, and each network node contains a control unit, a computing unit and a multi-level cache module. Each network node is relatively independent and can execute independent operation tasks in parallel; data of each network node is transmitted through the on-chip optical network link.

[0012] Neural Network-On-Chip Optical Network Node Mapping: The node mapping is a relationship-based ring mapping. The control module and memory module of the neural network are mapped to the center of the on-chip optical network as the mapping base point of the ring mapping scheme. The operation layer of the neural network takes specific kernel function modules as the basic mapping units. According to their pipeline operation priority relationship, the operation kernel modules that can be executed in parallel are mapped to the same vertical dimension, and the pipeline relationship is mapped to the horizontal dimension.

[0013] Preferably, in the on-chip optical network operation node, each operation node performs only one specific kernel operation at a time.

[0014] Preferably, the network nodes of the on-chip optical network are equipped with an L1 / L2 multi-level caching mechanism, wherein the L1 cache has a small capacity and fast memory access, and is local private to the network node; the L2 cache has a relatively large capacity and is shared by multiple network nodes.

[0015] The specific memory access process of the operation node is as follows: First, read and write the L1 cache. When the L1 cache is missed, send a data request to the memory node through the router. The memory node contains shared L2 cache usage information. Query through the memory node and send the data request information to another operation node containing the data information. This operation node then transmits the data information to the requesting data node.

[0016] Preferably, the on-chip optical network control node controls the operating state of the operation nodes. The control node contains logic control instructions, which divide the operating state of each operation node into two modes: parallel execution mode and serial pipeline execution mode. In the parallel mode, each node is relatively independent and located in the same vertical dimension, and can execute its internal operations simultaneously. In the serial mode, each node depends on the front-end data and achieves shortest path pipeline processing through mapping in the same horizontal dimension.

[0017] Preferably, the on-chip optical network adopts an optoelectronic hybrid interconnection system to construct an on-chip optical network system. The electrical module nodes in the network are interconnected by circuits to form the first layer of the topology network, and the optical routers are interconnected by optical waveguides to form the second layer of the topology network. The electrical connection of the first layer is responsible for transmitting control signals with small information volume, and the optical routers associated with the electrical modules are configured to occupy the waveguides. The optical connection of the second layer is responsible for transmitting data information with large information volume.

[0018] Preferably, the information transmission process between network nodes of the on-chip optical network is as follows: the source node performs data fragmentation. One type is control information with a small data volume, which includes destination node information, routing method and other information. This fragment is transmitted to the next-level electrical module through electrical connection first. The other type is data information with a large data volume. This data is transmitted to the optical router through electrical interconnection and then to the next-level optical router through optical waveguide, lagging behind the transmission of control information.

[0019] After data fragmentation is completed, the current electrical module transmits control information to the next level electrical module via routing. The next level electrical module receives the information, configures its corresponding optical router, and constructs a waveguide channel between the two levels of optical routers for data transmission.

[0020] Once the waveguide channel is constructed, a configuration completion signal is fed back through the waveguide path. After receiving the configuration completion signal, the optical router corresponding to the current electrical module starts data information transmission.

[0021] Preferably, the electrical module includes an input buffer module, a data fragmentation module, a routing arbitration module, an error checking module, and an output arbitration module;

[0022] The input buffer module is used to cache input data, which comes from the local computing storage control unit or control information transmitted via an electrical connection link.

[0023] The data sharding module includes a data arbitration function to determine the source of the data: if it comes from the local computing unit, then the control data information is sharded, the data information is passed to the optical routing module for transmission, and the control information is passed to the routing module; if it comes from external electrical connection input information, then it is directly passed to the routing module.

[0024] The routing arbitration module processes the input control information. This module is compatible with routing algorithms. If it determines that the data transmission is complete, and this node is the destination node, the routing module sends a signal to the optical routing module to drive the optical routing module to transmit the data to the error checking module to complete the data verification. If the data transmission is not complete, the control signal is passed to the output buffer according to the routing algorithm.

[0025] The error checking module is used to check the data received by the optical routing module for errors and to determine whether there are any errors in the transmission process.

[0026] The output arbitration module determines whether the output is a local computing unit or an external electrical connection link based on the routing information. If the output is an external electrical module, the configuration information is transmitted to the corresponding optical routing module to construct an optical waveguide channel in that direction.

[0027] Preferably, the optical router operates as follows: When the optical router receives an input signal from the electrical module, the optical router converts the electrical signal into an optical signal via its internal electro-optical converter and optical transmitter;

[0028] An optical waveguide channel is constructed through an optical network control module to manage the routing and control of optical signals, ensuring that the optical signals are transmitted along the required path;

[0029] When an optical signal is received from the optical waveguide path, the optical router determines whether there is a reserved optical waveguide channel. If there is a reserved optical waveguide channel, it means that the node is not the destination node for data transmission, and the optical input signal directly enters the reserved optical waveguide channel through the optical network control module. If there is no reserved optical waveguide channel, it means that the node is the final destination node for data transmission, and the optical signal is input to the optical signal processing module to complete the optical amplification process.

[0030] The optical signal enters the optical signal detection module, completes the conversion from optical signal to electrical signal, and is finally output as an electrical signal to the electrical module node.

[0031] The neural network computing acceleration structure based on on-chip optical networks provided in this disclosure can achieve the following technical effects:

[0032] This invention addresses the communication latency and energy consumption issues exhibited by existing neural network hardware acceleration devices such as GPUs, ASICs, and FPGAs as the scale of neural networks increases. It proposes a neural network computing acceleration scheme based on on-chip optical networks (OBNs). The scheme comprises two parts: a top-level architecture for mapping neural network modules to on-chip optical nodes and a low-level physical implementation for interconnecting on-chip optical networks, thus comprehensively realizing neural network computing acceleration based on on-chip optical networks. During operation, this scheme allows for relatively independent operation of each computing node, enabling efficient pipelined processing and parallel computing, thereby improving overall computing power. Furthermore, it fully leverages the superior characteristics of on-chip optical networks in terms of transmission latency and power consumption, reducing power consumption, increasing bandwidth, and enhancing the acceleration effect of neural network computing.

[0033] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0034] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0035] Figure 1 This is a schematic diagram of the neural network module-on-chip optical network node mapping structure;

[0036] Figure 2 This is a schematic diagram of an on-chip optical network topology based on optoelectronic hybrid interconnection;

[0037] Figure 3 This is a schematic diagram of the electrical module's workflow;

[0038] Figure 4 This is a schematic diagram of the optical router's workflow. Detailed Implementation

[0039] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0040] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0041] Combination Figure 1 A neural network computing acceleration structure based on on-chip optical networks, comprising:

[0042] Neural networks operate in three layers: an instruction layer, a data layer, and an operation layer. The instruction layer determines the neural network features that need acceleration based on acceleration instruction arbitration, controls the transmission and reception of neural network parameter weight information through a control module, and determines the specific neural network kernel operation functions that need acceleration. The data layer transmits and receives neural network data through a memory module. The operation layer contains the neural network operation kernel functions.

[0043] On-chip optical network: It adopts a 2D mesh network topology, is compatible with routing algorithms, and each network node contains a control unit, a computing unit and a multi-level cache module. Each network node is relatively independent and can execute independent operation tasks in parallel; data of each network node is transmitted through the on-chip optical network link.

[0044] Neural Network-On-Chip Optical Network Node Mapping: The node mapping is a relationship-based ring mapping. The control module and memory module of the neural network are mapped to the center of the on-chip optical network as the mapping base point of the ring mapping scheme. The operation layer of the neural network takes specific kernel function modules as the basic mapping units. According to their pipeline operation priority relationship, the operation kernel modules that can be executed in parallel are mapped to the same vertical dimension, and the pipeline relationship is mapped to the horizontal dimension.

[0045] Specifically, each operation node contains all computation modules, facilitating universal node mapping. However, each operation node performs only one specific kernel operation at a time, with multiple operation nodes coordinating to accelerate the entire neural network. This mapping scheme, using specific kernel function modules as the basic mapping unit, helps reduce the computation time of each operation node, fully utilizing the high-speed interconnectivity of on-chip optical networks and improving computational efficiency.

[0046] Specifically, the memory node serves as the base node for the on-chip optical network directory. In this invention, all network nodes incorporate an L1 / L2 multi-level caching mechanism. The L1 cache has a small capacity and fast access speed, and is locally private to the network node; the L2 cache has a relatively large capacity and is shared by multiple network nodes. The specific memory access process for the operating node is as follows: first, it reads and writes to the L1 cache. If an L1 cache miss occurs, a data request is sent to the memory node via the router. The memory node contains shared L2 cache usage information. The operating node queries the memory node and sends the data request information to another operating node containing the data information. This operating node then transmits the data information to the requesting data node. The same process applies when writing neural network-related data. Distributed storage of data information across multiple network nodes effectively improves the utilization of on-chip storage resources. Furthermore, choosing a mapping strategy centered on the memory node helps shorten the link path between the memory node and the operating node, further reducing transmission latency and improving memory access speed.

[0047] Specifically, the control node is responsible for controlling the operational status of the operator nodes. The control node contains logic control instructions that categorize the operational status of each operator node into two modes: parallel execution mode and serial pipelined execution mode. In parallel mode, each node operates relatively independently on the same vertical dimension and can execute its internal operations simultaneously. In serial mode, each node relies on front-end data and is mapped along the same horizontal dimension to achieve shortest path pipelined processing. The control node uniformly schedules and allocates the status of each operator node, ensuring coordinated and orderly operation between parallel and serial modes.

[0048] The overall architecture of the on-chip optical network of the present invention is as follows: Figure 2 As shown, an on-chip optical network system is constructed using a hybrid optoelectronic interconnect architecture. Electrical module nodes in the network are interconnected via circuits, forming the first layer of the topology. Optical routers are interconnected via optical waveguides, forming the second layer of the topology. The electrical connections in the first layer are responsible for transmitting small-volume control signals, while configuring the waveguide occupancy of the optical routers associated with the electrical modules. The optical connections in the second layer are responsible for transmitting larger-volume data information.

[0049] like Figure 2 As shown, taking XY routing as an example, the specific information transmission process from the source node S to the destination node D in the on-chip optical network is as follows: First, the electrical module node S performs data fragmentation. One type is control information with a small data volume, including destination node information, routing method, etc., which is transmitted to the next-level electrical module via electrical connection. The other type is data information with a large data volume, which is transmitted to the optical router via electrical interconnection, and then transmitted to the next-level optical router via optical waveguide, lagging behind the control information transmission. After data fragmentation is completed, the current electrical module transmits control information to the next-level electrical module via routing. The next-level electrical module receives the information and configures its corresponding optical router, establishing a waveguide channel between the two levels of optical routers for data information transmission. Once the waveguide channel is established, a configuration completion signal is fed back through the waveguide path. After receiving the configuration completion signal, the optical router corresponding to the current electrical module starts data information transmission.

[0050] The specific workflow of the electrical module is as follows: Figure 3As shown, the process comprises five steps: input buffering, data fragmentation, routing arbitration, error checking, and output arbitration. The input buffer module buffers input data, which may originate from the local computing, storage, and control unit, or from control information transmitted via an electrical connection link. The data fragmentation module includes a data arbitration function to determine the data source: if it originates from the local computing unit, it further fragments the control data, sending the fragmented data to the optical routing module for transmission, while the control information is sent to the routing module; if it originates from external electrical connection input, it is directly sent to the routing module. The routing module processes the input control information. This module is compatible with advanced industry routing algorithms, achieving efficient, deadlock-free routing. If it determines that data transmission is complete (i.e., the current node is the destination node), the routing module sends a signal to the optical routing module, driving it to transmit data to the error checking module for verification. If data transmission is incomplete, the control signal is sent to the output buffer according to the routing algorithm. The error checking module performs error checking on the data received by the optical routing module, determining whether errors occurred during transmission. The output buffer determines whether the output is from a local computing unit or an external electrical connection link based on the routing information. If the output is from an external electrical module, the configuration information is transmitted to the corresponding optical routing module to construct an optical waveguide channel in that direction.

[0051] The working process of an optical router is as follows: Figure 4 As shown, when an input signal is received from the electrical module, the optical routing module converts the electrical signal to an optical signal via its internal electro-optical converter and optical transmitter. Then, through the optical network control module, it constructs relevant optical waveguide channels to manage and control the routing of the optical signal, ensuring that the optical signal is transmitted along the required path, thus completing the output of the optical signal. When an optical signal is received from the optical waveguide path, the optical routing module checks whether there is a reserved optical waveguide channel. If there is a reserved optical waveguide channel, it means that the node is not the destination node for data transmission, and the optical input signal directly enters the reserved optical waveguide channel via the optical network control module. If there is no reserved optical waveguide channel, it means that the node is the final destination node for data transmission, and the optical input signal enters the optical processing signal, performs optical amplification and other operations, and then enters the optical signal detection module to complete the conversion from optical signal to electrical signal, finally outputting it as an electrical signal to the electrical module node.

[0052] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application refers to any and all possible combinations of one or more of the associated listed elements. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0053] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0054] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0055] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A neural network computing acceleration structure based on on-chip optical networks, characterized in that, include: Neural networks operate in three layers: an instruction layer, a data layer, and an operation layer. The instruction layer determines the neural network features that need acceleration based on acceleration instruction arbitration, controls the transmission and reception of neural network parameter weight information through a control module, and determines the specific neural network kernel operation functions that need acceleration. The data layer transmits and receives neural network data through a memory module. The operation layer contains the neural network operation kernel functions. On-chip optical network: It adopts a 2D mesh network topology, is compatible with routing algorithms, and each network node contains a control unit, a computing unit and a multi-level cache module. Each network node is relatively independent and can execute independent operation tasks in parallel; data of each network node is transmitted through the on-chip optical network link. Neural Network-On-Chip Optical Network Node Mapping: The node mapping is a relationship-based ring mapping. The control module and memory module of the neural network are mapped to the center of the on-chip optical network as the mapping base point of the ring mapping scheme. The operation layer of the neural network takes specific kernel function modules as the basic mapping units. According to their pipeline operation priority relationship, the operation kernel modules that can be executed in parallel are mapped to the same vertical dimension, and the pipeline relationship is mapped to the horizontal dimension.

2. The neural network computing acceleration structure based on on-chip optical networks according to claim 1, characterized in that, The on-chip optical network operation node performs only one specific kernel operation at a time.

3. The neural network computing acceleration structure based on on-chip optical networks according to claim 1, characterized in that, The network nodes of the on-chip optical network are equipped with an L1 / L2 multi-level caching mechanism. The L1 cache has a small capacity and fast memory access, and is local to the network node. The L2 cache has a relatively large capacity and is shared by multiple network nodes. The specific memory access process of the operation node is as follows: First, read and write the L1 cache. When the L1 cache is missed, send a data request to the memory node through the router. The memory node contains shared L2 cache usage information. Query through the memory node and send the data request information to another operation node containing the data information. This operation node then transmits the data information to the requesting data node.

4. The neural network computing acceleration structure based on on-chip optical networks according to claim 1, characterized in that, The on-chip optical network control node controls the operating state of the operation nodes. The control node contains logic control instructions, which divide the operating state of each operation node into two modes: parallel execution mode and serial pipeline execution mode. In the parallel mode, each node is relatively independent and is located in the same vertical dimension, and can execute its internal operations simultaneously. In the serial mode, each node depends on the front-end data and achieves shortest path pipeline processing through mapping in the same horizontal dimension.

5. The neural network computing acceleration structure based on on-chip optical networks according to claim 1, characterized in that, The on-chip optical network adopts a hybrid optoelectronic interconnection system to construct an on-chip optical network system. The electrical module nodes in the network are interconnected by circuits to form the first layer of the topology network. The optical routers are interconnected by optical waveguides to form the second layer of the topology network. The electrical connection of the first layer is responsible for transmitting control signals with small information volume, and the waveguide occupancy is configured by configuring the optical router associated with the electrical module. The optical connection of the second layer is responsible for transmitting data information with large information volume.

6. The neural network computing acceleration structure based on on-chip optical networks according to claim 5, characterized in that, The information transmission process between network nodes of the on-chip optical network is as follows: The source node performs data fragmentation. One type is control information with a small data volume, which includes destination node information, routing method and other information. This fragment is transmitted to the next-level electrical module through electrical connection first. The other type is data information with a large data volume. This data is transmitted to the optical router through electrical interconnection and then to the next-level optical router through optical waveguide, lagging behind the transmission of control information. After data fragmentation is completed, the current electrical module transmits control information to the next level electrical module via routing. The next level electrical module receives the information, configures its corresponding optical router, and constructs a waveguide channel between the two levels of optical routers for data transmission. Once the waveguide channel is constructed, a configuration completion signal is fed back through the waveguide path. After receiving the configuration completion signal, the optical router corresponding to the current electrical module starts data information transmission.

7. The neural network computing acceleration structure based on on-chip optical networks according to claim 6, characterized in that, The electrical module includes an input buffer module, a data fragmentation module, a routing arbitration module, an error checking module, and an output arbitration module; The input buffer module is used to cache input data, which comes from the local computing storage control unit or control information transmitted via an electrical connection link. The data sharding module includes a data arbitration function to determine the source of the data: if it comes from the local computing unit, then the control data information is sharded, the data information is passed to the optical routing module for transmission, and the control information is passed to the routing module; if it comes from external electrical connection input information, then it is directly passed to the routing module. The routing arbitration module processes the input control information. This module is compatible with routing algorithms. If it determines that the data transmission is complete, and this node is the destination node, the routing module sends a signal to the optical routing module to drive the optical routing module to transmit the data to the error checking module to complete the data verification. If the data transmission is not complete, the control signal is passed to the output buffer according to the routing algorithm. The error checking module is used to check the data received by the optical routing module for errors and to determine whether there are any errors in the transmission process. The output arbitration module determines whether the output is a local computing unit or an external electrical connection link based on the routing information. If the output is an external electrical module, the configuration information is transmitted to the corresponding optical routing module to construct an optical waveguide channel in that direction.

8. The neural network computing acceleration structure based on on-chip optical networks according to claim 7, characterized in that, The optical router operates as follows: When the optical router receives an input signal from the electrical module, it converts the electrical signal into an optical signal via an internal electro-optical converter and optical transmitter. An optical waveguide channel is constructed through an optical network control module to manage the routing and control of optical signals, ensuring that the optical signals are transmitted along the required path; When an optical signal is received from the optical waveguide path, the optical router determines whether there is a reserved optical waveguide channel. If there is a reserved optical waveguide channel, it means that the node is not the destination node for data transmission, and the optical input signal directly enters the reserved optical waveguide channel through the optical network control module. If there is no reserved optical waveguide channel, it means that the node is the final destination node for data transmission, and the optical signal is input to the optical signal processing module to complete the optical amplification process. The optical signal enters the optical signal detection module, completes the conversion from optical signal to electrical signal, and is finally output as an electrical signal to the electrical module node.

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