Micro light emitting diode and display device thereof

Abstract

A micro light emitting diode has a semiconductor layer sequence, an insulating layer is covered on the semiconductor layer sequence, the insulating layer includes openings in different positions of the semiconductor layer sequence, and a step structure is formed by arranging the openings of the insulating layer, which cooperates with a metal electrode to improve product yield.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing, specifically relating to micro light-emitting diodes and display devices. Background Technology

[0002] Micro-LEDs (mLEDs) are currently a hot research topic as a next-generation display light source. They boast advantages such as low power consumption, high brightness, ultra-high resolution and color saturation, fast response speed, low energy consumption, and long lifespan. Furthermore, their power consumption is approximately 10% of that of LCDs and 50% of that of OLEDs. Compared to OLEDs, which are also self-emissive, mLEDs offer several times the brightness and can achieve high pixel density. These significant advantages make mLEDs a promising candidate to replace current OLEDs and LCDs as the light source for next-generation displays. However, mLEDs cannot yet be mass-produced due to numerous technical challenges that need to be overcome, one of the most important being improving the yield rate of μm-level LED chips. Summary of the Invention

[0003] To address the issue of process yield in micro-light-emitting diodes (LEDs), such as chip yield or transfer yield, this invention proposes a micro-light-emitting diode that can effectively improve the process yield of micro-light-emitting diodes.

[0004] In one embodiment of the present invention, a micro light-emitting diode is provided, having a semiconductor layer sequence. To clearly define the location, the semiconductor layer sequence includes a front side and a back side disposed opposite to each other. From the front side to the back side, the semiconductor layer sequence sequentially includes: a first type semiconductor layer, a second type semiconductor layer, and an active layer between the two. The back side of the semiconductor layer sequence has a groove that penetrates the second type semiconductor layer and the active layer, exposing the first type semiconductor layer. The back side of the semiconductor layer sequence includes a first mesa within the groove, a second mesa on the second type semiconductor layer, and a groove sidewall located between the two. The back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected to a first type of semiconductor layer and a second metal electrode electrically connected to a second type of semiconductor layer. It also includes an insulating layer covering the semiconductor layer sequence, the insulating layer comprising a first insulating layer extending from the first mesa to the second mesa and a second insulating layer on the second mesa. The first insulating layer has a first opening, which is disposed on a first platform. A first metal electrode extends from the first platform within the first opening onto the first insulating layer. The second insulating layer has a second opening, which is disposed on a second platform. A second metal electrode portion is disposed within the second opening. The first insulating layer covers the surface of the second insulating layer to form a third opening. From a vertical projection perspective, the second opening is located within the third opening. The second metal electrode extends from the second platform within the second opening onto the insulating layer within the third opening. The insulating layer exposed within the third opening is either the first insulating layer or the second insulating layer. By setting an opening structure in the insulating layer, the product manufacturing yield is improved.

[0005] In one embodiment of the present invention, a display device is also provided, including a circuit board on which the aforementioned micro light-emitting diode is electrically connected. The micro light-emitting diode described in this invention refers to a light-emitting diode chip with a size of 100μm × 150μm or less, produced or fabricated by removing the support substrate.

[0006] This invention addresses and improves product yield through product structure innovation. Attached Figure Description

[0007] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention, but do not constitute a limitation thereof. Furthermore, the figures are descriptive outlines and are not drawn to scale.

[0008] Figure 1 and Figure 2 : A schematic diagram of the existing transfer process; Figure 3 and Figure 4 These are, respectively, a cross-sectional view and a three-dimensional view of the first embodiment of the present invention; Figure 5 : This is a cross-sectional structural diagram of the second embodiment of the present invention; Figure 6 : This is a cross-sectional structural schematic diagram and an enlarged schematic diagram of the first metal electrode according to the third embodiment of the present invention; Figure 7 This is a schematic cross-sectional view of the first metal electrode stack structure according to the fourth embodiment of the present invention. Figure 8 This is a schematic cross-sectional view of the first metal electrode stack structure according to the fifth embodiment of the present invention. Figure 9 and Figure 10 These are schematic cross-sectional views of the sixth embodiment of the present invention. Figure 11 This is a cross-sectional structural diagram of the seventh embodiment of the present invention; Figure 12 This is a cross-sectional structural diagram of the eighth embodiment of the present invention; Figure 13 and Figure 14 : These are cross-sectional and top views of the ninth embodiment of the present invention; Figures 15 to 18 This is a schematic diagram of the structure of the tenth embodiment of the present invention; Figure 19 This is a cross-sectional structural diagram of the eleventh embodiment of the present invention.

[0009] In the diagram, the markings are as follows: 100, Micro LED; 110, Semiconductor layer sequence; 111, Type 1 semiconductor layer; 112, Type 2 semiconductor layer; 113, Active layer; 120, Support layer; 200, Imprint stencil; 310, First metal electrode; 311, First metal layer; 312, Second metal layer; 313, Third metal layer; 314, Fourth metal layer; 331, Platinum layer; 332, Bonding metal layer; 320, Second metal electrode. ; 400, Insulating layer; 410, First insulating layer; 420, Second insulating layer; 500, Insulating protective layer; C1, Fracture; D1, D2, D3, D4, D5, Distance; d1, d2, Aperture; G1, First groove; G2, Second groove; K1, First opening; K2, Second opening; L1, Long side; L2, Short side; M1, First platform; M2, Second platform; S1, Sidewall of the first groove; PD1, Horizontal projection surface of the long side. Detailed Implementation

[0010] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples, so that the process of how the present invention uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0011] This invention provides an embodiment of a micro light-emitting diode (LED) having a semiconductor layer sequence, comprising a front side and a back side disposed opposite to each other. From the front side to the back side, the semiconductor layer sequence sequentially includes: a first type semiconductor layer, a second type semiconductor layer, and an active layer between the two. The back side of the semiconductor layer sequence has a groove penetrating the second type semiconductor layer and the active layer, exposing the first type semiconductor layer. The back side of the semiconductor layer sequence includes a first mesa within the groove, a second mesa on the second type semiconductor layer, and a groove sidewall located between the two. The back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected to a first type of semiconductor layer and a second metal electrode electrically connected to a second type of semiconductor layer. It also includes an insulating layer covering the semiconductor layer sequence, the insulating layer comprising a first insulating layer extending from the first mesa to the second mesa and a second insulating layer on the second mesa. The first insulating layer has a first opening, which is disposed on a first platform. A first metal electrode extends from the first platform within the first opening onto the first insulating layer. The second insulating layer has a second opening disposed on a second mesa. A second metal electrode portion is disposed within the second opening. The first insulating layer covers the surface of the second insulating layer and forms a third opening. Viewed vertically, the second opening is smaller than the third opening, and the second opening is located within the third opening. The second metal electrode extends from the second mesa within the second opening to the insulating layer within the third opening. The insulating layer within the third opening is the first insulating layer. The first insulating layer protects the second insulating layer, and the third opening helps reduce the risk of breakage due to excessive bridging height of the micron-sized metal electrode. In some embodiments, the first insulating layer may be etched completely down to the second insulating layer, meaning the second insulating layer is exposed at the third opening.

[0012] In these embodiments, preferably, the distance between the second metal electrode and the first insulating layer within the third opening is 0.5 μm to 10 μm. This improves the yield of the metal electrode fabrication and also protects the second insulating layer.

[0013] In these embodiments, preferably, the second insulating layer is an insulating reflective layer comprising titanium dioxide, and the second metal electrode extends from the exposed insulating layer inside the third opening to the first insulating layer outside the third opening. The second metal electrode covers the first insulating layer outside the third opening by a distance of 0.1 μm to 10 μm. The titanium dioxide is easily destroyed by the etching fluid during the etching process.

[0014] In these embodiments, preferably, the first insulating layer has a step within the third opening, the average thickness of the first insulating layer within the third opening is less than the average thickness of the first insulating layer on the second insulating layer outside the third opening, the thickness of the first insulating layer exposed within the third opening is greater than 0 to less than 0.2 μm, and the thickness of the first insulating layer on the second insulating layer outside the third opening is 0.15 μm to 2 μm, thereby protecting the second insulating layer from damage by the etching fluid through the sacrificial effect of the first insulating layer.

[0015] In these embodiments, preferably, the first metal electrode and / or the second metal electrode comprise at least one of chromium, aluminum, titanium, platinum, or gold.

[0016] In these embodiments, preferably, the thickness of the first insulating layer outside the third opening is 1 / 4 to 2 / 3, or 2 / 3 to 2, of the thickness of the second insulating layer. For example, the thickness of the first insulating layer on the first platform is 1 / 4 to 2 / 3, or 2 / 3 to 2, of the thickness of the second insulating layer. By significantly removing the insulating layer on the second platform to form the third opening, the difficulty of bridging the second metal electrode is significantly reduced.

[0017] In these embodiments, preferably, the thickness of the first insulating layer outside the third opening is 0.15 μm to 2 μm, and the thickness of the second insulating layer is 0.5 μm to 3 μm.

[0018] In these embodiments, preferably, the first insulating layer uses one type of dielectric material, while the second insulating layer uses two or more types of dielectric materials. Generally, the more types of dielectric materials there are, the greater the difficulty in etching control; the etching control difficulty of the first insulating layer is less than that of the second insulating layer.

[0019] In these embodiments, preferably, the dielectric material of the first insulating layer is silicon oxide and / or silicon nitride, and the dielectric material of the second insulating layer includes silicon oxide and titanium oxide, or includes silicon oxide, silicon nitride and titanium oxide.

[0020] In these embodiments, preferably, the angle between the first opening and the horizontal plane is θ1, and the angle between the second opening and the horizontal plane is θ2, wherein θ1 is not greater than θ2. The angle θ1 between the first opening and the horizontal plane is 20° to 55°, and the angle θ2 between the second opening and the horizontal plane is 30° to 60°. The first opening is composed of a first insulating layer, and the second opening is composed of a first insulating layer and a second insulating layer. The types of dielectric materials corresponding to the first opening are fewer than those corresponding to the second opening. The etching control difficulty of the first opening is lower than that of the second opening. Therefore, the angle between the first opening and the horizontal plane is made as small as possible to improve the electrode yield.

[0021] In these embodiments, the second opening is disposed on the second platform, and the aperture of the second opening is greater than or equal to the aperture of the first opening. The second opening includes a first insulating layer and a second insulating layer. The second opening has more types of insulating layers and is more difficult to manufacture with a large angle. Therefore, the second opening removes a larger area, thereby reducing the angle between the second opening and the horizontal plane.

[0022] In these embodiments, the area of ​​the first mesa is smaller than the area of ​​the second mesa, and the area of ​​the first mesa is 1 / 20 to 1 / 2, or 1 / 2 to 4 / 5, of the area of ​​the second mesa. The aperture of the first opening is 1 μm to 3 μm, and the aperture of the second opening is 1 μm to 5 μm, or 5 μm to 10 μm. The first opening is limited by the area of ​​the first mesa, and the smaller the opening, the better. Through the design of this embodiment, the fabrication difficulty of the metal electrode with a small opening is reduced.

[0023] In these embodiments, the micro-light-emitting diode is rectangular, with the short side length of the micro-light-emitting diode not exceeding 15 μm and the single-side dimension of the first mesa not exceeding 15 μm; or the short side length of the micro-light-emitting diode is 15 μm to 50 μm, and the single-side dimension of the first mesa is 15 μm to 50 μm.

[0024] In these embodiments, viewed from the vertical projection plane where the short side is located, the first metal electrode extends from the first platform to the second platform, and the width of the coverage area of ​​the first metal electrode on the second platform exceeds 20% of the length of the short side and is not greater than 90% of the length of the short side.

[0025] In these embodiments, the angle between the second opening and the horizontal plane is variable, including at least a first angle and a second angle, wherein the second angle is closer to the third opening than the first angle and the second angle is smaller than the first angle.

[0026] In these embodiments, the minimum distance between the first opening and the second opening is 5 μm to 20 μm, or 20 μm to 35 μm.

[0027] To better implement the technology of the present invention, the transfer process involved in the present invention will be explained, and specific embodiments of the present invention will be briefly described in conjunction with existing transfer processes.

[0028] See Figure 1 In conventional MicroLED transfer processes, such as high-pixel display chip manufacturing, the size of the microLED 100 is within 100μm × 150μm. This requires lamination and imprinting for the pickup and placement of ultra-thin and / or small devices. The design of this invention allows for the selection and application of these ultra-thin, fragile, and / or small devices through micro-transfer printing without damaging the chip itself.

[0029] The mass transfer method of micro-transfer printing allows for the decisive assembly and integration of arrays of microscale, high-performance devices onto non-native substrates. In its simplest embodiment, micro-transfer printing is analogous to using a rubber impression tool to transfer fluid-based ink from an inkpad onto paper. However, in micro-transfer printing, the "ink" is composed of high-performance solid-state semiconductor devices, and the "paper" can be a substrate containing circuit boards, films, plastics, or other semiconductors. The micro-transfer printing process utilizes a designed elastomer impression 200 coupled to a high-precision controlled printhead to selectively pick up and print large arrays of microscale devices onto non-native destination substrates.

[0030] See Figure 2 During the mass transfer process, the imprint 200 extrudes and prints on the micro LED 100. When the micro LED 100 has a first groove G1 on the side away from the imprint 200, for example, the N-type window layer of the semiconductor layer sequence 110 is provided with a first groove G1, especially when the side of the micro LED close to the imprint 200 is thinned, roughened or patterned etched and removed, the micro LED 100 is prone to breakage C1 at the first groove sidewall S1 and the first mesa M1.

[0031] See Figure 3 and Figure 4In a first embodiment of the present invention, a micro light-emitting diode is provided, comprising a semiconductor layer sequence 110. The semiconductor layer sequence 110 includes a front side and a back side disposed opposite to each other. Specifically, the upper surface of the semiconductor layer sequence 110 away from the first metal electrode 310 and the second metal electrode 320 is the front side, and the lower surface of the semiconductor layer sequence 110 close to the first metal electrode 310 and the second metal electrode 320 is the back side. The semiconductor layer sequence 110 includes a first type semiconductor layer 111, a second type semiconductor layer 112, and an active layer 113 between them. In this embodiment, the material of the semiconductor layer sequence 110 is gallium nitride series or aluminum gallium indium phosphide series. In a specific embodiment, the semiconductor layer sequence 110 emits light by recombination of electrons generated by the first type semiconductor layer 111 and holes generated by the second type semiconductor layer 112. After a substrate removal process, the front side of the semiconductor layer sequence 110 is exposed.

[0032] The semiconductor layer sequence 110 has a first groove G1 with a Mesa mesa on its back side. In this embodiment, the patterned first groove G1 is used to set a current injection window into the first type semiconductor layer 111. The first groove G1 sequentially penetrates the second type semiconductor layer 112, the active layer 113, and a portion of the first type semiconductor layer 111, exposing the first type semiconductor layer 111. Since the first type semiconductor layer 111 has a large thickness, a portion of the first type semiconductor layer 111 can serve as a support layer 120. On the vertical projection plane PD1 of the long side L1 of the support layer 120, the semiconductor layer sequence 110 is at least partially penetrated by the first groove G1. This is particularly suitable for the vertical projection plane PD1 of the long side L1, where the distance D1 of the area penetrated by the semiconductor layer sequence 110 is 25% to 60% of the length of the long side L1. Because a large area of ​​the semiconductor layer sequence 110 is removed laterally, this design is more suitable for the first metal electrode 310 design in this embodiment.

[0033] A first metal electrode 310 and a second metal electrode 320 are disposed on the back side of the semiconductor layer sequence 110. The first metal electrode 310 and the second metal electrode 320 are used to connect to an external circuit. The back side of the semiconductor layer sequence 110 includes a first mesa M1, a second mesa M2 in the first groove G1, and a first groove sidewall S1 located between the two. The first metal electrode 310 is disposed on the first mesa M1, which is located on the bottom surface of the first groove G1. The second metal electrode 320 is disposed on the second mesa M2. The first metal electrode 310 is directly connected to the first type semiconductor layer 111, and the second metal electrode 320 is electrically connected to the second type semiconductor layer 112. For example, the second metal electrode 320 is connected to the second type semiconductor layer 112 through a transparent current spreading layer (not shown in the figure in this embodiment).

[0034] The first type semiconductor layer 111 serves as a support layer 120, providing support for the semiconductor layer sequence 110. Viewed from above, the support layer 120 is generally rectangular, with a length ratio of 1.5 to 5 for its long side L1 and short side L2. This elongated design provides holding force. Considering the minimum thickness of the support layer and that the length-to-short side ratio is less than 1.5, the probability of breakage under stress is low. However, when the ratio is greater than 5, the probability of breakage increases significantly due to the increased torque. Vertically, the distance from at least a portion of the first groove G1 to the front side of the semiconductor layer sequence 110 is no greater than 4 μm, meaning the thickness of the first type semiconductor layer 111 within at least a portion of the first groove G1 is no greater than 4 μm. For example, the thickness of the first type semiconductor layer 111 within at least a portion of the first groove G1 is 1 μm to 4 μm. On the top-view projection surface, the area of ​​the first groove G1 is 25% to 60% of the area of ​​the first type semiconductor layer 111. Here, the area refers to the area of ​​the entire first groove G1 region, excluding the boundary area of ​​the second mesa M2. When it is less than 25%, the support layer 120 will not break during the transfer process due to the relatively small torque. When it exceeds 60%, the area loss of the light-emitting area will be too large.

[0035] The first metal electrode 310 extends along the long side L1 of the support layer 120, and the extension covers the second mesa M2 from the first groove sidewall S1, reinforcing the stress concentration area where the thickness of the semiconductor layer sequence 110 varies significantly. The first metal electrode 310 comprises multiple metal layers, wherein the total thickness of the metal layers with a deformation modulus of not less than 100 GPa is 30 angstroms to 1000 angstroms. The high deformation modulus of the first metal layer ensures that the semiconductor layer sequence is prevented from being cut when subjected to shear force torque.

[0036] An insulating layer 400 is provided between the first metal electrode 310 and the second mesa M2, and between the first metal electrode 310 and the first groove sidewall S1. The insulating layer 400 electrically isolates the first metal electrode 310 and the second mesa M2. The material of the insulating layer 400 includes silicon oxide, silicon nitride, or a distributed Bragg reflector (DBR). For example, if the material of the insulating layer 400 is silicon dioxide, the thickness of the insulating layer 400 is 1,000 angstroms to 10,000 angstroms. When the first metal electrode 310 and the second mesa M2 are viewed from the short side projection plane, the width distance D2 of the coverage area of ​​the first metal electrode 310 on the second mesa M2 exceeds 20% of the length of the short side L2. For example, the width distance D2 of the coverage area is 20% to 90% of the length of the short side L2, ensuring sufficient holding force.

[0037] The insulating layer 400 has a first opening K1 on the first mesa M1 and a second opening K2 on the second mesa M2. A first metal electrode 310 extends from the first mesa M1 within the first opening K1 to the insulating layer 400. A second metal electrode 320 extends from the second mesa M2 within the second opening K2 to the insulating layer 400. The insulating layer 400 is an insulating layer, and the number of dielectric material types in the insulating layer 400 on the first mesa M1 is less than the number of dielectric material types in the insulating layer 400 on the second mesa M2.

[0038] The first metal electrode 310 includes multiple metal layers. The first metal layer 311 of the first metal electrode 310 is in contact with the back side. The deformation modulus of the first metal layer 311 is not less than 100 GPa, and the thickness of the first metal layer 311 is 30 angstroms to 1000 angstroms. The first metal layer 311 includes ruthenium, rhodium, or chromium.

[0039] See Figure 5 In a second embodiment of the present invention, the positive side of the semiconductor layer sequence is a first type semiconductor layer 111 or an undoped semiconductor layer, and at least part of the positive side of the semiconductor layer sequence 110 is removed.

[0040] The front side of the semiconductor layer sequence 110 has a patterned or roughened surface. For example, to increase light emission from the front side and reduce total internal reflection, a roughened surface is typically created. This is achieved by removing a portion of the semiconductor material on the front side of the semiconductor layer sequence with an etchant, forming a roughened second groove G2 on the surface. After roughening, the first type of semiconductor layer 111 has a region with a thickness of no more than 4 μm in the vertical direction, for example, a thickness of 1 μm to 4 μm at the junction of the first mesa M1 and the second mesa M2.

[0041] The removal of some semiconductor layer sequences may improve optical performance, such as controlling the light pattern, but it may cause some damage or potential problems to the front side of the first type semiconductor layer 111, i.e., the support layer. The front side of the semiconductor layer sequence 110 is covered with an insulating protective layer 500, which is exposed. In this embodiment, it is completely exposed, and the thickness of the insulating protective layer 500 is 2000 angstroms to 10000 angstroms. According to this embodiment, although independently setting the insulating protective layer 500 in the micro-light-emitting diode has the potential to reduce the probability of fracture anomalies and provide retention force on the front side, it is still difficult to completely avoid fracture anomalies.

[0042] In this embodiment, based on the insulating protective layer 500 covering the front side, combined with the reinforcement design of the first metal electrode 310, the first metal electrode 310 includes multiple metal layers. The first metal layer of the first metal electrode 310 (not shown in the figure of this embodiment) is in contact with the back side. The deformation modulus of the first metal layer 311 is not less than 100 GPa, and the thickness of the first metal layer is 10 angstroms to 30 angstroms. The front side of the semiconductor layer sequence 110 is covered with an insulating protective layer 500, and the thickness of the insulating protective layer 500 is 2000 angstroms to 10000 angstroms. This can reduce the thickness requirement of the first metal layer 311 and help improve the flexibility of electrode thickness design, such as reducing the light absorption of the first metal layer 311.

[0043] See Figure 6 In the third embodiment of the present invention, based on embodiments 1 and 2, the design of the stacked metal of the first metal electrode 310 is further improved. In this embodiment, the stacked metal materials and the relative positional relationship between the stacked metals are mainly described. The first metal electrode 310 includes a first metal layer 311 in contact with the back side of the semiconductor layer sequence. A platinum layer 331 and a bonding metal layer 332 are disposed on the first metal layer 311. The material of the bonding metal layer 332 includes gold. The thickness of the platinum layer 331 is 300 angstroms to 1000 angstroms. Although the deformation modulus of platinum is slightly lower than that of the first metal layer 311, it still provides a reliable support with the added thickness. The thickness of the platinum layer 331 used in this embodiment is 500 angstroms.

[0044] In this embodiment, the first metal layer 311 extends along the long side L1 of the support layer 120 (first type semiconductor layer), and the extension covers the second mesa M2 from the first groove sidewall S1. The deformation modulus of the first metal layer 311 is not less than 100 GPa, and the thickness of the first metal layer 311 is 30 angstroms to 100 angstroms. In this embodiment, the thickness of the first metal layer 311 is 50 angstroms. The first metal layer 311 extends along the long side L1 of the support layer 120, and the extension covers the second mesa M2 from the first groove sidewall S1. Viewed from the horizontal projection plane of the short side L2, the width of the first metal layer 311 covering the second mesa M2 exceeds 20% of the length of the short side L2.

[0045] On the horizontal projection surface of the long side L1 of the support layer 120, the semiconductor layer sequence 110 is at least partially penetrated by the first groove G1. This is particularly suitable for the horizontal projection surface PD1 of the long side L1, where the penetration area of ​​the semiconductor layer sequence 110 is 25% to 60% of the length of the long side L1. Since a large area of ​​the semiconductor layer sequence 110 is removed laterally, it is more suitable for the design of the first metal electrode 310 in this embodiment. The difference in size between the first metal electrode area on the second mesa and the second metal electrode area on the second mesa is no more than 30%, which improves the stability of the bonding force during packaging bonding, reduces the shear torque, and improves the transfer yield.

[0046] See Figure 7 In the fourth embodiment of the present invention, based on embodiments 1 and 2, the design of the stacked metal of the first metal electrode 310 is further improved. This embodiment mainly describes the stacked metal materials and the relative positional relationships between the stacked metals. The first metal electrode 310 sequentially includes a first metal layer 311, a second metal layer 312, and a third metal layer 313. From a process perspective, the second metal layer 312 is located between the first metal layer 311 and the third metal layer 313, and the second metal layer 312 is in direct contact with both the first metal layer 311 and the third metal layer 313. The deformation modulus of the first metal layer 311 and the third metal layer 313 is greater than that of the second metal layer 312. From a hardness perspective, the deformation modulus of the first metal layer 311 and the third metal layer 313 is not less than 100 GPa. To ensure reliability, this embodiment preferably designs the sum of the thicknesses of the first metal layer 311 and the third metal layer 313 to be 30 angstroms to 100 angstroms. The third metal layer 313 is ruthenium, rhodium, or chromium. In this embodiment, the first metal layer 311 has a thickness of 10 to 30 angstroms, and the third metal layer 313 has a thickness of 20 to 70 angstroms. The first metal layer 311 and the third metal layer 313 together provide holding force.

[0047] In this embodiment, to improve the external quantum efficiency of the micro-LED, the second metal layer 312 is configured as a metal reflective layer. The material of the second metal layer 312 is aluminum or silver, and the thickness of the second metal layer 312 is 10 angstroms to 5000 angstroms. This ensures both product reliability and improves product brightness, because the second metal layer 312 has reflective properties required, and a thickness of less than 10 angstroms is insufficient to provide effective reflection contribution.

[0048] See Figure 8 In the fifth embodiment of the present invention, based on embodiments 1 and 2, the design of the stacked metal of the first metal electrode 310 is further improved. This embodiment mainly describes the stacked metal materials and the relative positional relationships between the stacked metals. The first metal electrode 310 sequentially includes a first metal layer 311, a platinum layer 331, a bonding metal layer 332, and a fourth metal layer 314. The first metal layer 311 comprises ruthenium, rhodium, or chromium, with a thickness of 40 to 60 angstroms; the platinum layer 331 is platinum, with a thickness of 100 to 1000 angstroms; the bonding metal layer 332 is gold, with a thickness of 100 to 1000 angstroms; and the fourth metal layer 314 comprises titanium, nickel, tin, silver, or copper.

[0049] See Figure 9 and Figure 10In the sixth embodiment of the present invention, even without roughening, the present invention is applicable to designs with a thinner support layer 120. In existing chip technology, the thickness of the support layer 120 is typically greater than 4 μm; for example, if a conventional-sized chip uses sapphire, the sapphire thickness is typically greater than 50 μm. As a contrasting design, this embodiment does not employ a support substrate design. Because the support substrate is stripped away and the semiconductor layer sequence 110 is penetrated laterally from the projection plane of the long side L1, stress concentration areas and stress defect areas exist throughout the semiconductor layer sequence 110, i.e., stress defects exist at the intersection line of the first mesa M1 and the second mesa M1. In this embodiment, the thickness of the first type semiconductor layer 111 of the first mesa M1 is 1 μm to 4 μm. The semiconductor layer sequence 110 is at least partially penetrated by the first groove G1. This is particularly applicable to the horizontal projection plane of the long side L1, where the penetration area of ​​the semiconductor layer sequence 110 is 25% to 60% of the length of the long side L1. Because a large area of ​​the semiconductor layer sequence 110 is removed laterally, this design is more suitable for the first metal electrode 310 design of this embodiment. Even if the front side of the first type semiconductor layer 111 is not roughened or patterned, it may still crack under pressure, resulting in poor overall structural stability.

[0050] In this embodiment, the first groove opening does not penetrate the horizontal projection plane of the long side alone. The length of the first groove on the short side is 30% to 80% of the short side length, but the support layer 120 is further thinned to less than 3 μm. The first metal electrode 310 extends along the long side L1 of the support layer 120, and the extension covers the second mesa M2 from the sidewall S1 of the first groove. The first metal electrode 310 comprises multiple layers of metal, wherein the total thickness of the metal layers with a deformation modulus of not less than 100 GPa is 30 angstroms to 1000 angstroms. Sufficient support force is provided for the first metal electrode 310.

[0051] In another embodiment of this invention, the first metal electrode 310 extends along the long side L1 of the support layer 120, and the extension covers the second mesa M2 from the first groove sidewall S1. The first metal electrode 310 comprises multiple layers of metal, and the first metal layer 311 of the first metal electrode 310 is in contact with the back side. The deformation modulus of the first metal layer 311 is not less than 100 GPa, and the thickness of the first metal layer 311 is 30 angstroms to 1000 angstroms. The first metal layer 311 comprises ruthenium, rhodium, or chromium.

[0052] In another embodiment of this invention, the first metal electrode 310 sequentially includes a first metal layer 311, a second metal layer 312, and a third metal layer 313. From a process perspective, the second metal layer 312 is located between the first metal layer 311 and the third metal layer 313. The second metal layer 312 is in direct contact with the first metal layer 311 and the third metal layer 313, respectively. The deformation modulus of the first metal layer 311 and the third metal layer 313 is greater than that of the second metal layer 312. In terms of hardness, the deformation modulus of the first metal layer 311 and the third metal layer 313 is not less than 100 GPa. To ensure reliability, this embodiment preferably designs the sum of the thicknesses of the first metal layer 311 and the third metal layer 313 to be 30 angstroms to 100 angstroms.

[0053] In this embodiment, any one of Embodiments 1 to 5, excluding the roughening of the front side, is used. For example, the design of the first metal electrode 310 and / or the design of the insulating protective layer 500 are employed to strengthen the structure itself. Taking the design of the insulating protective layer 500 as an example, the thickness of the insulating protective layer 500 is 2000 angstroms to 5000 angstroms, which can reduce the thickness requirement of the first metal layer 311 and improve the flexibility of electrode thickness design, such as reducing light absorption of the first metal layer 311. Alternatively, the thickness of the insulating protective layer 500 can be designed to be 5000 angstroms to 10000 angstroms, which eliminates the need for the design of the first metal layer 311. A soft metal can be used in the first metal layer 311 to improve the strength of the chip structure.

[0054] See Figure 11 In the seventh embodiment of the present invention, the back side of the semiconductor layer sequence 110 has a first groove G1, the first groove G1 penetrates the second type semiconductor layer 112 and the active layer 113, and exposes the first type semiconductor layer 111. The back side of the semiconductor layer sequence 110 includes a first mesa M1 in the first groove G1, a second mesa M2 on the second type semiconductor layer 112 and a first groove sidewall S1 located between the two.

[0055] The back side of the semiconductor layer sequence 110 is provided with a first metal electrode 310 electrically connected to the first type semiconductor layer 111 and a second metal electrode 320 electrically connected to the second type semiconductor layer 112.

[0056] It also includes a first insulating layer 410 and a second insulating layer 420. The first insulating layer 410 has a first opening K1, which is disposed on a first platform. A first metal electrode 310 is at least partially disposed on the first platform M1 and extends from the first platform M1 within the first opening K1 to the first insulating layer 410. The second insulating layer 420 is disposed on a second platform M2 and has a second opening K2, which is disposed on the second platform M2. A second metal electrode 320 is at least partially disposed on the second platform M2 and extends from the second platform within the second opening K2 to the second insulating layer 420. The number of dielectric material types in the second insulating layer 420 is greater than the number of dielectric material types in the first insulating layer 410.

[0057] In some embodiments of this example, the thickness of the second insulating layer 420 is greater than that of the first insulating layer 410. The thickness of the first insulating layer 410 is 1 / 4 to 2 / 3 of the thickness of the second insulating layer 420, and the thickness of the first insulating layer 410 is 0.15 μm to 2 μm, while the thickness of the second insulating layer 420 is 0.5 μm to 3 μm. The first insulating layer 410 extends from the first mesa M1 along the groove sidewall S1 to the second mesa M2.

[0058] In this embodiment, the dielectric material of the first insulating layer 410 is one type, such as silicon dioxide, while the dielectric material of the second insulating layer 420 is silicon dioxide and titanium dioxide. In some embodiments of this embodiment, the dielectric material of the first insulating layer 410 is silicon dioxide and silicon nitride, while the dielectric material of the second insulating layer 420 is silicon nitride, silicon dioxide, and titanium dioxide, in order to reduce the difficulty of etching control of the first insulating layer.

[0059] In this embodiment, the angle between the first opening K1 and the horizontal plane is θ1, and the angle between the second opening K2 and the horizontal plane is θ2, wherein θ1 is not greater than θ2, the angle θ1 between the first opening K1 and the horizontal plane is 20° to 55°, and the angle θ2 between the second opening K2 and the horizontal plane is 30° to 60°.

[0060] In some embodiments of this example, the micro-LED is rectangular, with the shorter side length not exceeding 15 μm, and the single-side dimension of the first mesa M1 not exceeding 15 μm. In small-size micro-LED products, the first mesa M1 requires sacrificing the area of ​​the active layer 113; therefore, the second mesa M2 has an area advantage relative to the first mesa M1. The area of ​​the first mesa M1 is smaller than the area of ​​the second mesa, which is 1 / 20 to 1 / 2, or 1 / 2 to 4 / 5, of the area of ​​the second mesa. A second opening K2 is disposed on the second mesa M2, and the aperture of the second opening K2 is greater than or equal to the aperture of the first opening K1. The aperture of the first opening K1 is 1 μm to 3 μm, and the aperture of the second opening K2 is 1 μm to 5 μm.

[0061] In some embodiments, the first insulating layer is over-etched within the third opening to expose the second insulating layer.

[0062] See Figure 12 In the eighth embodiment of the present invention, the difference from other embodiments of the present invention is that, in order to strengthen the device and prevent the support layer 120 of the micro light-emitting diode from being too thin on the first mesa M1 and breaking during transfer, the first metal electrode 310 is extended from the first mesa M1 along the first groove sidewall S1 to the second mesa M2, wherein the thickness of the first groove sidewall S1 is gradually changing, and the angle θ3 between the first groove sidewall S1 and the horizontal plane is not greater than 70°.

[0063] In some embodiments of this example, the second opening K2 has multiple angles with the horizontal plane, and all of these angles are greater than the angle θ1 between the first opening K1 and the horizontal plane.

[0064] refer to Figure 13 and Figure 14 In the ninth embodiment of the present invention, a first insulating layer 410 and a second insulating layer 420 are further included. The first insulating layer 410 and the second insulating layer 420 comprise silicon oxide, silicon nitride, or titanium oxide. The first insulating layer 410 has a first opening K1 disposed on a first mesa M1. The angle between the sidewall of the first opening K1 and the first mesa M1 is θ1. A first metal electrode 310 is at least partially disposed on the first mesa M1, extending from the first opening K1 on the first mesa M1 to the first insulating layer 410. The second insulating layer 420 is disposed on the second mesa M2. The dashed lines in the figure are only for illustrative purposes regarding the second insulating layer 420. In this embodiment, the second insulating layer 420 includes a portion of the first insulating layer 410. The first insulating layer 410 extends from the first mesa M1 along the sidewall S1 of the first groove to the second mesa M2. The second insulating layer 420 has a second opening K2 disposed on the second mesa M2. The second metal electrode 320 is at least partially disposed on the second mesa M2, extending from the second mesa M2 within the second opening K2 to the second insulating layer 420. The aperture of the second opening K2 is 1 μm to 5 μm. By appropriately enlarging the aperture of the second opening K2, etching conditions can be improved, and the angle between the sidewall of the second opening K2 and the horizontal plane can be reduced. In this embodiment, the thickness of the second insulating layer 420 is greater than that of the first insulating layer 410, and the thickness of the first insulating layer 410 is 1 / 4 to 2 / 3 of the thickness of the second insulating layer 420. In this embodiment, the thickness of the first insulating layer 410 is 0.15 μm to 2 μm, and the thickness of the second insulating layer 420 is 0.5 μm to 3 μm. Reducing the thickness of the first insulating layer 410 helps to improve the fabrication yield of the first metal electrode 310 and avoids cracking around the first opening K1.

[0065] To more clearly illustrate the concept of this embodiment, the first insulating layer 410 and the second insulating layer 420 are distinguished by a dashed line. The dashed line extends downwards along the third opening K3 to the bottom surface of the second insulating layer 420. The second insulating layer 420 includes a first portion 421 on which the second metal electrode 320 is disposed and a second portion 422 on which the second metal electrode 320 is not disposed. The first portion of the second insulating layer 420 does not include the first insulating layer 410, that is, there is no first insulating layer 410 under the second metal electrode 320. For example, the first portion 421 of the second insulating layer 420 does not include the first insulating layer 410 and is made of silicon dioxide and titanium dioxide. The second portion 422 of the second insulating layer 420 includes the first insulating layer 410 and is made of silicon nitride, silicon dioxide and titanium dioxide. In this embodiment, the material composition of the first insulating layer 410 is not entirely the same as that of the second insulating layer 420. For example, the first insulating layer 410 is silicon oxide and silicon nitride, while the second insulating layer 420 includes silicon nitride, silicon oxide, and titanium oxide. Reducing the thickness and / or types of dielectric materials under the second metal electrode 320 increases the difficulty of process control when fabricating the angle between the sidewall of the second opening K1 and the second mesa M2. When the aperture of the second opening K2 is 1 to 5 μm, the etching conditions can be improved by appropriately enlarging the aperture of the second opening K2, thereby reducing the angle θ2 between the sidewall of the second opening K2 and the horizontal plane. If both the first insulating layer 410 and the second insulating layer 420 are simultaneously provided under the second metal electrode 320, the angle control of the second opening K2 becomes more difficult due to the different removal characteristics of different materials. Therefore, in this embodiment, the first insulating layer 410 is not provided in the dielectric layer under the second metal electrode 320. A third opening K3 is formed on the second insulating layer 420.

[0066] In this embodiment, the micro-LED is rectangular, with a short side length not exceeding 15μm, and the single-side dimension of the first mesa M1 not exceeding 15μm. Due to application size requirements, μm-level LEDs cannot provide the same first mesa area as conventional LEDs. The area of ​​the first mesa M1 is smaller than the area of ​​the second mesa M2, which is 1 / 20 to 1 / 2, or 1 / 2 to 4 / 5, of the area of ​​the second mesa M2. The second mesa M2 is the main light-emitting area. In this embodiment, the first mesa M1 is reduced in size, further increasing the area of ​​the light-emitting region.

[0067] Since the first opening K1 is located on the first mesa M1, the smaller the area of ​​the first mesa M1, the larger the light-emitting area and the higher the device efficiency. Therefore, the area of ​​the first opening M1 is smaller than the area of ​​the second opening M2. The aperture of the first opening K1 is 1μm to 3μm, and the aperture of the second opening K2 is 1μm to 5μm. Here, aperture refers to the maximum distance of the opening when viewed from above. The second opening K2 is located on the second mesa M2, and the aperture of the second opening K2 is greater than or equal to the aperture of the first opening K1, further reducing the manufacturing difficulty of the second opening K2. The angle between the first opening K1 and the horizontal plane is θ1, and the angle between the second opening K2 and the horizontal plane is θ2, where θ1 is not greater than θ2. The angle θ1 between the first opening K1 and the horizontal plane is 20° to 55°, and the angle θ2 between the second opening K2 and the horizontal plane is 30° to 60°. This embodiment reduces the angle between the first opening K1 and the horizontal plane in the dry etching process by controlling the type and thickness of the insulating layer dielectric material, especially reducing the difficulty of angle control.

[0068] See Figures 15 to 16 In the tenth embodiment of the present invention, the difference from other embodiments is that the first insulating layer and the second insulating layer are defined independently, and the second metal electrode 320 extends from the second mesa M2 in the second opening K2 to the insulating layer in the third opening K3. The insulating layer exposed in the third opening K3 is the first insulating layer 410.

[0069] In this embodiment, the exposed insulating layer within the third opening K3 serves as the first insulating layer 410. The distance D3 covered by the second metal electrode 320 on the first insulating layer 410 within the third opening K3 is 0.5 μm to 10 μm. The second insulating layer 420 is an insulating reflective layer, including titanium oxide, such as a distributed Bragg reflective layer composed of silicon dioxide and titanium dioxide. The second metal electrode 320 extends from the exposed insulating layer within the third opening K3 to the first insulating layer 410 outside the third opening K3. The distance D4 covered by the second metal electrode 320 on the first insulating layer 410 outside the third opening K3 is 0.1 μm to 10 μm. The second metal electrode 320 seals the third opening K3, providing sufficient protection for the second insulating layer 420. The second metal electrode 320 ensures sufficient coverage distance on the first insulating layer 410 within the third opening K3, preventing cracks from occurring when it crosses over to the first insulating layer 410 outside the third opening K3.

[0070] In this embodiment, the first insulating layer 410 has a step within the third opening K3, and the thickness H1 of the first insulating layer 410 exposed within the third opening K3 is greater than 0 and less than 0.2 μm. The first insulating layer 410 is partially removed within the third opening K3.

[0071] The first metal electrode 310 and / or the second metal electrode 320 comprise at least one of chromium, aluminum, titanium, platinum, or gold. In this embodiment, on the second mesa M2, the second insulating layer 420 is covered by the first insulating layer 410. The thickness of the first insulating layer 410 is 1 / 4 to 2 / 3, or 2 / 3 to 2, of the thickness of the second insulating layer 420, thereby reducing the thickness of the insulating layer outside the first opening K1 and improving the manufacturing yield of the first metal electrode 310.

[0072] In this embodiment, the angle between the first opening K1 and the horizontal plane is θ1, and the angle between the second opening K2 and the horizontal plane is θ2, wherein θ1 is not greater than θ2. The angle θ1 between the first opening K1 and the horizontal plane is 20° to 55°, and the angle θ2 between the second opening K2 and the horizontal plane is 30° to 60°, thereby improving the fabrication yield of the first metal electrode 310. In this embodiment, the aperture of the first opening K1 is not larger than the aperture of the second opening K2. The aperture d1 of the first opening K1 is 1μm to 3μm, and the aperture d2 of the second opening K3 is 1μm to 5μm and 5μm to 10μm.

[0073] The micro-light-emitting diode (LED) is rectangular, with the shorter side L2 of the LED not exceeding 15 μm and the single-side dimension of the first mesa not exceeding 15 μm; or the shorter side L2 of the LED is between 15 μm and 50 μm, and the single-side dimension of the first mesa is between 15 μm and 50 μm. See Figure 17 The minimum distance D5 between the first opening K1 and the second opening K2 is 5μm to 20μm, or 20μm to 35μm. Here, the minimum distance refers to the minimum distance between the contact edge of the first metal electrode 310 with the epitaxial layer and the contact edge of the second metal electrode 320 with the epitaxial layer or with the transparent conductive layer, that is, the minimum distance at the bottom of the opening.

[0074] See Figure 18 In some embodiments of this example, the angle between the second opening K2 and the horizontal plane is variable, including at least the first angle θ. 21 The second included angle θ 22 The second included angle θ 22 Compared to the first included angle θ 21 Closer to the third opening K1, the second included angle θ 22 Less than the first included angle θ 21 Angle. Or, the sidewall of the second opening K2 exposing the second insulating layer 420 is a rounded chamfer, and the slope of the sidewall gradually decreases.

[0075] See Figure 19In the eleventh embodiment of the present invention, a display device is provided, having a substrate 600 and a plurality of micro light-emitting diodes 100, wherein the substrate 600 and the plurality of micro light-emitting diodes 100 are connected by wires or conductive pads 610, and the micro light-emitting diodes 100 are any one of those described in the above embodiments.

[0076] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A micro light-emitting diode having a semiconductor layer sequence, the semiconductor layer sequence including a front side and a back side disposed opposite to each other, the semiconductor layer sequence comprising, from the front side to the back side, the following: A first type semiconductor layer, a second type semiconductor layer, and an active layer between them are provided. The back side of the semiconductor layer sequence has a groove that penetrates the second type semiconductor layer and the active layer, exposing the first type semiconductor layer. The back side of the semiconductor layer sequence includes a first mesa within the groove, a second mesa on the second type semiconductor layer, and a groove sidewall located between them. The back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected to a first type of semiconductor layer and a second metal electrode electrically connected to a second type of semiconductor layer. Its features are, It also includes an insulating layer covering the semiconductor layer sequence, the insulating layer comprising a first insulating layer extending from the first mesa to the second mesa and a second insulating layer on the second mesa. The first insulating layer has a first opening, which is disposed on a first platform. A first metal electrode extends from the first platform within the first opening onto the first insulating layer. The second insulating layer has a second opening, which is disposed on a second platform. A second metal electrode portion is disposed within the second opening. The first insulating layer covers the surface of the second insulating layer and forms a third opening. From a vertical projection, the second opening is smaller than the third opening. The second opening is located within the third opening. The second metal electrode extends from the second platform within the second opening to the insulating layer within the third opening. The insulating layer within the third opening is the first insulating layer. The first insulating layer has a step within the third opening. The average thickness of the first insulating layer within the third opening is less than the average thickness of the first insulating layer on the second insulating layer outside the third opening. The dielectric material of the first insulating layer is one type, and the dielectric material of the second insulating layer is two or more types. The second insulating layer includes titanium oxide and is an insulating reflective layer. The diameter of the second opening is greater than or equal to the diameter of the first opening; The thickness of the first insulating layer outside the third opening is 1 / 4 to 2 / 3 of the thickness of the second insulating layer, or 2 / 3 to 2; The angle between the first opening and the horizontal plane is θ1, and the angle between the second opening and the horizontal plane is θ2, where θ1 is not greater than θ2. The angle between the first opening and the horizontal plane is θ1, which is between 20° and 55°, and the angle between the second opening and the horizontal plane is θ2, which is between 30° and 60°.

2. A micro light-emitting diode according to claim 1, characterized in that, The distance between the second metal electrode and the first insulating layer within the third opening is 0.5 μm to 10 μm.

3. A micro light-emitting diode according to claim 1, characterized in that, The insulating reflective layer includes titanium dioxide, and the second metal electrode extends from the exposed insulating layer inside the third opening to the first insulating layer outside the third opening. The second metal electrode covers the first insulating layer outside the third opening by a distance of 0.1 μm to 10 μm.

4. A micro light-emitting diode according to claim 1, characterized in that, The thickness of the first insulating layer exposed inside the third opening is greater than 0 to less than 0.2 μm, and the thickness of the first insulating layer on the second insulating layer outside the third opening is 0.5 μm to 2 μm.

5. A micro light-emitting diode according to claim 1, characterized in that, The first metal electrode and / or the second metal electrode comprise at least one of chromium, aluminum, titanium, platinum, or gold.

6. A micro light-emitting diode according to claim 1, characterized in that, The thickness of the first insulating layer outside the third opening is 0.15 μm to 2 μm, and the thickness of the second insulating layer is 0.5 μm to 3 μm.

7. A micro light-emitting diode according to claim 1, characterized in that, The dielectric material of the first insulating layer is silicon oxide or silicon nitride, and the dielectric material of the second insulating layer includes silicon oxide, or includes both silicon oxide and silicon nitride.

8. A micro light-emitting diode according to claim 1, characterized in that, The aperture of the first opening is 1 μm to 3 μm, and the aperture of the second opening is 1 μm to 5 μm.

9. A micro light-emitting diode according to claim 1, characterized in that, The micro-light-emitting diode is rectangular, with the short side length not exceeding 15μm and the single-side dimension of the first mesa not exceeding 15μm; or the short side length of the micro-light-emitting diode is between 15μm and 50μm, and the single-side dimension of the first mesa is between 15μm and 50μm.

10. A micro light-emitting diode according to claim 1, characterized in that, The area of ​​the first countertop is smaller than the area of ​​the second countertop. The area of ​​the first countertop is 1 / 20 to 1 / 2, or 1 / 2 to 4 / 5, of the area of ​​the second countertop.

11. A micro light-emitting diode according to claim 9, characterized in that, Viewed from the vertical projection plane where the short side is located, the first metal electrode extends from the first platform to the second platform. The width of the coverage area of ​​the first metal electrode on the second platform exceeds 20% of the length of the short side, but is not greater than 90% of the length of the short side.

12. A display device, comprising a substrate, characterized in that, The micro light-emitting diode includes any one of claims 1 to 11.

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