Semiconductor device manufacturing method, semiconductor device and electronic equipment
By using multiple wafer bonding and flipping methods during the preparation process of semiconductor devices, after forming the first gate structure of the first transistor and the first metal interconnect structure in the second source and drain structure of the second transistor, the problem of the thermal process of the stacking transistor upper device affecting the lower device and interconnection lines is solved, and the thermal budget of the device is improved.
CN118280925BActive Publication Date: 2025-03-18BEIJING INTPROP OPERATION MANAGEMENT CO LTD +1
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Patent Information
- Application Number
- CN202410434413.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-11
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2044-04-11
AI Technical Summary
Technical Problem
The thermal process in machining the upper device of stack transistors may affect the lower device and interconnects, resulting in a limited thermal budget.
Method used
By multiple wafer bonding and flipping, the first gate structure and the first metal interconnect structure of the first transistor are formed after the second source and drain structure of the second transistor are formed, and the higher process temperature of the second transistor when forming the second source and drain structure is avoided from affecting the structure of the first transistor.
Benefits of technology
The thermal budget of semiconductor devices is improved, ensuring that the preparation of upper devices does not affect the stability of lower devices and interconnection lines.
✦ Generated by Eureka AI based on patent content.
Abstract
The present application provides a method for preparing a semiconductor device, a semiconductor device and an electronic device, wherein the method for preparing the semiconductor device comprises: forming an active structure on a substrate; forming a first semiconductor structure; bonding the first semiconductor structure to a first carrier wafer and flipping it; removing the substrate to expose a second active structure; forming a second semiconductor structure; bonding the second semiconductor structure to a second carrier wafer and flipping it; removing the first carrier wafer to expose the first semiconductor structure; forming a first gate structure in the first semiconductor structure; forming a first source-drain metal on a first source-drain structure; forming a first metal interconnection structure on a first transistor; bonding the first metal interconnection structure to a third carrier wafer and flipping it; removing the second carrier wafer to expose the second semiconductor structure; and forming a second metal interconnection structure. The method avoids the high process temperature when forming the second source-drain structure from affecting the first gate structure and the first metal interconnection structure.
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