Heterojunction solar cell and method of manufacturing the same

Abstract

This disclosure provides a heterojunction solar cell and its fabrication method, applicable to the field of photovoltaic technology. The heterojunction solar cell includes: a silicon wafer having opposing front and back sides; an intrinsic amorphous silicon film layer located on both the front and back sides of the silicon wafer; and a doped layer located on the intrinsic amorphous silicon film layer, the doped layer having a first region and a second region, the second region surrounding the edge of the silicon wafer and enclosing the first region, the first region being made of microcrystalline silicon and the second region being made of amorphous silicon; wherein the doping type of the doped layer on the front side of the silicon wafer is N-type doped, and the doping type of the doped layer on the back side of the silicon wafer is P-type doped. By crystallizing the amorphous silicon in the first region into microcrystalline silicon, while the second region remains amorphous silicon, the high-rate deposition of amorphous silicon and the excellent electrical properties of microcrystalline silicon can be simultaneously utilized, improving the overall performance of the heterojunction solar cell.

Description

Technical Field

[0001] This disclosure relates to the photovoltaic field, and in particular to a heterojunction solar cell and its fabrication method. Background Technology

[0002] Heterojunction (HJT) solar cells have advantages such as high conversion efficiency, bifacial utilization power generation, and low-temperature manufacturing process, and are hailed as the next generation of photovoltaic technology.

[0003] Currently, the conversion efficiency of heterojunction solar cells in the laboratory has exceeded 26.81%, and the product cost is continuously decreasing. However, its power generation cost is still higher than that of traditional solar cells. Existing high-efficiency silicon heterojunction solar cell technology involves depositing doped microcrystalline silicon thin films on intrinsic amorphous silicon thin films to improve parameters such as fill factor (FF) and open-circuit voltage (Voc). The preparation methods for doped microcrystalline silicon thin films are direct deposition methods, including radio frequency plasma-enhanced chemical vapor deposition (RF-PECVD), hot-wire chemical vapor deposition (HWCVD), and very high frequency plasma-enhanced chemical vapor deposition (VHF-PECVD). However, the microcrystalline silicon thin films prepared by these processes are difficult to process, have high processing costs, and low microcrystalline growth rates. The doped microcrystalline silicon film layer at the edge of the cell is prone to leakage, affecting cell performance. Currently, plate-type PECVD equipment is commonly used to prepare doped microcrystalline silicon film layers. The film layer exhibits a coating phenomenon, and the good conductivity of microcrystalline silicon makes it prone to leakage at the edge of the cell. Furthermore, the preparation process of doped microcrystalline silicon is complex, costly, and time-consuming. The doped amorphous silicon film prepared by plate PECVD equipment is a mature process with dense and uniform film and low cost. However, the improvement of solar cell conversion efficiency by doped amorphous silicon film is limited. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a heterojunction solar cell and a method for its fabrication.

[0005] According to a first aspect of this disclosure, a heterojunction solar cell is provided, comprising:

[0006] A silicon wafer has a front and a back side;

[0007] An intrinsic amorphous silicon film layer is located on the front and back sides of the silicon wafer;

[0008] A doped layer is located on the intrinsic amorphous silicon film layer. The doped layer has a first region and a second region. The second region surrounds the edge of the silicon wafer and encloses the first region. The material of the first region is microcrystalline silicon, and the material of the second region is amorphous silicon.

[0009] The doping type of the doped layer on the front side of the silicon wafer is N-type doping, and the doping type of the doped layer on the back side of the silicon wafer is P-type doping.

[0010] In some embodiments of this disclosure, the width of the second region is between 0.01 and 5 millimeters.

[0011] In some embodiments of this disclosure, the crystallinity of the doped layer is not less than 60%.

[0012] In some embodiments of this disclosure, the thickness of the doped layer located on the front side of the silicon wafer is between 15 and 40 nanometers.

[0013] In some embodiments of this disclosure, the thickness of the doped layer located on the back side of the silicon wafer is between 15 and 40 nanometers.

[0014] In some embodiments of this disclosure, the heterojunction solar cell further includes:

[0015] A transparent conductive layer is located on the doped layer.

[0016] In some embodiments of this disclosure, the heterojunction solar cell further includes:

[0017] The electrode is located on the transparent conductive layer.

[0018] In some embodiments of this disclosure, the number of intrinsic amorphous silicon films deposited on the front and back sides of the silicon wafer is at least one.

[0019] In some embodiments of this disclosure, the material of the second region of the doped layer located on the front side of the silicon wafer is μc-SiOx:H.

[0020] The second aspect of this disclosure provides a heterojunction solar cell, which is fabricated using the heterojunction solar cell fabrication method described in the first aspect.

[0021] A third aspect of this disclosure provides a method for fabricating a heterojunction solar cell, comprising:

[0022] A silicon wafer with an amorphous silicon film deposited on both sides is provided. The silicon wafer includes a front side and a back side, and the amorphous silicon film includes a first region and a second region on both sides. The boundary line between the first region and the second region surrounds the edge of the silicon wafer. The second region is close to the edge of the silicon wafer, and the first region is farther away from the edge of the silicon wafer than the second region.

[0023] The amorphous silicon film layer on the front side is doped with N-type, and the amorphous silicon film layer on the back side is doped with P-type.

[0024] The amorphous silicon in the second region on both sides of the silicon wafer is crystallized into microcrystalline silicon.

[0025] According to the heterojunction solar cell and its fabrication method provided in this disclosure, by crystallizing the amorphous silicon film layer in the first region on the front and back sides of the silicon wafer into a microcrystalline silicon film layer, while the second region remains an amorphous silicon film layer, on the one hand, the high-rate deposition of amorphous silicon and the excellent electrical properties of microcrystalline silicon can be utilized simultaneously; on the other hand, the process is less difficult, which can significantly reduce costs and increase production capacity. Attached Figure Description

[0026] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0027] Figure 1 A flowchart illustrating a method for fabricating a heterojunction solar cell according to an embodiment of the present disclosure is shown schematically.

[0028] Figure 2 This schematic diagram illustrates the structure after deposition of an intrinsic amorphous silicon film according to an embodiment of the present disclosure;

[0029] Figure 3 A schematic diagram illustrating the structure after deposition of an amorphous silicon film according to an embodiment of the present disclosure is shown.

[0030] Figure 4 This schematic diagram illustrates the structure of a crystallized amorphous silicon film according to an embodiment of the present disclosure.

[0031] Figure 5A This schematically illustrates a test bitmap of regions 1 to 7 on the front side being crystallized using a Raman spectrometer according to an embodiment of the present disclosure;

[0032] Figure 5B The Raman spectra corresponding to test regions 1 to 7 are schematically shown according to embodiments of the present disclosure;

[0033] Figure 6 A schematic TEM image of the front side after crystallization treatment according to an embodiment of the present disclosure is shown.

[0034] Figure 7 A schematic diagram illustrating the structure after deposition of a TCO film according to an embodiment of the present disclosure is shown.

[0035] Figure 8 A schematic diagram of a heterojunction solar cell according to an embodiment of the present disclosure is shown.

[0036] Explanation of reference numerals in the attached figures:

[0037] Silicon wafer-10, intrinsic amorphous silicon film-20, amorphous silicon film-30, N-type doped amorphous silicon film-31, P-type doped amorphous silicon film-32, microcrystalline silicon film-40, TCO film-50, electrode-60, front electrode-61, back electrode-62, first region-100, second region-200; doped layer-70. Detailed Implementation

[0038] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0040] In the description of this disclosure, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0041] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0042] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0043] In the description of this disclosure, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If the terms "first" and "second" are used, they are merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0044] In this document, unless otherwise stated, the reaction steps may be performed in the order described herein or not. For example, other steps may be included between reaction steps, and the order of reaction steps may be appropriately interchanged. This is something that those skilled in the art can determine based on conventional knowledge and experience. Preferably, the reaction methods described herein are performed sequentially.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0046] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0047] When using expressions such as "at least one of A, B, and C", they should generally be interpreted in accordance with the meaning that is commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc.).

[0048] In related technologies, silicon heterojunction solar cell technology involves depositing a doped microcrystalline silicon film on an intrinsic amorphous silicon film to improve parameters such as the fill factor (FF) and open-circuit voltage (Voc). The preparation methods for the doped microcrystalline silicon film are direct deposition methods, including radio frequency plasma-enhanced chemical vapor deposition (RF-PECVD), hot-wire chemical vapor deposition (HWCVD), and very high frequency plasma-enhanced chemical vapor deposition (VHF-PECVD). However, these processes involve high processing difficulty and cost, low growth rates of the microcrystalline silicon film, and a tendency for leakage current, which affects cell performance.

[0049] This disclosure provides a heterojunction solar cell and its fabrication method, comprising: providing a silicon wafer with amorphous silicon films deposited on both sides, the two sides of the silicon wafer including a front side and a back side, each side of the amorphous silicon film including a first region and a second region, the boundary between the first region and the second region surrounding the edge of the silicon wafer, the second region being closer to the edge of the silicon wafer, and the first region being farther from the edge of the silicon wafer than the second region; doping the amorphous silicon film on the front side with N-type and the amorphous silicon film on the back side with P-type; and crystallizing the amorphous silicon in the second region on both sides of the silicon wafer into microcrystalline silicon. By crystallizing the amorphous silicon film in the middle region on the front and back sides of the silicon wafer, i.e., the first region, into a microcrystalline silicon film, while the region outside the middle region, i.e., the second region, remains an amorphous silicon film, on the one hand, the high-rate deposition of amorphous silicon and the excellent electrical properties of microcrystalline silicon can be utilized simultaneously; on the other hand, the process is less difficult, which can significantly reduce costs and increase production capacity, making silicon heterojunction solar cells more competitive in the market.

[0050] To more clearly illustrate the heterojunction solar cell and its fabrication method provided in the embodiments of this disclosure, the heterojunction solar cell and its fabrication method will be described below in conjunction with the accompanying drawings.

[0051] Figure 1 A flowchart illustrating a method for fabricating a heterojunction solar cell according to an embodiment of the present disclosure is shown.

[0052] like Figure 1 As shown, the method for fabricating a heterojunction solar cell in this embodiment includes operations S110 to S130.

[0053] In operation S110, a silicon wafer 10 with an amorphous silicon film layer 30 deposited on both sides is provided. The two sides of the silicon wafer 10 include a front side and a back side. The amorphous silicon film layer 30 includes a first region 100 and a second region 200 on both sides. The boundary line between the first region 100 and the second region 200 surrounds the edge of the silicon wafer 10. The second region 200 is closer to the edge of the silicon wafer 10, and the first region 100 is farther away from the edge of the silicon wafer 10 than the second region 200.

[0054] In operation S120, the amorphous silicon film layer on the front side is doped with N-type and the amorphous silicon film layer on the back side is doped with P-type.

[0055] In operation S130, the amorphous silicon in the second region 200 on both sides of the silicon wafer 10 is crystallized into microcrystalline silicon.

[0056] In some embodiments of this disclosure, providing a silicon wafer 10 with amorphous silicon film layers 30 deposited on both sides includes: providing an N-type monocrystalline silicon wafer 10; cleaning and texturing both sides of the N-type monocrystalline silicon wafer 10 to obtain a texturized wafer; and depositing amorphous silicon film layers 30 on both sides of the texturized wafer to obtain a silicon wafer 10 with amorphous silicon film layers 30 deposited on both sides.

[0057] In this disclosure, the cleaning and texturing process can be a pyramidal texturing process, a corrosion-resistant anti-texturing process, etc. Correspondingly, the resulting texturing sheet can have a pyramidal texturing structure, a corrosion-resistant anti-texturing structure, etc. This disclosure does not impose any limitations on this.

[0058] In some embodiments of this disclosure, the deposition of amorphous silicon film layers 30 on both sides of the textured wafer to obtain a silicon wafer 10 with amorphous silicon film layers 30 deposited on both sides can be: First, as... Figure 2 As shown, intrinsic amorphous silicon films 20 are deposited on the front and back sides of the textured wafer, respectively; then, as... Figure 3 As shown, an N-type doped amorphous silicon film 31 is deposited on the intrinsic amorphous silicon film 20 deposited on the front side of the textured wafer, and a P-type doped amorphous silicon film 32 is deposited on the intrinsic amorphous silicon film 20 deposited on the back side of the textured wafer; finally, a silicon wafer 10 with amorphous silicon film 30 deposited on both sides is obtained.

[0059] In this embodiment, the material of the intrinsic amorphous silicon film 20 is illustrated using a-Si:H(i) as an example. The material of the N-type doped amorphous silicon film 31 is illustrated using a-Si:H(n) as an example. + The following is an illustration using an example. The material of the p-type doped amorphous silicon film 32 is a-Si:H(p + The following example illustrates the process. The microcrystalline silicon film 40 obtained by crystallizing the N-type doped amorphous silicon film 31 uses the material μ-Si:H(n...)... + The following example illustrates the process. The microcrystalline silicon film 40 obtained by crystallizing the p-type doped amorphous silicon film 32 uses a material of μ-Si:H(p) = ... + The above example is used for illustration. It is understood that those skilled in the art may make other equivalent substitutions to the above materials without departing from the purpose of this disclosure.

[0060] In some embodiments of this disclosure, the number of intrinsic amorphous silicon film layers 20 deposited on the front and back sides of the silicon wafer 10 is at least one. The number of intrinsic amorphous silicon film layers 20 deposited on the front and back sides of the silicon wafer 10 may be the same or different.

[0061] In some embodiments of this disclosure, the thickness of the N-type doped amorphous silicon film 31 is between 15 and 40 nanometers. The thickness of the P-type doped amorphous silicon film 32 is between 15 and 40 nanometers. The thicknesses of the N-type doped amorphous silicon film 31 and the P-type doped amorphous silicon film 32 may be the same or different. This disclosure does not impose any limitations on this.

[0062] Figure 4 A schematic cross-sectional view of the crystallized amorphous silicon film 30 according to an embodiment of the present disclosure is shown.

[0063] like Figure 4 As shown, after the amorphous silicon in the second region 200 on both sides of the silicon wafer 10 is crystallized into microcrystalline silicon, a doped layer 70 is formed.

[0064] The doped layers 70 on both sides of the silicon wafer 10 include a first region 100 and a second region 200. The second region 200 is the periphery of the doped layer 70, that is, the edge region. The first region 100 is the region excluding the second region 200, that is, the central region.

[0065] According to the embodiments of this disclosure, the amorphous silicon film layer 30 of the second region 200 on the front and back sides of the silicon wafer 10 is retained. By crystallizing the amorphous silicon film layer 30 in the middle region into a microcrystalline silicon film layer 40, and retaining the amorphous silicon film layer 30 in the edge region, since the amorphous silicon film layer 30 in the edge region has better uniformity and lower conductivity than the microcrystalline silicon film layer 40, the amorphous silicon film layer 30 in the edge region of this disclosure embodiment can effectively improve the leakage current at the edge of the solar cell, while the microcrystalline silicon film layer 40 in the middle region can improve the VOC, FF, Rsh and other parameters of the prepared heterojunction solar cell and reduce the series resistance.

[0066] Understandably, in this embodiment, the edge of the first region 100 does not coincide with the edge of the silicon wafer 10. The edge of the second region 200 may coincide with the edge of the silicon wafer 10.

[0067] In some embodiments of this disclosure, the width of the second region 200 can be between 0.01 and 5 mm. For example, the width of the second region 200 can be 0.01 mm. Another example is that the width of the second region 200 can be 0.09 mm. Yet another example is that the width of the second region 200 can be 5 mm.

[0068] In an alternative implementation, the widths of the four sides of the second region 200 may be the same or different. In one example, the four sides of the second region 200 include a first side perimeter, a second side perimeter, a third side perimeter, and a fourth side perimeter. For example, as... Figure 5AAs shown, the width of the second region 200 is the same on all four sides. For example, the width of the first side perimeter of the second region 200 is 0.01 mm, the width of the second side perimeter of the second region 200 is 0.05 mm, the width of the third side perimeter of the second region 200 is 0.05 mm, and the width of the fourth side perimeter of the second region 200 is 0.09 mm.

[0069] The operation in S130, which crystallizes the amorphous silicon in the second region 200 on both sides of the silicon wafer 10 into microcrystalline silicon, can be achieved using laser heating crystallization technology. Laser heating crystallization technology is implemented using a laser device.

[0070] In one implementation, taking the N-type doped amorphous silicon film 31 of the first region 100 on the front side of the crystalline silicon wafer 10 as an example, the film thickness can be 20 nm. Green light with a center wavelength of 500–550 nm can be used to irradiate the N-type doped amorphous silicon film 31 of the first region 100. The scanning speed can be controlled between 0.1 and 1 m / s, the laser power can be controlled between 15% and 40%, the corresponding laser equipment power can be 50 W, and the optimal energy density range of the green sodium second laser can be 250–400 mJ / cm². 2 .

[0071] Figure 5A The diagram schematically illustrates a test bitmap of regions 1 to 7 on the front side being crystallized using a Raman spectrometer according to an embodiment of the present disclosure. Figure 5B The Raman spectra corresponding to test regions 1 to 7 are schematically shown according to an embodiment of the present disclosure.

[0072] like Figure 5A and 5B As shown, Raman spectroscopy was used to test the first region 100 (laser-irradiated region, regions 4-7) and the second region 200 (non-laser-irradiated region, regions 1-3). The characteristic peaks at test sites 4-7 in the μ-Si:H(n+) region were all asymmetric Lorentz line peaks, with a characteristic peak at 510 cm⁻¹. -1 The characteristic peak at test sites 1–3 in the a-Si:H(n+) region is 480 cm⁻¹. -1 This indicates that after laser irradiation, the first region 100 (laser-irradiated area) on the front of the solar cell was crystallized, while the second region 200 (non-laser-irradiated area) remained an amorphous silicon film 31 (characteristic peak of monocrystalline silicon at 520 cm⁻¹). -1 Characteristic peak of amorphous silicon at 480 cm⁻¹ -1 Characteristic peaks of microcrystalline silicon: 500–518 cm⁻¹ -1 ).

[0073] like Figure 6 As shown, calculations show that the crystallinity of the doped layer 70 after irradiation with green sodium laser reaches over 60%, and the presence of grains can be seen in the TEM image. Figure 6As indicated by the arrow.

[0074] In this embodiment, the output of laser energy can be controlled to change the temperature of the laser-irradiated interface. Laser energy density is positively correlated with the temperature of the laser-irradiated interface. Higher laser energy density results in a higher temperature at the laser-irradiated interface, making it easier to reach the crystallization temperature of the amorphous silicon film.

[0075] In some embodiments of this disclosure, the first region 100 on the front side of the silicon wafer 10 and the first region 100 on the back side of the silicon wafer 10 may be the same or different in size. The positions of the first region 100 on the front side of the silicon wafer 10 and the first region 100 on the back side of the silicon wafer 10 may be the same or different. For example, the first region 100 on the front side of the silicon wafer 10 has a width of 20 mm and is located in the exact center of the front side of the silicon wafer 10, while the first region 100 on the back side of the silicon wafer 10 has a width of 25 mm and is located slightly to the left of the center of the front side of the silicon wafer 10. Another example is that the first region 100 on both the front and back sides of the silicon wafer 10 has a width of 20 mm and is located in the exact center of the front side of the silicon wafer 10.

[0076] In some embodiments of this disclosure, the second region 200 on the front side of the silicon wafer 10 and the second region 200 on the back side of the silicon wafer 10 may have the same or different sizes. For example, the width of the second region 200 on the front side of the silicon wafer 10 is 0.09 mm, and the width of the second region 200 on the back side of the silicon wafer 10 is 3 mm. Another example is that the width of the second region 200 on both the front and back sides of the silicon wafer 10 is 3 mm.

[0077] Understandably, the sum of the width of the first region 100 and the width of the second region 200 can be equal to the width of the silicon wafer 10.

[0078] In some embodiments of this disclosure, after operation S130 crystallizes the amorphous silicon in the second region 200 on both sides of the silicon wafer 10 into microcrystalline silicon to obtain the initially prepared solar cell, it can also be further processed as follows: Figure 7 As shown, a transparent conductive oxide (TCO) layer 50 is deposited on both sides of the initially prepared solar cell. Then, as... Figure 8 As shown, a front electrode 61 is fabricated on the front side of the TCO layer 50, and a back electrode 62 is fabricated on the back side of the TCO layer 50 to obtain a completed heterojunction solar cell.

[0079] In one embodiment, a PVD process can be used to deposit a TCO layer 50 on the front and back sides of the initially prepared solar cell. Printing, photoinjection, and testing are then performed on the TCO layer 50 to fabricate the electrode 60.

[0080] Printing can be performed using screen printing or laser transfer of one or more of low-temperature silver paste, low-temperature copper paste, and silver-coated copper paste. Photoinjection can be performed by electroplating one or more alloys of Al, Ti, Ni, Co, Ag, Cu, and Sn to form patterned metal grid lines. This disclosure does not limit the scope of the application.

[0081] This disclosure also provides an embodiment of using... Figures 1 to 8 The heterojunction solar cell is prepared by the method shown.

[0082] Based on the above-described method for fabricating heterojunction solar cells, this disclosure also provides a heterojunction solar cell. The structure of this heterojunction solar cell can be referred to... Figure 8 As shown. The following will combine Figure 8 This heterojunction solar cell is described in detail.

[0083] like Figure 8 As shown, the heterojunction solar cell includes: a silicon wafer 10, an intrinsic amorphous silicon film layer 20, a doped layer 70, a TCO layer 50, and an electrode 60. The silicon wafer 10 has opposing front and back sides. The intrinsic amorphous silicon film layer 20 is located on both the front and back sides of the silicon wafer 10. The doped layer 70 is located on the intrinsic amorphous silicon film layer 20, and the doped layer 70 has a first region 100 and a second region 200. The second region 200 surrounds the edge of the silicon wafer 10 and encloses the first region 100. The first region 100 is made of microcrystalline silicon, forming a microcrystalline silicon film layer 40. The second region 200 is made of amorphous silicon, forming an amorphous silicon film layer 30. The TCO layer 50 is disposed on the doped layer 70. The electrode 60 is disposed on the TCO layer 50. The doped layer 70 on the front side of the silicon wafer 10 is N-type doped, and the doped layer 70 on the back side of the silicon wafer 70 is P-type doped.

[0084] In this disclosure, the placement and number of electrodes 60 can be selected according to actual conditions, and this disclosure does not impose any restrictions. For example, the position of the electrodes 60 may correspond to the amorphous silicon film layer 30. Another example is that the position of the electrodes 60 may correspond to the microcrystalline silicon film layer 40. Yet another example is that the position of the electrodes 60 may correspond to both the amorphous silicon film layer 30 and the microcrystalline silicon film layer 40. Still another example is that at least one electrode 60 may correspond to both the amorphous silicon film layer 30 and the microcrystalline silicon film layer 40.

[0085] According to embodiments of this disclosure, the material of the central region, i.e., the first region 100, is set to microcrystalline silicon, while the material of the edge region surrounding the first region 100, i.e., the second region 200, remains amorphous silicon. Since the amorphous silicon film layer 30 in the edge region has better uniformity and lower conductivity than the microcrystalline silicon film layer 40, the amorphous silicon film layer 30 in the edge region of this disclosure embodiment can effectively improve the leakage current at the edge of the solar cell, while the microcrystalline silicon film layer 40 in the central region can improve the VOC, FF, Rsh, and other parameters of the solar cell, and reduce the series resistance.

[0086] Table 1 shows a comparison of the performance parameters (Rs, Rsh, VOC, FF) of amorphous silicon heterojunction solar cells in related technologies and silicon heterojunction solar cells provided in the embodiments of this disclosure.

[0087] Table 1

[0088]

[0089]

[0090] As shown in Table 1 above, the series resistance Rs of amorphous silicon heterojunction solar cells in related technologies is between 4.00E-03Ω and 6.00E-03Ω, while the series resistance Rs of silicon heterojunction solar cells prepared according to embodiments of this disclosure is between 3.00E-04Ω and 7.00E-04Ω.

[0091] The parallel resistance Rsh of amorphous silicon heterojunction solar cells in related technologies is between 1.00E+03Ω and 5.00E+03Ω, while the parallel resistance Rsh of silicon heterojunction solar cells prepared according to embodiments of this disclosure is between 1.00E+05Ω and 3.00E+05Ω.

[0092] The open-circuit voltage Voc of amorphous silicon heterojunction solar cells in related technologies is between 0.745V and 0.748V, while the open-circuit voltage Voc of silicon heterojunction solar cells prepared according to embodiments of this disclosure is between 0.748V and 0.750V.

[0093] The efficiency Eff of amorphous silicon heterojunction solar cells in related technologies is between 24.90% and 25.40%, while the efficiency Eff of silicon heterojunction solar cells prepared according to embodiments of this disclosure is between 25.50% and 25.75%.

[0094] In embodiments of this disclosure, the crystallinity of the doped layer 70 can be any value. For example, the crystallinity of the doped layer 70 is 10%. Another example is that the crystallinity of the doped layer 70 is 60%, and yet another example is that the crystallinity of the doped layer 70 is 80%.

[0095] In an optional embodiment, the crystallinity of the doped layer 70 is not less than 60%. By setting the crystallinity of the doped layer 70 to not less than 60%, compared to the case where the crystallinity of the doped layer 70 is less than 60%, the parameters such as VOC, FF, and Rsh of the prepared heterojunction solar cell can be greatly improved, and the series resistance can be reduced.

[0096] In some embodiments of this disclosure, the width of the second region 200 is between 0.01 and 5 millimeters.

[0097] In some embodiments of this disclosure, the thickness of the doped layer 70, i.e., the N-type doped amorphous silicon film 31, located on the front side of the silicon wafer 10 is between 15 and 40 nanometers.

[0098] For example, the thickness of the N-type doped amorphous silicon film 31 is 15 nanometers. Another example is that the thickness of the N-type doped amorphous silicon film 31 is 18 nanometers. Yet another example is that the thickness of the N-type doped amorphous silicon film 31 is 40 nanometers.

[0099] In some embodiments of this disclosure, the thickness of the doped layer 70, i.e., the P-type doped amorphous silicon film 32, located on the back side of the silicon wafer 10, is between 15 and 40 nanometers.

[0100] For example, the thickness of the p-type doped amorphous silicon film 32 is 15 nanometers. Another example is that the thickness of the p-type doped amorphous silicon film 32 is 23 nanometers. Yet another example is that the thickness of the p-type doped amorphous silicon film 32 is 40 nanometers.

[0101] In some embodiments of this disclosure, the number of intrinsic amorphous silicon film layers 20 deposited on both the front and back sides of the silicon wafer is at least three. Those skilled in the art can specifically set the number of intrinsic amorphous silicon film layers 20 as needed.

[0102] For example, the number of intrinsic amorphous silicon film layers 20 deposited on the front side of the silicon wafer is 3, and the number of intrinsic amorphous silicon film layers 20 deposited on the back side of the silicon wafer is also 3. The first intrinsic amorphous silicon film layer adjacent to the silicon wafer 10 can be used to improve the short-circuit current of the heterojunction solar cell.

[0103] The second intrinsic amorphous silicon film layer can be used to improve the open-circuit voltage of heterojunction solar cells. The third intrinsic amorphous silicon film layer can be used to reduce the contact resistance of the intrinsic amorphous silicon film layer, improve the fill factor, reduce the light absorption of the intrinsic amorphous silicon film layer, and increase the short-circuit current.

[0104] For example, the number of intrinsic amorphous silicon film layers 20 deposited on the front side of the silicon wafer is 4, and the number of intrinsic amorphous silicon film layers 20 deposited on the back side of the silicon wafer is also 4. The first intrinsic amorphous silicon film layer adjacent to the silicon wafer 10 can be used to increase the short-circuit current of the heterojunction solar cell. The second intrinsic amorphous silicon film layer can be used to increase the open-circuit voltage of the heterojunction solar cell. The third intrinsic amorphous silicon film layer can be used to reduce the contact resistance of the intrinsic amorphous silicon film layer, increase the fill factor, reduce the light absorption of the intrinsic amorphous silicon film layer, and increase the short-circuit current. The fourth intrinsic amorphous silicon film layer can be used to prevent the diffusion of dopant atoms, while having high transmittance, thereby increasing the short-circuit current.

[0105] In some embodiments of this disclosure, the number of intrinsic amorphous silicon film layers 20 deposited on the front and back sides of the silicon wafer 10 may be the same or different.

[0106] For example, the number of intrinsic amorphous silicon film layers 20 deposited on the front side of silicon wafer 10 is two, and the number of intrinsic amorphous silicon film layers 20 deposited on the back side of silicon wafer 10 is three.

[0107] In some embodiments of this disclosure, the width of the first region 100 of the doped layer 70 on the front side of the silicon wafer 10 and the width of the first region 100 of the doped layer 70 on the back side of the silicon wafer 10 are the same or different.

[0108] In some embodiments of this disclosure, the first region 100 of the doped layer 70 on the front side of the silicon wafer 10 is located at the same or different position as the first region 100 of the doped layer 70 on the back side of the silicon wafer 10.

[0109] In some embodiments of this disclosure, the width of the second region 200 of the doped layer 70 on the front side of the silicon wafer 10 and the width of the second region 200 of the doped layer 70 on the back side of the silicon wafer 10 are the same or different.

[0110] In some embodiments of this disclosure, the material of the second region 200 of the doped layer 70, i.e. the N-type doped amorphous silicon film layer 31, located on the front side of the silicon wafer 10, is μc-SiOx:H.

[0111] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0112] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A heterojunction solar cell, comprising: A silicon wafer has a front and a back side; An intrinsic amorphous silicon film layer is located on the front and back sides of the silicon wafer; A doped layer is located on the intrinsic amorphous silicon film layer. The doped layer has a first region and a second region. The second region surrounds the edge of the silicon wafer and encloses the first region. The material of the first region is microcrystalline silicon, and the material of the second region is amorphous silicon. The doping type of the doped layer on the front side of the silicon wafer is N-type doping, and the doping type of the doped layer on the back side of the silicon wafer is P-type doping. The second region is the area surrounding the doped layer, and the first region is the area of ​​the doped layer excluding the second region.

2. The heterojunction solar cell according to claim 1, wherein, The width of the second region is between 0.01 and 5 millimeters.

3. The heterojunction solar cell according to claim 1, wherein, The crystallinity of the doped layer is not less than 60%.

4. The heterojunction solar cell according to claim 1, wherein, The thickness of the doped layer located on the front side of the silicon wafer is between 15 and 40 nanometers.

5. The heterojunction solar cell according to claim 1, wherein, The thickness of the doped layer located on the back side of the silicon wafer is between 15 and 40 nanometers.

6. The heterojunction solar cell according to claim 1, wherein, The heterojunction solar cell further includes: A transparent conductive layer is located on the doped layer.

7. The heterojunction solar cell according to claim 6, wherein, The heterojunction solar cell further includes: The electrode is located on the transparent conductive layer.

8. The heterojunction solar cell according to claim 1, wherein, The intrinsic amorphous silicon film deposited on both the front and back sides of the silicon wafer is at least one layer.

9. The heterojunction solar cell according to claim 1, wherein, The material of the first region of the doped layer located on the front side of the silicon wafer is μc-SiOx:H.

10. A method for fabricating a heterojunction solar cell, comprising: A silicon wafer with an amorphous silicon film deposited on both sides is provided. The silicon wafer includes a front side and a back side, and the amorphous silicon film includes a first region and a second region on both sides. The boundary line between the first region and the second region surrounds the edge of the silicon wafer. The second region is close to the edge of the silicon wafer, and the first region is farther away from the edge of the silicon wafer than the second region. The amorphous silicon film layer on the front side is doped with N-type, and the amorphous silicon film layer on the back side is doped with P-type. The amorphous silicon in the first region on both sides of the silicon wafer is crystallized into microcrystalline silicon; The second region is the area surrounding the doped layer, and the first region is the area of ​​the doped layer excluding the second region.

Images