Semiconductor device and manufacturing method thereof, power module, power conversion circuit, vehicle

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes: an epitaxial layer including a groove; an oxide layer and a polysilicon layer are included in the groove, and the oxide layer is located between the polysilicon layer and the epitaxial layer; the oxide layer includes a first oxide layer and a second oxide layer, the first oxide layer covers the sidewall of the groove, and the second oxide layer covers the first oxide layer and the bottom of the groove; the thickness of the second oxide layer at the bottom of the groove is greater than the sum of the thicknesses of the first oxide layer and the second oxide layer on the sidewall of the groove; alternatively, an oxidation barrier layer is further included in the groove, the oxidation barrier layer is located on the sidewall of the groove and between the first oxide layer and the second oxide layer, and the thickness of the second oxide layer at the bottom of the groove is greater than the sum of the thicknesses of the first oxide layer, the oxidation barrier layer, and the second oxide layer on the sidewall of the groove; the present invention can improve the switching speed and breakdown voltage of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] The trench metal-oxide-semiconductor (MOS) device has advantages such as a large current density and a small cell pitch. However, the high electric fields at the bottom and corners of the trench cause a very high electric field on the gate oxide layer, and the oxide layer is prone to breakdown. In order to better protect the gate oxide layer and obtain better reliability, the mainstream solutions in the industry are as follows: The first solution is to adopt a double trench structure, and source double trenches are constructed on both sides of the gate trench to shield the electric field at the bottom of the gate trench; the second solution adopts an asymmetric trench structure, and a p+ region is embedded at the bottom of the trench to weaken the electric field at the bottom of the trench; the third solution adopts a structure in which the gate oxide layer at the bottom of the trench is covered with a P+ well, and the electric field at the bottom corner part of the P+ well at the bottom of the trench reaches the maximum value, so that the electric field in the gate oxide is relaxed, and the reliability of the gate oxide layer is improved. However, when manufacturing a trench MOS device, the oxide layer thicknesses at the bottom and sidewalls of the trench are basically the same, which will cause problems such as easy breakdown of the device and slow switching speed of the device. Summary of the Invention

[0003] The present invention provides a semiconductor device and a preparation method thereof, a power module, a power conversion circuit, and a vehicle, which can improve the switching speed and breakdown voltage of the device.

[0004] According to one aspect of the present invention, there is provided a semiconductor device, including:

[0005] A substrate and an epitaxial layer stacked in sequence;

[0006] The epitaxial layer includes a groove; the groove is located on the side of the epitaxial layer away from the substrate; an oxide layer and a polysilicon layer are included in the groove, and the oxide layer is located between the polysilicon layer and the epitaxial layer; the oxide layer includes a first oxide layer and a second oxide layer, the first oxide layer covers the sidewall of the groove, the second oxide layer is located on the side of the first oxide layer away from the epitaxial layer, and the second oxide layer covers the first oxide layer and the bottom of the groove;

[0007] The thickness of the second oxide layer at the bottom of the groove is greater than the sum of the thicknesses of the first oxide layer and the second oxide layer on the sidewall of the groove; or, an oxidation barrier layer is further included in the groove, the oxidation barrier layer is located on the sidewall of the groove and between the first oxide layer and the second oxide layer, and the thickness of the second oxide layer at the bottom of the groove is greater than the sum of the thicknesses of the first oxide layer, the oxidation barrier layer, and the second oxide layer on the sidewall of the groove.

[0008] Optionally, the oxidation rate of the material of the oxidation barrier layer is lower than that of the material of the epitaxial layer.

[0009] Optionally, the material of the epitaxial layer includes silicon carbide;

[0010] The materials of the first oxide layer and the second oxide layer include silicon oxide;

[0011] The material of the oxidation barrier layer includes any one of silicon nitride and silicon oxynitride.

[0012] Optionally, when the oxidation barrier layer is not included in the groove, the thickness of the second oxide layer at the bottom of the groove is 100 - 150 nm; the sum of the thicknesses of the first oxide layer and the second oxide layer on the sidewall of the groove is 20 - 60 nm; the thickness of the first oxide layer is 10 - 20 nm;

[0013] When the oxidation barrier layer is included in the groove, the thickness of the second oxide layer at the bottom of the groove is 100 - 150 nm; the sum of the thicknesses of the first oxide layer, the oxidation barrier layer, and the second oxide layer on the sidewall of the groove is 20 - 60 nm; the thickness of the first oxide layer is 10 - 20 nm; the thickness of the oxidation barrier layer is 0 - 30 nm; the thickness of the second oxide layer on the sidewall of the groove is 10 - 50 nm.

[0014] Optionally, the groove includes a gate groove and a source groove;

[0015] The semiconductor device further includes an insulating layer and a metal layer. The insulating layer is located on the side of the gate groove away from the substrate and covers the polysilicon layer in the gate groove; the metal layer is located on the side of the insulating layer away from the epitaxial layer; the polysilicon layer in the source groove is connected through the metal layer.

[0016] According to another aspect of the present invention, a power module is provided, including a substrate and the semiconductor device according to any embodiment of the present invention, and the substrate is used to carry the semiconductor device.

[0017] According to another aspect of the present invention, a power conversion circuit is provided. The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0018] The power conversion circuit includes a circuit board and the semiconductor device according to any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0019] According to another aspect of the present invention, a vehicle is provided, including a load and the power conversion circuit according to any embodiment of the present invention. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0020] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, including:

[0021] Forming an epitaxial layer on one side of a substrate;

[0022] Forming a groove in the epitaxial layer; the groove is located on the side of the epitaxial layer away from the substrate;

[0023] Forming an oxide layer in the groove, wherein the oxide layer includes a first oxide layer and a second oxide layer, the first oxide layer covers the sidewall of the groove, the second oxide layer is located on the side of the first oxide layer away from the epitaxial layer, the second oxide layer covers the first oxide layer and the bottom of the groove, and the thickness of the second oxide layer at the bottom of the groove is greater than the sum of the thicknesses of the first oxide layer and the second oxide layer on the sidewall of the groove; or, forming an oxide layer and an oxidation barrier layer in the groove, wherein the oxidation barrier layer is located on the sidewall of the groove and between the first oxide layer and the second oxide layer, and the thickness of the second oxide layer at the bottom of the groove is greater than the sum of the thicknesses of the first oxide layer, the oxidation barrier layer, and the second oxide layer on the sidewall of the groove;

[0024] Forming a polysilicon layer on the side of the oxide layer away from the epitaxial layer.

[0025] Optionally, forming an oxide layer in the groove includes:

[0026] Forming a first oxide layer on the side of the epitaxial layer away from the substrate;

[0027] Forming an oxidation barrier layer on the side of the first oxide layer away from the epitaxial layer;

[0028] Removing the first oxide layer and the oxidation barrier layer at the bottom of the groove, and the first oxide layer and the oxidation barrier layer outside the groove;

[0029] Simultaneously performing an oxidation treatment on the epitaxial layer and the oxidation barrier layer on the sidewall of the groove until the oxidation barrier layer is completely oxidized to form a second oxide layer; wherein the oxidation rate of the material of the oxidation barrier layer is lower than the oxidation rate of the material of the epitaxial layer;

[0030] Removing the second oxide layer outside the groove.

[0031] Optionally, forming an oxide layer and an oxidation barrier layer in the groove includes:

[0032] Forming a first oxide layer on the side of the epitaxial layer away from the substrate;

[0033] Forming an oxidation barrier layer on the side of the first oxide layer away from the epitaxial layer;

[0034] Removing the first oxide layer and the oxidation barrier layer at the bottom of the groove, and the first oxide layer and the oxidation barrier layer outside the groove;

[0035] Meanwhile, an oxidation treatment is performed on both the epitaxial layer and the oxidation barrier layer on the sidewall of the groove, causing partial oxidation of the oxidation barrier layer to form a second oxide layer; wherein, the oxidation rate of the material of the oxidation barrier layer is lower than that of the material of the epitaxial layer;

[0036] Remove the second oxide layer outside the groove.

[0037] Optionally, forming a first oxide layer on the bottom and sidewalls of the groove, including:

[0038] Form a first oxide layer on the bottom and sidewalls of the groove through a thermal oxidation process;

[0039] Meanwhile, performing an oxidation treatment on both the epitaxial layer and the oxidation barrier layer on the sidewall of the groove, including:

[0040] Perform an oxidation treatment on both the epitaxial layer and the oxidation barrier layer on the sidewall of the groove through a thermal oxidation process.

[0041] Optionally, forming an oxidation barrier layer on the side of the first oxide layer away from the epitaxial layer, including:

[0042] Form an oxidation barrier layer on the side of the first oxide layer away from the epitaxial layer through a deposition process.

[0043] The semiconductor device provided by the technical solution of the embodiment of the present invention includes a substrate and an epitaxial layer stacked in sequence; the epitaxial layer includes a groove; the groove is located on the side of the epitaxial layer away from the substrate; the groove includes an oxide layer and a polysilicon layer, and the oxide layer is located between the polysilicon layer and the epitaxial layer; the oxide layer includes a first oxide layer and a second oxide layer, the first oxide layer covers the sidewall of the groove, the second oxide layer is located on the side of the first oxide layer away from the epitaxial layer, and the second oxide layer covers the first oxide layer and the bottom of the groove; the thickness of the second oxide layer at the bottom of the groove is greater than the sum of the thicknesses of the first oxide layer and the second oxide layer on the sidewall of the groove; or, an oxidation barrier layer is further included in the groove, the oxidation barrier layer is located on the sidewall of the groove and between the first oxide layer and the second oxide layer, and the thickness of the second oxide layer at the bottom of the groove is greater than the sum of the thicknesses of the first oxide layer, the oxidation barrier layer, and the second oxide layer on the sidewall of the groove. Since the electric field at the corner of the groove in the device is relatively large and breakdown is likely to occur, the relatively thick second oxide layer at the bottom of the groove can withstand a greater breakdown voltage without being broken down. Therefore, the present invention can increase the breakdown voltage of the device and avoid breakdown of the device. And since the sum of the thicknesses of the first oxide layer and the second oxide layer on the sidewall of the groove, or the sum of the thicknesses of the first oxide layer, the oxidation barrier layer, and the second oxide layer is thinner than the thickness of the second oxide layer at the bottom of the groove, the conductivity at the sidewall will be better, which can improve the switching speed of the device.

[0044] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0046] Figure 1 is a schematic structural diagram of a semiconductor device provided in Embodiment 1 of the present invention.

[0047] Figure 2 is a schematic structural diagram of another semiconductor device provided in Embodiment 1 of the present invention.

[0048] Figure 3 is a schematic structural diagram of another semiconductor device provided in Embodiment 1 of the present invention.

[0049] Figure 4 is a schematic structural diagram of another semiconductor device provided in Embodiment 1 of the present invention.

[0050] Figure 5 is a flowchart of a method for manufacturing a semiconductor device provided in Embodiment 2 of the present invention.

[0051] Figure 6 is Figure 5 a refined flowchart included in S130 in

[0052] Figure 7 is a schematic intermediate structure diagram of a semiconductor device provided in Embodiment 2 of the present invention.

[0053] Figure 8 is a schematic intermediate structure diagram of another semiconductor device provided in Embodiment 2 of the present invention.

[0054] Figure 9 is a schematic intermediate structure diagram of another semiconductor device provided in Embodiment 2 of the present invention.

[0055] Figure 10 is a schematic intermediate structure diagram of another semiconductor device provided in Embodiment 2 of the present invention.

[0056] Figure 11 is Figure 5 another refined flowchart included in S130 in

[0057] Figure 12 It is a schematic diagram of the intermediate structure of another semiconductor device provided in the second embodiment of the present invention. Detailed implementation manners

[0058] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0059] It should be noted that the terms "first", "second", etc. in the present invention are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0060] Embodiment 1

[0061] The embodiment of the present invention provides a semiconductor device. Figure 1 It is a schematic diagram of the structure of a semiconductor device provided in the first embodiment of the present invention. Figure 2 It is a schematic diagram of the structure of another semiconductor device provided in the first embodiment of the present invention. Refer to Figure 1 and Figure 2 , the semiconductor device includes:

[0062] A substrate 10 and an epitaxial layer 20 stacked in sequence; the epitaxial layer 20 includes a groove 30; the groove 30 is located on the side of the epitaxial layer 20 away from the substrate 10; the groove 30 includes an oxide layer 40 and a polysilicon layer 50, and the oxide layer 40 is located between the polysilicon layer 50 and the epitaxial layer 20; the oxide layer 40 includes a first oxide layer 41 and a second oxide layer 42, the first oxide layer 41 covers the side wall of the groove 30, the second oxide layer 42 is located on the side of the first oxide layer 41 away from the epitaxial layer 20, and the second oxide layer 42 covers the first oxide layer 41 and the bottom of the groove 30.

[0063] The thickness of the second oxide layer 42 at the bottom of the groove 30 is greater than the sum of the thicknesses of the first oxide layer 41 and the second oxide layer 42 on the side wall of the groove 30; or, refer toFigure 2 Moreover, the groove 30 further includes an oxidation barrier layer 60 which is located on the sidewall of the groove 30 and between the first oxide layer 41 and the second oxide layer 42. The thickness of the second oxide layer 42 at the bottom of the groove 30 is greater than the sum of the thicknesses of the first oxide layer 41, the oxidation barrier layer 60 and the second oxide layer 42 on the sidewall of the groove 30.

[0064] Wherein, the semiconductor device can be a silicon carbide trench metal oxide semiconductor field effect transistor (MOSFET). If the device is an N-type device, the substrate 10 is an N+ substrate, such as an N+ silicon carbide substrate; the epitaxial layer 20 is an N-epitaxial layer, such as an N-silicon carbide epitaxial layer; if the device is a P-type device, the substrate 10 is a P+ substrate and the epitaxial layer 20 is a P-epitaxial layer. The oxide layer 40 can be a silicon dioxide layer, and the oxidation barrier layer 60 can be a silicon nitride or silicon oxynitride. The polysilicon layer 50 can be used as a conductive electrode of the device.

[0065] Since the electric field at the corner of the groove of the device is relatively large and breakdown is likely to occur easily, the relatively thick second oxide layer 42 at the bottom of the groove 30 can withstand a greater breakdown voltage without being broken down. Therefore, the present invention can improve the breakdown voltage of the device and avoid breakdown of the device. And since the sum of the thicknesses of the first oxide layer 41 and the second oxide layer 42 on the sidewall of the groove 30, or the sum of the thicknesses of the first oxide layer 41, the oxidation barrier layer 60 and the second oxide layer 42 on the sidewall of the groove 30 is thinner than the thickness of the second oxide layer 42 at the bottom of the groove 30, the conductivity at the sidewall is better, which can improve the switching speed of the device.

[0066] The semiconductor device provided by the technical solution of the embodiment of the present invention includes a substrate 10 and an epitaxial layer 20 which are stacked in sequence; the epitaxial layer 20 includes a groove 30; the groove 30 is located on the side of the epitaxial layer 20 away from the substrate 10; the groove 30 includes an oxide layer 40 and a polysilicon layer 50, and the oxide layer 40 is located between the polysilicon layer 50 and the epitaxial layer 20; the oxide layer 40 includes a first oxide layer 41 and a second oxide layer 42, the first oxide layer 41 covers the side wall of the groove 30, the second oxide layer 42 is located on the side of the first oxide layer 41 away from the epitaxial layer 20, and the second oxide layer 42 covers the first oxide layer 41 and the bottom of the groove 30; the thickness of the second oxide layer 42 at the bottom of the groove 30 is greater than the sum of the thicknesses of the first oxide layer 41 and the second oxide layer 42 on the side wall of the groove 30; or, an oxidation barrier layer 60 is further included in the groove 30, the oxidation barrier layer 60 is located on the side wall of the groove 30 and between the first oxide layer 41 and the second oxide layer 42, and the thickness of the second oxide layer 42 at the bottom of the groove 30 is greater than the sum of the thicknesses of the first oxide layer 41, the oxidation barrier layer 60 and the second oxide layer 42 on the side wall of the groove 30. Since the electric field at the corner of the groove of the device is relatively large and breakdown is likely to occur, the second oxide layer 42 at the bottom of the groove 30 has a relatively large thickness and can withstand a greater breakdown voltage without being broken down. Therefore, the present invention can improve the breakdown voltage of the device and avoid breakdown of the device. And since the sum of the thicknesses of the first oxide layer 41 and the second oxide layer 42 on the side wall of the groove 30, or the sum of the thicknesses of the first oxide layer 41, the oxidation barrier layer 60 and the second oxide layer 42 is thinner than the thickness of the second oxide layer 42 at the bottom of the groove 30, the conductivity at the side wall is better, which can improve the switching speed of the device.

[0067] Optionally, the oxidation rate of the material of the oxidation barrier layer is lower than the oxidation rate of the material of the epitaxial layer.

[0068] Among them, the groove can be formed by conventional processes, such as etching process. The first oxide layer can be obtained by oxidizing the epitaxial layer, the oxidation barrier layer can be formed by deposition process, and the second oxide layer can be formed by oxidizing the epitaxial layer at the bottom of the groove and the oxidation barrier layer on the sidewall. The oxidation rate of the material of the oxidation barrier layer is lower than that of the material of the epitaxial layer. If the oxidation barrier layer is completely oxidized, due to the slow oxidation rate of the oxidation barrier layer and the fast oxidation rate of the epitaxial layer at the bottom of the groove, the thickness of the second oxide layer at the bottom of the groove will be greater than the sum of the thicknesses of the first oxide layer and the second oxide layer on the sidewall of the groove; if the oxidation barrier layer is partially oxidized, the remaining part of the oxidation barrier layer will cover the first oxide layer. Due to the slow oxidation rate of the oxidation barrier layer and the fast oxidation rate of the epitaxial layer at the bottom of the groove, the thickness of the second oxide layer at the bottom of the groove will be greater than the sum of the thicknesses of the first oxide layer, the oxidation barrier layer and the second oxide layer on the sidewall of the groove. The oxidation rate of the material of the oxidation barrier layer is lower than that of the material of the epitaxial layer. At the same time, the thickness of the oxidized oxidation barrier layer is smaller than that of the oxidized epitaxial layer. Therefore, when forming the second oxide layer, the thickness of the second oxide layer formed at the bottom of the groove will be greater than the thickness of the second oxide layer formed on the oxidation barrier layer on the sidewall of the groove; thus, the present invention can increase the breakdown voltage of the device and avoid breakdown of the device; at the same time, the conductivity at the sidewall will be better, and the switching speed of the device can be increased.

[0069] Optionally, the material of the epitaxial layer includes silicon carbide; the materials of the first oxide layer and the second oxide layer include silicon oxide; the material of the oxidation barrier layer includes any one of silicon nitride and silicon oxynitride.

[0070] Among them, after oxidizing silicon carbide by an oxidation process, a silicon oxide layer can be formed, and this silicon oxide layer is the first oxide layer; the oxidation barrier layer can be formed by depositing silicon nitride or silicon oxynitride. The second oxide layer can be formed by oxidizing the silicon carbide at the bottom of the groove and the silicon nitride and silicon oxynitride on the sidewall. The oxidation rates of silicon nitride and silicon oxynitride are lower than that of silicon carbide. Therefore, the thickness of the second oxide layer at the bottom of the groove can be greater than the sum of the thicknesses of the first oxide layer and the second oxide layer on the sidewall of the groove, or the thickness of the second oxide layer at the bottom of the groove can be greater than the sum of the thicknesses of the first oxide layer, the oxidation barrier layer and the second oxide layer on the sidewall of the groove, so that the breakdown voltage of the device can be increased and breakdown of the device can be avoided; at the same time, the conductivity at the sidewall will be better, and the switching speed of the device can be increased.

[0071] Optionally, when the oxidation barrier layer is not included in the groove, the thickness of the second oxide layer at the bottom of the groove is 100 - 150 nm; the sum of the thicknesses of the first oxide layer and the second oxide layer on the sidewall of the groove is 20 - 60 nm; the thickness of the first oxide layer is 10 - 20 nm; when the oxidation barrier layer is included in the groove, the thickness of the second oxide layer at the bottom of the groove is 100 - 150 nm; the sum of the thicknesses of the first oxide layer, the oxidation barrier layer and the second oxide layer on the sidewall of the groove is 20 - 60 nm; the thickness of the first oxide layer is 10 - 20 nm; the thickness of the oxidation barrier layer is 0 - 30 nm; the thickness of the second oxide layer on the sidewall of the groove is 10 - 50 nm.

[0072] Among them, the thicknesses of the formed first oxide layer and second oxide layer can be adjusted by controlling the oxidation conditions of the oxidation process. For example, the thicknesses of the first oxide layer and second oxide layer can be controlled to be thin or thick by adjusting the length of the oxidation time. When the oxidation barrier layer is not included in the groove, the thickness of the second oxide layer at the bottom of the groove is set to be 100 - 150 nm; the sum of the thicknesses of the first oxide layer and the second oxide layer on the sidewall of the groove is 20 - 60 nm; the thickness of the first oxide layer is 10 - 20 nm; when the oxidation barrier layer is included in the groove, the thickness of the second oxide layer at the bottom of the groove is set to be 100 - 150 nm; the sum of the thicknesses of the first oxide layer, the oxidation barrier layer and the second oxide layer on the sidewall of the groove is 20 - 60 nm; the thickness of the first oxide layer is 10 - 20 nm; the thickness of the oxidation barrier layer is 0 - 30 nm; the thickness of the second oxide layer on the sidewall of the groove is 10 - 50 nm; it can not only achieve a relatively thick thickness of the second oxide layer at the bottom of the groove, which can withstand a greater breakdown voltage without being broken down, but also make the sum of the thicknesses of the first oxide layer and the second oxide layer on the sidewall of the groove, or the sum of the thicknesses of the first oxide layer, the oxidation barrier layer and the second oxide layer thinner than the thickness of the second oxide layer at the bottom of the groove, so that the conductivity at the sidewall is better, thereby improving the switching speed of the device.

[0073] Optionally, Figure 3 is a schematic structural diagram of another semiconductor device provided in the first embodiment of the present invention, Figure 4 is a schematic structural diagram of another semiconductor device provided in the first embodiment of the present invention, referring to Figure 3 and Figure 4 , the groove 30 includes a gate groove 32 and a source groove 31.

[0074] The semiconductor device further includes an insulating layer 70 and a metal layer 80. The insulating layer 70 is located on the side of the gate groove 32 away from the substrate 10, and the insulating layer 70 covers the polysilicon layer 50 in the gate groove 32; the metal layer 80 is located on the side of the insulating layer 70 away from the epitaxial layer 20; the polysilicon layer 50 in the source groove 31 is connected through the metal layer 80.

[0075] Among them, the semiconductor device further includes a drain metal 90, the drain metal 90 is located on the side of the substrate 10 away from the epitaxial layer 20, the polysilicon layer 50 in the gate groove 32 can be used as a gate, and the metal layer 80 can be used as a source metal. The semiconductor device further includes a first conductivity type region 21 and a second conductivity type region 22; the second conductivity type region 22 is located on the side of the first conductivity type region 21 away from the substrate 10, and both the first conductivity type region 21 and the second conductivity type region 22 are located between the source groove 31 and the gate groove 32. The first conductivity type region 21 is formed by implanting first conductivity type ions in the epitaxial layer 20, and the first conductivity type region 21 can be a lightly doped region; the second conductivity type region 22 is formed by implanting second conductivity type ions in the epitaxial layer 20, and the second conductivity type region 22 can be a second conductivity type + region, that is, a heavily doped region. If the device is an N-type device, the first conductivity type is P-type and the second conductivity type is N-type; if the device is a P-type device, the first conductivity type is N-type and the second conductivity type is P-type.

[0076] Based on the above embodiments, an embodiment of the present invention further provides a power module, including a substrate and the semiconductor device according to any embodiment of the present invention, and the substrate is used to carry the semiconductor device.

[0077] The power module provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device according to any embodiment of the present invention.

[0078] Based on the above embodiments, an embodiment of the present invention further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and the semiconductor device according to any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0079] The power conversion circuit provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device according to any embodiment of the present invention.

[0080] Based on the above embodiments, an embodiment of the present invention further provides a vehicle, including a load and the power conversion circuit according to any embodiment of the present invention, and the power conversion circuit is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current and then input it to the load.

[0081] The vehicle provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device according to any embodiment of the present invention.

[0082] Embodiment 2

[0083] An embodiment of the present invention provides a method for manufacturing a semiconductor device based on the above embodiments. Figure 5 It is a flowchart of a method for manufacturing a semiconductor device provided in the second embodiment of the present invention. Refer to Figure 5 , the manufacturing method includes:

[0084] S110. Form an epitaxial layer on one side of the substrate.

[0085] Among them, if the device is an N-type device, the substrate is an N+ substrate, for example, it can be an N+ silicon carbide substrate; the epitaxial layer is an N-epitaxial layer, for example, it can be an N-silicon carbide epitaxial layer; if the device is a P-type device, the substrate 10 is a P+ substrate, and the epitaxial layer 20 is a P-epitaxial layer.

[0086] S120. Form a groove in the epitaxial layer; the groove is located on the side of the epitaxial layer away from the substrate.

[0087] Among them, a photoresist can be formed on the side of the epitaxial layer away from the substrate, the photoresist is patterned, and the epitaxial layer is etched to form a groove.

[0088] S130. Form an oxide layer in the groove. Among them, the oxide layer includes a first oxide layer and a second oxide layer. The first oxide layer covers the side wall of the groove, the second oxide layer is located on the side of the first oxide layer away from the epitaxial layer, and the second oxide layer covers the first oxide layer and the bottom of the groove. The thickness of the second oxide layer at the bottom of the groove is greater than the sum of the thicknesses of the first oxide layer and the second oxide layer on the side wall of the groove; or, form an oxide layer and an oxidation barrier layer in the groove. Among them, the oxidation barrier layer is located on the side wall of the groove and is located between the first oxide layer and the second oxide layer. The thickness of the second oxide layer at the bottom of the groove is greater than the sum of the thicknesses of the first oxide layer, the oxidation barrier layer, and the second oxide layer on the side wall of the groove.

[0089] Among them, the oxidation rate of the material of the oxidation barrier layer is lower than the oxidation rate of the material of the epitaxial layer; the first oxide layer can be obtained by oxidizing the epitaxial layer, the oxidation barrier layer can be formed by a deposition process, and the second oxide layer can be formed by oxidizing the epitaxial layer at the bottom of the groove and the oxidation barrier layer on the side wall. If the oxidation barrier layer is completely oxidized, since the oxidation rate of the oxidation barrier layer is slow and the oxidation rate of the epitaxial layer at the bottom of the groove is fast, the thickness of the second oxide layer at the bottom of the groove will be greater than the sum of the thicknesses of the first oxide layer and the second oxide layer on the side wall of the groove; if the oxidation barrier layer is partially oxidized, the remaining part of the oxidation barrier layer will cover the first oxide layer. Since the oxidation rate of the oxidation barrier layer is slow and the oxidation rate of the epitaxial layer at the bottom of the groove is fast, the thickness of the second oxide layer at the bottom of the groove will be greater than the sum of the thicknesses of the first oxide layer, the oxidation barrier layer, and the second oxide layer on the side wall of the groove.

[0090] S140. Form a polysilicon layer on the side of the oxide layer away from the epitaxial layer.

[0091] Among them, the polysilicon layer can be formed on the side of the oxide layer away from the epitaxial layer through a deposition process.

[0092] In the method for manufacturing a semiconductor device provided by the technical solution of the embodiment of the present invention, the thickness of the second oxide layer at the bottom of the groove is relatively thick, which can withstand a greater breakdown voltage without being broken down. Therefore, the present invention can improve the breakdown voltage of the device and prevent the device from breaking down. And since the sum of the thicknesses of the first oxide layer and the second oxide layer on the sidewall of the groove, or the sum of the thicknesses of the first oxide layer, the oxidation barrier layer, and the second oxide layer is thinner than the thickness of the second oxide layer at the bottom of the groove, the conductivity at the sidewall is better, which can improve the switching speed of the device.

[0093] Optionally, Figure 6 Yes Figure 5 is a detailed flowchart included in S130. Forming an oxide layer in the groove includes:

[0094] S131. Form a first oxide layer on the side of the epitaxial layer away from the substrate.

[0095] Among them, Figure 7 is a schematic diagram of an intermediate structure of a semiconductor device provided by the second embodiment of the present invention. Referring to Figure 7 , a first oxide layer 41 is formed on the side of the epitaxial layer 20 away from the substrate 10 through thermal oxidation.

[0096] S132. Form an oxidation barrier layer on the side of the first oxide layer away from the epitaxial layer.

[0097] Among them, Figure 8 is another schematic diagram of an intermediate structure of a semiconductor device provided by the second embodiment of the present invention. Referring to Figure 8 , an oxidation barrier layer 60 is formed on the side of the first oxide layer 41 away from the epitaxial layer 20 through a deposition process.

[0098] S133. Remove the first oxide layer and the oxidation barrier layer at the bottom of the groove, as well as the first oxide layer and the oxidation barrier layer outside the groove.

[0099] Among them, Figure 9 is another schematic diagram of an intermediate structure of a semiconductor device provided by the second embodiment of the present invention. Referring to Figure 8 and Figure 9 , the first oxide layer 41 and the oxidation barrier layer 60 at the bottom of the groove 30, as well as the first oxide layer 41 and the oxidation barrier layer 60 outside the groove 30, can be removed through an etching process.

[0100] S134. Oxidize the oxidation barrier layer on the epitaxial layer and the sidewall of the groove simultaneously until the oxidation barrier layer is completely oxidized to form a second oxide layer. Among them, the oxidation rate of the material of the oxidation barrier layer is lower than that of the material of the epitaxial layer.

[0101] Among them, Figure 10 is a schematic diagram of the intermediate structure of another semiconductor device provided in the second embodiment of the present invention. Refer to Figure 10 , the oxidation treatment can be thermal oxidation treatment; the oxidation treatment process is simple, it can avoid damage to the device caused by the etching process, and it can improve the performance of the device.

[0102] S135. Remove the second oxide layer outside the groove.

[0103] Among them, the second oxide layer outside the groove can be removed by an etching process, and finally the Figure 1 structure is formed, Figure 1 which is the structure of the completely oxidized oxidation barrier layer.

[0104] Optionally, Figure 11 is Figure 5 a further refined flowchart included in S130 in Figure 10 . Forming an oxide layer and an oxidation barrier layer in the groove includes:

[0105] S136. Form a first oxide layer on the side of the epitaxial layer away from the substrate.

[0106] S137. Form an oxidation barrier layer on the side of the first oxide layer away from the epitaxial layer.

[0107] S138. Remove the first oxide layer and the oxidation barrier layer at the bottom of the groove, and the first oxide layer and the oxidation barrier layer outside the groove; among them, the oxidation rate of the material of the oxidation barrier layer is lower than that of the material of the epitaxial layer.

[0108] Among them, S136 - S138 is the same as S131 - S133 and has the same beneficial effects.

[0109] S139. Oxidize the oxidation barrier layer on the epitaxial layer and the sidewall of the groove simultaneously to partially oxidize the oxidation barrier layer to form a second oxide layer.

[0110] Among them, Figure 12 is a schematic diagram of the intermediate structure of another semiconductor device provided in the second embodiment of the present invention. Refer to Figure 12 , the oxidation treatment can be thermal oxidation treatment; the oxidation treatment process is simple, it can avoid damage to the device caused by the etching process, and it can improve the performance of the device.

[0111] S1310. Remove the second oxide layer outside the groove.

[0112] Among them, the second oxide layer outside the groove can be removed by an etching process, and finally a Figure 2 structure is formed. Figure 2 This is the structure of a partially oxidized oxidation barrier layer.

[0113] Optionally, a first oxide layer is formed on the bottom and side walls of the groove, including: forming a first oxide layer on the bottom and side walls of the groove by a thermal oxidation process.

[0114] Optionally, the epitaxial layer and the oxidation barrier layer on the side wall of the groove are simultaneously oxidized, including: simultaneously oxidizing the epitaxial layer and the oxidation barrier layer on the side wall of the groove by a thermal oxidation process.

[0115] Among them, the thickness of the formed first oxide layer and second oxide layer can be adjusted by controlling the thermal oxidation time of the epitaxial layer and the oxidation barrier layer.

[0116] Optionally, an oxidation barrier layer is formed on the side of the first oxide layer away from the epitaxial layer, including: forming an oxidation barrier layer on the side of the first oxide layer away from the epitaxial layer by a deposition process.

[0117] Among them, the deposition process is simple and easy to operate.

[0118] The method for preparing a semiconductor device provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device described in any embodiment of the present invention.

[0119] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0120] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A substrate and an epitaxial layer are stacked in sequence; The epitaxial layer comprises a groove; the groove is located on a side of the epitaxial layer away from the substrate; the groove comprises an oxide layer and a polysilicon layer, the oxide layer is located between the polysilicon layer and the epitaxial layer; the oxide layer comprises a first oxide layer and a second oxide layer, the first oxide layer covers the sidewall of the groove, the second oxide layer is located on a side of the first oxide layer away from the epitaxial layer, and the second oxide layer covers the first oxide layer and the bottom of the groove; The thickness of the second oxide layer at the bottom of the groove is greater than the sum of the thickness of the first oxide layer and the second oxide layer at the sidewall of the groove; The groove also includes an oxidation barrier layer, which is located on a side of the first oxide layer away from the epitaxial layer. The second oxide layer is formed by oxidizing the epitaxial layer at the bottom of the groove and the oxidation barrier layer on the sidewall of the groove.

2. The semiconductor device according to claim 1, wherein: The oxidation rate of the material of the oxidation barrier layer is lower than the oxidation rate of the material of the epitaxial layer.

3. The semiconductor device according to claim 1, wherein: The material of the epitaxial layer includes silicon carbide; The materials of the first oxide layer and the second oxide layer include silicon oxide; The material of the oxidation blocking layer includes any one of silicon nitride and silicon oxynitride.

4. The semiconductor device according to claim 1, wherein: The thickness of the second oxide layer at the bottom of the groove is 100-150 nm; the sum of the thickness of the first oxide layer and the second oxide layer on the sidewall of the groove is 20-60 nm; and the thickness of the first oxide layer is 10-20 nm.

5. The semiconductor device according to claim 1, wherein: The grooves include a gate groove and a source groove; The semiconductor device also includes an insulating layer and a metal layer, wherein the insulating layer is located on a side of the gate groove away from the substrate, and the insulating layer covers the polysilicon layer in the gate groove; the metal layer is located on a side of the insulating layer away from the epitaxial layer; and the polysilicon layer in the source groove is connected via the metal layer.

6. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 5, wherein the substrate is used for carrying the semiconductor device.

7. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is electrically connected to the circuit board.

8. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 7, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

9. A method for preparing a semiconductor device, characterized in that: include: forming an epitaxial layer on one side of the substrate; forming a groove in the epitaxial layer; the groove is located on a side of the epitaxial layer away from the substrate; An oxide layer is formed in the groove, wherein the oxide layer includes a first oxide layer and a second oxide layer, the first oxide layer covers the sidewall of the groove, the second oxide layer is located on a side of the first oxide layer away from the epitaxial layer, the second oxide layer covers the first oxide layer and the bottom of the groove, and the thickness of the second oxide layer at the bottom of the groove is greater than the sum of the thickness of the first oxide layer and the second oxide layer on the sidewall of the groove; forming a polysilicon layer on a side of the oxide layer away from the epitaxial layer; Forming an oxide layer in the groove comprises: forming a first oxide layer on a side of the epitaxial layer away from the substrate; forming an oxidation barrier layer on a side of the first oxide layer away from the epitaxial layer; removing the first oxide layer and the oxidation barrier layer at the bottom of the groove, and the first oxide layer and the oxidation barrier layer outside the groove; Simultaneously, the epitaxial layer and the oxidation barrier layer on the sidewall of the groove are oxidized until the oxidation barrier layer is completely oxidized to form a second oxide layer; wherein the oxidation rate of the material of the oxidation barrier layer is lower than the oxidation rate of the material of the epitaxial layer; The second oxide layer outside the groove is removed.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: Forming a first oxide layer on a side of the epitaxial layer away from the substrate, comprising: forming a first oxide layer on a side of the epitaxial layer away from the substrate by a thermal oxidation process; Simultaneously performing oxidation treatment on the epitaxial layer and the oxidation barrier layer on the sidewall of the groove, comprising: The epitaxial layer and the oxidation barrier layer on the sidewall of the groove are oxidized simultaneously by a thermal oxidation process.

11. The method for preparing a semiconductor device according to claim 9, characterized in that: Forming an oxidation barrier layer on a side of the first oxide layer away from the epitaxial layer comprises: An oxidation barrier layer is formed on a side of the first oxide layer away from the epitaxial layer through a deposition process.

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