A method for multi-level chip assembly sorting

Abstract

The application discloses a multi-grade chip combination sorting method, relates to the field of advanced sorting technology of integrated circuits, and comprises the following steps: step one: multi-grade chip simultaneous sorting equipment capacity development: software development support can select multi-grade chip simultaneous sorting capacity, multi-step detection capacity is required in an equipment image optical detection system, the multi-step detection results are classified according to different chip grades, and a multi-grade chip basic database is established according to the classified data; and step two: multi-grade chip simultaneous sorting system process establishment; according to the method, multi-grade chip simultaneous sorting is carried out, a map coordinate file is generated, traceability is provided for packaging processes, chip loss, cracking and other abnormalities caused by multiple sorting are reduced, yield is improved, meanwhile, multi-grade chip simultaneous sorting improves the effective operation rate of equipment, output is improved by 200% to 400%, material waste is reduced, and the workload of employees is reduced.

Description

Technical Field

[0001] This invention relates to a method for multi-level chip combination sorting, belonging to the field of advanced integrated circuit sorting technology. Background Technology

[0002] After wafer chip production is completed, the chips on the entire wafer are tested and classified into different grades according to their test performance. Then, chips of different grades are screened out manually or by equipment. Currently, the industry practice is to classify chips of the same type together. This results in several rounds of screening to classify a wafer, which consumes a lot of personnel, material and equipment resources. Furthermore, individual dies after sorting cannot be traced, causing the 2Dstrip traceability system to fail during the packaging stage. At the same time, multiple sorting can cause edge damage, cracking and other quality problems on the wafer dies, resulting in a loss of product yield. Summary of the Invention

[0003] To address the aforementioned technical problems, the objective of this invention is to propose a method for multi-level chip combination sorting.

[0004] The technical solution of this invention is implemented as follows: a method for multi-level chip combination sorting, comprising the following steps:

[0005] Step 1: Development of multi-level chip simultaneous sorting equipment capabilities:

[0006] The software development supports the ability to sort multiple levels of chips simultaneously. This requires the equipment's imaging optical inspection system to have multi-step inspection capabilities, classify the results of multi-step inspection according to different chip levels, and establish a multi-level chip basic database from the classified data.

[0007] Step Two: Establishment of a Multi-Level Chip Simultaneous Sorting System Process:

[0008] First, establish the following systems:

[0009] The packaging and warehousing system interfaces with the customer's warehousing system;

[0010] Establishment of a multi-bin work order system;

[0011] IT data transmission system;

[0012] A mapping system was established;

[0013] After the above four systems are established, the customer issues a work order request. The packaging plant receives the customer's multi-bin work order request and the plant's work order system simultaneously issues a multi-bin work order and transmits the work order information to the client system. After receiving the work order information, the warehousing system sends the materials to the sorting process. The sorting process performs sorting operations according to the sorting code rules. After the sorting operation, the generated map is uploaded to the map system. After completion, the materials are put into the warehousing system. The multi-bin warehousing system is distinguished from the single-bin system, and the packaging requirements are opened according to the information in the warehousing system.

[0014] Step 3: Mapping System Setup:

[0015] During the sorting process, a unique barcode is printed on the new film. The sorting machine reads the barcode and generates a map file name based on the barcode information. The bin code information is not changed during the operation. The original grain information is brought into the new map. Image recognition identifies the quality of the sorted grains. If a defect is found, the grain code on the map is changed to an abnormal code to distinguish it.

[0016] Step 4: Establish a multi-level chip sorting and traceability system:

[0017] Establishing a traceability system allows for tracing back to the original information in case of chip failure or other anomalies later on. The prerequisite for establishing a traceability system is the generation of traceability files, and after sorting is completed, a chip information file needs to be generated.

[0018] Step 5: Upload the map and traceability file system:

[0019] Once the new map from step three and the grain information file from step four are completed, they will be automatically uploaded to the system. The system will then bind the map file to the work order number to prevent material mixing.

[0020] Step Six: Package and retrieve map tasks:

[0021] The packaging equipment inputs the work order number, which retrieves the corresponding map information from the map system. The packaging machine reads the barcode information on the film and matches it with the corresponding map operation. During the operation, the chip information is captured from the chip information file in step four and imported into the 2D strip mapping system.

[0022] Preferably, the multi-level chip basic database in step one includes:

[0023] Information on sorted chips, quantity of chips of each grade, corresponding defect statistics form, quantity of chips of different grades after sorting, and defect statistics form for chips of different grades after sorting.

[0024] Preferably, the multi-step detection in step one includes incoming detection, backside detection, and outgoing detection of chips of multiple grades.

[0025] Preferably, in step three, the Mapping system establishes a mapping map of the sorting device and generates mapping files.

[0026] Preferably, the mapping file includes chip size information, a summary of the total number of chips in the mapping, and a summary of the number of chips of different grades.

[0027] Preferably, the grain information file to be generated after sorting in step four includes:

[0028] The data includes: operation time, original mapping ID, number of rows and columns in the original mapping, coordinate position of each chip on the original mapping, chip grade at the corresponding coordinate position, new mapping ID after sorting, number of rows and columns in the new mapping file, coordinate position of the corresponding chip on the new mapping, and chip grade at the corresponding coordinate position.

[0029] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0030] (1) Multi-level chips are sorted simultaneously to generate map coordinate files, providing traceability for the packaging process; reducing chip loss, cracking and other abnormalities caused by multiple sorting, and improving yield.

[0031] (2) Simultaneous sorting of multi-level chips improves the effective operating rate of equipment and increases output by 200%-400%; simultaneous sorting of multi-level chips reduces material waste and reduces the workload of employees. Attached Figure Description

[0032] Appendix Figure 1 This is a schematic diagram of the multi-level chip basic database in step one of the multi-level chip combination sorting method of the present invention;

[0033] Appendix Figure 2 This is a schematic diagram of step two of the multi-level chip combination sorting method described in this invention;

[0034] Appendix Figure 3 This is a schematic diagram of the mapping map in step three of the multi-level chip combination sorting method described in this invention;

[0035] Appendix Figure 4 This is a schematic diagram of the mapping file in step three of the multi-level chip combination sorting method described in this invention;

[0036] Appendix Figure 5 This is a schematic diagram of step four of the multi-level chip combination sorting method described in this invention;

[0037] Appendix Figure 6 This is a schematic diagram of step five of the multi-level chip combination sorting method described in this invention;

[0038] Appendix Figure 7 This is a schematic diagram of step six of the multi-level chip combination sorting method described in this invention. Detailed Implementation

[0039] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0040] The multi-level chip combination sorting method of the present invention includes the following steps:

[0041] Step 1: Development of multi-level chip simultaneous sorting equipment capabilities:

[0042] As attached Figure 1 As shown, the software development supports the ability to sort multiple chip grades simultaneously. This requires the equipment's imaging optical inspection system to have multi-step inspection capabilities, classifying the results of these multi-step inspections according to different chip grades. This multi-step inspection includes incoming inspection, backside inspection, and outgoing inspection of chips of multiple grades. The classified data is used to establish a multi-grade chip basic database 1. Within this database, users can easily and quickly view the sorted chip information 2, the quantity of each grade of chip upon arrival 3, the corresponding incoming defect statistics form 4, the quantity of chips of different grades after sorting 5, and the defect statistics form for chips of different grades after sorting 6. The system can simultaneously sort multiple chips or establish multiple chip basic databases.

[0043] Step Two: Establishment of a Multi-Level Chip Simultaneous Sorting System Process:

[0044] As attached Figure 2 As shown, the following system will be established first:

[0045] The packaging and warehousing system interfaces with the customer's warehousing system;

[0046] Establishment of a multi-bin work order system;

[0047] IT data transmission system;

[0048] A mapping system was established;

[0049] After establishing the above four systems, the customer issues a work order request. The packaging plant receives the customer's multi-bin work order request 7, and the plant's work order system simultaneously creates a multi-bin work order and transmits the work order information 9 to the client system. After receiving the work order information 9, the warehousing system sends the materials to the sorting process. The sorting process performs sorting operations 10 according to the sorting code rules. After sorting operations 10, the generated map is uploaded to the map system. After completion, the materials are stored in the warehousing system. The multi-bin warehousing system is distinguished from the single-bin system, and the packaging requirements are opened according to the warehousing system information. This establishes the chip sorting factory system capability, specifically the establishment of multiple chip sorting work order systems, the establishment of an IT system, the integration with the client's T-LOG system, and the integration with the customer's or other SUBCONMapping systems.

[0050] Step 3: Establish the Mapping system, as shown in the attached document. Figure 3 , 4 As shown, the mapping system consists of two parts: the creation of a mapping map for the sorting devices and the generation of mapping files, as detailed below:

[0051] During the sorting process, a unique barcode is printed on the new film. The sorting machine reads the barcode and generates a map file named with the barcode information (11). The bincode information is not changed during the process; the original grain information is incorporated into the new map (12). Image recognition identifies the quality of the sorted grains. If defects are found, the grain code on the map is changed to an exception code for differentiation (see attached). Figure 3 As shown, the file includes chip size information 13, a summary of the total number of chips in the mapping 14, and a summary of the number of chips of different grades 15.

[0052] Step 4: Establish a multi-level chip sorting and traceability system:

[0053] As attached Figure 5 As shown, a traceability system is established so that the original information can be traced back to when a chip fails or other abnormalities occur later. The prerequisite for establishing a traceability system is to generate a traceability file. After sorting is completed, a chip information file needs to be generated. This file includes the operation time 16, the original mapping ID 17, the number of rows and columns of the original mapping 18, the coordinate position of each chip on the original mapping 19, the chip level of the corresponding coordinate position 20, the new mapping ID after sorting 21, the number of rows and columns of the new mapping file 22, the coordinate position of the corresponding chip placed on the new mapping 23, and the chip level of the corresponding coordinate position 24.

[0054] Step 5: Upload the map and traceability file system:

[0055] As attached Figure 6As shown, once the new map from step three and the chip information file from step four are completed, they are automatically uploaded to the system. The system binds the map file to the work order number to prevent material mixing; a multi-level chip mapping upload, query, and download system is established.

[0056] Step Six: Package and retrieve map tasks:

[0057] As attached Figure 7 As shown, the packaging equipment inputs the work order number, which retrieves the corresponding map information from the map system. The packaging machine reads the barcode information on the film and matches it with the corresponding map operation. During the operation, the chip information is captured from the chip information file in step four and imported into the 2D strip mapping system.

[0058] The multi-level chip combination sorting method described in this invention can preserve the original chip information, increase production capacity, and change the traditional sorting operation mode.

[0059] The above embodiments are only for illustrating the technical concept and features of the present invention. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it. They should not be used to limit the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for sorting multi-level chip combinations, characterized in that: Includes the following steps: Step 1: Development of multi-level chip simultaneous sorting equipment capabilities: The software development supports the ability to sort multiple levels of chips at the same time. It is necessary to have multi-step detection capability in the equipment image optical inspection system, classify the results of multi-step detection according to different chip levels, and establish a multi-level chip basic database after classification (1). Step Two: Establishment of a Multi-Level Chip Simultaneous Sorting System Process: First, establish the following systems: The packaging and warehousing system interfaces with the customer's warehousing system; Establishment of a multi-bin work order system; IT data transmission system; A mapping system was established; After the above four systems are established, the customer issues a work order request. The packaging plant receives the customer's multibin work order request (7). The plant's work order system simultaneously issues a multibin work order and transmits the work order information (9) to the client system. After the warehousing system receives the work order information (9), it sends the materials to the sorting process. The sorting process performs sorting operations (10) according to the sorting code rules. After the sorting operation (10), the generated map is uploaded to the map system. After completion, the materials are put into the warehousing system. The multibin warehousing system is distinguished from the single-bin system. The packaging request is opened according to the warehousing system information. Step 3: Mapping System Setup: During the sorting operation, a unique barcode is printed on the new film. The sorting machine reads the barcode and generates a map file name based on the barcode information (11). The bin code information is not changed during the operation. The original grain information is brought into the new map (12). The image recognition identifies the quality of the sorted grains. If a defect is found, the grain code on the map is changed to an abnormal code for distinction. Step 4: Establish a multi-level chip sorting and traceability system: Establishing a traceability system allows for tracing back to the original information in case of chip failure or other anomalies later on. The prerequisite for establishing a traceability system is the generation of traceability files, and after sorting is completed, a chip information file needs to be generated. Step 5: Upload the map and traceability file system: Once the new map (12) in step three and the grain information file in step four are completed, they will be automatically uploaded to the system. The system will bind the map file with the work order number to prevent material mixing. Step Six: Encapsulate the map retrieval task: The packaging equipment inputs the work order number, which retrieves the corresponding map information from the map system. The packaging machine reads the barcode information on the film and matches it with the corresponding map operation. During the operation, the chip information is captured from the chip information file in step four and imported into the 2D strip mapping system.

2. The method for multi-level chip combination sorting according to claim 1, characterized in that: The multi-level chip basic database in step one includes: (2) Information on sorted chips, (3) Quantity of chips of each grade, (4) Statistical table of incoming defects, (5) Quantity of chips of different grades after sorting, (6) Statistical table of defects of chips of different grades after sorting.

3. The method for multi-level chip combination sorting according to claim 1, characterized in that: The multi-step detection in step one includes incoming detection, backside detection, and outgoing detection of chips of multiple grades.

4. The method for multi-level chip combination sorting according to claim 1, characterized in that: Step three involves the establishment of a mapping system, which includes the generation of a mapping map and mapping files for the sorting equipment.

5. The method for multi-level chip combination sorting according to claim 4, characterized in that: The mapping file includes chip size information (13), a summary of the total number of chips in the mapping (14), and a summary of the number of chips of different grades (15).

6. The method for multi-level chip combination sorting according to claim 1, characterized in that: After sorting is completed in step four, a grain information file needs to be generated, including: Operation time (16), original mapping ID (17), number of rows and columns in the original mapping (18), coordinate position of each chip on the original mapping (19), chip level at the corresponding coordinate position (20), new mapping ID after sorting (21), number of rows and columns in the new mapping file (22), coordinate position of the corresponding chip placed on the new mapping (23), chip level at the corresponding coordinate position (24).

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