Semiconductor structure preparation method, semiconductor structure, device and equipment

Abstract

The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus, the method comprising: forming an active structure on a substrate; depositing an insulating material on the active structure to form a shallow trench isolation structure; forming a hard mask layer on the shallow trench isolation structure, and etching the shallow trench isolation structure using the hard mask layer as a mask to form a gate groove; depositing a semiconductor material in the gate groove to form an initial pseudo gate structure; self-aligning a first pseudo gate structure and a second pseudo gate structure; removing a portion of the shallow trench isolation structure that wraps the first active structure to expose the first active structure; forming a first transistor based on the first active structure; flipping the wafer and removing the substrate; removing a portion of the shallow trench isolation structure that wraps the second active structure to expose the second active structure; forming a second transistor based on the second active structure. Through the present application, the process flow can be optimized.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] When using the traditional monolithic solution to prepare stacked transistors, there are the following technical difficulties: the pseudo-gate re-crystallization causes the process flow to be complicated. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus to optimize the process flow.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, the method comprising: forming an active structure on a substrate; the active structure comprising a first active structure and a second active structure; depositing an insulating material on the active structure to form a shallow trench isolation structure; the shallow trench isolation structure wraps the active structure; forming a hard mask layer on the shallow trench isolation structure, and etching the shallow trench isolation structure using the hard mask layer as a mask to form a gate groove; depositing a semiconductor material in the gate groove to form an initial dummy gate structure; the initial dummy gate structure comprises a first dummy gate structure corresponding to the first active structure and a second dummy gate structure corresponding to the second active structure, the first dummy gate structure and the second dummy gate structure being self-aligned; removing a portion of the shallow trench isolation structure that wraps the first active structure to expose the first active structure; forming a first transistor based on the first active structure; flipping the wafer and removing the substrate; removing a portion of the shallow trench isolation structure that wraps the second active structure to expose the second active structure; forming a second transistor based on the second active structure; the first transistor and the second transistor are self-aligned.

[0006] In some possible embodiments, a first gate isolation layer is arranged between the first dummy gate structure and the second dummy gate structure; the gate groove includes a first gate groove corresponding to the first active structure and a second gate groove corresponding to the second active structure; a semiconductor material is deposited in the gate groove to form an initial dummy gate structure, including: depositing a semiconductor material in the second gate groove to form a second dummy gate structure; depositing an oxide on the second dummy gate structure to form a first gate isolation layer; the first gate isolation layer is used to isolate the first dummy gate structure from the second dummy gate structure; and depositing a semiconductor material on the first gate isolation layer to form a first dummy gate structure.

[0007] In some possible embodiments, a first transistor is formed based on a first active structure, including: forming a first source-drain structure and a first interlayer dielectric layer based on the first active structure; removing the first dummy gate structure, depositing an insulating material on the surface of the first active structure located in a first gate groove, and depositing a metal material in the first gate groove to form a first gate dielectric layer and a first gate structure; performing post-processing on the first gate structure and the first interlayer dielectric layer to form a first metal interconnection layer.

[0008] In some possible embodiments, a second transistor is formed based on a second active structure, including: forming a second source-drain structure and a second interlayer dielectric layer based on the second active structure; removing the second dummy gate structure, depositing an insulating material on the surface of the second active structure located in the second gate groove, and depositing a metal material in the second gate groove to form a second gate dielectric layer and a second gate structure; performing post-processing on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

[0009] In some possible embodiments, the first dummy gate structure and the second dummy gate structure are formed by one process, and the gate groove includes a first gate groove corresponding to the first active structure and a second gate groove corresponding to the second active structure; semiconductor material is deposited in the gate groove to form an initial dummy gate structure, including: depositing semiconductor material in the second gate groove and the first gate groove to form a second dummy gate structure and the first dummy gate structure; the second dummy gate structure and the first dummy gate structure are arranged as one body.

[0010] In some possible implementations, a first transistor is formed based on a first active structure, including: forming a first source-drain structure and a first interlayer dielectric layer based on the first active structure; performing a post-processing on the first dummy gate structure and the first interlayer dielectric layer to form a first metal interconnection layer.

[0011] In some possible embodiments, a second transistor is formed based on a second active structure, including: forming a second source-drain structure and a second interlayer dielectric layer based on the second active structure; removing the first dummy gate structure and the second dummy gate structure to expose the gate groove; depositing an insulating material on the surface of the active structure located in the gate groove to form a gate dielectric layer; depositing a metal material in the first gate groove and the second gate groove to form a first gate structure of the first transistor and a second gate structure of the second transistor; the first gate structure and the first gate structure are arranged as one body; and performing a post-processing on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

[0012] In some possible embodiments, a second transistor is formed based on a second active structure, including: forming a second source-drain structure and a second interlayer dielectric layer based on the second active structure; removing the first dummy gate structure and the second dummy gate structure to expose the first gate groove and the second gate groove; depositing an insulating material on the surface of the active structure located in the gate groove to form a gate dielectric layer; depositing a metal material in the first gate groove and the second gate groove, respectively, to form a first gate structure of the first transistor and a second gate structure of the second transistor; performing a post-processing on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

[0013] In some possible embodiments, metal material is deposited in the first gate groove and the second gate groove, respectively, to form a first gate structure of the first transistor and a second gate structure of the second transistor, including: depositing metal material in the first gate groove to form a first gate structure; depositing oxide on the first gate structure to form a second gate isolation layer; the second gate isolation layer is used to isolate the first gate structure from the second gate structure; and depositing metal material on the second gate isolation layer to form a second gate structure.

[0014] In some possible embodiments, the substrate includes a top substrate, a first sacrificial layer and a bottom substrate that are stacked, the top substrate is used to form an active structure; forming an active structure on the substrate includes: etching the top substrate and the first sacrificial layer to form an active structure and a second sacrificial layer; the second sacrificial layer connects the bottom substrate and the active structure; after flipping the wafer and removing the substrate, the method also includes: removing the bottom substrate and the second sacrificial layer to form a first groove; filling the first groove with semiconductor material to form a dummy gate structure; the dummy gate structure wraps the active structure in the gate groove.

[0015] In a second aspect, an embodiment of the present application provides a semiconductor structure, including: a first transistor; a second transistor; wherein the first transistor and the second transistor are stacked and self-aligned; and the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

[0016] In some possible implementations, the first gate structure and the second gate structure are integrally provided; or, a gate isolation layer is provided between the first gate structure and the second gate structure, and the gate isolation layer is used to isolate the first gate structure from the second gate structure.

[0017] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the above embodiment.

[0018] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

[0019] In the present application, by first forming a shallow trench isolation structure and then forming the first dummy gate structure and the second dummy gate structure, recrystallization of the first dummy gate structure and the second dummy gate structure can be avoided, thereby optimizing the process flow.

[0020] Furthermore, since the first dummy gate structure and the second dummy gate structure are formed before the first transistor is flipped, the first dummy gate structure and the second dummy gate structure are self-aligned, and thus the first gate structure and the second gate structure formed based on the first dummy gate structure and the second dummy gate structure are also self-aligned.

[0021] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0023] Figure 1 A schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application;

[0024] Figure 2 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application;

[0025] Figures 3A to 3G A schematic diagram of a first preparation process of a semiconductor structure in an embodiment of the present application;

[0026] Figure 4 This is a schematic diagram of a second structure of a semiconductor structure in an embodiment of the present application;

[0027] Figure 5A and Figure 5B A schematic diagram of a second preparation process of a semiconductor structure in an embodiment of the present application;

[0028] Figure 6 This is a schematic diagram of a third structure of a semiconductor structure in an embodiment of the present application;

[0029] Figure 7 A schematic diagram of a third preparation process of a semiconductor structure in an embodiment of the present application;

[0030] The above pictures:

[0031] 10. semiconductor structure; 11. first transistor; 111. first active structure; 112. first gate structure; 113. first spacer; 114. first source-drain structure; 115. first interlayer dielectric layer; 116. first gate dielectric layer; 117. first metal interconnect layer; 12. second transistor; 121. second active structure; 122. second gate structure; 123. second spacer; 124. second source-drain structure; 125. second interlayer dielectric layer; 126. second gate dielectric layer; 127. second metal interconnect layer; The present invention comprises the following steps: a first interconnection layer; 13, a first gate isolation layer; 14, a second gate isolation layer; 15, an insulating layer; 16, a carrier wafer; 21, a substrate; 211, a top substrate; 212, a first sacrificial layer; 213, a bottom substrate; 214, a second sacrificial layer; 22, a shallow trench isolation structure; 221, a shallow trench isolation layer; 23, a hard mask layer; 24, a gate groove; 241, a first gate groove; 242, a second gate groove; 25, an oxide isolation layer; 261, a first dummy gate structure; 262, a second dummy gate structure; 31, a first groove. DETAILED DESCRIPTION

[0032] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0033] As Moore's Law continues to deepen, after the technology node of gate-all-around FET (GAA), continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0034] In one embodiment, the technology for manufacturing stacked transistors includes two schemes, one is a monolithic scheme and the other is a sequential scheme.

[0035] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0036] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding a wafer on top of the already fabricated lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonded wafer; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy.

[0037] However, the original stacking solution needs to take into account the problem of pseudo-gate re-crystallization, which complicates the process flow.

[0038] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a semiconductor structure to optimize the process flow.

[0039] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memory and processor.

[0040] In some embodiments, the semiconductor structure may include a first transistor and a second transistor disposed opposite to each other and stacked, wherein a first gate structure of the first transistor and a second gate structure of the second transistor are self-aligned in a direction perpendicular to the active region.

[0041] In some embodiments, the first gate structure and the second gate structure in the semiconductor structure may be integrated, that is, the first transistor and the second transistor share a common gate.

[0042] In some other embodiments, a gate isolation layer may be disposed between the first gate structure and the second gate structure in the semiconductor structure, and the gate isolation layer is used to isolate the first gate structure from the second gate structure.

[0043] In the embodiment of the present application, the active region is a collective name for the source region, the drain region and the channel region.

[0044] In an embodiment of the present application, the first transistor and the second transistor in the semiconductor structure can be transistors of the same type, such as any one of the following: a nanosheet field effect transistor (GAA Nanosheet), a fin field effect transistor (FinFET), a planar transistor, a vertical transistor (VTFET) and a forksheet transistor, etc.

[0045] Figure 2 The semiconductor structure composed of fin field effect transistors is combined below Figure 2 The semiconductor structure shown illustrates the method for preparing the semiconductor structure provided in the embodiment of the present application.

[0046] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application, see Figure 1 As shown, the method for preparing the semiconductor structure may include:

[0047] S101, forming an active structure on a substrate, wherein the active structure includes a first active structure and a second active structure.

[0048] It can be understood that the first active structure of the first transistor and the second active structure of the second transistor in the semiconductor structure are formed by the same process (such as etching process), so that the active area of ​​the first transistor and the active area of ​​the second transistor can be self-aligned.

[0049] In some possible implementations, the substrate includes a top substrate, a first sacrificial layer, and a bottom substrate that are stacked together, and the top substrate is used to form an active structure.

[0050] It is understandable that the substrate in the embodiment of the present application may be a multi-layer structure. Specifically, a sacrificial layer (i.e., a first sacrificial layer) is epitaxially grown on the bottom substrate, and a top substrate (i.e., a first sacrificial layer) is epitaxially grown on the first sacrificial layer. Figure 3A ), the first sacrificial layer is used to protect the main structure of the top substrate, reduce the impact and vibration from the outside, improve the durability and reliability of the top substrate, and extend the service life.

[0051] In some embodiments, the height of the sacrificial layer is about 10-20 nm, and the height of the top substrate is greater than 100 nm. It should be noted that the heights of the first sacrificial layer and the top substrate can be selected according to actual use requirements, and the embodiments of the present application do not specifically limit this.

[0052] In some embodiments, when the types of the first transistor and the second transistor in the semiconductor structure are different, the arrangement of the substrate is also different accordingly. For example, when the first transistor and the second transistor are any one of a fin field effect transistor, a planar transistor, and a vertical field effect transistor, the top substrate may be a silicon (Si) material. When the first transistor and the second transistor are nanosheet field effect transistors or fork plate transistors, the top substrate may be a stack formed by alternating deposition of silicon material and silicon germanium (SiGe) material.

[0053] In some possible implementations, the above S101 may include: etching the top substrate and the first sacrificial layer to form an active structure and a second sacrificial layer, wherein the second sacrificial layer connects the bottom substrate and the active structure.

[0054] It can be understood that the active structure is formed by etching the substrate, and the specific steps are: etching the top substrate and the first sacrificial layer, the etched top substrate forms the active structure, and the etched first sacrificial layer forms the second sacrificial layer. The active structure is divided into two parts, the upper part is used as the first active structure in the first transistor, and the lower part is used as the second active structure in the second transistor.

[0055] It should be noted that the etching process mentioned in the embodiments of the present application may include any one of the following: dry etching, wet etching, reactive ion etching and chemical oxide removal process, which is not limited in the embodiments of the present application.

[0056] S102, depositing insulating material on the active structure to form a shallow trench isolation (STI), wherein the shallow trench isolation structure wraps the active structure.

[0057] It can be understood that by depositing insulating material on the active structure, the first sacrificial layer and the bottom substrate, a shallow trench isolation structure can be formed that encapsulates the active structure and the first sacrificial layer. The height of the shallow trench isolation structure is greater than the height of the active structure.

[0058] In the embodiment of the present application, the insulating material forming the shallow trench isolation structure can be: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO), etc., or it can be other insulating materials, and the embodiment of the present application does not make specific limitations on this.

[0059] In some embodiments, in order to facilitate subsequent processing, after S102, the shallow trench isolation structure can also be polished or chemical-mechanical planarization (CMP) processed, so that when the shallow trench isolation structure is subsequently etched, the corresponding corrosion depths of the shallow trench isolation structure in different areas are the same, thereby making the top height of the exposed active structure the same.

[0060] S103, forming a hard mask layer on the shallow trench isolation structure, and etching the shallow trench isolation structure using the hard mask layer as a mask to form a gate groove.

[0061] It can be understood that a layer of hard mask material (referred to as the first hard mask layer) is first deposited on top of the shallow trench isolation structure. At this time, the first hard mask layer covers the surface of the shallow trench isolation structure. Then, a photoresist is coated on the first hard mask layer, and after the photoresist is developed and a photolithography pattern is formed, the first hard mask layer is etched according to the photolithography pattern to form a hard mask layer. The hard mask layers are arranged at intervals on the surface of the shallow trench isolation structure, and the gaps between the hard mask layers correspond to the gate region of the semiconductor structure. Finally, the shallow trench isolation structure is etched using the hard mask layer as a mask, and the etching stops at the bottom substrate to form a gate groove.

[0062] It should be noted that the gate groove is a groove formed in the gate region of the semiconductor structure, and the semiconductor structure includes a first transistor and a second transistor. Accordingly, the gate groove also includes a first gate groove and a second gate groove, the first gate groove corresponds to the first transistor, and the second gate groove corresponds to the second transistor.

[0063] S104, depositing a semiconductor material in the gate groove to form an initial dummy gate structure.

[0064] The initial dummy gate structure includes a first dummy gate structure corresponding to the first active structure and a second dummy gate structure corresponding to the second active structure, and the first dummy gate structure and the second dummy gate structure are self-aligned.

[0065] It can be understood that depositing semiconductor material (such as polysilicon) in the gate groove can form an initial dummy gate structure of the semiconductor structure, corresponding to the first transistor and the second transistor, and the initial dummy gate structure also includes a first dummy gate structure and a second dummy gate structure.

[0066] In some embodiments, before the above S104, the above method may further include: depositing a layer of oxide on the surface of the active structure located inside the gate groove, the surface of the second sacrificial layer, and the upper surface of the bottom substrate to form an oxide isolation layer (such as Figure 3B shown).

[0067] In the embodiment of the present application, the oxide isolation layer can isolate and protect the active structure in the subsequent preparation process.

[0068] It should be noted that, for the process flow of first forming the dummy gate structure and then forming the shallow trench isolation structure, since the shallow trench isolation structure requires a very high temperature during the formation process to ensure the quality of the shallow trench isolation structure, this causes the dummy gate structure to face the problem of recrystallization during the formation of the shallow trench isolation structure. However, the process flow of first forming the shallow trench isolation structure and then forming the initial dummy gate structure in the embodiment of the present application can avoid the problem of recrystallization of the initial dummy gate structure.

[0069] S105 , removing a portion of the shallow trench isolation structure that wraps the first active structure to expose the first active structure.

[0070] It is understandable that a portion of the shallow trench isolation structure may be removed by etching until the first active structure is exposed, so as to facilitate the preparation of the first transistor in a subsequent process flow.

[0071] S106 , forming a first transistor based on the first active structure.

[0072] It can be understood that other structures in the first transistor (such as the first source-drain structure, the first spacer, the first interlayer dielectric layer and the first metal interconnect layer of the first transistor) can be formed based on the first active structure.

[0073] S107, flip the wafer and remove the substrate.

[0074] It is understandable that after the first transistor is prepared, the first transistor is flipped over so that the second active structure can be placed upward to facilitate the preparation of the second transistor. The specific steps are: after flipping over, the bottom substrate is placed upward, the bottom substrate is removed, and the shallow trench isolation structure that wraps the second active structure is exposed, as well as the surface of the second active structure away from the first active structure.

[0075] In some possible implementations, before the above S107, the above method may further include: depositing an insulating material on the surface of the first transistor to form an insulating layer; and bonding the insulating layer to the carrier wafer.

[0076] It can be understood that the bonded carrier wafer can provide physical support for the flipped first transistor after inversion, effectively preventing the first transistor from being broken by external force during the preparation of the second transistor.

[0077] In some possible implementations, after S107, the method may further include: removing the bottom substrate and the second sacrificial layer to form a first groove; and filling the first groove with a semiconductor material to form a dummy gate structure, wherein the dummy gate structure encapsulates an active structure in the gate groove.

[0078] It can be understood that the initial dummy gate structure does not cover the surface of the second active structure away from the first active structure. After flipping the wafer and removing the bottom substrate, the second sacrificial layer between the second active structure and the bottom substrate can be removed. At this time, the surface of the second active structure away from the first active structure is exposed in the first groove. Then, the same semiconductor material as the initial dummy gate structure (such as polysilicon) is filled in the first groove. The filled polysilicon material and the initial dummy gate structure together form a dummy gate structure. The dummy gate structure wraps the first active structure and the second active structure in the gate area.

[0079] S108, removing a portion of the shallow trench isolation structure that wraps the second active structure to expose the second active structure.

[0080] It is understandable that a portion of the shallow trench isolation structure may be removed by etching until the second active structure is exposed, so as to facilitate the preparation of the second transistor in a subsequent process flow.

[0081] In some embodiments, in the process of etching the shallow trench isolation structure to expose the second active structure, a shallow trench isolation structure of a preset thickness is retained. For ease of distinction, the retained shallow trench isolation structure of a preset thickness is recorded as a shallow trench isolation layer. The shallow trench isolation layer is located between the first transistor and the second transistor and is used to isolate the first transistor from the second transistor.

[0082] S109, forming a second transistor based on the second active structure, wherein the first transistor and the second transistor are self-aligned.

[0083] It can be understood that other structures in the second transistor (such as a second source-drain structure of the second transistor, a second spacer, a second interlayer dielectric layer, and a second metal interconnect layer, etc.) can be formed based on the second active structure.

[0084] In the embodiment of the present application, since the active region of the first transistor and the active region of the second transistor are self-aligned, the first transistor and the second transistor are also self-aligned.

[0085] In the embodiment of the present application, the first dummy gate structure and the second dummy gate structure may be formed through the same process (i.e., the first dummy gate structure and the second dummy gate structure are integrated); or they may be formed through different processes respectively. When the first dummy gate structure and the second dummy gate structure are formed through different processes respectively, a gate isolation layer is provided between the first dummy gate structure and the second dummy gate structure. The gate isolation layer may be used to isolate the first dummy gate structure from the second dummy gate structure, or may be used to isolate the first gate structure formed based on the first dummy gate structure from the second gate structure formed based on the second dummy gate structure. When the first dummy gate structure and the second dummy gate structure are formed through the same process, in the process of forming the first gate structure and the second gate structure, the first gate structure and the second gate structure may be formed in the same process (i.e., a "common gate" design is adopted); or the first gate structure and the second gate structure may be formed through different processes respectively, and a gate isolation layer may be provided between the first gate structure and the second gate structure.

[0086] According to the above, the design of the dummy gate structure (i.e., the first dummy gate structure and the second dummy gate structure) and the gate structure (i.e., the first gate structure and the second gate structure) in the embodiments of the present application may include three situations: 1. A gate isolation layer is arranged between the first dummy gate structure and the second dummy gate structure, and a gate isolation layer is also arranged between the first gate structure and the second gate structure; 2. The first dummy gate structure and the second dummy gate structure are arranged as a whole, and the first gate structure and the second gate structure are also arranged as a whole; 3. The first dummy gate structure and the second dummy gate structure are arranged as a whole, and a gate isolation layer is arranged between the first gate structure and the second gate structure.

[0087] In some possible embodiments, when a gate isolation layer is provided between the first dummy gate structure and the second dummy gate structure, and a gate isolation layer is also provided between the first gate structure and the second gate structure, the above S104 may include: depositing semiconductor material in the second gate groove to form a second dummy gate structure; depositing oxide on the second dummy gate structure to form a first gate isolation layer; the first gate isolation layer is used to isolate the first dummy gate structure from the second dummy gate structure; and depositing semiconductor material on the first gate isolation layer to form a first dummy gate structure.

[0088] It can be understood that since the second gate groove is located below the first gate groove before flipping the wafer, in the process of forming the initial dummy gate structure, semiconductor material should first be deposited in the second gate groove to form a second dummy gate structure; then a layer of oxide with a preset thickness is deposited above the second dummy gate structure to form a first gate isolation layer; finally, the same semiconductor material as the second dummy gate structure is deposited above the first gate isolation layer to form a first dummy gate structure.

[0089] It should be noted that the thickness of the first gate isolation layer can be designed according to actual needs, and the embodiment of the present application does not specifically limit this.

[0090] In some possible embodiments, when a gate isolation layer is provided between the first dummy gate structure and the second dummy gate structure, and a gate isolation layer is also provided between the first gate structure and the second gate structure, the above S106 may include: forming a first source-drain structure and a first interlayer dielectric layer based on the first active structure; removing the first dummy gate structure, depositing an insulating material on the surface of the first active structure located in the first gate groove, and depositing a metal material in the first gate groove to form a first gate dielectric layer and a first gate structure; performing post-processing on the first gate structure and the first interlayer dielectric layer to form a first metal interconnection layer.

[0091] It can be understood that when a gate isolation layer is provided between the first dummy gate structure and the second dummy gate structure and a gate isolation layer is also provided between the first gate structure and the second gate structure, the first gate structure is formed during the preparation of the first transistor (ie before flipping).

[0092] In some embodiments, the formation of the first source-drain structure and the first interlayer dielectric layer based on the first active structure may include: firstly, depositing insulating material on both sides of the first dummy gate structure to form a first spacer; then, removing a portion of the first active structure by etching to provide a first source-drain groove of the first transistor. Using the first spacer as a mask, forming a strained material such as silicon germanium or silicon carbide in the first source-drain groove of the first transistor by selective epitaxial growth to fill the first source-drain groove of the first transistor, and then forming the first source-drain structure on the strained material by a heavy doping process; finally, depositing an insulating material (such as silicon dioxide (SiO2)) above the first active structure and the first source-drain structure to form a first interlayer dielectric layer; the first interlayer dielectric layer may cover the first active structure and the first source-drain structure.

[0093] In some embodiments, the above-mentioned removal of the first dummy gate structure, deposition of an insulating material on the surface of the first active structure in the first gate groove, and deposition of a metal material in the first gate groove to form a first gate dielectric layer and a first gate structure may include: removing the first dummy gate structure by etching to expose the first gate groove of the first transistor, removing the oxide isolation layer covering the surface of the first active structure, and deposition of an insulating material on the surface of the first active structure in the first gate groove to form a first gate dielectric layer; then, deposition of a metal material in the first gate groove to form a first gate structure of the first transistor. The first gate dielectric layer is used to isolate the first active structure from the first gate structure.

[0094] In some embodiments, the above-mentioned back-end process processing on the first gate structure and the first interlayer dielectric layer to form a first metal interconnection layer may include: performing interconnection line dielectric deposition, metal line formation, lead pad formation and other processes on the first interlayer dielectric layer and the first gate structure to form the first metal interconnection layer of the first transistor.

[0095] In some possible embodiments, when a gate isolation layer is provided between the first dummy gate structure and the second dummy gate structure, and a gate isolation layer is also provided between the first gate structure and the second gate structure, the above S109 may include: forming a second source-drain structure and a second interlayer dielectric layer based on the second active structure; removing the second dummy gate structure, depositing an insulating material on the surface of the second active structure located in the second gate groove, and depositing a metal material in the second gate groove to form a second gate dielectric layer and a second gate structure; performing post-processing on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

[0096] It can be understood that when a gate isolation layer is provided between the first dummy gate structure and the second dummy gate structure and a gate isolation layer is also provided between the first gate structure and the second gate structure, the second gate structure is formed during the preparation of the second transistor (ie after flipping).

[0097] In some embodiments, the second source-drain structure and the second interlayer dielectric layer are formed based on the second active structure, which may include: first, depositing insulating material on both sides of the second pseudo-gate structure to form a second spacer; then, removing a portion of the second active structure by etching to provide a second source-drain groove of the second transistor. Using the second spacer as a mask, a strained material such as silicon germanium or silicon carbide is formed in the second source-drain groove of the second transistor by selective epitaxial growth to fill the second source-drain groove of the second transistor, and then forming a second source-drain structure on the strained material by a heavy doping process; finally, depositing an insulating material (such as silicon dioxide) on top of the second active structure and the second source-drain structure to form a second interlayer dielectric layer; the second interlayer dielectric layer may cover the second active structure and the second source-drain structure.

[0098] In some embodiments, the above-mentioned removal of the second dummy gate structure, deposition of an insulating material on the surface of the second active structure in the second gate groove, and deposition of a metal material in the second gate groove to form a second gate dielectric layer and a second gate structure may include: removing the second dummy gate structure by etching to expose the second gate groove of the second transistor, removing the oxide isolation layer covering the surface of the second active structure, and deposition of an insulating material on the surface of the second active structure in the second gate groove to form a second gate dielectric layer; then, deposition of a metal material in the second gate groove to form a second gate structure of the second transistor. The second gate dielectric layer is used to isolate the second active structure from the second gate structure.

[0099] In some embodiments, the above-mentioned post-processing on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer may include: performing interconnection line dielectric deposition, metal line formation, lead pad formation and other processes on the second interlayer dielectric layer and the second gate structure to form the second metal interconnection layer of the second transistor.

[0100] In an embodiment of the present application, the metal material forming the first gate structure and / or the second gate structure may include but is not limited to: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN). The materials of the first gate structure and the second gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

[0101] In some possible implementations, when the first dummy gate structure and the second dummy gate structure are integrally arranged, and the first gate structure and the second gate structure are also integrally arranged, the above S104 may include: depositing semiconductor material in the second gate groove and the first gate groove to form the second dummy gate structure and the first dummy gate structure. The second dummy gate structure and the first dummy gate structure are integrally arranged.

[0102] It can be understood that the first dummy gate structure and the second dummy gate structure that are integrally arranged can be formed by directly depositing semiconductor materials in the gate grooves (the first gate groove and the second gate groove).

[0103] In some possible implementations, when the first dummy gate structure and the second dummy gate structure are integrally arranged, and the first gate structure and the second gate structure are also integrally arranged, the above S106 may include: forming a first source-drain structure and a first interlayer dielectric layer based on the first active structure; performing post-processing on the first dummy gate structure and the first interlayer dielectric layer to form a first metal interconnection layer.

[0104] It can be understood that in the second situation mentioned above, since the first gate structure and the second gate structure are arranged as an integral whole, the first gate structure and the second gate structure are formed in the process of preparing the second transistor. Except for the first gate structure, other structures in the first transistor (such as the first spacer, the first source-drain structure, the first interlayer dielectric layer and the first metal interconnection layer, etc.) are the same as the preparation process in the first situation mentioned above, and the embodiments of the present application will not be elaborated on this.

[0105] In some possible embodiments, when the first dummy gate structure and the second dummy gate structure are integrally arranged, and the first gate structure and the second gate structure are also integrally arranged, the above S109 may include: forming a second source-drain structure and a second interlayer dielectric layer based on the second active structure; removing the first dummy gate structure and the second dummy gate structure to expose the gate groove; depositing an insulating material on the surface of the active structure located in the gate groove to form a gate dielectric layer; depositing a metal material in the first gate groove and the second gate groove to form a first gate structure of the first transistor and a second gate structure of the second transistor; the first gate structure and the first gate structure are integrally arranged; performing a post-processing on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

[0106] It can be understood that in the second case above, during the preparation of the second transistor, the first dummy gate structure and the second dummy gate structure are removed by the same etching process to expose the active structure (the first active structure and the second active structure) located in the gate groove, and after removing the oxide isolation layer on the surface of the active structure, an insulating material is deposited on the surface of the active structure to form a gate dielectric layer (i.e., the first gate dielectric layer and the second gate dielectric layer), and at this time, the first gate dielectric layer and the second gate dielectric layer are also integrally arranged; finally, a metal material is deposited in the gate groove (i.e., the first gate groove and the second gate groove) to form an integrally arranged first gate structure and second gate structure. Except for the first gate structure in the first transistor and the second gate structure in the second transistor, other structures in the second transistor (such as the second spacer, the second source-drain structure, the second interlayer dielectric layer and the second metal interconnect layer, etc.) are the same as the preparation process in the first case above, and the embodiments of the present application will not be described in detail.

[0107] In some possible embodiments, when the first dummy gate structure and the second dummy gate structure are integrally arranged and a gate isolation layer is arranged between the first gate structure and the second gate structure, the above S109 may include: forming a second source-drain structure and a second interlayer dielectric layer based on the second active structure; removing the first dummy gate structure and the second dummy gate structure to expose the first gate groove and the second gate groove; depositing an insulating material on the surface of the active structure located in the gate groove to form a gate dielectric layer; depositing a metal material in the first gate groove and the second gate groove respectively to form a first gate structure of the first transistor and a second gate structure of the second transistor; performing a post-processing on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

[0108] It can be understood that in the above-mentioned third situation, the first gate structure and the second gate structure are formed in the process of preparing the second transistor. Different from the above-mentioned second situation, the first gate structure and the second gate structure are formed through different processes, and a gate isolation layer is arranged between the first gate structure and the second gate structure.

[0109] It should be noted that, in the third situation described above, the first gate dielectric layer and the second gate dielectric layer are integrally provided.

[0110] In some possible embodiments, the above-mentioned depositing metal material in the first gate groove and the second gate groove, respectively, to form a first gate structure of the first transistor and a second gate structure of the second transistor, may include: depositing metal material in the first gate groove to form a first gate structure; depositing oxide on the first gate structure to form a second gate isolation layer; the second gate isolation layer is used to isolate the first gate structure from the second gate structure; and depositing metal material on the second gate isolation layer to form a second gate structure.

[0111] It can be understood that in the third situation mentioned above, after flipping the wafer, the first gate groove is located below the second gate groove, and metal material can be first deposited in the first gate groove to form a first gate structure; then, oxide is deposited on the first gate structure to form a second gate isolation layer; finally, a second gate structure is formed on the second gate isolation layer.

[0112] It should be noted that the first gate isolation layer and the second gate isolation layer can both be recorded as gate isolation layers, and the first gate isolation layer and the second gate isolation layer are both located between the first gate structure and the second gate structure, and are used to isolate the first gate structure from the second gate structure. The difference between the first gate isolation layer and the second gate isolation layer is that the first gate isolation layer is formed in the process of preparing the initial dummy gate structure, and the second gate isolation layer is formed in the process of preparing the first gate structure and the second gate structure.

[0113] It should be noted that the first source-drain structure represents the source and / or drain in the first transistor. Accordingly, other expressions related to "source and drain" in the embodiments of the present application are all used to represent "source and / or drain", such as: the second source-drain structure, the first source-drain groove and the second source-drain groove, etc.

[0114] Below, the semiconductor structure provided in the embodiment of the present application is described by taking the first transistor and the second transistor as fin-type field effect transistors as an example. Figure 2 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application. Figure 2 (a) is the design layout of the semiconductor structure. It should be noted that, for ease of understanding, only the fin structure, gate structure, and source-drain structure are shown in the design layout; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the fin structure (i.e., CC' direction).

[0115] See also Figure 2 As shown, the semiconductor structure 10 includes a first transistor 11 and a second transistor 12, and the active structure in the semiconductor structure 10 is a plurality of fin structures. The fin structure is divided into two parts, one part is used as the first active structure 111 in the first transistor 11, and the other part is used as the second active structure 121 in the second transistor 12. The first gate structure 112 in the first transistor 11 and the second gate structure 122 in the second transistor 12 are self-aligned, and a first gate isolation layer 13 is provided between the first gate structure 112 and the second gate structure 122, and the first gate isolation layer 13 is used to isolate the first gate structure 112 from the second gate structure 122.

[0116] In combination with the above preparation method, Figure 2 The preparation process of the semiconductor structure 10 is described below. Figure 2 The semiconductor structure shown can be Figures 3A to 3G The process shown is prepared Figures 3A to 3G It is a schematic diagram of the first preparation process of the semiconductor structure in the embodiment of the present application.

[0117] The first step is to provide a substrate 21. The substrate 21 includes a top substrate 211, a first sacrificial layer 212 and a bottom substrate 213 stacked in sequence (see Figure 3A (a) in the figure.

[0118] Step 2: Patterning of the fin structure is performed, and the top substrate 211 and the first sacrificial layer 212 are etched in sequence, and the etching stops at the bottom substrate 213 to form an active structure (i.e., the first active structure 111 and the second active structure 121) and a second sacrificial layer 214 (see Figure 3A (b) in the figure.

[0119] Step 3: Deposit an insulating material (such as SiO2) on the top substrate 211, the first sacrificial layer 212 and the bottom substrate 213 to form a shallow trench isolation structure 22 (see Figure 3A (c) in the figure.

[0120] Step 4: Form a hard mask layer 23 on the shallow trench isolation structure 22 by photolithography (see Figure 3B (a) in the figure.

[0121] Step 5: Under the masking effect of the hard mask layer 23, the shallow trench isolation structure 22 is etched to form a gate groove 24, wherein the gate groove 24 includes a first gate groove 241 and a second gate groove 242 (see Figure 3B (b) in the figure.

[0122] Step 6: Remove the hard mask layer 23, and deposit oxide on the surfaces of the first active structure 111, the second active structure 121, and the second sacrificial layer 214 in the gate groove 24 to form an oxide isolation layer 25 (see Figure 3B (c) in the figure.

[0123] Step 7: deposit polysilicon in the second gate groove 242 to form a second dummy gate structure 262; deposit a layer of oxide on the second dummy gate structure 262 to form a first gate isolation layer 13; deposit polysilicon in the first gate groove 241 to form a first dummy gate structure 261 (see Figure 3C ).

[0124] Step 8: Remove the shallow trench isolation structure 22 that encapsulates the first active structure 111 to expose the first active structure 111 (see Figure 3D (a) in the figure.

[0125] Step 9: Based on the first active structure 111, a first spacer 113, a first source-drain structure 114 and a first interlayer dielectric layer 115 are formed (see Figure 3D (b) in the figure.

[0126] Step 10: Remove the first dummy gate structure 261 and the oxide isolation layer 25 covering the surface of the first active structure 111; deposit a layer of insulating material on the surface of the first active structure 111 to form a first gate dielectric layer 116; then, deposit a metal material in the first gate groove 241 to form a first gate structure 112 (see Figure 3D(c) in the figure.

[0127] Step 11: Perform post-processing on the first gate structure 112 and the first interlayer dielectric layer 115 to form a first metal interconnection layer 117 (see Figure 3E (a) in the figure.

[0128] Step 12: Deposit an insulating material on the surface of the first metal interconnect layer 117 to form an insulating layer 15, and bond the carrier wafer 16 to the insulating layer 15, and then flip the first transistor 11 so that the bottom substrate 213 is placed upward (see Figure 3E (b) in the figure.

[0129] Step 13: Remove the bottom substrate 213 by CMP treatment to achieve wafer thinning (see Figure 3E (c) in the figure.

[0130] Step 14: Remove the second sacrificial layer 214 to form a first groove 31 (see Figure 3F (a) in the figure.

[0131] Step 15: Fill the first groove 31 with polysilicon (see Figure 3F (b) in the figure.

[0132] Step 16: Remove the shallow trench isolation structure 22 that wraps the second active structure 121 to expose the second active structure 121 and form a shallow trench isolation layer 221 (see Figure 3F (c) in the figure.

[0133] Step 17: Based on the second active structure 121, a second spacer 123, a second source-drain structure 124 and a second interlayer dielectric layer 125 are formed (see Figure 3G (a) in the figure.

[0134] Step 18: Remove the second dummy gate structure 262 and the oxide isolation layer 25 covering the surface of the second active structure 121; deposit a layer of insulating material on the surface of the second active structure 121 to form a second gate dielectric layer 126; then, deposit a metal material in the second gate groove 242 to form a second gate structure 122 (see Figure 3G (b) in the figure.

[0135] It should be noted that the oxide isolation layer 25 located inside the first gate isolation layer 13 is not removed but is still retained and located between the first gate dielectric layer 116 and the second gate dielectric layer 126 .

[0136] Step 19: Perform a post-processing on the second gate structure 122 and the second interlayer dielectric layer 125 to form a second metal interconnection layer 127 (see Figure 3G (c) in the figure.

[0137] At this point, with a gate isolation layer provided between the first dummy gate structure and the second dummy gate structure and a gate isolation layer provided between the first gate structure and the second gate structure, the semiconductor structure 10 in which the first transistor 11 and the second transistor 12 are fin field effect transistors is completed.

[0138] Figure 4 This is a schematic diagram of the second structure of the semiconductor structure in the embodiment of the present application. Figure 4 (a) is the design layout of the semiconductor structure. It should be noted that, for ease of understanding, only the fin structure, gate structure, and source-drain structure are shown in the design layout; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the fin structure (i.e., CC' direction).

[0139] See also Figure 4 As shown, the semiconductor structure 10 includes a first transistor 11 and a second transistor 12, and the active structure in the semiconductor structure 10 is a plurality of fin structures. The fin structure is divided into two parts, one part is used as a first active structure 111 in the first transistor 11, and the other part is used as a second active structure 121 in the second transistor 12. The first gate structure 112 in the first transistor 11 and the second gate structure 122 in the second transistor 12 are integrally arranged and self-aligned.

[0140] In combination with the above preparation method, Figure 4 The preparation process of the semiconductor structure 10 is described below. Figure 4 The semiconductor structure shown can be Figure 5A and Figure 5B The process shown is prepared Figure 5A and Figure 5B Schematic diagram of the second preparation process of the semiconductor structure in the embodiment of the present application.

[0141] Step 1: providing a substrate 21; forming a first active structure 111 and a second active structure 121 and a second sacrificial layer 214; forming a shallow trench isolation structure 22; forming a gate groove 24, wherein the gate groove 24 includes a first gate groove 241 and a second gate groove 242 (see Figure 5A (a)) (For the specific process, please refer to the first to fifth steps of the first preparation process of the above-mentioned semiconductor structure).

[0142] Step 2: Polysilicon is deposited in the first gate groove 241 and the second gate groove 242 to form a first dummy gate structure 261 and a second dummy gate structure 262 that are integrally arranged (see Figure 5A (b) in the figure.

[0143] Step 3: Expose the first active structure 111, and based on the first active structure 111, form a first spacer 113, a first source-drain structure 114, a first interlayer dielectric layer 115 and a first metal interconnect layer (see Figure 5A (c)) (except that the first gate structure 112 and the first gate dielectric layer 116 are not formed, the process for preparing other structures in the first transistor 11 can refer to the eighth to eleventh steps of the first preparation process of the above-mentioned semiconductor structure).

[0144] Step 4: After flipping the wafer, a second spacer 123, a second source-drain structure 124, and a second interlayer dielectric layer 125 of the second transistor 12 are formed (see Figure 5B (a)) (For the specific process, please refer to the twelfth to seventeenth steps of the first preparation process of the above-mentioned semiconductor structure).

[0145] Step 5: Remove the first dummy gate structure 261, the second dummy gate structure 262 and the oxide isolation layer 25, deposit an insulating material on the surface of the first active structure 111 and the second active structure 121 to form an integrated first gate dielectric layer 116 and a second gate dielectric layer 126, and deposit a metal material in the first gate groove 241 and the second gate groove 242 to form an integrated first gate structure 112 and a second gate structure 122 (see Figure 5B (b) in the figure.

[0146] Step 6: Perform post-processing on the second gate structure 122 and the second interlayer dielectric layer 125 to form a second metal interconnect layer 127 (see Figure 5B (c) in the figure.

[0147] At this point, when the first dummy gate structure and the second dummy gate structure are integrally arranged and the first gate structure and the second gate structure are also integrally arranged, the semiconductor structure 10 in which the first transistor 11 and the second transistor 12 are fin field effect transistors is completed.

[0148] Figure 6 This is a schematic diagram of the third structure of the semiconductor structure in the embodiment of the present application. Figure 6 (a) is the design layout of the semiconductor structure. It should be noted that, for ease of understanding, only the fin structure, gate structure, and source-drain structure are shown in the design layout; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the fin structure (i.e., CC' direction).

[0149] See also Figure 6 As shown, the semiconductor structure 10 includes a first transistor 11 and a second transistor 12, and the active structure in the semiconductor structure 10 is a plurality of fin structures. The fin structure is divided into two parts, one part is used as the first active structure 111 in the first transistor 11, and the other part is used as the second active structure 121 in the second transistor 12. The first gate structure 112 in the first transistor 11 and the second gate structure 122 in the second transistor 12 are self-aligned, and a second gate isolation layer 14 is provided between the first gate structure 112 and the second gate structure 122, and the second gate isolation layer 14 is used to isolate the first gate structure 112 from the second gate structure 122.

[0150] In combination with the above preparation method, Figure 6 The preparation process of the semiconductor structure 10 is described below. Figure 6 The semiconductor structure shown can be Figure 7 The process shown is prepared Figure 7 Schematic diagram of the third preparation process of the semiconductor structure in the embodiment of the present application.

[0151] Step 1: forming a first transistor 11, wherein the first dummy gate structure 261 and the second dummy gate structure 262 are integrally arranged; flipping the first transistor 11, removing the bottom substrate 213, and filling the first groove 31; forming a second spacer 123, a second source-drain structure 124, and a second interlayer dielectric layer 125 in the second transistor 12 (see Figure 7 (a)) (except that the first gate structure 112 and the first gate dielectric layer 116 are not formed, the specific processes can refer to the first step to the seventeenth step of the first preparation process of the semiconductor structure mentioned above).

[0152] Step 2: remove the first dummy gate structure 261, the second dummy gate structure 262 and the oxide isolation layer 25; deposit an insulating material on the surface of the first active structure 111 and the second active structure 121 to form a first gate dielectric layer 116 and a second gate dielectric layer 126, wherein the first gate dielectric layer 116 and the second gate dielectric layer 126 are integrally arranged; deposit a metal material in the first gate groove 241 to form a first gate structure 112, deposit an oxide on the first gate structure 112 to form a second gate isolation layer 14, and deposit a metal material in the second gate groove 242 to form a second gate structure 122 (see Figure 7 (b) in the figure.

[0153] Step 3: Perform post-processing on the second gate structure 122 and the second interlayer dielectric layer 125 to form a second metal interconnection layer 127 (see Figure 7 (c) in the figure.

[0154] At this point, the semiconductor structure 10 in which the first transistor 11 and the second transistor 12 are fin field effect transistors is completed when the first dummy gate structure and the second dummy gate structure are integrally arranged and a gate isolation layer is arranged between the first gate structure and the second gate structure.

[0155] In the embodiment of the present application, by first forming a shallow trench isolation structure and then forming the first dummy gate structure and the second dummy gate structure, recrystallization of the first dummy gate structure and the second dummy gate structure can be avoided, thereby optimizing the process flow.

[0156] Furthermore, since the first dummy gate structure and the second dummy gate structure are formed before the first transistor is flipped, the first dummy gate structure and the second dummy gate structure are self-aligned, and thus the first gate structure and the second gate structure formed based on the first dummy gate structure and the second dummy gate structure are also self-aligned.

[0157] Furthermore, the semiconductor structure provided in the embodiment of the present application can be detected using a detection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the semiconductor structure provided in the embodiment of the present application can be detected by TEM slicing, such as the first gate structure and the second gate structure arranged integrally, or the first gate structure and the second gate structure with a gate isolation layer arranged therebetween.

[0158] In the embodiment of the present application, the method for preparing the semiconductor structure not only optimizes the process flow of the semiconductor structure, but also takes into account the consistency, defect density and alignment of the active regions of the upper and lower transistors (i.e., the first transistor and the second transistor). In addition, the method for preparing the semiconductor structure further solves the long-standing problems of the existing mainstream technical solutions for stacked transistors, such as complex process, fixed polarity (monolithic solution), difficult alignment, and high defect density of the upper semiconductor material (sequential solution), thereby promoting the industrialization of stacked transistor technology.

[0159] Secondly, the preparation method of the semiconductor structure described in the embodiment of the present application is also an organic fusion of the current sequential and monolithic stacked transistor solutions. The mature technology has high reuse, can avoid a large amount of expensive process development to save costs, and has high feasibility. At the same time, in the embodiment of the present application, the semiconductor structure adopts a self-aligned "back-to-back" active area and metal gate design, and the front and back transistors (i.e., the first transistor and the second transistor) have independent signal and power supply networks, and are connected through local interconnection. Without changing the extremely miniaturized 4T track unit design, the metal wiring resources are greatly released (can be increased by more than 60%), and there is huge space in the direction of collaborative optimization of process design. Finally, the flip-chip transistor solution is compatible with the existing mainstream device architecture, and can realize the front and back stacking of nanosheet field effect transistors, fin field effect transistors, planar transistors, vertical transistors and fork-plate transistors without the need for special process development for specific device architectures. It has strong flexibility and is highly extensible from the perspective of semiconductor process node iteration. The flip-chip stacked transistor is very advanced in concept, has important industrial value, and has strong practicality and broad prospects for expansion.

[0160] The present application embodiment provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can be found in the above Figure 2 , Figure 4 and Figure 6 The semiconductor structure shown will not be described in detail here.

[0161] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be found in the above Figure 2 , Figure 4 and Figure 6 The semiconductor structure shown will not be described in detail here.

[0162] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0163] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: An active structure is formed on a substrate; the active structure comprises a first active structure and a second active structure; Depositing an insulating material on the active structure to form a shallow trench isolation structure; the shallow trench isolation structure wraps the active structure; Forming a hard mask layer on the shallow trench isolation structure, and etching the shallow trench isolation structure using the hard mask layer as a mask to form a gate groove; Depositing oxide in the gate groove and on the surface of the active structure to form an oxide isolation layer; Depositing a semiconductor material in the gate groove to form an initial dummy gate structure; the initial dummy gate structure includes a first dummy gate structure corresponding to the first active structure and a second dummy gate structure corresponding to the second active structure, and the first dummy gate structure and the second dummy gate structure are self-aligned; removing a portion of the shallow trench isolation structure that wraps the first active structure to expose the first active structure; Based on the first active structure, forming a first transistor; flipping the wafer and removing the substrate; removing a portion of the shallow trench isolation structure that wraps the second active structure to expose the second active structure; A second transistor is formed based on the second active structure; and the first transistor and the second transistor are self-aligned.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: A first gate isolation layer is disposed between the first dummy gate structure and the second dummy gate structure; the gate groove includes a first gate groove corresponding to the first active structure and a second gate groove corresponding to the second active structure; Depositing a semiconductor material in the gate groove to form an initial dummy gate structure includes: depositing a semiconductor material in the second gate groove to form the second dummy gate structure; Depositing oxide on the second dummy gate structure to form the first gate isolation layer; the first gate isolation layer is used to isolate the first dummy gate structure from the second dummy gate structure; A semiconductor material is deposited on the first gate isolation layer to form the first dummy gate structure.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The forming of a first transistor based on the first active structure comprises: Based on the first active structure, forming a first source-drain structure and a first interlayer dielectric layer; Removing the first dummy gate structure, depositing an insulating material on the surface of the first active structure located in the first gate groove, and depositing a metal material in the first gate groove to form a first gate dielectric layer and a first gate structure; A back-end process is performed on the first gate structure and the first interlayer dielectric layer to form a first metal interconnection layer.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that: The forming of a second transistor based on the second active structure comprises: Based on the second active structure, forming a second source-drain structure and a second interlayer dielectric layer; removing the second dummy gate structure, depositing an insulating material on the surface of the second active structure in the second gate groove, and depositing a metal material in the second gate groove to form a second gate dielectric layer and a second gate structure; A back-end process is performed on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first dummy gate structure and the second dummy gate structure are formed by one process, and the gate groove includes a first gate groove corresponding to the first active structure and a second gate groove corresponding to the second active structure; The step of depositing a semiconductor material in the gate groove to form an initial dummy gate structure comprises: Depositing a semiconductor material in the second gate groove and the first gate groove to form the second dummy gate structure and the first dummy gate structure; The second dummy gate structure and the first dummy gate structure are integrally arranged.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The forming of a first transistor based on the first active structure comprises: Based on the first active structure, forming a first source-drain structure and a first interlayer dielectric layer; A back-end process is performed on the first dummy gate structure and the first interlayer dielectric layer to form a first metal interconnection layer.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that: The forming of a second transistor based on the second active structure comprises: Based on the second active structure, forming a second source-drain structure and a second interlayer dielectric layer; removing the first dummy gate structure and the second dummy gate structure to expose the gate groove; Depositing an insulating material on the surface of the active structure in the gate groove to form a gate dielectric layer; Depositing a metal material in the first gate groove and the second gate groove to form a first gate structure of the first transistor and a second gate structure of the second transistor; A back-end process is performed on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

8. The method for preparing a semiconductor structure according to claim 5, characterized in that: The forming of a second transistor based on the second active structure comprises: Based on the second active structure, forming a second source-drain structure and a second interlayer dielectric layer; removing the first dummy gate structure and the second dummy gate structure to expose the first gate groove and the second gate groove; Depositing an insulating material on the surface of the active structure in the gate groove to form a gate dielectric layer; Depositing metal materials in the first gate groove and the second gate groove respectively to form a first gate structure of the first transistor and a second gate structure of the second transistor; A back-end process is performed on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The depositing of metal material in the first gate groove and the second gate groove to form a first gate structure of the first transistor and a second gate structure of the second transistor respectively comprises: Depositing a metal material in the first gate groove to form the first gate structure; Depositing oxide on the first gate structure to form a second gate isolation layer; the second gate isolation layer is used to isolate the first gate structure from the second gate structure; A metal material is deposited on the second gate isolation layer to form the second gate structure.

10. The method for preparing a semiconductor structure according to claim 1, characterized in that: The substrate comprises a top substrate, a first sacrificial layer and a bottom substrate which are stacked, and the top substrate is used to form the active structure; The forming of the active structure on the substrate comprises: etching the top substrate and the first sacrificial layer to form the active structure and the second sacrificial layer; the second sacrificial layer connects the bottom substrate and the active structure; After flipping the wafer and removing the substrate, the method further includes: removing the bottom substrate and the second sacrificial layer to form a first groove; filling the first groove with the semiconductor material to form a dummy gate structure; and the dummy gate structure wraps the active structure in the gate groove.

Images