Time-to-digital conversion device and conversion method thereof

Abstract

The present invention provides a time-to-digital conversion device and a conversion method. A first digital code is generated by counting the output signal of a first ring oscillator circuit. A second digital code is generated by counting the output signal of a second ring oscillator circuit. A corresponding third digital code is generated at a time point when the phase of one of the outputs of a plurality of first delay stages of the first ring oscillator circuit and the phase of one of the outputs of a plurality of second delay stages of the second ring oscillator circuit coincide.

Description

Technical Field

[0001] This invention relates to a conversion device, and more particularly to a time-to-digital conversion device and its conversion method. Background Technology

[0002] With the development of integrated circuits, converting the sensing information obtained by sensors into digital code can enable wider applications. In time measurement systems, time-to-digital converters can be used to measure the time interval between two events and convert this time information into a digital signal.

[0003] In many modern applications (such as radar ranging, time of flight, etc.), the measurement resolution requirements of time-to-digital converters are increasing to meet the accuracy requirements of time measurement. Therefore, how to improve the measurement resolution of time-to-digital converters is an important issue. Summary of the Invention

[0004] This invention provides a time-to-digital conversion device and method, which can provide high-resolution time measurement.

[0005] The time-to-digital converter of the present invention converts the time difference between a received start signal and a stop signal into a digital code signal. The time-to-digital converter includes a first ring oscillator circuit, a first counter circuit, a second ring oscillator circuit, a second counter circuit, an arbitrator circuit, and an encoding circuit. The first ring oscillator circuit receives the start signal and includes N first delay stages, where N is an odd number greater than 1. The first counter circuit is coupled to the first ring oscillator circuit, counts the output signal of the first ring oscillator circuit to generate a first digital code, and stops counting the output signal of the first ring oscillator circuit based on a stop signal. The second ring oscillator circuit receives the stop signal and includes N second delay stages. The second counter circuit is coupled to the second ring oscillator circuit, counts the output signal of the second ring oscillator circuit to generate a second digital code. The arbitrator circuit is coupled to the first and second ring oscillator circuits, and generates multiple arbitration signals based on the outputs of each first and second delay stage. These arbitration signals indicate the transition state of the outputs of each first and second delay stage. The encoding circuit is coupled to the arbitrator circuit and the second counter circuit. Based on the above-mentioned multiple arbitration signals, it outputs a counting stop signal and a third digital code. The counting stop signal is used to control the second counter circuit to stop counting, and the third digital code indicates the time point at which one of the outputs of the multiple first delay stages coincides with one of the outputs of the multiple second delay stages.

[0006] In one embodiment of the present invention, the first ring oscillator circuit includes a NAND gate and N-1 inverters. One input of the NAND gate receives a start signal, and the other input of the NAND gate is coupled to the output of the first ring oscillator circuit. The N-1 inverters are connected in series between the output of the NAND gate and the other input of the NAND gate. The output of the NAND gate and the output of each inverter are coupled to an arbitrator circuit.

[0007] In one embodiment of the present invention, the second ring oscillator circuit described above includes a NAND gate and N-1 inverters. One input terminal of the NAND gate receives a stop signal, and the other input terminal of the NAND gate is coupled to the output terminal of the second ring oscillator circuit. The N-1 inverters are connected in series between the output terminal of the NAND gate and the other input terminal of the NAND gate. The output terminal of the NAND gate and the output terminals of each inverter are coupled to an arbitrator circuit.

[0008] In one embodiment of the present invention, each of the first delay stages has a first delay time, each of the second delay stages has a second delay time, and the first delay time is greater than the second delay time.

[0009] In one embodiment of the present invention, the above-described encoding circuit outputs a counting stop signal and a third digital code when the arbitration signal indicates that one of the outputs of the N first delay stages coincides with the phase of one of the N second delay stages.

[0010] In one embodiment of the present invention, the arbitrator circuit includes a plurality of arbitrators, each arbitrator being coupled between the output terminal of the corresponding first delay stage and the output terminal of the corresponding second delay stage, and generating a corresponding arbitration signal based on the outputs of the corresponding first delay stage and the corresponding second delay stage.

[0011] In one embodiment of the present invention, the above-mentioned time-to-digital conversion device further includes a buffer circuit, which is coupled to a first counter circuit, a second counter circuit and an encoding circuit, and outputs a first digital code, a second digital code and a third digital code as digital code signals according to a clock signal.

[0012] This invention also provides a conversion method for a time-to-digital converter. The time-to-digital converter can convert the time difference between a received start signal and a stop signal into a digital code signal. The time-to-digital converter includes a first ring oscillator circuit for receiving the start signal and a second ring oscillator circuit for receiving the stop signal. The first ring oscillator circuit includes N first delay stages, and the second ring oscillator circuit includes N second delay stages, where N is an odd number greater than 1. The conversion method includes the following steps: Counting the output signal of the first ring oscillator circuit to generate a first digital code. Stopping the counting of the output signal of the first ring oscillator circuit according to the stop signal. Counting the output signal of the second ring oscillator circuit to generate a second digital code. Generating a plurality of arbitration signals based on the outputs of each first delay stage and each second delay stage, these arbitration signals indicating the transition state of the outputs of each first delay stage and each second delay stage. Outputting a counting stop signal and a third digital code based on the plurality of arbitration signals, wherein the counting stop signal indicates the cessation of counting the output signal of the second ring oscillator circuit, and the third digital code indicates the time point at which the phase of one output of the plurality of first delay stages coincides with that of one output of the plurality of second delay stages. A digital code signal is generated based on the first digital code, the second digital code, and the third digital code.

[0013] In one embodiment of the present invention, the first ring oscillator circuit described above includes a NAND gate and N-1 inverters. One input of the NAND gate receives a start signal, and the other input of the NAND gate is coupled to the output of the first ring oscillator circuit. The N-1 inverters are connected in series between the output of the NAND gate and the other input of the NAND gate.

[0014] In one embodiment of the present invention, the second ring oscillator circuit described above includes a NAND gate and N-1 inverters. One input of the NAND gate receives a start signal, and the other input of the NAND gate is coupled to the output of the second ring oscillator circuit. The N-1 inverters are connected in series between the output of the NAND gate and the other input of the NAND gate.

[0015] In one embodiment of the present invention, each of the first delay stages has a first delay time, each of the second delay stages has a second delay time, and the first delay time is greater than the second delay time.

[0016] In one embodiment of the present invention, the conversion method of the above-mentioned time-to-digital conversion device includes outputting a counting stop signal and a third digital code when the plurality of arbitration signals indicate that one of the outputs of N first delay stages coincides with one of the outputs of N second delay stages.

[0017] Based on the above, embodiments of the present invention generate a first digital code by counting the output signal of a first ring oscillator circuit, generate a second digital code by counting the output signal of a second ring oscillator circuit, and generate a corresponding third digital code based on the time point when the phases of one of the outputs of a plurality of first delay stages of the first ring oscillator circuit and one of the outputs of a plurality of second delay stages of the second ring oscillator circuit coincide. In this way, the time difference between the start signal and the stop signal is converted into a digital code signal including the first digital code, the second digital code, and the third digital code, which can provide high-resolution time measurement.

[0018] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a time-to-digital conversion device according to an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of a time-to-digital conversion device according to another embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of the operation timing of a time-to-digital converter according to an embodiment of the present invention;

[0022] Figure 4 This is a flowchart of a conversion method of a time-to-digital conversion device according to an embodiment of the present invention. Detailed Implementation

[0023] Figure 1 This is a schematic diagram of a time-to-digital conversion device according to an embodiment of the present invention. Please refer to... Figure 1The time-to-digital converter 100 converts the time difference between the received start signal ST1 and stop signal SP1 into a digital code signal SD1. The time-to-digital converter 100 may include ring oscillator circuits 102 and 104, counter circuits 106 and 108, an arbiter circuit 110, an encoder circuit 112, and a buffer circuit 114. The arbiter circuit 110 is coupled to the ring oscillator circuits 102 and 104 and the encoder circuit 112. The counter circuit 106 is coupled to the ring oscillator circuit 102 and the buffer circuit 114. The counter circuit 108 is coupled to the ring oscillator circuit 104, the encoder circuit 112, and the buffer circuit 114. The buffer circuit 114 is also coupled to the encoder circuit 112. The start signal ST1 and stop signal SP1 can, for example, come from the multiplexer MUX. The input of the multiplexer MUX is used to receive the target signal STG, which is the object of measurement. The multiplexer MUX can be controlled by the selection signal SCON to transmit the target signal STG as the start signal ST1 to the ring oscillator circuit 102, or transmit the target signal STG as the stop signal SP1 to the ring oscillator circuit 104.

[0024] Furthermore, the ring oscillator circuits 102 and 104 may each include N delay stages (not shown), where N is an odd number greater than 1. Counter circuits 106 and 108 are used to count the clock signals output by the ring oscillator circuits 102 and 104, respectively, generating a first digital code CA and a second digital code CB. Counter circuit 106 also receives a stop signal SP1; when it receives the stop signal SP1 from the multiplexer MUX, it stops counting. Arbitrator circuit 110 can generate multiple arbitration signals SB1 to SB2N based on the outputs of each delay stage in ring oscillator circuit 102 and ring oscillator circuit 104. Arbitration signals SB1 to SB2N indicate the transition state of the corresponding delay stage output, such as a transition from a low voltage level to a high voltage level, or from a high voltage level to a low voltage level. The encoding circuit 112 can output a counting stop signal SE1 and a third digital code CC based on the arbitration signals SB1 to SB2N. Furthermore, the encoding circuit 112 can determine the time point when the phases of one of the outputs of multiple delay stages in the ring oscillator circuit 102 and one of the outputs of multiple delay stages in the ring oscillator circuit 104 coincide based on the arbitration signals SB1 to SB2N, and output the corresponding third digital code CC and the counting stop signal SE1 to the counter circuit 108 to control the counter circuit 108 to stop counting.

[0025] The buffer circuit 114 can temporarily store the first digital code CA and the second digital code CB corresponding to when the counter circuits 106 and 108 stop counting, as well as the third digital code CC provided by the encoding circuit 112. Controlled by the clock signal, it outputs the first digital code CA, the second digital code CB, and the third digital code CC as the digital code signal SD1 to the subsequent processing circuit. The processing circuit can calculate the time difference between the start signal ST1 and the stop signal SP1 based on the first digital code CA, the second digital code CB, and the third digital code CC. For example, the time difference T between the start signal ST1 and the stop signal SP1 can be calculated using the following formula.

[0026] T=2*N*t1*CA+(2*N*CB+CC)*(t1-t2) (1)

[0027] Where N represents the number of delay stages included in the ring oscillator circuits 102 and 104 respectively, t1 represents the delay time of the delay stage in the ring oscillator circuit 102, and t2 represents the delay time of the delay stage in the ring oscillator circuit 104, wherein the delay time t1 is greater than the delay time t2. It is worth noting that due to process factors, the values ​​of delay times t1 and t2 may differ from the expected values. In the case where the actual values ​​of delay times t1 and t2 are uncertain, two sets of known start signals ST1 and stop signals SP1 with different time differences can be provided to the ring oscillator circuits 102 and 104 to obtain the corresponding two sets of first digital codes CA, second digital codes CB, and third digital codes CC. The two sets of known first digital codes CA, second digital codes CB, and third digital codes CC are then substituted into equation (1) to obtain the accurate delay times t1 and t2. After obtaining the accurate delay times t1 and t2, the start signal ST1 and stop signal SP1 with unknown time differences can be accurately measured.

[0028] Figure 2 This is a schematic diagram of a time-to-digital conversion device according to another embodiment of the present invention. Please refer to... Figure 2 .exist Figure 2In this embodiment, the ring oscillator circuits 102 and 104 of the time-to-digital converter 100 each include five delay stages. The five delay stages of ring oscillator circuit 102 are implemented using AND gates AND1 and inverters A1-A4, while the five delay stages of ring oscillator circuit 104 are implemented using AND gates AND2 and inverters B1-B4. In ring oscillator circuit 102, AND gates AND1 and inverters A1-A4 are sequentially connected in series between the input and output terminals of ring oscillator circuit 102. One input terminal of AND gate AND1 is used to receive the start signal ST1, and the other input terminal is coupled to the output terminal of inverter A4. Similarly, in ring oscillator circuit 104, AND gates AND2 and inverters B1-B4 are sequentially connected in series between the input and output terminals of ring oscillator circuit 104. One input terminal of AND gate AND2 is used to receive the stop signal SP1, and the other input terminal is coupled to the output terminal of inverter B4.

[0029] In addition, Figure 2 In this embodiment, the arbitrator circuit 110 includes five arbitrators AB1 to AB5, each of which may include two phase detectors for detecting rising and falling edges. Arbitrators AB1 to AB5 are coupled to the outputs of their respective delay stages. For example, arbitrator AB1 is coupled to the outputs of AND1 and AND2, arbitrator AB2 is coupled to the outputs of inverters A1 and B1, and so on. Furthermore, arbitrators AB1 to AB5 are also coupled to an encoding circuit 112. Arbitrators AB1 to AB5 can determine the transition states of the outputs of AND1 and AND2, and the outputs of inverters A1 to A4 and B1 to B4, based on output signals S0 to S4 and F0 to F4, and output the corresponding arbitration signals. For example, such as... Figure 3As shown, arbitrators AB1 to AB5 can output arbitration signals SB1 to SB10 at the transition times 10 to 100 of output signals F0 to F4, respectively. For example, when output signal F0 changes from a high voltage level to a low voltage level, if output signal F0 and the corresponding output signal S0 are not in phase, arbitrator AB1 can output arbitration signal SB1 with a bit value of "0", otherwise it outputs arbitration signal SB1 with a bit value of "1". Similarly, when output signal F1 changes from a low voltage level to a high voltage level, if output signal F1 and the corresponding output signal S1 are not in phase, arbitrator AB2 can output arbitration signal SB2 with a bit value of "0", otherwise it outputs arbitration signal SB2 with a bit value of "1". And so on. Arbitrators AB3 to AB5 can also determine whether output signals S2 to S4 and the corresponding output signals F2 to F4 are in phase when output signals F2 to F4 change state, and output arbitration signals based on the determination result. The encoding circuit 112 can generate a third digital code CC based on the bit values ​​of the arbitration signals SB1 to SB10 output by the arbitrators AB1 to AB5, and generate a counting stop signal SE1 for the counter circuit 108.

[0030] For example, in Figure 3 In this embodiment, when the output signal F1 of inverter B1 of ring oscillator circuit 104 changes from a low voltage level to a high voltage level at transition time ②, the output signal S1 of inverter A1 of ring oscillator circuit 102 also changes from a low voltage level to a high voltage level simultaneously. That is, the output signal F1 and the output signal S1 are in phase. At this time, the bit value of arbitration signal SB2 corresponding to transition time ② is "1", and the bit values ​​of the other arbitration signals SB1, SB3 to SB10 are "0". Encoding circuit 112 can generate a third digital code CC based on the arbitration signals SB1 to SB10 output by arbitrators AB1 to AB5, and generate a counting stop signal SE1 for counter circuit 108. The buffer circuit 114 is controlled by the clock signal CLK. When the counter circuit 106 stops counting, the first digital code CA, the second digital code CB, and the third digital code CC corresponding to the stop counting of the counter circuit 108 are used as digital code signals SD1 and sent to the subsequent processing circuit. The processing circuit can calculate the time difference between the start signal ST1 and the stop signal SP1 according to the above formula (1). The time difference between the start signal ST1 and the stop signal SP1 can be calculated as follows: Figure 3As shown, it is equal to time T1 + T2, where time T1 is equal to 2 * 5 * t1 * CA, and time T2 is equal to (2 * 5 * CB + CC) * (t1 - t2). In this embodiment, the value of the first digital code CA is 5 (counter circuit 106 counts to the 5 rising edges of output signal S4), the value of the second digital code CB is 1 (counter circuit 108 counts to the 1 rising edge of output signal F4), and the value of the third digital code CC is 2 (the position where the phase of the output signal coincides is at the transition time point ②).

[0031] Figure 4 This is a flowchart of a conversion method using a time-to-digital converter according to an embodiment of the present invention. The time-to-digital converter can convert the time difference between a received start signal and a stop signal into a digital code signal. The time-to-digital converter includes a first ring oscillator circuit for receiving the start signal and a second ring oscillator circuit for receiving the stop signal. The first ring oscillator circuit includes N first delay stages, and the second ring oscillator circuit includes N second delay stages, where N is an odd number greater than 1. Each first delay stage has a first delay time, and each second delay stage has a second delay time, with the first delay time being greater than the second delay time. Further, the first ring oscillator circuit may include N NAND gates and N-1 inverters as the N first delay stages. The first input of the NAND gate receives the start signal, the second input of the NAND gate is coupled to the output of the first ring oscillator circuit, and the N-1 inverters are connected in series between the output of the NAND gate and the second input of the NAND gate. In addition, the second ring oscillator circuit may also include N NAND gates as second delay stages and N-1 inverters. The first input of the NAND gate receives a stop signal, the second input of the NAND gate is coupled to the output of the second ring oscillator circuit, and the N-1 inverters are connected in series between the output of the NAND gate and the second input of the NAND gate.

[0032] As can be seen from the above embodiments, the conversion method of the time-to-digital converter may include at least the following steps. First, a first digital code is generated by counting the output signal of the first ring oscillator circuit (step S402). Then, counting the output signal of the first ring oscillator circuit is stopped according to a stop signal (step S404), and a second digital code is generated by counting the output signal of the second ring oscillator circuit (step S406). Then, a plurality of arbitration signals are generated according to the output of each first delay stage and the output of each second delay stage (step S408), wherein these arbitration signals indicate the transition state of the output of each first delay stage and the output of each second delay stage, for example, indicating whether a rising edge or a falling edge occurs simultaneously. Subsequently, a counting stop signal and a third digital code are output based on multiple arbitration signals (step S410). For example, the counting stop signal and the third digital code are output when the arbitration signals indicate that one of the outputs of the N first delay stages coincides with one of the outputs of the N second delay stages. The counting stop signal is used to indicate the cessation of counting the output signal of the second ring oscillator circuit, and the third digital code indicates the time point at which one of the outputs of the first delay stage coincides with one of the outputs of the second delay stage. Finally, a digital code signal is generated based on the first digital code, the second digital code, and the third digital code (step S412). The time difference between the start signal and the stop signal can be accurately calculated using the first digital code, the second digital code, the third digital code in the digital code signal, and the above equation (1).

[0033] In summary, embodiments of the present invention generate a first digital code by counting the output signal of a first ring oscillator circuit, generate a second digital code by counting the output signal of a second ring oscillator circuit, and generate a corresponding third digital code based on the time point when the phases of one of the outputs of a plurality of first delay stages of the first ring oscillator circuit and one of the outputs of a plurality of second delay stages of the second ring oscillator circuit coincide. In this way, the time difference between the start signal and the stop signal is converted into a digital code signal including the first digital code, the second digital code, and the third digital code, which can provide high-resolution time measurement.

[0034] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A time-to-digital conversion device, characterized in that, The time-to-digital converter converts the time difference between the received start and stop signals into a digital code signal. A first ring oscillator circuit receives the start signal. The first ring oscillator circuit includes N first delay stages, where N is an odd number greater than 1. A first counter circuit is coupled to the first ring oscillator circuit, counts the output signal of the first ring oscillator circuit to generate a first digital code, and stops counting the output signal of the first ring oscillator circuit according to the stop signal. A second ring oscillator circuit receives the stop signal, and the second ring oscillator circuit includes N second delay stages; The second counter circuit is coupled to the second ring oscillator circuit and counts the output signal of the second ring oscillator circuit to generate a second digital code. An arbitrator circuit, coupled to the first ring oscillator circuit and the second ring oscillator circuit, generates a plurality of arbitration signals based on the outputs of each first delay stage and each second delay stage. These arbitration signals indicate the transition states of the outputs of each first delay stage and each second delay stage. An encoding circuit, coupled to the arbitrator circuit and the second counter circuit, outputs a counting stop signal and a third digital code based on the plurality of arbitration signals. The counting stop signal is used to control the second counter circuit to stop counting, and the third digital code indicates the time point at which one of the outputs of the N first delay stages coincides with one of the outputs of the N second delay stages.

2. The time-to-digital conversion device according to claim 1, characterized in that, The first ring oscillator circuit includes: A NAND gate, one input of which receives the start signal, and the other input of which is coupled to the output of the first ring oscillator circuit; and N-1 inverters are connected in series between the output of the NAND gate and the other input of the NAND gate. The output of the NAND gate and the output of each inverter are coupled to the arbitrator circuit.

3. The time-to-digital conversion device according to claim 1, characterized in that, The second ring oscillator circuit includes: A NAND gate, one input of which receives the stop signal, and the other input of which is coupled to the output of the second ring oscillator circuit; and N-1 inverters are connected in series between the output of the NAND gate and the other input of the NAND gate. The output of the NAND gate and the output of each inverter are coupled to the arbitrator circuit.

4. The time-to-digital conversion device according to claim 1, characterized in that, Each first delay stage has a first delay time, and each second delay stage has a second delay time, wherein the first delay time is greater than the second delay time.

5. The time-to-digital conversion device according to claim 1, characterized in that, The encoding circuit outputs the counting stop signal and the third digital code when the plurality of arbitration signals indicate that one of the outputs of the N first delay stages is in phase with one of the N second delay stages.

6. The time-to-digital conversion device according to claim 1, characterized in that, The arbitrator circuit includes multiple arbitrators, each of which is coupled between the output of the corresponding first delay stage and the output of the corresponding second delay stage, and generates a corresponding arbitration signal based on the outputs of the corresponding first delay stage and the corresponding second delay stage.

7. The time-to-digital conversion device according to claim 1, characterized in that, Also includes: The buffer circuit is coupled to the first counter circuit, the second counter circuit, and the encoding circuit, and outputs the first digital code, the second digital code, and the third digital code as the digital code signal according to the clock signal.

8. A conversion method for a time-to-digital converter, characterized in that, The time-to-digital converter converts the time difference between the received start signal and stop signal into a digital code signal. The time-to-digital converter includes a first ring oscillator circuit for receiving the start signal and a second ring oscillator circuit for receiving the stop signal. The first ring oscillator circuit includes N first delay stages, and the second ring oscillator circuit includes N second delay stages, where N is an odd number greater than 1. The conversion method of the time-to-digital converter includes: The first digital code is generated by counting the output signals of the first ring oscillator circuit. The counting of the output signal of the first ring oscillator circuit is stopped according to the stop signal. The second digital code is generated by counting the output signal of the second ring oscillator circuit; Multiple arbitration signals are generated based on the outputs of each first delay stage and each second delay stage, and the multiple arbitration signals indicate the transition status of the outputs of each first delay stage and each second delay stage; Based on the plurality of arbitration signals, a counting stop signal and a third digital code are output, wherein the counting stop signal is used to indicate the cessation of counting the output signal of the second ring oscillator circuit, and the third digital code indicates the time point at which the phase of one output of the N first delay stages coincides with the phase of one output of the N second delay stages; and A digital code signal is generated based on the first digital code, the second digital code, and the third digital code.

9. The conversion method of the time-to-digital conversion device according to claim 8, characterized in that, The first ring oscillator circuit includes: A NAND gate, one input of which receives the start signal, and the other input of which is coupled to the output of the first ring oscillator circuit; and N-1 inverters are connected in series between the output of the NAND gate and the other input of the NAND gate.

10. The conversion method of the time-to-digital converter according to claim 8, characterized in that, The second ring oscillator circuit includes: A NAND gate, one input of which receives the stop signal, and the other input of which is coupled to the output of the second ring oscillator circuit; and N-1 inverters are connected in series between the output of the NAND gate and the other input of the NAND gate.

11. The conversion method of the time-to-digital conversion device according to claim 8, characterized in that, Each first delay stage has a first delay time, and each second delay stage has a second delay time, wherein the first delay time is greater than the second delay time.

12. The conversion method of the time-to-digital conversion device according to claim 8, characterized in that, include: When the plurality of arbitration signals indicate that one of the outputs of the N first delay stages is in phase with one of the N second delay stages, the counting stop signal and the third digital code are output.

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