A super junction IGBT half-cell structure, device and preparation method

Abstract

The present invention relates to a super junction IGBT half-cell structure, device and preparation method in the field of semiconductor technology, comprising an emitter structure, a gate structure and a collector structure, wherein the emitter structure and the gate structure are arranged in contact with each other side by side, and a drift region structure is arranged between the emitter structure and the gate structure arranged in contact with each other side by side and the collector structure, the drift region structure is arranged in partial contact with the gate structure, a carrier storage layer is arranged between the drift region structure and the emitter structure, and the gate structure is arranged in partial contact with the carrier storage layer, and a hole channel region is arranged between the gate structure, the drift region structure and the carrier storage layer, thereby solving the problem that the existing IGBT device cannot achieve the improvement of conductivity modulation effect and the reduction of device turn-off loss at the same time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a super junction IGBT half-cell structure, a device and a preparation method thereof. Background Art

[0002] IGBT is the abbreviation of insulated gate bipolar transistor, which is a voltage-controlled power semiconductor device used in high-frequency and high-voltage applications. It can be used in DC-DC conversion, AC-DC conversion, motor control, inverters, electric vehicles and other fields.

[0003] The super junction (SJ) can reduce the forward conduction power consumption of the device, improve the forward conduction performance of the device, and increase the speed of establishing the electric field when the device is turned off. It is located in the drift region of the IGBT and includes N-type columns and P-type columns arranged alternately.

[0004] In an existing SJ-IGBT device, there is a P-type well region above the drift region, and there is a mutual contact area between the P-type well region and the P-type column, and even an overlapping area, which causes holes to be extracted when the device is forward-conducted, suppressing the conductivity modulation effect, increasing the forward conduction voltage of the device, and increasing the conduction loss. When improving the existing scheme, another SJ-IGBT device is proposed, namely: using a gate to separate the P-type well region from the P-type column, to a certain extent suppressing the extraction of holes when the device is forward-conducted, reducing the forward conduction voltage of the device, but because the P-type well region is separated from the P-type column, it is difficult for the holes in the P-type column to be quickly extracted when the device is turned off, increasing the turn-off loss of the device. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention provides a super junction IGBT half-cell structure, a device and a preparation method, which solves the problem that the existing IGBT device cannot achieve the improvement of the conductivity modulation effect and reduce the device turn-off loss at the same time.

[0006] In order to solve the above technical problems, the present invention is solved by the following technical solutions:

[0007] A super junction IGBT half-cell structure comprises an emitter structure, a gate structure and a collector structure, wherein the emitter structure and the gate structure are arranged in contact with each other side by side, and a drift region structure is arranged between the emitter structure and the gate structure arranged in contact with each other side by side, and the collector structure, the drift region structure is arranged in contact with part of the gate structure, a carrier storage layer is arranged between the drift region structure and the emitter structure, and the gate structure is arranged in contact with part of the carrier storage layer, a hole channel region is arranged between the gate structure, the drift region structure and the carrier storage layer, the doping concentration of the carrier storage layer is lower than the doping concentration of the hole channel region, and the carrier storage layer and the hole channel region are semiconductors of opposite conductivity types.

[0008] Optionally, the hole channel region is located at a corner portion of the gate structure, and a cross section of the hole channel region is in a stepped or convex polygonal shape, forming a stepped or convex polygonal groove.

[0009] Optionally, the convex polygon is in the shape of an oblique ladder.

[0010] Optionally, the carrier storage layer is a low-doped N-type semiconductor, and the doping concentration of the carrier storage layer is 2×e 16 cm -3 ~6×e 16 cm -3 The hole channel region is a low-doped P-type semiconductor, and the doping concentration of the hole channel region is 7×e 16 cm -3 ~5×e 17 cm -3 .

[0011] Optionally, the gate structure includes a polysilicon gate, a gate oxide layer and a gate electrode, the polysilicon gate is arranged on the gate oxide layer, and the gate electrode is arranged on the polysilicon gate.

[0012] Optionally, the emitter structure includes a first cathode region, a second cathode region, a base region and a first electrode, the first cathode region and the second cathode region are both arranged on the base region, and the first cathode region and the second cathode region are arranged in contact with each other, the first electrode is arranged on the first cathode region and the second cathode region, and the first cathode region and the second cathode region are both arranged in partial contact with the first electrode, the conductivity type of the first cathode region and the base region is the same as the conductivity type of the hole channel region, and the second cathode region and the carrier storage layer are the same conductivity type.

[0013] Optionally, the drift region structure includes an N column region, a P column region and a buffer region, the P column region and the N column region are both arranged on the buffer region, and the P column region is arranged in contact with the N column region, the conductivity type of the N column region and the buffer region is the same as the carrier storage layer, and the P column region and the hole channel region are the same conductivity type.

[0014] Optionally, when the device is turned off, the hole channel region forms a hole channel between the P column region and the base region.

[0015] Optionally, the hole channel region is arranged on the lower surface of the gate oxide layer and is in partial contact with the gate oxide layer. The lower surface of the hole channel is also respectively in contact with part of the N column region and part of the P column region, and the side wall of the hole channel region is also in contact with part of the carrier storage layer.

[0016] Optionally, the carrier storage layer is disposed on the lower surface of the base region and is disposed in contact with the N column region, and a portion of the sidewall of the carrier storage layer is disposed in contact with the hole channel region.

[0017] Optionally, the thickness of the N column region is greater than or equal to the thickness of the P column region.

[0018] Optionally, the collector structure includes a collector region and a second electrode, the second electrode is arranged on the collector region, and the collector region and the hole channel region have the same conductivity type.

[0019] A super junction IGBT device comprises one or more super junction IGBT cell structures, wherein the super junction IGBT cell structure comprises any one of the super junction IGBT half cell structures described above.

[0020] Optionally, a group of the above-mentioned super junction IGBT cell structures includes symmetrically arranged super junction IGBT half cell structures.

[0021] Optionally, one or more of the super junction IGBT cell structures include a super junction IGBT half cell structure and a traditional half cell structure, and the super junction IGBT half cell structure and the traditional half cell structure are arranged in contact with each other side by side, and a hole channel region is not arranged at the corner of the gate structure of the traditional half cell structure, and the gate structure of the traditional half cell structure is directly arranged in contact with the N column region and the base region.

[0022] A method for preparing a super junction IGBT half-cell structure, the method for preparing a super junction IGBT half-cell structure as described in any one of the above, specifically comprising the following steps:

[0023] S1, selecting silicon as a substrate, the substrate including a collector region and a buffer region, performing epitaxy on the substrate and injecting N-type impurities to form an N column region;

[0024] S2, setting a mask for etching on the upper surface of the N column region, performing etching to form a column region trench, and depositing P-type doped silicon in the trench to form a P column region;

[0025] S3, setting a mask for etching on the upper surface of the P column region, etching to form a portion of the gate trench, setting a mask for etching on the upper surface of a portion of the N column region, etching to form another portion of the gate trench, and the two together constitute the gate trench;

[0026] S4, forming a mask on the upper surface of a portion of the N column region and the P column region, and performing ion implantation and high-temperature diffusion to form a carrier storage layer;

[0027] S5, forming a mask on the upper surface of part of the N column region and part of the P column region, and performing ion implantation and high-temperature diffusion to form a hole channel region;

[0028] S6, growing a 0.1 um gate oxide layer on the surface of the gate trench, and depositing polysilicon on the surface of the gate oxide layer to form a polysilicon gate;

[0029] S7, performing ion implantation and high-temperature diffusion on the upper surface of the carrier storage layer to form a base region;

[0030] S8, forming a mask on the upper surface of the base region to perform ion implantation and high-temperature diffusion to form a first cathode region;

[0031] S9, forming a mask on the upper surface of the base region to perform ion implantation and high-temperature diffusion to form a second cathode region;

[0032] S10, injecting N-type impurities into the lower surfaces of the N column region and the P column region to form an N-buffer region;

[0033] S11, injecting P-type impurities into the lower surface of the N-buffer region to form a P-collector region;

[0034] S12, depositing metal on the lower surface of the P-collector region to form a second electrode;

[0035] S13, depositing metal on a portion of the upper surface of the first cathode region and the second cathode region to form a first electrode;

[0036] S14, depositing metal on a portion of the upper surface of the polysilicon gate to form a gate electrode.

[0037] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0038] By introducing the hole channel region and the carrier storage layer, the hole channel region is used to form a hole channel between the P-column region and the base region when the device is turned off, thereby increasing the speed of hole extraction and reducing the turn-off loss. During forward conduction, the space charge region generated in the hole channel region by the positive voltage of the polysilicon gate and the carrier storage layer jointly hinder the movement of holes, thereby enhancing the conductivity modulation effect during forward conduction and reducing the forward conduction voltage drop. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0040] Figure 1 This is one of the structural diagrams of a super junction IGBT half-cell structure proposed in the first embodiment;

[0041] Figure 2 (a) is a schematic diagram of the working principle of a super junction IGBT half-cell structure proposed in the first embodiment when it is forward-conducting;

[0042] Figure 2 (b) is a schematic diagram of the working principle of a super junction IGBT half-cell structure proposed in the first embodiment when it is turned off;

[0043] Figure 3 The breakdown voltage and forward conduction voltage diagram of the carrier storage layer of a super junction IGBT half-cell structure proposed in the first embodiment are analyzed by the doping concentration deviation.

[0044] Figure 4 A comparison diagram of blocking characteristics between a super junction IGBT half-cell structure proposed in the first embodiment and a conventional super junction IGBT;

[0045] Figure 5 A comparison diagram of forward conduction characteristics between a super junction IGBT half-cell structure proposed in the first embodiment and a conventional super junction IGBT;

[0046] Figure 6 A circuit diagram for the simulated dynamic switch test proposed in the first embodiment;

[0047] Figure 7 A comparison diagram of turn-off waveforms of a super junction IGBT half-cell structure and a traditional super junction IGBT proposed in the first embodiment;

[0048] Figure 8A waveform comparison diagram of dV / dt when a super junction IGBT half-cell structure proposed in the first embodiment is turned off with a traditional super junction IGBT;

[0049] Fig. 9 The V of the half-cell structure of a super junction IGBT proposed in the first embodiment and the traditional super junction IGBT is shown in FIG. ON -E OFF Trade-off comparison chart;

[0050] Fig.10 The V of the half-cell structure of a super junction IGBT proposed in the first embodiment and the traditional super junction IGBT is shown in FIG. peak -E OFF Weigh and compare;

[0051] Fig.11 This is the second structural diagram of a super junction IGBT half-cell structure proposed in the first embodiment;

[0052] Fig.12 A structural diagram of a super junction IGBT half-cell structure proposed in the second embodiment;

[0053] Fig.13 This is one of the cell structure diagrams of a super junction IGBT half-cell device proposed in the third embodiment;

[0054] Fig.14 This is the second cell structure diagram of a super junction IGBT half-cell device proposed in the third embodiment.

[0055] Figure numerals: 1. polysilicon gate; 2. gate oxide layer; 3. gate electrode; 4. first cathode region; 5. second cathode region; 6. base region; 7. first electrode; 8. carrier storage layer; 9. hole channel region; 10. N column region; 11. P column region; 12. buffer region; 13. collector region; 14. second electrode. DETAILED DESCRIPTION

[0056] The present invention is further described in detail below in conjunction with embodiments. The following embodiments are for explanation of the present invention but the present invention is not limited to the following embodiments.

[0057] Embodiment 1

[0058] like Figure 1As shown, a super junction IGBT half-cell structure includes an emitter structure, a gate structure and a collector structure. The emitter structure and the gate structure are arranged in contact with each other side by side, and a drift region structure is arranged between the emitter structure and the gate structure arranged in contact with each other side by side and the collector structure. The drift region structure is arranged in contact with a portion of the gate structure. A carrier storage layer 8 (also known as an N-cs region) is arranged between the drift region structure and the emitter structure, and the gate structure is arranged in contact with a portion of the carrier storage layer 8. A hole channel region 9 (also known as a P-ph region) is arranged between the gate structure, the drift region structure and the carrier storage layer 8. The carrier storage layer 8 is a low-doped N-type semiconductor, and the doping concentration range is set to 2×e 16 cm -3 ~6×e 16 cm -3 The hole channel region 9 is a low-doped P-type semiconductor, and the doping concentration range is set to 7×e 16 cm -3 ~5×e 17 cm -3 .

[0059] The emitter structure and the gate structure are arranged in contact side by side, which means that the emitter structure and the gate structure fit each other in the horizontal direction, the emitter structure and the gate structure are both located above the drift region structure, and the collector structure is located below the drift region structure.

[0060] In this embodiment, the emitter structure includes a first cathode region 4, a second cathode region 5, a base region 6 and a first electrode 7. The first cathode region 4 and the second cathode region 5 are both arranged on the base region 6, and the first cathode region 4 and the second cathode region 5 are arranged in contact with each other. The first electrode 7 is arranged on the first cathode region 4 and the second cathode region 5, and the first cathode region 4 and the second cathode region 5 are both arranged in partial contact with the first electrode 7.

[0061] The conductivity type of the first cathode region 4 and the base region 6 is the same as that of the hole channel region 9, both of which are P-type semiconductors, and the first cathode region 4 is a heavily doped P-type semiconductor, with a doping concentration range of 8×e 18 cm -3 ~2×e 19 cm -3 , the base region 6 is a low-doped P-type semiconductor, and the doping concentration range is set to 1×e 17 cm -3 ~3×e 17 cm -3 The second cathode region 5 and the carrier storage layer 8 are of the same conductivity type, that is, the second cathode region 5 is a heavily doped N-type semiconductor, and the doping concentration range is set to 8×e 18 cm -3 ~2×e 19 cm -3 .

[0062] The gate structure includes a polysilicon gate 1, a gate oxide layer 2 and a gate electrode 3. The polysilicon gate 1 is arranged on the gate oxide layer 2, and the gate electrode 3 is arranged on the polysilicon gate 1. Specifically, the gate electrode 3 is located on a portion of the upper surface of the polysilicon gate 1. The polysilicon gate 1 formed by depositing N-type doped polysilicon is located on the upper surface of the gate oxide layer 2, and the gate structure is arranged in contact with the emitter structure through the gate oxide layer 2, and the polysilicon gate 1 is not in contact with the emitter structure.

[0063] The drift region structure includes an N column region 10, a P column region 11 and a buffer region 12. The P column region 11 and the N column region 10 are both arranged on the buffer region 12, and the P column region 11 is arranged in contact with the N column region 10. The conductivity type of the N column region 10 and the buffer region 12 is the same as that of the carrier storage layer 8, and the N column region 10 and the buffer region 12 are both N-type low doping, and the doping concentration range of the N column region 10 is set to 1×e 15 cm -3 ~4×e 15 cm -3 , the doping concentration range of the buffer area 12 is set to 1×e 16 cm -3 ~5×e 16 cm -3 The P column region 11 and the hole channel region 9 have the same conductivity type, and the P column region 11 is P-type low doping, and the doping concentration range is set to 1×e 15 cm -3 ~4×e 15 cm -3 .

[0064] On the other hand, the carrier storage layer 8 is arranged on the lower surface of the base region 6 and is in contact with the N column region 10 of the drift region structure. The hole channel region 9 is arranged on the lower surface of the gate oxide layer 2 and is in contact with part of the gate oxide layer 2. The lower surface of the hole channel region 9 is also in contact with part of the N column region 10 and part of the P column region 11, respectively, and the side surface of the hole channel region 9 is also in contact with part of the carrier storage layer 8. In order to facilitate mutual depletion with the carrier storage layer 8 and the realization of the process, the thickness of the N column region 10 is greater than or equal to the thickness of the P column region 11, and the cross-section of the hole channel region 9 is stepped.

[0065] Among them, the stepped arrangement in this embodiment can be as follows Figure 1 The following figure shows only one step shape, which can also be set as follows Fig.11 As shown, it is arranged into a two-step stepped shape. In this embodiment, it is only used as an example. The staff can set the number of steps according to the actual situation, so as to alleviate the electric field concentration phenomenon through the multi-step stepped hole channel area 9 at the corner part of the gate.

[0066] At the same time, in order to make the gate turn-on voltage within the standard range, the side of the carrier storage layer 8 needs to be in contact with the gate oxide layer 2. Therefore, the gate oxide layer 2 is configured to contact the second cathode region 5 and the base region 6 carrier storage layer 8 from top to bottom, and the gate oxide layer 2 is in partial contact with the carrier storage layer 8.

[0067] The collector structure includes a collector region 13 and a second electrode 14. The second electrode 14 is disposed on the collector region 13. The collector region 13 has the same conductivity type as the hole channel region 9. The collector region 13 is a low-doped P-type semiconductor. The doping concentration range is set to 1×e 17 cm -3 ~1×e 18 cm -3 .

[0068] In this embodiment, the above-mentioned structural setting is adopted to introduce the hole channel region 9 and the carrier storage layer 8. When the device is turned off, the hole channel region 9 is used to form a hole channel between the P column region 11 and the base region 6, thereby increasing the speed of hole extraction and reducing the turn-off loss. When the device is forward-conducted, the space charge region generated by the positive voltage of the polysilicon gate 1 in the hole channel region 9 and the carrier storage layer 8 jointly hinder the movement of holes, thereby enhancing the conductivity modulation effect during forward conduction and reducing the forward conduction voltage drop.

[0069] More specifically, if Figure 2 As shown in (a), the polysilicon gate 1 forms a depletion region in the hole channel region 9 at its edge during the forward conduction stage, and together with the carrier storage layer 8, blocks holes from entering the base region 6, thereby increasing the conductivity modulation level and reducing the forward conduction voltage; Figure 2 As shown in (b), during forward blocking, the phenomenon of higher potential at the edge of the lower surface of the hole channel region 9 and the polysilicon gate 1 is alleviated. At the same time, the hole channel region 9 can deplete the carrier storage layer 8, so that the doping concentration of the carrier storage layer 8 is relatively high while maintaining a certain breakdown voltage. On the other hand, the hole channel region 9 located between the base region 6 and the P column region 11 will serve as a channel connecting the base region 6 and the P column region 11 when turned off, which accelerates the rapid extraction of holes, so that the electric field of the drift region structure can be quickly established, the turn-off time is reduced, and the turn-off loss is reduced. During forward blocking, the stepped trench design can alleviate the phenomenon of electric field concentration at the bottom of the traditional trench gate, so that the breakdown voltage is improved to a certain extent. The hole channel region 9 and the carrier storage region deplete each other, so that the carrier storage region can ensure a certain breakdown voltage at a higher doping concentration.

[0070] Furthermore, when the doping concentration of the hole channel region 9 is low, the effect of reducing the turn-off loss is not obvious, but when the doping concentration of the hole channel region 9 is too high, the breakdown voltage will be affected. Therefore, considering that the hole channel region 9 needs to balance the charge with the N column region 10 and the carrier storage layer 8 to obtain the optimal performance, the doping concentration of the hole channel region 9 is set to 1×e 17 cm -3 .

[0071] When the doping concentration of the carrier storage layer 8 is low, the effect of reducing the forward conduction voltage is not obvious, but when the doping concentration of the carrier storage layer 8 is too high, the breakdown voltage will be sharply reduced. Therefore, after setting the doping concentration of the hole channel region 9, the doping concentration of the carrier storage layer 8 is analyzed by pulling bias, and the following is obtained: Figure 3 As shown in the figure, it can be seen that with the increase of the doping concentration of the carrier storage layer 8, the breakdown voltage is 6×e 16 cm -3 With 7×e 16 cm -3 Therefore, the doping concentration of the carrier storage layer 8 is set to 6×e 16 cm -3 , that is, in one embodiment of the present invention, the doping concentration of the carrier storage layer 8 can be set to be lower than the doping concentration of the hole channel region 9.

[0072] In order to verify the performance superiority of the novel super junction IGBT half-cell structure proposed in this embodiment, this embodiment takes a 1200V super junction IGBT as an example to compare the performance between the novel super junction IGBT half-cell structure proposed in this embodiment and the traditional super junction IGBT.

[0073] like Figure 4 As shown in the figure, it can be seen that the blocking voltage of the new super junction IGBT half-cell structure proposed in this embodiment is similar to that of the traditional super junction IGBT, that is, the new super junction IGBT half-cell structure proposed in this embodiment does not cause the blocking performance to degrade. On the contrary, compared with the traditional super junction IGBT, the new super junction IGBT half-cell structure proposed in this embodiment alleviates the phenomenon of electric field concentration at the bottom of the trench gate, and the blocking voltage is increased by about 70V.

[0074] like Figure 5 As shown in the figure, at 100A / cm 2 At an on-state current density of , the on-state voltage drop of the novel super junction IGBT half-cell structure proposed in this embodiment is 1.285V, which is slightly lower than 1.315V of the conventional super junction IGBT.

[0075] like Figure 6As shown in FIG. 1 , a circuit diagram for simulating a dynamic switch test is shown. In this circuit, the novel super junction IGBT half-cell structure proposed in this embodiment and a conventional super junction IGBT device are used for testing, and the following results are obtained: Figure 7 The shutdown waveform comparison diagram shown in the figure and Figure 8 The dV / dt waveform comparison diagram at turn-off is shown in the figure. 2% V is used to calculate the turn-off loss. CE to 1%I CE The turn-off loss of the new super junction IGBT half-cell structure proposed in this embodiment is 2.05mJ / cm 2 , compared to 3.078mJ / cm of conventional super junction IGBT 2 , a decrease of 33.4%.

[0076] Depend on Figure 8 It can be seen that the dV / dt of the novel super junction IGBT half-cell structure proposed in this embodiment is greater than that of the traditional super junction IGBT, so the electric field can be quickly established when turned off, thereby reducing the turn-off time and the turn-off loss.

[0077] like Fig. 9 As shown in FIG. 1 , under the same forward conduction voltage, compared with the traditional super junction IGBT, the turn-off loss E of the new super junction IGBT half-cell structure proposed in this embodiment is off The V ON -E OFF Trade-off curve.

[0078] like Fig.10 As shown in FIG. 1 , under the same turn-off loss, compared with the traditional super junction IGBT, the peak voltage V of the new super junction IGBT half-cell structure proposed in this embodiment is peak The V peak -E OFF Trade-off curve.

[0079] Through the above comparison of the key parameters of the static and dynamic characteristics of the device, the results show that compared with the traditional super junction IGBT half-cell structure, the new super junction IGBT half-cell structure proposed in this embodiment has the advantages of lower forward conduction voltage drop, smaller turn-off loss and alleviated electric field concentration phenomenon in the gate trench.

[0080] Embodiment 2

[0081] like Fig.12As shown, the difference between this embodiment and embodiment one is that the cross-section of the hole channel region 9 of this embodiment is set to a convex polygon, wherein the convex polygon includes but is not limited to a quadrilateral, a pentagon, and a hexagon. In this embodiment, a quadrilateral is taken as an example. At this time, the hole channel region 9 formed is in the shape of an inclined ladder, connecting the carrier storage layer 8, the gate oxide layer 2, the N column region 10 and the P column region 11.

[0082] At this time, since the gate corner is a convex polygon, the phenomenon of electric field concentration here is alleviated, and the quadrilateral inclined ladder-shaped cross-section setting of the hole channel region 9 enables holes to be more quickly drawn away by the hole channel region 9 when the device is turned off, further reducing the turn-off loss.

[0083] Embodiment 3

[0084] A super junction IGBT device includes a half-cell structure formed by the super junction IGBT half-cell structure as described in any one of the first embodiment or the second embodiment.

[0085] Specifically, Fig.13 As shown, the super junction IGBT device of this embodiment includes a symmetrically arranged super junction IGBT half-cell structure, where two groups of emitter structures are symmetrically arranged on both sides of the gate structure, the gate structure is "T"-shaped, the drift region structure is arranged below the emitter structure and the gate structure, the collector structure is arranged below the drift region structure, and a hole channel region 9 and a carrier storage layer 8 are arranged at the corners on both sides of the gate structure, so that when the device is turned off, the holes in the P column region 11 are quickly drawn away through the hole channel regions 9 on both sides, thereby effectively reducing the turn-off loss of the device.

[0086] On the other hand, Fig.14 As shown, the super junction IGBT device of this embodiment may also include only one group of super junction IGBT half-cell structures as described in Example 1. At this time, the complete cell structure of the super junction IGBT device is a half-cell formed by the super junction IGBT half-cell structure described in Example 1 on the left side, and a traditional half-cell structure on the right side. At this time, a hole channel region 9 is set at the left corner of the gate structure, while the hole channel region 9 is not set at the right corner of the gate structure, and is directly contacted with the N column region 10 and the base region 6.

[0087] At this time, since there is a hole channel region 9 only on one side of the device, the difficulty of process manufacturing is reduced to a certain extent; at the same time, when the device is turned off, the holes in the P column region 11 are mainly extracted by the hole channel region 9 on one side, so that the turn-off time and turn-off loss are improved compared to when the hole channel region 9 is provided on both sides.

[0088] Embodiment 4

[0089] A method for preparing a super junction IGBT half-cell structure is provided. The method is used to prepare the super junction IGBT half-cell structure as described in the first or second embodiment. This embodiment takes a super junction IGBT half-cell structure with a withstand voltage of 1500V as an example to illustrate the preparation method.

[0090] The specific preparation method is as follows:

[0091] S1, select silicon as a substrate, the substrate includes a collector region 13 and a buffer region 12, perform epitaxy on the substrate and inject N-type impurities to form an N column region 10;

[0092] S2, setting a mask for etching on the upper surface of the N column region 10, performing etching to form a column region trench, and depositing P-type doped silicon in the trench to form a P column region 11;

[0093] S3, setting a mask for etching on the upper surface of the P column region 11, etching to form a portion of the gate trench, setting a mask for etching on the upper surface of a portion of the N column region 10, etching to form another portion of the gate trench, and the two together constitute the gate trench;

[0094] S4, forming a mask on the upper surface of a portion of the N column region 10 and the P column region 11, and performing ion implantation and high-temperature diffusion to form a carrier storage layer 8;

[0095] S5, forming a mask on the upper surface of part of the N column region 10 and part of the P column region 11, and performing ion implantation and high-temperature diffusion to form a hole channel region 9;

[0096] S6, growing a gate oxide layer 2 with a thickness of 0.1 um on the surface of the gate trench, and depositing polysilicon on the surface of the gate oxide layer 2 to form a polysilicon gate 1;

[0097] S7, performing ion implantation and high temperature diffusion on the upper surface of the carrier storage layer 8 to form a base region 6;

[0098] S8, forming a mask on the upper surface of the base region 6 to perform ion implantation and high-temperature diffusion to form a first cathode region 4;

[0099] S9, forming a mask on the upper surface of the base region 6 to perform ion implantation and high-temperature diffusion to form a second cathode region 5;

[0100] S10, N-type impurities are implanted into the lower surfaces of the N column region 10 and the P column region 11 to form an N-buffer region 12;

[0101] S11, implanting P-type impurities into the lower surface of the N-buffer region 12 to form a P-collector region 13;

[0102] S12, depositing metal on the lower surface of the P-collector region 13 to form a second electrode 14;

[0103] S13, depositing metal on a portion of the upper surface of the first cathode region 4 and the second cathode region 5 to form a first electrode 7;

[0104] S14 , depositing metal on a portion of the upper surface of the polysilicon gate 1 to form a gate electrode 3 .

[0105] The above is only a preferred embodiment of the present invention, and is not any formal or substantial limitation of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and supplements without departing from the method of the present invention, and these improvements and supplements should also be regarded as the protection scope of the present invention. Any technician familiar with this profession, without departing from the spirit and scope of the present invention, can make some changes, modifications and evolutions of the technical content disclosed above, which are equivalent embodiments of the present invention; at the same time, any changes, modifications and evolutions of any equivalent changes made to the above embodiments based on the essential technology of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A super junction IGBT half-cell structure, characterized in that: The present invention comprises an emitter structure, a gate structure and a collector structure, wherein the emitter structure and the gate structure are arranged in contact with each other side by side, and a drift region structure is arranged between the emitter structure and the gate structure arranged in contact with each other side by side, and the drift region structure is arranged in contact with a portion of the gate structure, a carrier storage layer is arranged between the drift region structure and the emitter structure, and the gate structure is arranged in contact with a portion of the carrier storage layer, a hole channel region is arranged between the gate structure, the drift region structure and the carrier storage layer, and the hole channel region is located at a corner portion of the gate structure, the doping concentration of the carrier storage layer is lower than the doping concentration of the hole channel region, the carrier storage layer and the hole channel region are semiconductors of opposite conductivity types, and the doping concentration of the carrier storage layer is 2×e 16 cm -3 ~6×e 16 cm -3 ; The doping concentration of the hole channel region is 7×e 16 cm -3 ~5×e 17 cm -3 .

2. A super junction IGBT half-cell structure according to claim 1, characterized in that: Furthermore, the cross section of the hole channel region is in a stepped or convex polygonal shape, forming a stepped or convex polygonal groove.

3. A super junction IGBT half-cell structure according to claim 2, characterized in that: The convex polygonal shape is an oblique ladder shape.

4. The super junction IGBT half-cell structure according to claim 1, characterized in that: The carrier storage layer is a low-doped N-type semiconductor, and the hole channel region is a low-doped P-type semiconductor.

5. The super junction IGBT half-cell structure according to claim 1, characterized in that: The gate structure comprises a polysilicon gate, a gate oxide layer and a gate electrode. The polysilicon gate is arranged on the gate oxide layer, and the gate electrode is arranged on the polysilicon gate.

6. A super junction IGBT half-cell structure according to claim 5, characterized in that: The emitter structure includes a first cathode region, a second cathode region, a base region and a first electrode, the first cathode region and the second cathode region are both arranged on the base region, and the first cathode region and the second cathode region are arranged in contact with each other, the first electrode is arranged on the first cathode region and the second cathode region, and the first cathode region and the second cathode region are both arranged in contact with part of the first electrode, the conductivity type of the first cathode region and the base region is the same as the conductivity type of the hole channel region, and the second cathode region and the carrier storage layer are the same conductivity type.

7. A super junction IGBT half-cell structure according to claim 6, characterized in that: The drift region structure includes an N column region, a P column region and a buffer region. The P column region and the N column region are both arranged on the buffer region, and the P column region is arranged in contact with the N column region. The conductivity type of the N column region and the buffer region is the same as that of the carrier storage layer, and the P column region and the hole channel region are the same conductivity type.

8. The super junction IGBT half-cell structure according to claim 7, characterized in that: When the device is turned off, the hole channel region forms a hole channel between the P column region and the base region.

9. The super junction IGBT half-cell structure according to claim 7, characterized in that: The hole channel region is arranged on the lower surface of the gate oxide layer and is in partial contact with the gate oxide layer. The lower surface of the hole channel is also in contact with part of the N column region and part of the P column region respectively, and the side wall of the hole channel region is also in contact with part of the carrier storage layer.

10. The super junction IGBT half-cell structure according to claim 7, characterized in that: The carrier storage layer is arranged on the lower surface of the base region and is arranged in contact with the N column region, and a part of the side wall of the carrier storage layer is arranged in contact with the hole channel region.

11. The super junction IGBT half-cell structure according to claim 7, characterized in that: The thickness of the N column region is greater than or equal to the thickness of the P column region.

12. The super junction IGBT half-cell structure according to claim 1, characterized in that: The collector structure includes a collector region and a second electrode, wherein the second electrode is arranged on the collector region, and the collector region and the hole channel region have the same conductivity type.

13. A super junction IGBT device, characterized in that: The super junction IGBT device includes more than one group of super junction IGBT cell structures, and the super junction IGBT cell structure includes the super junction IGBT half cell structure according to any one of claims 1 to 12.

14. A super junction IGBT device according to claim 13, characterized in that: A group of the super junction IGBT cell structures described above includes symmetrically arranged super junction IGBT half cell structures.

15. The super junction IGBT device according to claim 13, characterized in that: One or more super junction IGBT cell structures include a super junction IGBT half cell structure and a traditional half cell structure. The super junction IGBT half cell structure and the traditional half cell structure are arranged side by side in contact with each other. No hole channel region is arranged at the corner of the gate structure of the traditional half cell structure. The gate structure of the traditional half cell structure is directly arranged in contact with the N column region and the base region.

16. A method for preparing a super junction IGBT half-cell structure, characterized in that: The preparation method is used to prepare the super junction IGBT half-cell structure according to any one of claims 1 to 12, and specifically comprises the following steps: S1, selecting silicon as a substrate, the substrate including a collector region and a buffer region, performing epitaxy on the substrate and injecting N-type impurities to form an N column region; S2, setting a mask for etching on the upper surface of the N column region, performing etching to form a column region trench, and depositing P-type doped silicon in the trench to form a P column region; S3, setting a mask for etching on the upper surface of the P column region, etching to form a portion of the gate trench, setting a mask for etching on the upper surface of a portion of the N column region, etching to form another portion of the gate trench, and the two together constitute the gate trench; S4, forming a mask on the upper surface of a portion of the N column region and the P column region, and performing ion implantation and high-temperature diffusion to form a carrier storage layer; S5, forming a mask on the upper surface of part of the N column region and part of the P column region, and performing ion implantation and high-temperature diffusion to form a hole channel region; S6, growing a 0.1 um gate oxide layer on the surface of the gate trench, and depositing polysilicon on the surface of the gate oxide layer to form a polysilicon gate; S7, performing ion implantation and high-temperature diffusion on the upper surface of the carrier storage layer to form a base region; S8, forming a mask on the upper surface of the base region to perform ion implantation and high-temperature diffusion to form a first cathode region; S9, forming a mask on the upper surface of the base region to perform ion implantation and high-temperature diffusion to form a second cathode region; S10, injecting N-type impurities into the lower surfaces of the N column region and the P column region to form an N-buffer region; S11, injecting P-type impurities into the lower surface of the N-buffer region to form a P-collector region; S12, depositing metal on the lower surface of the P-collector region to form a second electrode; S13, depositing metal on a portion of the upper surface of the first cathode region and the second cathode region to form a first electrode; S14, depositing metal on a portion of the upper surface of the polysilicon gate to form a gate electrode.

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