Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a plurality of shift register units connected in cascade. In each display frame of the display panel, the reset clock signal and the output control signal each comprise a plurality of effective pulses. The working mode of the display panel comprises a first mode. The first mode comprises at least one first display frame, and the driving circuit comprises a first shift register unit. In the first display frame, at least part of the output control signal received by the first shift register unit is a first type of output control signal. In the first shift register unit, the interval time of two adjacent effective pulses of the first type of output control signal is a first interval time, and the interval time of two adjacent effective pulses of the reset clock signal is a second interval time. The first interval time and the second interval time overlap, and the first interval time is greater than the second interval time. Thus, the display quality of the display panel is ensured, and the power consumption of the display panel is reduced.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Display panels typically have multiple pixels arranged in an array. By using a shift register to scan each pixel line by line, data signals can be written into each pixel line by line, so that each pixel can display and emit light according to the data signals it receives, thereby presenting the corresponding display image.

[0003] When displaying images on a display panel, a higher refresh rate results in a shorter pixel scan cycle, leading to higher power consumption. Reducing the refresh rate can effectively lower the power consumption of the display panel. However, a lower refresh rate can affect the display quality of certain images, such as videos and games. Therefore, how to reduce the power consumption of the display panel without affecting the display quality has become a pressing technical problem. Summary of the Invention

[0004] This invention provides a display panel and a display device that can simplify the circuit design of the display panel and reduce the power consumption of the display panel while ensuring the display quality of the displayed image.

[0005] According to one aspect of the present invention, a display panel is provided, comprising: a driving circuit; the driving circuit comprising a plurality of cascaded shift register units;

[0006] The shift register unit includes an input module, a reset module, a node inter-control module, and N output modules; N is a positive integer. Within the same shift register unit: the input module receives at least an input signal and a scan control signal to control the signal of the first node; the reset module receives at least a reset clock signal and the scan control signal to control the signal of the second node; the node inter-control module receives at least the signal of the first node and the signal of the second node, controls the signal of the second node based on the signal of the first node, and controls the signal of the first node based on the signal of the second node; the output modules receive at least the signal of the first node, the signal of the second node, a first level signal, and an output control signal to control the gate drive signal.

[0007] Wherein, at least one of the gate drive signals of the i-th stage shift register unit is the input signal of the j-th stage shift register unit; i ≠ j, and i and j are both positive integers;

[0008] Within each display frame of the display panel, both the reset clock signal and the output control signal include multiple valid pulses;

[0009] The operating mode of the display panel includes a first mode; the first mode includes at least one first display frame, and the driving circuit includes a first shift register unit; in the first display frame, at least a portion of the output control signals received by the first shift register unit are first type output control signals; in the first shift register unit, the interval between two adjacent valid pulses of the first type output control signals is a first interval time, and the interval between two adjacent valid pulses of the reset clock signal is a second interval time; the first interval time overlaps with the second interval time, and the first interval time is greater than the second interval time.

[0010] According to another aspect of the present invention, a display device is provided, comprising the display panel described above.

[0011] The technical solution of this invention, when the display panel is in a first working mode, ensures that at least one first shift register exists in the driving circuit. In the first display frame of this first working mode, by setting the interval between two adjacent valid pulses in the output control signal of the first shift register as a first interval, and the time interval between two adjacent valid pulses in the reset clock signal overlapping with the first interval as a second interval, and setting the first interval to be greater than the second interval, the valid pulse time of the reset clock signal precedes the valid pulse time of the output control signal. This allows the signal of the first node to be reset to an invalid level before the valid pulse of the output control signal received by the first shift register unit. Consequently, the signal of the first node cannot control the output module to output the valid pulse of the output control signal as a gate drive signal. Therefore, in the first display frame of the first mode, the gate drive signal output by the output module of the first shift register unit remains at an invalid level or a first level signal of the output control signal, and the first shift register unit... The gate drive signal output by the cascaded shift register unit after the bit register unit remains at an invalid level or a first level signal, which prevents the pixel circuit electrically connected to this part of the shift register from refreshing the screen and thus prevents the corresponding nodes in the pixel circuit from charging and discharging, effectively reducing the power consumption of the display panel. At the same time, the display panel is usually driven by a driver chip. In this case, the driver chip can determine the first shift register unit in the driver circuit and the time interval between the reset clock signal and the output control signal provided to the first shift register unit according to the display requirements of the display panel. Therefore, it is not necessary to change the cascaded method of the shift registers in the driver circuit or the structure of each shift register. Only by adjusting the effective pulse interval time of the reset clock signal and / or the output control signal according to the display requirements of the display panel, the signal refresh frequency of the sub-pixels electrically connected to at least some shift registers can be realized. Without increasing the complexity of the driver circuit, the design of the display panel is simplified, which is beneficial to the narrow bezel design of the display panel.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of the structure of a shift register unit provided in an embodiment of the present invention;

[0016] Figure 3 This is a timing diagram of the driving circuit provided in an embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0019] Figure 6 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0020] Figure 7 This is a driving timing diagram of another shift register unit provided in an embodiment of the present invention;

[0021] Figure 8 This is a timing diagram of another shift register unit provided in an embodiment of the present invention;

[0022] Figure 9 This is a driving timing diagram of another shift register unit provided in an embodiment of the present invention;

[0023] Figure 10 This is a driving timing diagram of another shift register unit provided in an embodiment of the present invention;

[0024] Figure 11 This is a schematic diagram of a driving circuit provided in an embodiment of the present invention;

[0025] Figure 12 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0026] Figure 13 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0027] Figure 14 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0028] Figure 15 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0029] Figure 16 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0030] Figure 17 This is a driving timing diagram of another shift register unit provided in an embodiment of the present invention;

[0031] Figure 18 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention;

[0032] Figure 19 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0033] Figure 20 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0034] Figure 21 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention;

[0035] Figure 22 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0036] Figure 23 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0038] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0039] As described in the background section, dynamic images requiring high display quality necessitate a higher refresh rate for the display panel. Conversely, static images with lower display quality requirements can have a lower refresh rate to reduce power consumption. Currently, different refresh rates for different display areas of a display panel are typically achieved by adding shift register units or modifying their circuitry. This requires the addition of corresponding clock and control signals, complicating the driver circuit design and hindering narrow bezel designs.

[0040] To address the aforementioned technical problems, embodiments of the present invention provide a display panel, comprising: a driving circuit; the driving circuit includes multiple cascaded shift register units; each shift register unit includes an input module, a reset module, a node inter-control module, and N output modules; N is a positive integer; within the same shift register unit: the input module is used to receive at least an input signal and a scan control signal, and control the signal of a first node; the reset module is used to receive at least a reset clock signal and a scan control signal, and control the signal of a second node; the node inter-control module is used to receive at least the signals of the first node and the second node, and control the signal of the second node according to the signal of the first node, and control the signal of the first node according to the signal of the second node; the output module is used to receive at least the signal of the first node, the signal of the second node, a first level signal, and an output control signal, and control the gate drive. Signal; wherein, at least one gate drive signal of the i-th level shift register unit is the input signal of the j-th level shift register unit; i ≠ j, and i and j are both positive integers; within each display frame of the display panel, the reset clock signal and the output control signal each include multiple valid pulses; the operating mode of the display panel includes a first mode; the first mode includes at least one first display frame, and the driving circuit includes a first shift register unit; in the first display frame, at least a portion of the output control signals received by the first shift register unit are first type output control signals; in the first shift register unit, the interval between two adjacent valid pulses of the first type output control signal is a first interval time, and the interval between two adjacent valid pulses of the reset clock signal is a second interval time; the first interval time and the second interval time overlap, and the first interval time is greater than the second interval time.

[0041] By adopting the above technical solution, when the display panel is in the first working mode, at least one first shift register is present in the driving circuit. In the first display frame of the first working mode, the time interval between two adjacent valid pulses in the output control signal of the first shift register is set as the first interval time, and the time interval between two adjacent valid pulses in the reset clock signal that overlap with the first interval time is set as the second interval time. Furthermore, the first interval time is set to be greater than the second interval time, so that the valid pulse time of the reset clock signal is before the valid pulse time of the output control signal. This allows the signal of the first node to be reset to an invalid level before the valid pulse of the output control signal received by the first shift register unit. Consequently, the signal of the first node cannot control the output module to output the valid pulse of the output control signal as the gate drive signal. Therefore, in the first display frame of the first mode, the gate drive signal output by the output module of the first shift register unit remains at an invalid level or a first level signal of the output control signal, and the first shift register... The gate drive signal output by the cascaded shift register unit after the register unit remains at an invalid level or a first level signal, which prevents the pixel circuit electrically connected to this part of the shift register from refreshing the screen and thus prevents the corresponding nodes in the pixel circuit from charging and discharging, effectively reducing the power consumption of the display panel. At the same time, the display panel is usually driven by a driver chip. In this case, the driver chip can determine the first shift register unit in the driver circuit and the time interval between the reset clock signal and the output control signal provided to the first shift register unit according to the display requirements of the display panel. Therefore, it is not necessary to change the cascaded method of the shift registers in the driver circuit or the structure of each shift register. Only by adjusting the effective pulse interval time of the reset clock signal and / or the output control signal according to the display requirements of the display panel, the signal refresh frequency of the sub-pixels electrically connected to at least some shift registers can be realized. Without increasing the complexity of the driver circuit, the design of the display panel is simplified, which is beneficial to the narrow bezel design of the display panel.

[0042] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of a shift register unit provided in an embodiment of the present invention. Figure 3 This is a driving timing diagram of the driving circuit provided in an embodiment of the present invention, in conjunction with reference to... Figure 1 , Figure 2 and Figure 3The display panel 100 includes: a driving circuit 10; the driving circuit 10 includes multiple cascaded shift register units G; each shift register unit G includes an input module 110, a reset module 120, a node inter-control module 130, and N output modules 140; N is a positive integer; in the same shift register unit G: the input module 110 is used to receive at least the input signal inf and the scan control signal (fw and bw) to control the signal of the first node N1; the reset module 120 is used to receive at least the reset clock signal (rstf and rstb) and the scan control signal (fw and bw) to control the signal of the second node N2; the node inter-control module 130 is used to receive at least the signal of the first node N1 and the signal of the second node N2, and to control the signal of the second node N2 according to the signal of the first node N1, and to control the signal of the first node N1 according to the signal of the second node N2; the output module 140 is used to receive at least the signal of the first node N1, the signal of the second node N2, the first level signal vgl, and the output control signal out to control the gate drive signal gou. t; where at least one gate drive signal gout of the i-th level shift register unit Gi is the input signal inf of the j-th level shift register unit Gj; i ≠ j, and i and j are both positive integers; in each display frame of the display panel 100, the reset clock signal rstf and the output control signal out both include multiple valid pulses; the operating mode of the display panel 100 includes a first mode Mode1; the first mode Mode1 includes at least one first display frame T1, and the driving circuit 10 includes a first shift register unit 11; in the first display frame T1, at least a portion of the output control signal out received by the first shift register unit 11 is a first type of output control signal out′; in the first shift register unit 11, the interval between two adjacent valid pulses of the first type of output control signal out′ is the first interval time t1, and the interval between two adjacent valid pulses of the reset clock signal rstf is the second interval time t2; the first interval time t1 and the second interval time t2 overlap, and the first interval time t1 is greater than the second interval time t2.

[0043] It should be noted that the above description is only exemplified by the example of the driving circuit 10 being located in the non-display area A1 and the pixel circuit 20 being located in the display area A2. In other embodiments of the present invention, the pixel circuit 20 and the driving circuit 10 may both be located in the display area A2, so that the number of devices set in the non-display area A1 of the display panel 100 is sufficiently small, thereby reducing the size of the non-display area A1 of the display panel 100. This is beneficial for the narrow bezel of the display panel 100 and gives the display panel 100 a high screen ratio.

[0044] For ease of description, unless otherwise specified, the embodiments of the present invention will be described exemplarily with the driving circuit 10 located in the non-display area A1 of the display panel 100 and the pixel circuit 20 located in the display area A2 of the display panel 100.

[0045] Each shift register unit G may include one output module 140 or multiple output modules 140. The number of output modules 140 in each shift register unit G may be the same or different. The following embodiments first take each shift register unit G as including one output module 140 as an example to illustrate the technical solution of the present invention. Unless otherwise specified, the number of output modules 140 in each shift register unit G in the present invention is the same.

[0046] The gate drive signal gouti of the i-th stage shift register unit Gi is the input signal (inf or inb) of the j-th stage shift register unit Gj. Thus, the gate drive signal gouti of the i-th stage shift register unit Gi can control the operation of the j-th stage shift register unit Gj, thereby controlling the gate drive signal goutj of the j-th stage shift register unit Gj.

[0047] When the shift register unit G includes an output module 140, that is, when N equals 1, the i-th level shift register unit Gi and the j-th level shift register unit Gj can be set to be two adjacent levels of shift register units G, respectively connected to two adjacent rows of pixel circuits 20. In this case, when the screen refresh rate of each display area in the display panel 100 is the same, each level of shift register unit G can output a gate drive signal gout that is shifted sequentially by valid pulses, thereby realizing the line-by-line scanning of the pixel circuit 20. In other feasible embodiments, the i-th level shift register unit Gi and the j-th level shift register unit Gj can also be set to be two non-adjacent shift register units. Unless otherwise specified, the present invention preferably sets the i-th level shift register unit Gi and the j-th level shift register unit Gj to be two adjacent levels of shift register units, respectively connected to two adjacent rows of pixel circuits 20.

[0048] The shift register unit G may include two input terminals (INF and inb) for receiving input signals inf and inb, respectively. Each shift register unit G may also include two scan control terminals (FW and BW) for receiving scan control signals fw and bw, respectively. Each shift register unit G may also include two reset clock signal terminals (RSTF and RSTB) for receiving reset clock signals rstf and rstb, respectively. When the driving circuit 10 is in the forward scanning phase, the scan control signal fw can be set to an active level and the scan control signal bw can be set to an inactive level. Then, each shift register unit G responds at least to the input signal inf, the scan control signal fw, and the reset clock signal rstf, causing the active pulses of the gate drive signal gout output by each shift register unit G to be shifted sequentially in the forward direction (e.g., from top to bottom), thus achieving line-by-line scanning of the pixel circuit 20 from top to bottom. When the driving circuit 10 is in the reverse scanning phase, the scan control signal fw can be set to an inactive level and the scan control signal bw can be set to an active level. Then, each shift register unit G responds at least to the input signal inb, the scan control signal bw, and the reset clock signal rstb, causing the active pulses of the gate drive signal gout output by each shift register unit G to be shifted sequentially in the reverse direction (e.g., from bottom to top), thus achieving line-by-line scanning of the pixel circuit 20 from bottom to top. Active pulses include active levels, and inactive pulses include inactive levels.

[0049] Understandably, the input terminal INF of the first-stage shift register unit G1 and the input terminal INB of the Nth-stage shift register unit Gn are both electrically connected to the start signal output terminal STV of the start control circuit (not shown in the figure) used to provide the start signal stf. During the forward scan phase, the start control circuit (not shown in the figure) can provide the first-stage shift register unit G1 with a start signal stv including a valid pulse. This start signal stv serves as the input signal inf of the first-stage shift register unit G1, causing the first-stage shift register unit G1 to output the first-stage gate drive signal gout1 in response to at least the start signal stv and the scan control signal fw. During the reverse scan phase, the start control circuit (not shown in the figure) can provide the Nth-stage shift register unit Gn with a start signal stv including a valid pulse. This start signal stv serves as the input signal inb of the Nth-stage shift register unit Gn, causing the Nth-stage shift register unit Gn to output the Nth-stage gate drive signal goutn in response to at least the start signal stv and the scan control signal bw. For other shift register units G, the input terminal INF of the i-th stage shift register unit Gi is electrically connected to the gate drive signal output terminal GOUT of the (i-1)-th stage shift register unit Gi-1, and the input terminal inb of the i-th stage shift register unit Gi is electrically connected to the gate drive signal output terminal GOUT of the (i+1)-th stage shift register unit Gi+1. That is, the input signal inf of the i-th stage shift register unit Gi is the gate drive signal gouti-1 of the (i-1)-th stage shift register unit Gi-1, and the input signal inb of the i-th stage shift register unit Gi is the gate drive signal gouti+1 of the (i+1)-th stage shift register unit Gi+1. For ease of description, the following embodiments use the forward scanning stage of the driving circuit 20 as an example to illustrate the technical solution of the present invention.

[0050] In the same shift register unit G, input module 110 and node control module 130 are electrically connected to the first node N1, node control module 130 and reset module 120 are electrically connected to the second node N2, and output module 140 is electrically connected to both the first node N1 and the second node. Input module 110 can provide corresponding signals to the first node N1 based on the received input signal inf and scan control signal fw. For example, when the input signal inf is at an active level, input module 110 can control the first node N1 to be at an active level based on the received input signal inf and scan control signal fw.

[0051] The reset module 120 can provide corresponding signals to the second node N2 based on the received reset clock signal rstf and scan control signal fw. For example, when the reset clock signal rstf is active, the reset module 120 can control the second node N2 to be active based on the reset clock signal rstf and scan control signal fw; when the reset clock signal rstf is inactive, the reset module 120 can control the second node N2 to be inactive based on the reset clock signal rstf and scan control signal fw.

[0052] Correspondingly, within the same shift register unit G, the node inter-control module 130 can control the signal of the second node N2 based on the signal received from the first node N1, and control the signal of the first node N1 based on the signal received from the second node N2. For example, when the signal of the first node N1 is at an active level, the node inter-control module 130 can control the signal of the second node N2 to be at an inactive level, and when the signal of the second node N2 is at an active level, the node inter-control module 130 can control the signal of the first node N1 to be at an inactive level.

[0053] The output module 140 can receive at least the signal from the first node N1, the signal from the second node N2, the first level signal vgl, and the output control signal out, and control the gate drive signal gout. For example, when the signal from the first node N1 is at an active level, the output module 140 can output the output control signal out to the corresponding pixel circuit 20, using the output control signal out as the gate drive signal gout; while when the signal from the second node N2 is at an active level, the output module 140 can output the first level signal vgl to the corresponding pixel circuit 20, using the first level signal vgl as the gate drive signal gout.

[0054] In this embodiment of the invention, it is preferable to set the first level signal vgl to an invalid level. When the first node N1 is at an valid level, the output module 140 outputs the output control signal out as the gate drive signal gout. For the output gate drive signal gout to be a valid pulse, the output control signal out must be included in the valid level for at least the duration the signal at the first node N1 remains at an valid level. After the signal at the first node N1 is reset to an invalid level, the output module 140 cannot output the output control signal out as the gate drive signal gout. Therefore, when the signal at the first node N1 needs to be reset, the reset clock signal rstf can be set to an valid level. This allows the reset module 120 to control the signal at the second node N2 to be at a valid level based on the valid levels of the scan control signal fw and the reset clock signal rstf. Consequently, the node inter-control module 130 controls the signal at the first node N1 to be at an invalid level based on the signal at the second node N2. In other words, the valid pulse of the reset clock signal rstf needs to be after the valid pulse of the output control signal out to ensure that the output module 140 outputs the valid level of the gate drive signal gout.

[0055] Among them, the reset clock signal rstf, output control signal out, scan control signal fw, and gate drive signal gout can all be pulse signals composed of high and low levels, with one of the high and low levels being the active level and the other the inactive level. (Reference) Figure 3 Within a display frame of the display panel, each shift register unit G sequentially outputs the effective level of the gate drive signal gout. During this stage, both the reset clock signal rstf and the output control signal out include multiple effective pulses, so that each shift register unit G can output the corresponding gate drive signal gout according to the transition of the reset clock signal rstf and the output control signal out after receiving the effective level of the input signal inf.

[0056] Accordingly, the display panel 100 may include a first operating mode, Mode 1. In the first operating mode, the display panel 100 may have two sub-display areas with different refresh rates, such as a first sub-display area A21 with a higher refresh rate and a second sub-display area A22 with a lower refresh rate, meaning that the gate drive signals gout output by at least some of the shift register units G in the driving circuit 10 have different frequencies. The first operating mode, Mode 1, includes at least one first display frame, T1. In the first display frame, T1 may refresh only the signals of the pixel circuits in the first sub-display area A21 with the higher refresh rate, while the signals of the pixel circuits in the second sub-display area A22 with the lower refresh rate remain unchanged.

[0057] For example, the display panel 100 includes a display area A2; the display area A2 is provided with multiple gate drive lines SCAN; each shift register unit G is electrically connected to each gate drive line SCAN respectively; in the first mode Mode1, the display area A2 includes a first sub-display area A21 and a second sub-display area A22; in the first display frame T1, the gate drive line SCAN located in the first sub-display area A21 is the first gate drive line SCAN1, and the gate drive line SCAN located in the second sub-display area A22 is the second gate drive line SCAN2; the effective pulse time of the gate drive signal gout transmitted by the first gate drive line SCAN1 is shifted sequentially, and the gate drive signal gout transmitted by the second gate drive line SCAN2 is at an invalid level.

[0058] In the driving circuit 10, each level of shift register unit G can be electrically connected to each gate driving line SCAN. Each level of shift register unit G electrically connected to each second gate driving line SCAN2 located in the second display area A2 can be a first shift register unit 11. Alternatively, the shift register unit G electrically connected to the second gate driving line SCAN2 located in the second display area A22 and closest to the first display area A21 can be a first shift register unit 11. The figure exemplarily shows the sixth level shift register unit G6 as a first shift register unit 11. For a first shift register unit 11 including one output module 140, the output control signal out it receives is a first type of output control signal out′; for a first shift register unit 11 including multiple output modules 140, each output module 140 receives one corresponding output control signal out, that is, the first shift register unit 11 needs to receive multiple output control signals. At this time, at least some of the output control signals received by the first shift register unit 11 are first type of output control signals out′. That is, taking the first shift register unit 11 including two output modules 140 as an example, one of the two output control signals received by the first shift register unit 11 is a first type of output control signal or both are first type of output control signals. It can be set according to actual needs. This embodiment of the invention does not make specific limitations in this regard.

[0059] Taking the shift register unit G electrically connected to the second gate drive line SCAN2, which is located in the second display area A22 and is closest to the first display area A21, as the first shift register unit 11, and the first shift register unit 11 including an output module 140 as an example. In the first display frame T1, the first type of output control signal out′ received by the first shift register unit 11 contains two adjacent valid pulses with an interval of the first interval time t1, and the reset clock signal rstf received by the first shift register unit 11 contains two adjacent valid pulses with an interval of the second interval time t2. The first interval time t1 can overlap with the second interval time t2. At this time, in order to keep the signals of each pixel circuit in the second sub-display area A22 unchanged, the first interval time t1 can be set to be greater than the second interval time t2. Thus, in the first shift register unit, the second interval time t2 is relatively short, and the reset clock signal rstf can become an effective pulse before the effective pulse of the first type of output control signal out′. This allows the reset module 120 to first control the second node N2 to an effective level based on the effective pulse of the reset clock signal rstf and the scan control signal fw. Consequently, the node control module 120 controls the first node N1 to an ineffective level, that is, the first node N1 jumps to an ineffective level before the effective pulse of the first type of output control signal out′. When the first type of output control signal out′ is an effective pulse, the output module 140 uses the effective pulse of the first type of output control signal out′ as the gate drive signal gout, thereby making the gate drive signal gout output by the first shift register unit 11 ineffective. When the first shift register unit 11 is the i-th stage shift register unit Gi, since the input signal of the j-th stage shift register unit Gj is the gate drive signal gout output by the first shift register unit 11, the j-th stage shift register unit Gi... When shift register unit Gj cannot receive an input signal including a valid pulse, the signal of the first node N1 in the j-th stage shift register unit Gj remains at an invalid level. The output module 140 of the j-th stage shift register unit Gj cannot output the received output control signal, and the gate drive signal output by the j-th stage shift register unit Gj will remain at an invalid level. At the same time, because the shift base units of each stage are cascaded in sequence, the other shift shift register units G located after the j-th stage shift register unit Gj also cannot receive an input signal including a valid pulse. When the gate control signal gout output by the other shift shift register units G located after the j-th stage shift register unit Gj is at an invalid level, the signal of the pixel circuit in the second sub-display area A22 cannot be refreshed in the first display frame T1. That is, the image presented by the second sub-display area A22 remains unchanged, so that the corresponding nodes in the pixel circuit 20 in the second sub-display area A22 cannot be charged or discharged, thereby reducing the power consumption of the display panel 100.Meanwhile, by adjusting the effective pulse interval time of the reset clock signal rstf received by the first shift register unit and / or the output control signal out, the display requirements of the display panel 100 can be met without changing the cascading method of the shift register units G in the driving circuit 10 or the structure of each shift register unit G. This reduces the refresh frequency of some pixel circuits 20 in the display panel 100, simplifies the design of the display panel 100 without increasing the complexity of the driving circuit 10, and facilitates the narrow bezel design of the display panel 100.

[0060] The display panel provided in this embodiment of the invention, when the display panel is in a first working mode, ensures that at least one first shift register exists in the driving circuit. In the first display frame of this first working mode, by setting the interval between two adjacent valid pulses in the output control signal of the first shift register as a first interval, and the time interval between two adjacent valid pulses in the reset clock signal that overlaps with the first interval as a second interval, and setting the first interval to be greater than the second interval, the valid pulse time of the reset clock signal is positioned before the valid pulse time of the output control signal. This allows the signal of the first node to be reset to an invalid level before the valid pulse of the output control signal received by the first shift register unit. Consequently, the signal of the first node cannot control the output module to output the valid pulse of the output control signal as a gate drive signal. Therefore, in the first display frame of the first mode, the gate drive signal output by the output module of the first shift register unit remains at an invalid level or a first level signal of the output control signal, and the first... The gate drive signal output by the cascaded shift register unit after the shift register unit remains at an invalid level or a first level signal, which prevents the pixel circuit electrically connected to this part of the shift register from refreshing the screen and thus prevents the corresponding nodes in the pixel circuit from charging and discharging, effectively reducing the power consumption of the display panel. At the same time, the display panel is usually driven by a driver chip. In this case, the driver chip can determine the first shift register unit in the driver circuit and the time interval between the reset clock signal and the output control signal provided to the first shift register unit according to the display requirements of the display panel. Therefore, it is not necessary to change the cascaded method of the shift registers in the driver circuit or the structure of each shift register. Only by adjusting the effective pulse interval time of the reset clock signal and / or the output control signal according to the display requirements of the display panel, the signal refresh frequency of the sub-pixels electrically connected to at least some shift registers can be realized. Without increasing the complexity of the driver circuit, the design of the display panel is simplified, which is beneficial to the narrow bezel design of the display panel.

[0061] Optional, see reference Figure 1 , Figure 2 and Figure 3In the first mode (Mode1), some display frames are the second display frame (T2). In the second display frame (T2), the effective pulse time of the gate drive signal gout transmitted by each first gate drive line (SCAN1) and each second gate drive line (SCAN2) is shifted sequentially.

[0062] Specifically, the second display frame T2 can be a display frame with the same refresh rate as the pixel circuits of the first sub-display area A21 and the second sub-display area A22. That is, in the second display frame T2 of the first mode (Mode1), each shift register unit G sequentially outputs effective pulses of the gate drive signal gout, realizing line-by-line scanning of each row of pixel circuits 20 in display area A. This ensures that the signals in each row of pixel circuits 20 are refreshed, preventing the display brightness of some pixel circuits with lower refresh rates from being affected by prolonged periods without refresh. Thus, in the first mode (Mode1), adding a second display frame T2 that refreshes the entire image presented in display area A can improve the display quality while reducing power consumption.

[0063] It is understood that the cascading method of each level of shift register unit in the driving circuit of the display panel provided in the embodiments of the present invention, as well as the structure of each level of shift register unit, can be set according to actual needs. The embodiments of the present invention do not make specific limitations in this regard. The following is an exemplary description of the structure of the shift register unit mentioned in the embodiments of the present invention using typical examples.

[0064] Optional, Figure 4 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, with reference to... Figure 4Taking a driving circuit capable of simultaneous forward and reverse scanning as an example, the scanning control terminal of the shift register unit can include a forward scanning control terminal FW and a reverse scanning control terminal BW, and the input terminal of the shift register unit can include a forward input terminal INF and a reverse input terminal INB. Correspondingly, the input module 110 can include a first input transistor M1 and a second input transistor M2. The first terminal of the first input transistor M1 is electrically connected to the forward scanning control terminal FW, receiving the forward scanning control signal fw provided by the forward scanning control terminal FW. The gate of the first transistor M1 is electrically connected to the forward input terminal INF, receiving the forward input signal inf provided by the forward input terminal INF. The second terminal of the first transistor M1 is electrically connected to the first node N1. The first terminal of the second input transistor M2 is electrically connected to the reverse scanning control terminal BW, receiving the reverse scanning control signal bw from the reverse scanning control terminal BW. The gate of the second transistor M2 is electrically connected to the reverse input terminal INB, receiving the reverse input signal inb from the reverse input terminal INB. The second terminal of the second transistor M2 is electrically connected to the first node N1. The forward input signal *inf* controls the first transistor M1 to turn on or off, while the reverse input signal *inb* controls the second transistor M2 to turn on or off. When the input signal *inf* is active, the first transistor M1 is on, transmitting the forward scan control signal *fw* to the first node N1, ensuring that the signal at the first node N1 is consistent with the forward scan control signal *fw*. When the reverse input signal *inb* is active, the second transistor M2 is on, transmitting the reverse scan control signal *bw* to the first node N1, ensuring that the signal at the first node N1 is consistent with the reverse scan control signal *bw*. Thus, during forward scanning, the forward scan control signal *fw* can be kept active, allowing the signal at the first node N1 to be controlled by the forward input signal *inf*; conversely, during reverse scanning, the reverse scan control signal *bw* can be kept active, allowing the signal at the first node N1 to be controlled by the reverse input signal *inb*.

[0065] Optionally, when the driving circuit can perform forward and reverse scanning simultaneously, the reset clock signal terminal may include a forward reset clock signal terminal RSTF and a reverse reset clock signal terminal RSTB. The reset module 120 may include a first reset transistor M3, a second reset transistor M4, and a third reset transistor M5. The first terminal of the first reset transistor M3 is electrically connected to the forward reset clock signal terminal RSTF to receive the forward reset clock signal rstf from RSTF. The gate of the first reset transistor M3 is electrically connected to the forward scan control terminal FW to receive the forward scan control signal fw from FW. The second terminal of the first reset transistor M3 is electrically connected to the gate of the second reset transistor M4. The first terminal of the second reset transistor M4 is electrically connected to the second level signal terminal VGH. The first terminal of the first reset transistor M4 is connected to the second node N2 to receive the second level signal vgh from the second level signal terminal VGH. The second terminal of the second reset transistor M4 is electrically connected to the second node N2. The first terminal of the third reset transistor M5 is electrically connected to the reverse reset clock signal terminal RSTB to receive the reverse reset clock signal rstb from the reverse reset clock signal terminal RSTB. The gate of the third reset transistor M5 is electrically connected to the reverse scan control terminal BW to receive the reverse scan control signal bw from the reverse scan control terminal BW. The second terminal of the third reset transistor M5 is electrically connected to the gate of the second reset transistor M4. The forward scan control signal fw from the forward scan control terminal FW can control the first reset transistor M3 to be turned on or off, and the reverse scan control signal bw from the reverse scan control terminal BW can control the third reset transistor M5 to be turned on or off.

[0066] Specifically, when the forward scan control signal fw is active, the first reset transistor M3 is turned on, transmitting the forward reset clock signal rstf to the gate of the second reset transistor M4. If the forward reset clock signal rstf is active at this time, it can control the second reset transistor M4 to turn on, enabling it to transmit the second level signal vgh to the second node N2, thus ensuring that the signal at the second node N2 is consistent with the second level signal vgh. Similarly, when the reverse scan control signal bw is active, the third reset transistor M5 is turned on, transmitting the reverse reset clock signal rstb to the gate of the second reset transistor M4. If the reverse reset clock signal rstb is active at this time, the second reset transistor M4 is active, allowing the second level signal vgh to be transmitted to the second node N2, thus ensuring that the signal at the second node N2 is consistent with the second level signal vgh. Thus, when the driving circuit performs a forward scan, the forward scan control signal fw can be controlled to be at an active level, so that the signal of the second node N2 can be controlled by the forward reset clock signal rstf; while when the driving circuit performs a reverse scan, the reverse scan control signal bw can be controlled to be at an active level, so that the signal of the second node N2 can be controlled by the reverse reset clock signal rstb.

[0067] Optionally, the node inter-control module 130 may include a first inter-control transistor M6 and a second inter-control transistor M7. In the same shift register unit G: the first terminal of the first inter-control transistor M6 is electrically connected to the first level signal terminal VGL to receive the first level signal vgl of the first level signal terminal VGL; the second terminal of the first inter-control transistor M6 is electrically connected to the first node N1; the gate of the first inter-control transistor M6 is electrically connected to the second node N2; the first terminal of the second inter-control transistor M7 is electrically connected to the first level signal terminal VGL to receive the first level signal vgl of the first level signal terminal VGL; the second terminal of the second inter-control transistor M7 is electrically connected to the second node N2; the gate of the second control transistor M7 is electrically connected to the first node N1. The signal at the first node N1 can control the second inter-control transistor M7 to turn on or off, and the signal at the second node N2 can control the first inter-control transistor M6 to turn on or off.

[0068] Specifically, when the signal of the second node N2 is at an active level, the first control transistor M6 is turned on, transmitting the first level signal vgl to the first node N1, thereby controlling the signal of the first node N1 to be consistent with the first level signal vgl, i.e., the signal of the first node N1 is at an active level. When the signal of the first node N1 is at an active level, the second control transistor M7 is turned on, transmitting the first level signal vgl to the second node N2, thereby controlling the signal of the second node N2 to be consistent with the first level signal vgl, i.e., the signal of the second node N2 is at an active level. Thus, by setting the first inter-control transistor M6 and the second inter-control transistor M7 in the node inter-control module 130, the signals of the first node N1 and the second node N2 can be mutually constrained, preventing the situation where the signals of the first node N1 and the second node N2 are simultaneously at active levels.

[0069] Optionally, the output module 140 includes a first output transistor M8 and a second output transistor M9. The first terminal of the first output transistor M8 is electrically connected to the output control signal terminal OUT to receive the output control signal out from the output control signal terminal OUT. The gate of the first output transistor M8 is electrically connected to the first node N1. The second terminal of the first output transistor M8 is electrically connected to the gate drive signal terminal GOUT to output the gate drive signal gout. The first terminal of the second output transistor M9 is electrically connected to the first level signal terminal VGL to receive the first level signal vgl from the first level signal terminal VGL. The gate of the second output transistor M9 is electrically connected to the second node N2. The second terminal of the second output transistor M9 is electrically connected to the gate drive signal terminal GOUT to output the gate drive signal gout. Specifically, the first output transistor M8 can be turned on or off under the control of the signal from the first node N1. When the first node N1 is at an active level, the first output transistor M8 is turned on and outputs the output control signal out as the gate drive signal gout. The second output transistor M9 can be turned on or off under the control of the signal from the second node N2. When the second node N2 is at an active level, the second output transistor M9 is turned on and outputs the first level signal vgl as the gate drive signal gout.

[0070] Based on the above embodiments, optionally, Figure 5 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, with reference to... Figure 5The shift register unit G may also include a voltage regulator module 150. In the same shift register unit, the voltage regulator module 150 can be electrically connected to the first node N1 and the third node N3 respectively to stabilize the signals of the first node N1 and the third node N3. Specifically, when the signals of the first node N1 and the second node N3 are both within a set range, the voltage regulator module 150 can be in a conducting state, allowing the signal of the first node N1 to be transmitted to the third node N3 through the voltage regulator module 150. At this time, the output module 140 can be electrically connected to the first node N1 through the voltage regulator module 150, enabling the output module 140 to receive the same signal from the third node N3 as the signal from the first node N1. Conversely, when the voltage of the signal from the third node N3 and / or the signal from the first node N1 is too high or too low, the voltage regulator module 150 can be in a closed state to prevent the signal from the first node N1 from affecting the signal from the third node N3, or vice versa. Thus, by setting a voltage regulator module 150 in the shift register unit G, the first node N1 and the third node N3 can be isolated, ensuring that the signals of the first node N1 and the third node N3 are relatively stable. This prevents the signal fluctuations of the first node N1 and / or the third node N3 from affecting the accuracy of the gate drive signal gout output by the drive output module 140, thereby improving the working stability of the shift register unit G and thus improving the display effect of the display panel.

[0071] Optional, Figure 6 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, with reference to... Figure 6The voltage regulator module 150 includes a Zener transistor M10. The first terminal of Zener transistor M10 is electrically connected to the first node N1, and the second terminal of Zener transistor M10 is electrically connected to the gate of the first output transistor M8 and to the third node N3. The gate of Zener transistor M10 receives a second-level signal vgh. Thus, Zener transistor M10 can remain in a conducting state under the control of the second-level signal vgh, allowing the signal from the first node N1 to be regulated by Zener transistor M10 and transmitted to the third node N3. This controls the signal at the gate of the first output transistor M8, which is electrically connected to the third node N3, ensuring that the signals from the first node N1 and the third node N3 are essentially consistent. Simultaneously, because the conducting Zener transistor M10 has a certain resistance, when the signal at the third node N3, which is electrically connected to the drive module 140, changes, Zener transistor M10 can reduce the amount of change in the signal of the first node N1 as the signal of the third node N3 changes. Similarly, when the signal at the first node N1 changes, Zener transistor M10 can also reduce the amount of change in the signal of the third node N3 as the signal of the first node N1 changes. Thus, by setting a Zener transistor M10 between the first node N1 and the third node N3, the stability of the signals at the first node N1 and the third node N3 can be guaranteed, thereby improving the stability of the gate drive signal gout output by the drive output module 140.

[0072] Optional, continue to refer to Figure 5 The shift register unit G may also include a bootstrap module 160, which is electrically connected between the third node N3 and the gate drive signal terminal GOUT. The bootstrap module 160 can control the signal of the third node N3 to change with the gate drive signal gout of the gate drive signal terminal GOUT. Thus, when the gate drive signal gout changes from an invalid level to an effective level, the signal of the third node N3 changes accordingly. This allows the signal of the third node N3 to control the conduction level of the output module 140, enabling the output module 140 to accurately and quickly pull the gate drive signal gout high to an effective level, thereby improving the accuracy and stability of the gate drive signal gout output by the shift register unit G.

[0073] Optional, continue to refer to Figure 6 The bootstrap module 160 may include a first capacitor C1, the first plate of which is electrically connected to the third node N3, and the second plate of which is electrically connected to the gate drive signal terminal GOUT. Thus, due to the coupling effect of the first capacitor C1, the signal at the third node N3 will change with the gate drive signal gout of the gate drive signal terminal GOUT.

[0074] Optional, continue to refer to Figure 5The shift register unit G may also include a first holding module 170. One end of the first holding module 170 receives a first level signal vgl, and the other end of the first holding module 170 is electrically connected to the first node N1. The first holding module 170 can maintain the stability of the signal of the first node N1.

[0075] Optional, continue to refer to Figure 6 The first holding module 170 may include a second capacitor C2, which serves as an energy storage capacitor and is capable of storing the signal of the first node N1 to maintain the stability of the first node N1.

[0076] Optional, continue to refer to Figure 5 The shift register unit G may also include a second holding module 180. One end of the second holding module 180 receives a first level signal vgl, and the other end of the second holding module 180 is electrically connected to the second node N2. The second holding module 180 can maintain the stability of the second node N2.

[0077] Optional, continue to refer to Figure 6 The second holding module 180 includes a third capacitor C3, which serves as an energy storage capacitor and is capable of storing the signal of the second node N2 to maintain the stability of the second node N2.

[0078] It is understood that each transistor in the shift register unit G can be an N-channel insulated-gate field-effect transistor (IGFET), in which case the effective level controlling the conduction of each transistor is high. Alternatively, each transistor in the shift register unit G can also be a P-channel IGFET, in which case the effective level controlling the conduction of each transistor is low. For ease of explanation, unless otherwise specified, the embodiments of the present invention will be illustrated by taking the example that each transistor in the shift register unit G can be an N-channel IGFET, and the embodiments of the present invention will be explained by way of example. Exemplarily, in conjunction with reference to... Figure 1 , Figure 3 and Figure 6 Taking the sixth-level shift register G6 as the first shift register as an example.

[0079] In stage t01, the input signal inf (i.e., the start signal stv) of the first-stage shift register unit G1 is at an active level, controlling the first input transistor M1 in the first-stage shift register unit G1 to turn on. This allows the scan control signal fw to be transmitted to the first node N1 of the first-stage shift register unit G1, and the first output transistor M8 of the first-stage shift register unit G1 to turn on, controlling the output control signal out received by the first-stage shift register unit G1 as the gate drive signal gout1. Since the output control signal out of the first shift register unit G1 is at an active level in this stage, the first-stage shift register unit G1 outputs an active pulse of the gate drive signal gout1. Simultaneously, in stage t01, the high level of the first node N1 in the first shift register unit controls the second inter-control transistor M7 to turn on. The first level signal VGL is transmitted to the second node N2 through the second inter-control transistor M7. The second node N2 is at an inactive level, controlling the second output transistor M9 to turn off. Correspondingly, since the input signal inf of the second-stage shift register unit G2 is the gate drive signal gout1 output by the first-stage shift register unit G1, the first input transistor M1 in the second-stage shift register unit G2 will be turned on under the control of the received input signal inf (i.e., the gate drive signal gout1). The signal of the first node N1 of the second-stage shift register unit G2 controls the first output transistor M8 to be turned on, and the second-stage shift register unit G2 outputs its output control signal out as its gate drive signal. However, because the output control signal out of the second-stage shift register unit G2 is low at this time, the gate drive signal gout2 output by the second-stage shift register unit G is invalid; the input signals inf of other shift register units (G3, G4, G5, G6, ...) are all invalid, making the gate drive signals (gout3, gout4, gout5, gout6, ...) output by other shift register units (G3, G4, G5, G6, ...) invalid.

[0080] In stage t02, the reset clock signal rstf received by the first-stage shift register unit G1 becomes active, thereby transmitting the active level of the reset clock signal rstf in the first-stage shift register unit G1 to the gate of the second reset transistor M4 through the first reset transistor M3, controlling the second reset transistor M4 to turn on, controlling the second level signal VGH to be transmitted to the second node N2, the second node N2 becomes active, the second output transistor M9 turns on, causing the first level signal vgl to be output through the second output transistor M9 and used as its gate drive signal gout1, the gate drive signal gout1 output by the first-stage shift register unit G1 becomes inactive; correspondingly, the input signal inf received by the second-stage shift register unit G2 becomes inactive, and because the reset clock signal rstf of the second-stage shift register unit G2 remains inactive in this stage, the signal of the first node N1 in the second-stage shift register unit G2 remains active, and the signal of the second node N2 remains inactive. The first output transistor M8 of the second-stage shift register unit G2 remains on. Simultaneously, since the output control signal out of the second-stage shift register unit G2 is a valid pulse during this stage, the gate drive signal gout2 of the second-stage shift register unit G2 is also a valid pulse. Furthermore, since the input signal inf of the third-stage shift register unit G3 is the gate drive signal gout2 of the second-stage shift register unit G2, the third-stage shift register unit G3 can output its output control signal out as its gate drive signal gout3. And since the output control signal out of the third-stage shift register unit G3 is invalid, the gate drive signal gout3 output by the third-stage shift register unit G3 is also invalid. For the input signals inf of the other shift register units (G4, G5, G6, ...), all are invalid, resulting in the gate drive signals (gout4, gout5, gout6, ...) output by the other shift register units (G4, G5, G6, ...) being invalid.

[0081] In stage t03, the first-stage shift register unit G1 maintains the invalid level of the output gate drive signal gout1; the reset clock signal rstf received by the second-stage shift register unit G1 is valid, causing the valid level of the reset clock signal rstf in the second-stage shift register unit G2 to control the second node N2 to be valid, the second output transistor M9 is turned on, and the first level signal vgl is output to the gate drive signal output terminal GOUT through the second output transistor M9, and the gate drive signal gout2 output by the second-stage shift register unit G2 becomes invalid; at the same time, because the input signal inf in the third-stage shift register unit G3 becomes invalid, and its reset clock signal rstf is also invalid, the third-stage shift register unit G3 continues to output its output control signal out as the gate drive signal gout3, and because at this time the third The output control signal 'out' of the third-stage shift register unit G3 is active, making the gate drive signal 'gout3' of the third-stage shift register unit G3 active. Furthermore, since the input signal 'inf' of the fourth-stage shift register unit G4 is the gate drive signal 'gout3' of the third-stage shift register unit G3, the fourth-stage shift register unit G4 outputs its output control signal 'out' as its gate drive signal 'gout4'. Because the output control signal 'out' of the fourth-stage shift register unit G4 is inactive, the gate drive signal 'gout4' of the fourth-stage shift register unit G4 is inactive. For the input signals 'inf' of all other shift register units (G5, G6, ...), they are all inactive, making the gate drive signals (gout5, gout6, ...) output by the other shift register units (G5, G6, ...) inactive.

[0082] In stage t04, based on the same principle, the first-stage shift register unit G1 maintains the invalid level of the output gate drive signal gout1, and the second-stage shift register unit G1 also maintains the invalid level of the output gate drive signal gout2; the reset clock signal rstf of the third-stage shift register unit G3 controls the invalid level of its output gate drive signal gout3, and the fourth-stage shift register unit G4 outputs the valid level of the gate drive signal gout4; the fifth-stage shift register unit G5 outputs its output control signal out as the gate drive signal gout5, and this gate drive signal gout5 is invalid; the gate drive signals (gout6, ...) output by other shift register units (G6, ...) are all invalid.

[0083] In stage t05, based on the same principle, the first-stage shift register units G1 to the fourth-stage shift register unit G4 all output invalid levels of the gate drive signals (gout1, gout2, gout3, gout4), while the fifth-stage shift register unit G5 outputs an effective pulse of the gate drive signal gout4. The sixth-stage shift register unit G6 can receive an effective level of the input signal inf, causing it to output its output control signal out as the gate drive signal gout6. Since the output control signal out of the sixth-stage shift register unit G6 is invalid, its gate drive signal gout6 also remains invalid. Furthermore, the other shift register units after the sixth-stage shift register unit G6 will continue to output invalid levels of the gate drive signals.

[0084] In stage t06, in the sixth-stage shift register unit G6, the output control signal out remains at an invalid level, while the reset clock signal rstf becomes valid. That is, before the valid pulse of the output control signal out of the sixth-stage shift register unit G6 arrives, the sixth-stage shift register unit G6 receives the valid pulse of the reset clock signal rstf. At this time, the valid pulse of the reset clock signal rstf controls the second node N2 in the sixth-stage shift register unit G6 to be valid, and controls the first node N1 to be invalid through the first inter-control transistor M6. This causes the first output transistor M8 of the sixth-stage shift register unit G6 to turn off, and the ninth output transistor M9 to turn on, outputting the first level signal vgl as its gate drive signal gout6. That is, the gate drive signal gout6 output by the sixth-stage shift register unit G6 remains invalid, causing other shift register units after the sixth-stage shift register unit G6 to continue to output invalid gate drive signals.

[0085] In stage t07, the output control signal out of the sixth-stage shift register unit G6 becomes valid. That is, after the valid pulse of its reset clock signal rstf, the sixth-stage shift register unit G6 receives the valid pulse of the output control signal out. However, since the first output transistor M8 is already in the off state, the output control signal out cannot be output to the gate drive signal output terminal GOUT through the first output transistor M8. At this time, the gate drive signal gout6 of the sixth-stage shift register unit G6 is still the first level signal vgl, that is, the gate drive signal gout6 of the sixth-stage shift register unit G6 is invalid. At the same time, in the subsequent process, the sixth-stage shift register unit G6 cannot receive the valid level of the input signal inf, so the sixth-stage shift register unit G6 cannot output its output control signal out as the gate drive signal gout6. That is, the sixth-stage shift register unit G6 cannot output the valid pulse of the gate drive signal gout6, so the gate drive signal output by the sixth-stage shift register unit G6 and other subsequent shift register units is invalid.

[0086] Thus, in the display panel 100, each level of the shift register unit from the first-level shift register unit G1 to the fifth-level shift register unit G5 can sequentially output an effective level of the gate drive signal, enabling the pixel circuits 20 connected to it to refresh the signal line by line. However, the gate drive signals output by the sixth-level shift register unit G6 to the last-level shift register unit remain at an ineffective level, thereby preventing the pixel circuits 20 connected to them from refreshing the signal. At this time, the area where the pixel circuits of each row electrically connected to each level of the shift register unit from the first-level shift register unit G1 to the fifth-level shift register unit G5 are located is the first sub-display area A21, and the area where the pixel circuits of each row electrically connected to each level of the shift register unit from the sixth-level shift register unit G6 to the last-level shift register unit are located is the second sub-display area A22. Since the first sub-display area A21... The pixel circuits in the first sub-display area A21 can continuously refresh signals, while the pixel circuits in the second sub-display area A22 cannot. This results in a higher display refresh rate for the first sub-display area A21 compared to the second sub-display area A22, effectively reducing power consumption while maintaining display quality. Furthermore, without altering the cascading method or structure of the shift registers in the driving circuit, the signal refresh rate of at least some of the electrically connected pixel circuits can be controlled by adjusting the effective pulse interval of the reset clock signal and / or the output control signal, based solely on the display requirements of the display panel. This simplifies the display panel design without increasing the complexity of the driving circuit, facilitating narrow bezel designs.

[0087] It is understood that the above example only exemplifies that the display refresh frequency of the first sub-display area A21 is greater than the display refresh frequency of the second sub-display area A22. In the embodiments of the present invention, the display refresh frequency of the first sub-display area A21 can also be less than the display refresh frequency of the second sub-display area A22. In this case, the gate drive signal gout output by each shift register unit G electrically connected to the pixel circuit in the first sub-display area A21 can be kept at an invalid level through the reverse scanning process of the driving circuit. The specific driving process is similar to the forward scanning process described above, and the similarities can be referred to the above description. No specific limitation is made here.

[0088] Optional, continue to refer to the references Figure 1 , Figure 2 , Figure 3 and Figure 6 In the first display frame T1, in the first shift register unit 11, the input signal inf includes a valid pulse IEP, the reset clock signal rstf includes a first valid reset pulse REP1, and the first type of output control signal out′ includes a first valid output pulse CEP1. Among the valid pulses of the reset clock signal rstf, the first valid pulse after the valid pulse EP1 of the input signal inf is the first valid reset pulse REP1. Among the valid pulses of the first type of output control signal out′, the first valid pulse after the valid pulse IEP of the input signal inf is the first valid output pulse CEP1. The time of the first valid reset pulse REP1 is before the time of the first valid output pulse CEP1.

[0089] Specifically, taking the sixth-level shift register unit G6 as the first shift register unit 11 as an example, since the input signal inf of the sixth-level shift register unit G6 is the gate drive signal gout5 of the fifth-level shift register unit G5, when the first effective pulse after the effective pulse IEP of the gate drive signal gout5 in each effective pulse of the reset clock signal rstf (fourth clock signal ck4) is the first reset effective pulse REP1, and the first effective pulse after the effective pulse IEP of the gate drive signal gout5 in each effective pulse of the first type of output control signal out′ is the first output effective pulse CEP1, by setting the time of the first reset effective pulse REP1 to be before the time of the first output effective pulse CEP1, the reset module 120 of the sixth shift register unit G6 can reset the signal of its first node N1 before its output module 140 receives the effective pulse of the first type of output control signal out′, making the signal of the first node N1 become invalid, thereby enabling the output module 140 to receive the first type of output before the first type of output control signal out′. When the first output valid pulse CEP1 of the control signal out′ is emitted, the first output transistor M8 will be in the off state, and the output module 140 will not be able to output the first output valid pulse EP3 of the first type of output control signal out′. This will prevent the gate drive signal gout6 output by the sixth-level shift register unit G6 from controlling the pixel circuit connected to it to refresh the signal. As a result, the input signal inf received by the other shift register units G cascaded with the sixth-level shift register unit G6 and located after the sixth-level shift register unit G6 will always be at an invalid level. This will cause the gate drive signal gout output by the other shift register units G after the sixth-level shift register unit G6 to remain at an invalid level. This will prevent the pixel circuit connected to the sixth-level shift register unit G6 and the other shift register units G after the sixth-level shift register unit G6 from refreshing the signal. This will allow the two sub-display areas of the display panel 100 to have different refresh frequencies without increasing the complexity of the drive circuit 10, and will effectively reduce the power consumption of the display panel 100.

[0090] Optional, continue to refer to the references Figure 1 , Figure 2 , Figure 3 and Figure 6In the first display frame T1, the reset clock signal rstf of the first shift register unit 11 further includes a second valid reset pulse REP2; the time of the second valid reset pulse REP2 is before the time of the first valid reset pulse REP1, and the first valid reset pulse REP1 and the second valid reset pulse REP2 are two adjacent valid pulses; the interval between the first valid reset pulse REP1 and the second valid reset pulse REP2 is the second interval time t2; in the first display frame T1, the first type of output control signal out′ of the first shift register unit 11 further includes a second valid output pulse CEP2; the time of the second valid output pulse CEP2 is before the time of the first valid output pulse CEP1, and the first valid output pulse CEP1 and the second valid output pulse CEP2 are two adjacent valid pulses; the interval between the first valid output pulse CEP1 and the second valid output pulse CEP2 is the first interval time t1; the time of the second valid output pulse CEP2 is before the time of the second valid reset pulse REP2.

[0091] Specifically, by positioning the second output valid pulse CEP2 before the second reset valid pulse REP2, i.e. before the first reset valid pulse REP1, the valid pulse of the reset clock signal rstf received by the first shift register unit is positioned after the valid pulse CEP2 of the first type of output control signal out′ received by it. This ensures that each level of the shift register unit G works normally before the first reset valid pulse REP1, and that the display panel 100 can display accurately.

[0092] Optional, Figure 7 This is a driving timing diagram of another shift register unit provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 1 , Figure 2 , Figure 3 and Figure 7 In the first display frame T1, in the first shift register unit 11, the reset clock signal rstf further includes at least one third reset valid pulse REP3 located before the second reset valid pulse REP2, and the first type of output control signal out′ further includes at least one third output valid pulse CEP3 located before the second output valid pulse CEP2; in the first type of output control signal out′, the interval time between the second output valid pulse CEP2 and the third output valid pulse adjacent to the second output valid pulse CEP2 is the third interval time t3; in the reset clock signal rstf, the interval time between the second reset valid pulse REP2 and the third reset valid pulse REP3 adjacent to the second reset valid pulse REP2 is the fourth interval time t4; the third interval time t3 is equal to the fourth interval time t4.

[0093] It is understandable that in the reset clock signal rstf, the time intervals between each valid pulse preceding the second valid reset pulse REP2 can be equal; similarly, in the first type of output control signal out′, the time intervals between each valid pulse preceding the second valid output pulse CEP2 can be equal. By setting the third interval time t3 to equal the fourth interval time t4, that is, before the second valid reset pulse REP2 and the second valid output pulse CEP2, the interval between each valid pulse of the reset clock signal rstf can be equal to the interval between each valid pulse of the first type of output control signal out′, thereby ensuring that each stage of the shift register unit 11 can accurately output the gate drive signal gout.

[0094] Optional, continue to refer to Figure 1 , Figure 2 , Figure 3 and Figure 7 The first interval t1 is greater than the third interval t3; the second interval t2 is less than the fourth interval t4.

[0095] Specifically, based on the third interval time t3 being equal to the fourth interval time t4, the first interval time t1 is set to be greater than the third interval time t3, and the second interval time t2 is set to be less than the fourth interval time t4. Thus, when providing the first type of output control signal out′ and the reset clock signal rstf to the first shift register unit 11, the first output valid pulse CEP1 of the first type of output control signal out′ can be delayed by a preset time before being provided to the first shift register unit 11, while the first reset valid pulse REP1 is provided to the first shift register unit 11 ahead of a preset time. This allows the first reset valid pulse REP1 of the reset clock signal rstf to be provided to the first shift register unit 11 within the originally scheduled time for providing the first output valid pulse CEP1 of the first type of output control signal out′, and the first reset valid pulse REP1 of the reset clock signal rstf to be provided to the first shift register unit 11 within the originally scheduled time for providing the first reset valid pulse REP1 of the reset clock signal rstf. The storage unit 11 provides a first valid output pulse CEP1 for the first type of output control signal out′. Therefore, before providing the first valid output pulse CEP1 of the first type of output control signal out′ to the output module 140 of the first shift register unit 11, the first valid reset pulse REP1 of the reset clock signal rstf of the first shift register unit 11 can be provided to reset the signals of the first node N1 and the second node N2, so that the first valid output pulse CEP1 of the first type of output control signal out′ cannot be output through the output module 140, thereby preventing the gate drive signal gout output by the first shift register unit 11 from controlling the pixel circuit 20 connected to it to refresh the signal.

[0096] Optional, Figure 8 This is a driving timing diagram of another shift register unit provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 1 , Figure 2 , Figure 3 and Figure 8 The first interval t1 is equal to the third interval t3; the second interval t2 is less than the fourth interval t4.

[0097] Specifically, based on the third interval time t3 being equal to the fourth interval time t4, the first interval time t1 is set to be equal to the third interval time t3, and the second interval time t2 is less than the fourth interval time t4. In this way, without changing the first type of output control signal out′, the time of the first reset valid pulse REP1 of the reset clock signal rstf can be advanced. Similarly, before the first output valid pulse CEP1 of the first type of output control signal out′ is transmitted to the output module 140, the reset module 130 can reset the signal of the first node N1 according to the first reset valid pulse REP1.

[0098] Optional, Figure 9 This is a driving timing diagram of another shift register unit provided in an embodiment of the present invention, in conjunction with the reference figure. Figure 1 , Figure 2 , Figure 3 and Figure 9 The first interval t1 is greater than the third interval t3; the second interval t2 is equal to the fourth interval t4.

[0099] Specifically, based on the third interval time t3 being equal to the fourth interval time t4, the first interval time t1 is set to be greater than the third interval time t3, and the second interval time t2 is equal to the fourth interval time t4. In this way, without changing the reset clock signal rstf, the time of the first output valid pulse CEP1 of the first type of output control signal out′ is delayed. Similarly, before the first output valid pulse CEP1 of the first type of output control signal out′ is transmitted to the output module 140, the reset module 130 resets the signal of the first node N1 according to the first reset valid pulse REP1.

[0100] Based on the above embodiments, optionally, Figure 10 This is a driving timing diagram of another shift register unit provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 1 , Figure 6 and Figure 10The display panel 100 also includes a second mode, Mode2. In a display frame under Mode2, the interval t3 between two adjacent valid pulses of the output control signal out in the same shift register unit G is equal to the interval t4 between two adjacent valid pulses of the reset clock signal rstf. Thus, each shift register unit G can sequentially output valid pulses of the gate drive signal gout, enabling line-by-line scanning of the pixel circuit 20 and ensuring the display quality of the image.

[0101] Optional, refer to the reference Figure 1 and Figure 3 When N equals 1, the gate drive signal goutj of the j-th stage shift register Gj is the input signal inf of the (j+1)-th stage shift register Gj+1; j is a positive integer; the reset clock signal rstf of the j-th stage shift register Gj is multiplexed to the reset clock signal rstf of the (j+4)-th stage shift register Gj+4; and / or, the output control signal out of the j-th stage shift register Gj is multiplexed to the output control signal out of the (j+4)-th stage shift register Gj+4.

[0102] Specifically, when N=1, the gate drive signal goutj of the j-th stage shift register Gj is set as the input signal inf of the (j+1)-th stage shift register Gj+1, so that each shift register G is cascaded sequentially. Based on the timing analysis above, it can be seen that the effective pulse time of the reset clock signal rstf of the j-th stage shift register unit Gj can be the same as the effective pulse time of the reset clock signal rstf of the (j+4)-th stage shift register unit Gj+4. For example, the effective pulse time of the reset clock signal rstf of the first stage shift register unit G1 can be the same as the effective pulse time of the reset clock signal rstf of the fifth stage shift register unit G5. Therefore, the reset clock signal rstf of the first stage shift register unit G1 can be multiplexed as the reset clock signal rstf of the fifth stage shift register unit G5. That is, the reset clock signal rstf of the j-th stage shift register unit Gj can be multiplexed as the reset clock signal rstf of the (j+4)-th stage shift register unit Gj+4. In this way, while ensuring that each stage shift register unit G outputs the drive control signal gout normally, the number of signals provided to the drive circuit 10 and the number of signal lines providing clock signals to the drive line 10 can be reduced, which is beneficial to the narrow bezel design of the display panel 100.

[0103] It should be noted that the above embodiments only illustrate the technical solution of the present invention with the case of N=1. In other feasible embodiments of the present invention, N≥2 can also be set, in which case the shift register unit G includes two or more output modules 140.

[0104] In an optional embodiment, Figure 11 This is a schematic diagram of a driving circuit provided in an embodiment of the present invention. Figure 12 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention. Figure 13 and Figure 14 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 11 and Figure 13 or in conjunction with references Figure 12 and Figure 14 The shift register unit G includes multiple output modules 140, i.e., N is greater than or equal to 2, and the gate drive signal gout of each output module 140 in the same shift register unit G can be provided to the pixel circuits 20 in different rows respectively, so that one shift register unit G can provide gate drive signals to N rows of pixel circuits 20, which can greatly reduce the number of shift register units G set in the driving circuit 10, thereby facilitating the narrow bezel design of the display panel.

[0105] It is understood that when the shift register unit G includes multiple output modules 140, the effective level of the gate drive signal gout output by each output module 140 of the same shift register unit G can be shifted sequentially, and the effective level of the gate drive signal gout output by each output module in two adjacent shift register units G can be shifted sequentially, thus enabling line-by-line scanning of the pixel circuit 20. Alternatively, the effective level time of the gate drive signal output by each output module 140 of the same shift register unit can also be set in other ways, and this embodiment of the invention does not specifically limit this. Unless otherwise specified, the following embodiments are illustrated by the example of the effective level of the gate drive signal gout output by each output module 140 of the same shift register unit G being shifted sequentially, and the gate drive signal gout output by the output modules 140 in two adjacent shift register units G being shifted sequentially.

[0106] Optionally, when the shift register unit G includes multiple output modules 140, i.e. N is greater than or equal to 2, at least one gate drive signal gouti of the i-th stage shift register unit Gi is the input signal inf of the j-th stage shift register unit Gj; thus, the j-th stage shift register unit Gj can output a gate drive signal goutj according to at least one gate drive signal gouti.

[0107] In an optional embodiment, when the shift register unit G includes multiple output modules 140, the i-th stage shift register unit Gj can be electrically connected to an even number of gate drive signal lines SCAN (e.g., ...). Figure 11 As shown), the i-th stage shift register unit Gj can also be electrically connected to an odd number of gate drive signal lines SCAN (as shown). Figure 12as shown).

[0108] Exemplarily, with reference to Figure 11 and Figure 13 the shift register unit G includes two output modules 140, and the two output modules 140 are respectively the first output module 141 and the second output module 142; the first output module 141 is electrically connected to the first level signal terminal VGL, the first type of output control signal terminal OUT1, the first gate driving signal terminal GOUT1, the first node N1 and the second node N2, and is used to at least control the first gate driving signal provided to the first gate driving signal terminal GOUT1 according to the first level signal vgl provided by the first level signal terminal VGL, the output control signal out1 received by the first type of output control signal terminal OUT1, the signal of the first node N1 and the signal of the second node N2; the second output module 142 is electrically connected to the first level signal terminal VGL, the second output control signal terminal OUT2, the second gate driving signal terminal GOUT2, the first node N1 and the second node N2, and is used to at least control the second gate driving signal provided to the second gate driving signal terminal GOUT2 according to the first level signal vgl provided by the first level signal terminal VGL, the output control signal out2 of the second output control signal terminal OUT2, the signal of the first node N1 and the signal of the second node N2; at this time, each stage of the shift register unit G can be respectively electrically connected to two gate driving signal lines SCAN, and the two gate driving signal lines SCAN can be respectively electrically connected to adjacent two rows of pixel circuits to control the signal refreshing of the adjacent two rows of pixel circuits; at the same time, the second gate driving signal terminal GOUT2 of the i-th stage shift register unit Gi can also be respectively electrically connected to the forward input terminal INF of the j-th stage shift register unit Gj and the reverse input terminal INB of the m-th stage shift register unit Gm, so that the gate driving signal output by the second gate driving signal terminal GOUT2 of the i-th stage shift register unit Gi can be used as the forward input signal of the forward input terminal INF of the j-th stage shift register unit Gj and as the reverse input signal of the reverse input terminal INB of the m-th stage shift register unit Gm; where m < i < j, and m, i, and j are all positive integers.

[0109] In an exemplary embodiment, the second gate drive signal terminal GOUT2 of the third-stage shift register unit G3 can be electrically connected to both the inverting input terminal INB of the second-stage shift register unit G2 and the positive input terminal INF of the fourth-stage shift register unit G4. During forward scanning, the gate drive signal gout6 output from the second gate drive signal terminal GOUT2 of the third-stage shift register unit G3 can be used as the input signal to the positive input terminal INF of the fourth-stage shift register unit G4. During reverse scanning, the gate drive signal gout6 output from the second gate drive signal terminal GOUT2 of the third-stage shift register unit G3 can be used as the input signal to the inverting input terminal INB of the second-stage shift register unit G2.

[0110] In another alternative embodiment, Figure 15 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 15 and Figure 12 When the i-th stage shift register unit Gi includes two output modules 140, and the two output modules 140 are the first output module 141 and the second output module 142 respectively, in the i-th stage shift register unit Gi, the first gate drive signal terminal GOUT1, which is electrically connected to the first output module 141, can be electrically connected to the positive input terminal INF of the j-th stage shift register unit Gj, and the second gate drive signal terminal GOUT2, which is electrically connected to the second output module 141, can be electrically connected to the inverted input terminal INB of the m-th stage shift register unit Gm. For example, the first gate drive signal terminal GOUT1 of the third stage shift register unit can be electrically connected to the positive input terminal INF of the fourth stage shift register unit G4, and the second gate drive signal terminal GOUT2 of the third stage shift register unit can be electrically connected to the inverted input terminal INB of the second stage shift register unit G2.

[0111] In other optional embodiments, when the i-th stage shift register unit includes two output modules, and the two output modules are a first output module and a second output module, in the i-th stage shift register unit, the second gate drive signal terminal electrically connected to the first output module can be electrically connected to the positive input terminal of the j-th stage shift register unit, and the first gate drive signal terminal electrically connected to the second output module can be electrically connected to the negative input terminal of the m-th stage shift register unit.

[0112] It is understood that the above description is merely an example of the cascading method of shift register units, with each shift register unit including two output modules. Under the premise of achieving the core inventive points of the present invention, the present invention does not specifically limit the number of output modules included in each shift register unit.

[0113] Optional, Figure 16This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, with reference to... Figure 16 or Figure 14 When N is greater than or equal to 2, the circuit structure of each module in the shift register unit G is the same as when N=1. The following only describes the differences. When N is greater than or equal to 2, in the same shift register unit G, each output module 140 receives a different output control signal out, and the effective pulse time of the output control signal out received by each shift register unit G is shifted sequentially.

[0114] For example, such as Figure 16 As shown, taking each shift register unit G as including two output modules 140, and the two output modules 140 of the same shift register unit G being the first output module 141 and the second output module 142 respectively, since the effective pulse of the gate drive signal output by the first output module 141 is provided by the output control signal out1 it receives, and the effective pulse of the gate drive signal output by the second output module 142 is provided by the output control signal out2 it receives, by setting the output control signal out received by the first output module 141 and the second output module 142 to shift sequentially, the effective pulse time of the gate drive signal output by the first output module 141 and the gate drive signal output by the second output module 142 can be shifted sequentially. Thus, when the two output modules 140 are electrically connected to pixel circuits in different rows respectively, the two rows of pixel circuits can be controlled to refresh the signal in a time-division manner, ensuring the display accuracy of the display panel 100.

[0115] Optional, see reference Figure 11 or Figure 12 When the shift register unit G includes N output modules, in the same shift register unit G, the output control signal out received by the k-th output module 14k is the k-th output control signal outk; the effective pulse time of the k-th output control signal outk is located before the effective pulse time of the (k+1)-th output control signal outk+1; k is a positive integer and k is less than N; the gate drive signal gout output by one of the first output module 141 and the N-th output module 14N of the i-th stage shift register unit G is the input signal inf received by the input module 110 in the j-th stage shift register unit Gj.

[0116] For example, such as Figure 12 and Figure 14As shown, taking a shift register unit G comprising three output modules 140 as an example, the three output modules 140 of the same shift register unit G are a first output module 141, a second output module 142, and a third output module 143. The effective pulse time of the first output control signal out1 received by the first output module 141 is before the effective pulse time of the second output control signal out2 received by the second output module 142. The effective pulse time of the second output control signal out2 received by the second output module 142 is before the effective pulse time of the third output control signal out2 received by the third output module 143. This results in the effective pulse time of the gate drive signal output by the first drive signal output terminal GOUT1 electrically connected to the first output module 141 being before the effective pulse time of the gate drive signal output by the second drive signal output terminal GOUT2 electrically connected to the second output module 142. The effective pulse time of the gate drive signal output by the second drive signal output terminal GOUT2 electrically connected to the second output module 142 is before the effective pulse time of the gate drive signal output by the third drive signal output terminal GOUT3 electrically connected to the third output module 143. At this time, by using the gate drive signal gout output by the first output module 140 of the i-th stage shift register unit Gi as the input signal inf of the j-th stage shift register unit Gj, the input signal inf of the j-th stage shift register unit Gj can be kept consistent with the gate drive signal gout output by the first output module 140 of the i-th stage shift register unit Gi. This ensures that when the gate drive signal gout output by the first output module 140 of the i-th stage shift register unit Gi is at an effective level, each output module 140 of the j-th stage shift register unit Gj controls its respective output control signal out as its respective output gate drive signal. At this time, it is only necessary to ensure that the effective pulse time of the output control signal out received by each output module 140 of the j-th stage shift register unit Gj is after the effective pulse time of the output control signal out received by each output module 140 of the i-th stage shift register unit Gi. This ensures that the gate drive signal output by the i-th stage shift register unit Gi and the gate drive signal output by the j-th stage shift register unit Gj are shifted sequentially.

[0117] In other alternative embodiments, the gate drive signal gout of the Nth output module 140 of the i-th shift register unit Gi can also be used as the input signal inf of the j-th shift register unit Gj. In this case, it is only necessary to ensure that the effective pulse time of the output control signal out received by each output module 140 of the j-th shift register unit Gj is after the effective pulse time of the Nth output control signal outN received by the Nth output module 140 of the i-th shift register unit Gi. This ensures that the gate drive signal output by the i-th shift register unit Gi and the gate drive signal output by the j-th shift register unit Gj are shifted sequentially.

[0118] Optional, Figure 17 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 12 , Figure 14 Figure 17 Or refer to reference 3. Figure 11 and Figure 13 The reset clock signal of the j-th stage shift register is multiplexed as the first output control signal of the (j+1)-th stage shift register.

[0119] Specifically, since the effective pulse time of the output control signal received by the (j+1)th stage shift register unit is after the effective pulse time of the output control signal received by the j-th stage shift register unit, and the reset clock signal of the j-th stage shift register unit is also after the effective pulse time of the output control signal it receives, the reset clock signal of the j-th stage shift register unit can be multiplexed as the first output control signal of the (j+1)th stage shift register unit. In this way, while ensuring that each stage shift register unit outputs drive control signals normally, the number of signals provided to the drive circuit and the number of signal lines providing clock signals to the drive line can be reduced, which is beneficial to the narrow bezel design of the display panel.

[0120] In one exemplary embodiment, in conjunction with reference to Figure 3 , Figure 11 and Figure 13 When j=1, the reset clock signal rstf of the first-stage shift register unit G1 and the first output control signal out1 of the second-stage shift register unit G2 are both clock signals ck4; when j=2, the reset clock signal rstf of the second-stage shift register unit G2 and the first output control signal out1 of the third-stage shift register unit G3 are both clock signals ck2; and so on, so that the reset clock signal of the previous shift register unit can be multiplexed as the first output control signal of the next-stage shift register unit.

[0121] In another exemplary embodiment, in conjunction with reference to Figure 12 , Figure 14 and Figure 17When j=1, the reset clock signal rstf of the first-stage shift register unit G1 and the first output control signal out1 of the second-stage shift register unit G2 are both clock signals ck5; when j=2, the reset clock signal rstf of the second-stage shift register unit G2 and the first output control signal out1 of the third-stage shift register unit G3 are both clock signals ck2; and so on, the reset clock signal of the previous shift register unit can also be multiplexed as the first output control signal of the next-stage shift register unit.

[0122] Optional, continue to refer to the references Figure 12 , Figure 14 Figure 17 Or refer to reference 3. Figure 11 and Figure 13 The reset clock signal rstf of the j-th stage shift register G is multiplexed as the reset clock signal rstf of the (j+2)-th stage shift register Gj+2; and / or, the k-th output control signal outk of the j-th stage shift register Gj is multiplexed as the k-th output control signal outk of the (j+2)-th stage shift register Gj+2.

[0123] Specifically, since the output control signal is used to control the effective pulse time of the gate drive signal output by the shift register unit G, and the effective pulse time of each output control signal out received by the same shift register unit G is shifted sequentially, each output module in the same shift register unit G can sequentially output the effective pulse of the gate drive signal. Simultaneously, in two adjacent shift register units G, the effective pulse time of the output control signal out received by the previous shift register unit is before the effective pulse time of the output control signal out received by the next shift register unit. This ensures that the effective pulse time of the gate drive signal output by the previous shift register unit is before the effective pulse time of the gate drive signal output by the next shift register unit. For example, the effective pulse time of the output control signal of the j-th shift register unit G is before the effective pulse time of the output control signal of the (j+1)-th shift register unit Gj+1. The effective pulse time is before the effective pulse time of the output control signal of the (j+2)th stage shift register unit Gj+2; after the effective pulse of the gate drive signal output by each output module of the j-th stage shift register unit Gj, the (j+1)th stage shift register unit Gj+1 starts to output the effective pulse of the gate drive signal. At this time, the first node N1 and the second node N2 of the j-th stage shift register unit Gj can be reset, so that the j-th stage shift register unit Gj starts to output the first level signal vgl as the gate drive signal; after the effective pulse of the gate drive signal output by each output module of the (j+1)th stage shift register unit Gj+1, the (j+2)th stage shift register unit Gj+2 starts to output the effective pulse of the gate drive signal. Since the first node N1 and the second node N2 of the j-th stage shift register unit Gj have been reset at this time, when the j-th stage shift register unit Gj receives the effective pulse of the output control signal, it can still maintain the invalid level of the output gate drive signal. In this way, the k-th output control signal outk of the j-th shift register unit Gj can be multiplexed into the k-th output control signal outk of the (j+2)-th shift register unit Gj+2, thereby reducing the number of output control signals provided to the driving circuit and reducing the number of signal lines set in the display panel for transmitting output control signals. This helps to simplify the structure of the display panel and facilitates a narrow bezel.

[0124] Correspondingly, after the valid pulse of the gate drive signal output by the (j+2)th stage shift register unit Gj+2, the first node N1 and the second node N2 of the (j+2)th stage shift register unit Gj+2 can be reset. Since the reset of the first node N1 and the second node N2 in the j-th stage shift register unit Gj has been completed at this time, when the valid pulse of the reset clock signal retf of the j-th stage shift register unit Gj arrives again, it will not affect the accuracy of the gate drive signal output by the j-th stage shift register unit Gj. In this way, the reset clock signal rstf of the j-th stage shift register unit Gj can be multiplexed as the reset clock signal rstf of the (j+2)th stage shift register unit Gj+2, so as to reduce the number of signals provided to the drive circuit 10 and the number of signal lines providing clock signals to the drive line 10 while ensuring that each stage shift register unit G outputs the drive control signal gout normally.

[0125] In one exemplary embodiment, in conjunction with reference to Figure 3 , Figure 11 and Figure 13 When j=1, the reset clock signal rstf of the first-stage shift register unit G1 and the reset clock signal rstf of the third-stage shift register unit G3 are both clock signals ck4; when j=2, the reset clock signal rstf of the second-stage shift register unit G2 and the reset clock signal rstf of the fourth-stage shift register unit G4 are both clock signals ck2; and so on, so that the reset clock signal of the j-th stage shift register unit can be multiplexed as the reset clock signal of the (j+2)-th stage shift register unit. Similarly, when j=1, the first output control signal out1 of the first-stage shift register unit G1 and the first output control signal out1 of the third-stage shift register unit G3 are both clock signals ck2, and the second output control signal out2 of the first-stage shift register unit G1 and the second output control signal out2 of the third-stage shift register unit G3 are both clock signals ck3; when j=2, the first output control signal out1 of the second-stage shift register unit G2 and the first output control signal out1 of the fourth-stage shift register unit G4 are both clock signals ck4, and the second output control signal out2 of the second-stage shift register unit G2 and the second output control signal out2 of the fourth-stage shift register unit G4 are both clock signals ck1; and so on, so that the k-th output control signal outk of the j-th stage shift register unit Gj can be multiplexed into the k-th output control signal outk of the (j+2)-th stage shift register unit Gj+2.

[0126] In another exemplary embodiment, in conjunction with reference to Figure 12 , Figure 14 and Figure 17When j=1, the reset clock signal rstf of the first-stage shift register unit G1 and the reset clock signal rstf of the third-stage shift register unit G3 are both clock signals ck5; when j=2, the reset clock signal rstf of the second-stage shift register unit G2 and the reset clock signal rstf of the fourth-stage shift register unit G4 are both clock signals ck2; and so on, so that the reset clock signal of the j-th stage shift register unit can be multiplexed as the reset clock signal of the (j+2)-th stage shift register unit. Similarly, when j=1, the first output control signal out1 of the first-stage shift register unit G1 and the first output control signal out1 of the third-stage shift register unit G3 are both clock signals ck2, the second output control signal out2 of the first-stage shift register unit G1 and the second output control signal out2 of the third-stage shift register unit G3 are both clock signals ck3, and the third output control signal out3 of the first-stage shift register unit G1 and the third output control signal out3 of the third-stage shift register unit G3 are both clock signals ck4; when j=2, the first output control signal out1 of the second-stage shift register unit G2 is... The first output control signal out1 of the fourth-level shift register unit G4 is clock signal ck5. The second output control signal out2 of the second-level shift register unit G2 and the second output control signal out2 of the fourth-level shift register unit G4 are both clock signals ck6. The third output control signal out3 of the second-level shift register unit G2 and the third output control signal out3 of the fourth-level shift register unit G4 are both clock signals ck1. And so on, the k-th output control signal outk of the j-th shift register unit Gj can be multiplexed into the k-th output control signal outk of the (j+2)-th shift register unit Gj+2.

[0127] Optional, Figure 18 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention, in conjunction with reference to... Figure 2 , Figure 12 and 18 In the first display frame T1, the scan control signal fw received by the first shift register 11 includes a scan invalid pulse.

[0128] Specifically, in order to further ensure that the gate drive signal gout output by the first shift register unit 11 is at an invalid level of the first type of output control signal out′ or a first level signal vgl, the scan control signal fw received by the first shift register unit 11 can also be set to include a scan invalid pulse FIP, so as to ensure that the transistor used to transmit the first type of output control signal out′ in the output module 140 remains in the off state, thereby improving the accuracy of the gate drive signal gout output by the first shift register unit 11.

[0129] Optional, continue to refer to the references Figure 2 , Figure 12 and 18 In the first display frame T1, the input signal inf received by the first shift register unit 11 includes an input valid pulse IEP; the time of scanning the invalid pulse FIP covers the time of the input valid pulse IEP.

[0130] Specifically, in the first display frame T1, the scan invalid pulse FIP of the scan control signal fw in the first shift register unit 11 (as shown in the sixth-level shift register unit G6 in the figure) is set to cover the time of the input valid pulse IEP (as shown in the figure in the fifth-level gate drive signal gout5 valid pulse). In this way, during the process of the input signal inf controlling the input module 110 to be turned on, the scan invalid pulse FIP of the scan control signal fw can be transmitted to the first node N1 through the turned-on input module 110, so that the signal of the first node N1 of the first shift register unit 11 is always kept at a low level. This can further ensure that the output module 140 remains in the off state during the process when the first type of output control signal out′ is a valid pulse, so as to ensure that the gate drive signal gout output by the first shift register unit 11 is either the invalid level of the first type of output control signal out′ or the first level signal vgl.

[0131] Optional, refer to the reference Figure 1 and Figure 18 Each shift register unit G receives the same scan control signal fw; in the first display frame T1, the scan control signal fw also includes the scan valid level FEP located after the scan invalid pulse FIP; in the first mode Mode1, the drive circuit 10 also includes a second shift register unit 12; in the first display frame T1, in the second shift register unit 12, each valid pulse of the reset clock signal rstf includes two adjacent valid pulses, namely the fourth reset valid pulse REP4 and the fifth reset valid pulse REP5; the fourth reset valid pulse REP4 overlaps with the scan invalid pulse FIP; the fifth reset valid pulse REP5 overlaps with the scan valid level FEP.

[0132] Specifically, in the first mode (Mode1), the driving circuit 10 further includes a second shift register unit 12 that normally outputs an effective pulse of the gate drive signal gout. After the second shift register unit 12 outputs an effective level of the gate drive signal, it needs to reset the first node N1 and the second node N2 of the second shift register unit 12 through the reset clock signal it receives, so that the second node N2 becomes an effective level and the first node N1 becomes an ineffective level. In the first display frame T1, by setting the scan control signal fw to include the scan invalid pulse FIP, the signal of the first node N1 of the first shift register unit 11 can be kept at an invalid level. If the scan control signal fw is the scan invalid pulse FIP, the reset clock signal rstf of the second shift register unit 12 is the fourth reset valid pulse REP4. This will prevent the fourth reset valid pulse REP4 from being written into the second shift register unit 12, thereby preventing the second shift register unit 12 from being reset during this time period. At this time, by setting the reset clock signal rstf of the second shift register unit 12 to the fifth reset valid pulse REP5 after the scan control signal fw becomes valid, the fifth reset valid pulse REP5 can be written into the second shift register unit 12, so as to reset the first node N1 and the second node N2 of the second shift register unit 12, so as to avoid the signals of the first node N1 and the second node N2 from being unable to be reset effectively, thus affecting the accuracy of the gate drive signal gout output by the second shift register unit 12.

[0133] Optional, Figure 19 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, with reference to... Figure 19 When the shift register unit G includes multiple output modules 140, the shift register unit G may include a voltage regulator module 150 corresponding to each output module 140 and a bootstrap module 160 corresponding to each output module 140, thereby enabling stability control of the gate drive signal gout output by each output module 140.

[0134] Based on the above embodiments, optionally, Figure 20 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 21 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention, in conjunction with reference to... Figure 20 and Figure 21The shift register unit G also includes a set module 190; the set module 190 is used to receive at least a set signal grest and a first level signal vgl, and when the set signal GAS is at an active level, control the first level signal vgl as a gate drive signal gout; in the first display frame T1, the set signal grest includes at least one set active pulse GEP, and the input signal inf received by the first shift register unit 11 includes one input active pulse IEP; the time of at least one set active pulse GEP is after the time of the input active pulse IEP.

[0135] Specifically, the setting module 190 is electrically connected to the setting signal terminal GR and the first level signal terminal VGL to receive the grest provided by the setting signal terminal GR and the first level signal vgl provided by the first level signal terminal VGL. In the first display frame T1, the effective pulse GEP of the set signal grest is set after the effective pulse IEP of the input signal inf received by the first shift register unit 11. This allows the first shift register unit 11 to control the first node N1 to a low level after receiving the effective pulse IEP of the input signal inf through the effective pulse GEP of the set signal grest. This further ensures that when the first type of output control signal out′ received by the first shift register unit 11 is an effective pulse, the output module 140 of the first shift register unit 11 can continuously output an invalid level of the gate drive signal. This further ensures that the invalid level of the gate drive signal gout output by the first shift register unit 11 and other shift register units G located after the first shift register unit 11 allows the two sub-display areas of the display panel 100 to have different refresh frequencies.

[0136] The set module 190 may include a set transistor M11. The gate of the set transistor M11 is electrically connected to the set signal terminal GR and receives the set signal grest. The first terminal of the set transistor M11 is electrically connected to the first level signal terminal VGL and receives the first level signal vgl. The second terminal of the set transistor M11 is electrically connected to the gate drive signal terminal GOUT. When the set signal grest is a valid pulse, the set transistor M11 is turned on and the first level signal vgl is transmitted to the gate drive signal terminal GOUT.

[0137] It is understood that when the shift register unit includes multiple output modules, the set modules electrically connected to each output module can be the same set module or different set modules. This embodiment of the invention does not specifically limit this.

[0138] For example, Figure 22 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, as shown below. Figure 22As shown, when N≥2, the shift register unit G may include a set module 190 that corresponds one-to-one with each output module 140. For example, the first set module 191 is electrically connected to the first gate drive signal terminal GOUT1, and the second set module 192 is electrically connected to the second gate drive signal terminal GOUT2. In this way, each set module can clear the signal of the first node N1 received by each output module 140.

[0139] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the display panel provided in the embodiments of the present invention. Therefore, this display device possesses the technical features of the display panel and its driving method provided in the embodiments of the present invention, and can achieve the beneficial effects of the display panel provided in the embodiments of the present invention. Similarities can be found in the above description of the display panel provided in the embodiments of the present invention, and will not be repeated here.

[0140] For example, Figure 23 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 23 As shown, the display device 200 includes the display panel 100 provided in this embodiment of the invention. The display device 200 provided in this embodiment of the invention can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc., and this embodiment of the invention does not make any special limitations on these categories.

[0141] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: The driving circuit includes multiple cascaded shift register units. The shift register unit includes an input module, a reset module, a node inter-control module, and N output modules; N is a positive integer. Within the same shift register unit: the input module receives at least an input signal and a scan control signal to control the signal of the first node; the reset module receives at least a reset clock signal and the scan control signal to control the signal of the second node; the node inter-control module receives at least the signal of the first node and the signal of the second node, controls the signal of the second node based on the signal of the first node, and controls the signal of the first node based on the signal of the second node; the output modules receive at least the signal of the first node, the signal of the second node, a first level signal, and an output control signal to control the gate drive signal. Wherein, at least one of the gate drive signals of the i-th stage shift register unit is the input signal of the j-th stage shift register unit; i ≠ j, and i and j are both positive integers; Within each display frame of the display panel, both the reset clock signal and the output control signal include multiple valid pulses; The display panel's operating mode includes a first mode; the first mode includes at least one first display frame, and the driving circuit includes a first shift register unit; in the first display frame, at least a portion of the output control signals received by the first shift register unit are first type output control signals; in the first shift register unit, the interval between two adjacent valid pulses of the first type output control signals is a first interval time, and the interval between two adjacent valid pulses of the reset clock signal is a second interval time; the first interval time overlaps with the second interval time, and the first interval time is greater than the second interval time; In the first display frame, in the first shift register unit, the input signal includes a valid pulse, the reset clock signal includes a first reset valid pulse, and the first type of output control signal includes a first output valid pulse; Of the valid pulses of the reset clock signal, the first valid pulse following the valid pulse of the input signal is the first valid reset pulse. In each valid pulse of the first type of output control signal, the first valid pulse following the valid pulse of the input signal is the first valid output pulse; The timing of the first valid reset pulse precedes the timing of the first valid output pulse.

2. The display panel according to claim 1, characterized in that, In the first display frame, the reset clock signal of the first shift register unit further includes a second valid reset pulse; the time of the second valid reset pulse is before the time of the first valid reset pulse, and the first valid reset pulse and the second valid reset pulse are two adjacent valid pulses; the interval between the first valid reset pulse and the second valid reset pulse is the second interval time; In the first display frame, the first type of output control signal of the first shift register unit further includes a second valid output pulse; the time of the second valid output pulse is before the time of the first valid output pulse, and the first valid output pulse and the second valid output pulse are two adjacent valid pulses; the interval between the first valid output pulse and the second valid output pulse is the first interval time; The timing of the second valid output pulse precedes the timing of the second valid reset pulse.

3. The display panel according to claim 2, characterized in that, In the first display frame, in the first shift register unit, the reset clock signal further includes at least one third reset valid pulse located before the second reset valid pulse, and the first type of output control signal further includes at least one third output valid pulse located before the second output valid pulse; In the first type of output control signal, the time interval between the second valid output pulse and the third valid output pulse adjacent to the second valid output pulse is the third interval time; In the reset clock signal, the interval between the second valid reset pulse and the third valid reset pulse adjacent to the second valid reset pulse is the fourth interval time; The third interval time is equal to the fourth interval time.

4. The display panel according to claim 3, characterized in that, The first interval is longer than the third interval; the second interval is shorter than the fourth interval.

5. The display panel according to claim 3, characterized in that, The first interval time is equal to the third interval time; the second interval time is less than the fourth interval time.

6. The display panel according to claim 3, characterized in that, The first interval is greater than the third interval; the second interval is equal to the fourth interval.

7. The display panel according to claim 1, characterized in that, When N is greater than or equal to 2, in the same shift register unit, each output module receives a different output control signal, and the effective pulse time of the output control signal received by each shift register unit is shifted sequentially.

8. The display panel according to claim 7, characterized in that, In the same shift register unit, the output control signal received by the k-th output module is the k-th output control signal; the effective pulse time of the k-th output control signal is located before the effective pulse time of the (k+1)-th output control signal; k is a positive integer and k is less than N; The gate drive signal output by one of the first output module and the Nth output module of the i-th stage shift register unit is the input signal received by the input module of the j-th stage shift register unit.

9. The display panel according to claim 8, characterized in that, The reset clock signal of the shift register unit of the j-th stage is multiplexed as the first output control signal of the shift register unit of the (j+1)-th stage.

10. The display panel according to claim 8, characterized in that, The reset clock signal of the shift register unit of the j-th stage is multiplexed as the reset clock signal of the shift register unit of the (j+2)-th stage; and / or, The k-th output control signal of the j-th level shift register unit is multiplexed into the k-th output control signal of the (j+2)-th level shift register unit.

11. The display panel according to claim 1, characterized in that, When N equals 1, the gate drive signal of the j-th stage shift register is the input signal of the (j+1)-th stage shift register; j is a positive integer; The reset clock signal of the shift register unit of level j is multiplexed as the reset clock signal of the shift register unit of level j+4; and / or, The output control signal of the shift register unit of level j is multiplexed as the output control signal of the shift register unit of level j+4.

12. The display panel according to claim 1, characterized in that, In the first display frame, the scan control signal received by the first shift register unit includes a scan invalid pulse.

13. The display panel according to claim 12, characterized in that, In the first display frame, the input signal received by the first shift register unit includes a valid input pulse; the time of the scan invalid pulse covers the time of the valid input pulse.

14. The display panel according to claim 12, characterized in that, Each of the shift register units receives the same scan control signal; in the first display frame, the scan control signal also includes a scan valid level located after the scan invalid pulse; In the first mode, the driving circuit further includes a second shift register unit; in the first display frame, in the second shift register unit, each valid pulse of the reset clock signal includes two adjacent valid pulses, namely a fourth valid reset pulse and a fifth valid reset pulse; the fourth valid reset pulse overlaps with the scan invalid pulse; the fifth valid reset pulse overlaps with the scan valid level.

15. The display panel according to claim 1, characterized in that, The shift register unit also includes a set module; The setting module is used to receive at least a setting signal and the first level signal, and when the setting signal is an active level, control the first level signal as the gate drive signal; In the first display frame, the set signal includes at least one set valid pulse, and the input signal received by the first shift register unit includes one input valid pulse; the time of at least one set valid pulse is after the time of the input valid pulse.

16. The display panel according to claim 1, characterized in that, include: The display area is provided with multiple gate drive lines; each shift register unit is electrically connected to each of the gate drive lines respectively; In the first mode, the display area includes a first sub-display area and a second sub-display area; In the first display frame, the gate driving line located in the first sub-display area is the first gate driving line, and the gate driving line located in the second sub-display area is the second gate driving line; the effective pulse time of the gate driving signal transmitted by the first gate driving line is shifted sequentially, and the gate driving signal transmitted by the second gate driving line is at an invalid level.

17. The display panel according to claim 16, characterized in that, In the first mode, some display frames are second display frames; In the second display frame, the effective pulse time of the gate drive signal transmitted by each of the first gate drive lines and each of the second gate drive lines is shifted sequentially.

18. The display panel according to claim 1, characterized in that, The display panel also includes a second mode; In a display frame of the second mode, within the same shift register unit, the interval between two adjacent valid pulses of the output control signal is equal to the interval between two adjacent valid pulses of the reset clock signal.

19. The display panel according to claim 1, characterized in that, The node inter-control module includes a first inter-control transistor and a second inter-control transistor. In the same shift register unit: The gate of the first inter-controlling transistor is electrically connected to the second node, the first terminal of the first inter-controlling transistor receives the first level signal, and the second terminal of the first inter-controlling transistor is electrically connected to the first node; The gate of the second inter-control transistor is electrically connected to the first node, the first terminal of the second inter-control transistor receives the first level signal, and the second terminal of the second inter-control transistor is electrically connected to the second node.

20. A display device, characterized in that, include: The display panel according to any one of claims 1-19.

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