Gate structure and its fabrication method

Abstract

This invention discloses a gate structure and its fabrication method. The gate structure includes: a contact metal layer, a connecting post, and a gate body stacked together; wherein, the contact metal layer includes a Schottky contact portion and an edge portion; the Schottky contact portion forms a Schottky contact with a semiconductor layer; at least one first passivation layer is disposed between the edge portion and the semiconductor layer; at least one second passivation layer is disposed between the gate body and the contact metal layer; the second passivation layer has a first opening; the connecting post fills the first opening and connects the contact metal layer and the gate body. This invention, with lower process cost and difficulty, improves the thermomechanical stress of the semiconductor material around the gate and the parasitic capacitance of the gate and semiconductor material, thereby enhancing device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a gate structure and its fabrication method. Background Technology

[0002] High Electron Mobility Transistor (HEMT) devices based on gallium nitride (GaN), or GaN HEMT, are wide-bandgap radio frequency power semiconductor devices that form a two-dimensional electron gas (2DEG) based on the piezoelectric effect of GaN material. They offer advantages such as high voltage, high frequency, high power density, high efficiency, and operation at high junction temperatures. Whether enhancement-mode or depletion-mode, to reduce gate control delay and thus improve frequency response, the gate metal, a major component of the device, always contains a metal layer with excellent conductivity (e.g., Au or Al), and the total thickness of the gate metal typically reaches sub-micrometer levels (e.g., 500 μm or more), while the gate width is typically about 1 μm or narrower. The accompanying problems mainly include the following two aspects:

[0003] Firstly, the gate metal surface exhibits significant height variations, making it difficult to achieve ideal quality and density when dielectric material is deposited on the gate. In existing technologies, process optimization is necessary to ensure device reliability, thereby increasing process costs and complexity.

[0004] Secondly, the coefficient of thermal expansion of the gate (e.g., Au or Al) is much larger than that of GaN (4.8 ppm / °C), resulting in significant differences in the thermomechanical stress exerted by the gate metal on the semiconductor material surrounding the gate at different junction temperatures. Since GaN exhibits piezoelectricity, these differences in thermomechanical stress lead to variations in device performance; therefore, the presence of the gate metal becomes a crucial factor affecting the device's temperature stability. Furthermore, the large parasitic capacitance formed between the thick gate sidewalls and GaN also negatively impacts the device's high-frequency performance. Summary of the Invention

[0005] This invention provides a gate structure and its fabrication method, which improves the thermomechanical stress of the semiconductor material around the gate and the parasitic capacitance of the gate and semiconductor material with lower process cost and difficulty, thereby improving device performance.

[0006] According to one aspect of the present invention, a gate structure is provided, comprising: a contact metal layer, a connecting pillar, and a gate body stacked thereon;

[0007] The contact metal layer includes a Schottky contact portion and an edge portion; the Schottky contact portion forms a Schottky contact with the semiconductor layer; and at least one first passivation layer is disposed between the edge portion and the semiconductor layer.

[0008] At least one second passivation layer is disposed between the gate body and the contact metal layer; the second passivation layer is provided with a first opening; the connecting post fills the first opening and connects the contact metal layer and the gate body.

[0009] Optionally, the thickness of the contact metal layer is less than half the thickness of the first passivation layer.

[0010] Optionally, the thickness of the contact metal layer ranges from 40 nm to 50 nm.

[0011] Optionally, the positional relationship between the contact metal layer and the source field plate is such that the projection of the contact metal layer on the semiconductor layer overlaps with the projection of the source field plate on the semiconductor layer.

[0012] Optionally, the projection of the connecting post onto the semiconductor layer is a first projection, and the projection of the contact metal layer onto the semiconductor layer is a second projection;

[0013] The first projection is located within the second projection, and the area of ​​the first projection is smaller than the area of ​​the second projection.

[0014] Optionally, the first projection is located within the projection of the Schottky contact on the semiconductor layer.

[0015] Optionally, the area of ​​the first projection is smaller than the projected area of ​​the Schottky contact on the semiconductor layer.

[0016] Optionally, the projection of the contact metal layer onto the semiconductor layer is a second projection, and the projection of the gate body onto the semiconductor layer is a third projection.

[0017] The area of ​​the third projection is smaller than the area of ​​the second projection; and the volume of the gate body is larger than the volume of the contact metal layer.

[0018] Optionally, the projection of the connecting post onto the semiconductor layer is a first projection, and the projection of the gate body onto the semiconductor layer is a third projection.

[0019] The area of ​​the third projection is greater than the area of ​​the first projection; and the volume of the gate body is greater than the volume of the connecting post.

[0020] Optionally, the gate structure further includes: at least one metal interconnect layer;

[0021] The metal connection layer is located between the contact metal layer and the connection post; and / or, the metal connection layer is located between the connection post and the gate body.

[0022] Optionally, the material of the contact metal layer includes at least one of nickel or tungsten;

[0023] And / or, the material of the connecting post includes: tungsten;

[0024] And / or, the material of the gate body includes at least one of gold or aluminum.

[0025] According to another aspect of the present invention, a method for fabricating a gate structure is provided, comprising:

[0026] A contact metal layer is formed, a portion of which forms a Schottky contact with a semiconductor layer to form a Schottky contact portion of the contact metal layer, and another portion of which is located on at least one first passivation layer to form an edge portion of the contact metal layer.

[0027] At least one second passivation layer is formed on the contact metal layer, and a first opening is formed on the second passivation layer, the first opening exposing the contact metal layer;

[0028] The first opening is filled with conductive material to form a connecting post;

[0029] A gate body is formed on the connecting post; the connecting post connects the contact metal layer and the gate body.

[0030] Optionally, the process for forming the contact metal layer includes at least one of a metal sputtering-etching process and a peeling-stripping process;

[0031] And / or, the process for forming the connecting post includes: metal sputtering-etching process;

[0032] And / or, the process for forming the gate body includes at least one of a peel-off process and a deposition-etch forming process.

[0033] This invention employs a multi-layered gate structure, comprising a contact metal layer, connecting pillars, and a gate body, with the gate body positioned away from the semiconductor layer. This configuration offers several advantages. First, it reduces the ramp height of the dielectric layers (such as the first and second passivation layers), facilitating the use of lower process costs and complexity to improve the quality and density of the dielectric layers. Second, it reduces the metal volume near the semiconductor layer surface, preventing stress from the gate body affecting the semiconductor layer after heating, thus mitigating the impact of thermomechanical stress on the semiconductor layer and improving thermo-mechanical device instability (leakage) and reliability. Third, the greater distance between the gate body and the semiconductor layer reduces parasitic capacitance between the gate and the semiconductor layer, thereby improving the high-frequency performance of the device.

[0034] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A schematic diagram of a gate structure provided in an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of another gate structure provided in an embodiment of the present invention;

[0038] Figure 3 A flowchart illustrating a method for fabricating a gate structure according to an embodiment of the present invention;

[0039] Figures 4-7 This is a schematic diagram of the structure formed in each step of a method for fabricating a gate structure according to an embodiment of the present invention;

[0040] Figures 8-13 This is a schematic diagram of the structure formed in each step of a method for fabricating a gate structure according to an embodiment of the present invention. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0043] Figure 1 This is a schematic diagram of a gate structure provided in an embodiment of the present invention. See also... Figure 1 The gate structure includes a contact metal layer 310, a connecting pillar 320, and a gate body 330 stacked together. The contact metal layer 310 includes a Schottky contact portion and an edge portion; the Schottky contact portion forms a Schottky contact with the semiconductor layer 100; at least one first passivation layer 210 is disposed between the edge portion and the semiconductor layer 100. Exemplarily, the contact metal layer 310 is located within a gate trench 211 and forms a Schottky contact with the semiconductor layer 100; the gate trench 211 is formed by an opening in the first passivation layer 210; the contact metal layer 310 extends from within the gate trench 211 onto the first passivation layer 210.

[0044] The connecting post 320 is located on the side of the contact metal layer 310 away from the semiconductor layer 100, and the gate body 330 is located on the side of the connecting post 320 away from the contact metal layer 310. At least one second passivation layer is disposed between the gate body 330 and the contact metal layer 310. Figure 1 Two second passivation layers are shown as an example, namely second passivation layer 220 and second passivation layer 230; the second passivation layer is provided with a first opening; the connecting post 320 fills the first opening and connects the contact metal layer 310 and the gate body 330.

[0045] This invention employs a multi-layered stacked structure for the gate, comprising a contact metal layer 310, connecting pillars 320, and a gate body 330, such that the gate body 330 is positioned away from the semiconductor layer 100. This configuration offers several advantages. First, it reduces the ramp height of the dielectric layers (such as the first passivation layer 210 and the second passivation layer), facilitating the use of lower process costs and complexity to improve the quality and density of the dielectric layers. Second, it reduces the metal volume near the surface of the semiconductor layer 100, thus preventing stress on the gate body 330 from affecting the semiconductor layer 100 after heating, thereby mitigating the impact of thermomechanical stress on the semiconductor layer 100 and improving device instability (leakage) and reliability caused by thermo-mechanical factors. Third, the greater distance between the gate body 330 and the semiconductor layer 100 reduces the parasitic capacitance between the gate and the semiconductor layer 100, thereby improving the high-frequency performance of the device.

[0046] The above is the core inventive concept of this invention. The specific structures of the contact metal layer 310, the connecting post 320 and the gate body 330 will be described below.

[0047] See also Figure 1 Based on the above embodiments, optionally, the thickness of the contact metal layer 310 is as thin as possible. Specifically, the thickness can be close to that of the gate trench 211. Preferably, the thickness of the contact metal layer 310 is less than half the thickness of the first passivation layer 210. Preferably, the thickness of the contact metal layer 310 ranges from 40 nm to 50 nm.

[0048] It should be noted that, in the above embodiments, the connecting post 320 is shown to fill the first opening, that is, the upper surface of the connecting post 320 is flush with the upper surface of the second passivation layer 230, and the gate body 330 is located on the side of the second passivation layer 230 away from the semiconductor layer 100. This is not a limitation of the present invention. In other embodiments, the connecting post 320 may not fill the first opening, and correspondingly, the gate body 330 may partially fill the first opening.

[0049] Figure 2 This is a schematic diagram of another gate structure provided in an embodiment of the present invention. See also... Figure 2 Based on the above embodiments, optionally, the Schottky contact portion of the contact metal layer 310 completely covers the gate trench 211, and the edge portion of the contact metal layer 310 extends to the first passivation layer 210 outside the gate trench 211. Further, the semiconductor device also includes a source field plate 410, which connects to the source (…). Figure 2(Not shown in the diagram) Connection. In this embodiment of the invention, the extension range of the edge portion of the contact metal layer 310 on the first passivation layer 210 is further defined by defining the positional relationship between the contact metal layer 310 and the source field plate 410. Specifically, the projection of the contact metal layer 310 onto the semiconductor layer 100 overlaps with the projection of the source field plate 410 onto the semiconductor layer 100. That is, the projection of the edge portion of the contact metal layer 310 onto the semiconductor layer 100 overlaps with the projection of the source field plate 410 onto the semiconductor layer 100. This arrangement allows for continuous modulation of the electric field with the source field plate 410. Specifically, in practical applications, the requirements for gate-source capacitance vary. This embodiment of the invention allows for flexible adjustment of the position and shape of the source field plate 410, thereby flexibly adjusting the gate-source capacitance as needed. Therefore, the structure provided by this embodiment of the invention has greater inclusiveness and adaptability. For example, when the main body of the source field plate 410 overlaps with the projections of the gate body 330 and the contact metal layer 310, a composite gate-source capacitance is formed, and gate-source capacitances are formed between the main body of the source field plate 410 and the gate body 330 and the contact metal layer 310 respectively.

[0050] Furthermore, within the extended plane of the source field plate 410, the source field plate 410 is located between the connecting post 320 and the drain ( Figure 2 (Not shown) and the source field plate 410 and the connecting post 320 do not overlap, and the space between the source field plate 410 and the connecting post 320 is a second passivation layer.

[0051] Alternatively, the source field plate 410 can be positioned in various ways, such as... Figure 1 As shown, in one embodiment, the second passivation layer comprises two layers, with a source field plate 410 disposed between the two second passivation layers. The source field plate 410 is insulated from the gate. The connecting post 320 is the structure between the contact metal layer 310 and the gate body 330, and the second passivation layer is a film layer between the contact metal layer 310 and the gate body 330. Disposing the source field plate 410 between the two second passivation layers is equivalent to placing the source field plate 410 between the contact metal layer 310 and the gate body 330. This configuration allows the source field plate 410 to be fabricated before the gate body 330. Therefore, during the fabrication of the source field plate 410, the device surface is relatively flat. Compared with existing technologies, this avoids the step-up issues of the source field plate 410, which is beneficial for reducing the thickness of the source field plate 410. It also improves the step coverage of the source field plate 410 with lower process costs and difficulty, thereby improving device performance. Furthermore, the thinner thickness of the contact metal layer 310 and the thinner thickness of the source field plate 410 help reduce the gate-source parasitic capacitance Cgs and further improve the high-frequency characteristics of the device.

[0052] In another embodiment, the source field plate 410 is disposed on the side of at least one second passivation layer away from the contact metal layer 310. This arrangement helps to reduce the number of second passivation layers; for example, the source field plate 410 and the gate body 330 are fabricated on the same layer.

[0053] There are multiple ways to connect the source field plate 410 to the source electrode. In one embodiment, an opening is provided in the second passivation layer 230 to connect the source field plate 410 and the source electrode.

[0054] In another implementation, the interconnect metal that needs to be connected to the source location is fabricated simultaneously with the source field plate 410, which is manifested by extending the interconnect metal to the source (i.e., the location of the passive region). This arrangement helps to avoid making openings in the second passivation layer 230.

[0055] See also Figure 1 and Figure 2 Based on the above embodiments, optionally, the area of ​​the connecting post 320 is smaller than the area of ​​the contact metal layer 310, thereby reducing the volume of the connecting post 320. Specifically, the projection of the connecting post 320 onto the semiconductor layer 100 is a first projection, and the projection of the contact metal layer 310 onto the semiconductor layer 100 is a second projection; the first projection is located within the second projection, and the area of ​​the first projection is smaller than the area of ​​the second projection. Preferably, the first projection is located within the gate trench 211, that is, the first projection is located within the projection of the Schottky contact portion onto the semiconductor layer 100. Further, the area of ​​the first projection is smaller than the area of ​​the gate trench 211, that is, the area of ​​the first projection is smaller than the projection area of ​​the Schottky contact portion onto the semiconductor layer 100. In addition to filling the connecting post 320, the gate trench 211 is also filled with a second passivation layer. The advantage of this configuration is that it reduces the volume of the connecting post 320, thereby helping to reduce the parasitic capacitance generated between the connecting post 320 and other metals, thereby improving the high-frequency characteristics of the device.

[0056] See also Figure 1 and Figure 2 Based on the above embodiments, optionally, the area of ​​the gate body 330 is smaller than the area of ​​the contact metal layer 310. Specifically, the projection of the contact metal layer 310 onto the semiconductor layer 100 is a second projection, and the projection of the gate body 330 onto the semiconductor layer 100 is a third projection; the area of ​​the third projection is smaller than the area of ​​the second projection. Furthermore, the volume of the gate body 330 is larger than the volume of the contact metal layer 310. The advantage of this arrangement is that the volume of the gate near the surface of the semiconductor layer 100 is reduced, which helps improve device instability (leakage) and reliability caused by thermal stress.

[0057] See also Figure 1 and Figure 2Based on the above embodiments, optionally, the area and volume of the gate body 330 are both larger than those of the connecting post 320. Specifically, the projection of the connecting post 320 onto the semiconductor layer 100 is a first projection, and the projection of the gate body 330 onto the semiconductor layer 100 is a third projection; the area of ​​the third projection is larger than the area of ​​the first projection; and the volume of the gate body 330 is larger than the volume of the connecting post 320. In summary, the gate body 330, which is furthest from the semiconductor layer 100, has the largest volume, and at least one second passivation layer is provided between the gate body 330 and the semiconductor layer 100 to prevent stress caused by the gate body 330 after heating from affecting the semiconductor layer 100. This helps to further improve the device instability (e.g., leakage current) and reliability caused by thermal stress while effectively reducing the gate resistance.

[0058] Based on the above embodiments, optionally, the metal layers such as the contact metal layer 310, the connecting pillar 320, and the gate body 330 can be a single metal or composed of at least two metals. Specifically, the gate structure further includes: at least one metal connection layer; the metal connection layer is located between the contact metal layer 310 and the connecting pillar 320; and / or, the metal connection layer is located between the connecting pillar 320 and the gate body 330. In this embodiment of the invention, metal connection layers can be provided between other metal layers besides the metal layer in contact with the semiconductor layer 100. The material of the metal connection layer can be, for example, titanium (Ti) or titanium nitride (TiN). The metal connection layer begins as an adhesion layer and an interdiffusion barrier layer, and ends with TiN as a capping layer.

[0059] Based on the above embodiments, optionally, the material of the contact metal layer 310 includes at least one of nickel (Ni) or tungsten (W). This arrangement facilitates the formation of a semiconductor contact between the contact metal layer 310 and the semiconductor layer 100. Furthermore, the coefficient of thermal expansion of tungsten is relatively close to that of the semiconductor layer 100 (e.g., GaN), which helps to mitigate the problem of device instability caused by thermal stress.

[0060] Based on the above embodiments, optionally, the material of the connecting post 320 includes tungsten. Tungsten's coefficient of thermal expansion is close to that of the semiconductor layer 100 (e.g., GaN), which is beneficial for mitigating device instability caused by thermal stress. Furthermore, the diameter of the first opening (connecting post 320) is generally set to a few tenths of a micrometer, and the process of using tungsten to fill the first opening is mature.

[0061] Based on the above embodiments, optionally, the material of the gate body 330 includes at least one of gold (Au) or aluminum (Al). Gold and aluminum have better conductivity, which is beneficial for improving device performance.

[0062] It should be noted that in the above embodiments, the number of first passivation layers 210 is shown to be one, which is not a limitation of the present invention. In other embodiments, two first passivation layers 210 may be provided, or more first passivation layers 210 may be provided as needed.

[0063] It should also be noted that in the above embodiments, the gate trench 211 is formed by opening on the first passivation layer 210, which is not a limitation of the present invention. In other embodiments, the gate trench 211 can be extended to the semiconductor layer 100, that is, the gate trench 211 is formed by opening on the first passivation layer 210 and forming a groove on the semiconductor layer 100.

[0064] This invention also provides a method for fabricating a gate structure, which can be used to prepare the gate structure provided in any embodiment of this invention, and its technical principle and the resulting effects are similar. The method for fabricating the gate structure will be described in detail below with reference to the accompanying drawings, and the beneficial effects of this invention will be explained from the perspective of the fabrication process.

[0065] Figure 3 This is a flowchart illustrating a method for fabricating a gate structure according to an embodiment of the present invention. Figures 4-7 This is a schematic diagram of the structure formed in each step of a method for fabricating a gate structure according to an embodiment of the present invention. See also... Figures 3-7 The method for fabricating the gate structure includes the following steps:

[0066] S110, a contact metal layer 310 is formed. A portion of the contact metal layer 310 forms a Schottky contact with the semiconductor layer 100 to form a Schottky contact portion of the contact metal layer 310. Another portion of the contact metal layer 310 is located on at least one first passivation layer 210 to form an edge portion of the contact metal layer 310.

[0067] Specifically, S110, the method for forming the contact metal layer 310 includes the following steps:

[0068] S111, A gate trench 211 is formed by opening an opening in the first passivation layer 210, and the gate trench 211 exposes the semiconductor layer 100.

[0069] The first passivation layer 210 is located on the semiconductor layer 100. The semiconductor layer 100 can also be referred to as an epitaxial layer. Exemplarily, the semiconductor layer 100 includes a nucleation layer, a buffer layer, a channel layer, and a barrier layer. The nucleation layer and buffer layer are used for lattice matching between the substrate and the channel layer. The channel layer and the barrier layer form a heterojunction structure, and a two-dimensional electron gas can be formed at the heterojunction interface between the channel layer and the barrier layer. Specifically, the material of the nucleation layer can be, for example, gallium nitride (GaN) or aluminum nitride (AlN) or other nitrides; the material of the buffer layer can be, for example, gallium nitride (GaN) or aluminum nitride (AlN) or other nitrides; the material of the channel layer can be, for example, GaN or other semiconductor materials; and the material of the barrier layer can be, for example, aluminum gallium nitride (AlGaN) or indium gallium nitride (InGaN). Therefore, the semiconductor layer 100 can be one or more combinations of common semiconductor layers 100 such as AlN, GaN, AlGaN, and InGaN.

[0070] S112. A contact metal layer 310 is formed in the gate trench 211. The contact metal layer 310 forms a Schottky contact with the semiconductor layer 100. The contact metal layer 310 extends from the gate trench 211 to the first passivation layer 210.

[0071] The contact metal layer 310 should be as thin as possible. Specifically, its thickness can be close to that of the gate trench 211; preferably, the thickness of the contact metal layer 310 is less than half the thickness of the first passivation layer 210. Preferably, the thickness of the contact metal layer 310 ranges from 40 nm to 50 nm. For metal layers of tens of nanometers, such as the contact metal layer 310, a metal sputtering process can be used. Therefore, optionally, the process for forming the contact metal layer 310 includes at least one of a metal sputtering-etching process and a peel-off process. Specifically, the metal sputtering-etching process (i.e., sputter+etch process) can involve first forming a complete metal layer on the first passivation layer 210 by metal sputtering, and then using an etching process to remove the excess metal layer, retaining the pattern of the contact metal layer 310. The lift-off process can be specifically as follows: First, a full layer of photoresist is formed on the first passivation layer 210, and the photoresist is exposed and developed to expose the opening where the contact metal layer 310 needs to be formed; then, the contact metal layer 310 is formed in the opening by metal sputtering; finally, the photoresist and the metal layer on the photoresist are removed.

[0072] In this embodiment of the invention, the contact metal layer 310 can be formed using a metal sputtering-etching process and a peel-off process, eliminating the need for trailing corrosion, thereby reducing costs and pollution. Furthermore, using a metal sputtering process to form the metal has the following advantages: First, the wafer can be preheated, which facilitates degassing and reduces interface impurities. Simultaneously, deposition is performed at a high initial temperature, improving the quality of the initial deposited layer material and its adhesion to the underlying semiconductor layer surface. Second, the gate trench can be bombarded with ions (e.g., N+) before deposition, which is expected to further improve interface characteristics. Third, during the deposition process, metal atoms bombard the deposited surface, which is beneficial for further enhancing interface adhesion and metal material density.

[0073] S120. At least one second passivation layer is formed on the contact metal layer 310, and a first opening 321 is formed on the second passivation layer, the first opening 321 exposing the contact metal layer 310.

[0074] S130. The first opening 321 is filled with conductive material to form a connecting post 320.

[0075] Optionally, the process for forming the connector post 320 includes a metal sputtering-etching process. Specifically, firstly, a full layer of photoresist is formed on the second passivation layer, and the photoresist is exposed and developed to expose the opening where the connector post 320 is to be formed; then, the connector post 320 is formed in the opening by metal sputtering; finally, the photoresist and the metal layer on the photoresist are removed.

[0076] S140, A gate body 330 is formed on the connecting post 320; the connecting post 320 connects the contact metal layer 310 and the gate body 330.

[0077] Optionally, the process for forming the gate body 330 includes at least one of a lift-off process and a deposition-etching process. Specifically, the deposition-etching process may involve first depositing a full-length metal layer on the first passivation layer 210, and then using an etching process to remove excess metal, retaining the pattern of the gate body 330. The lift-off process may involve first forming a full-length photoresist layer on the connecting pillar 320, and then exposing and developing the photoresist to expose the opening where the gate body 330 will be formed; then depositing a contact metal layer 310 within this opening; and finally removing the photoresist and the metal layer on top of it.

[0078] Based on the above embodiments, the gate structure provided by the present invention can also reduce the ramp height of the source field plate, which helps to avoid the source field plate from climbing the steps, thereby greatly reducing the thickness of the source field plate; at the same time, the area overlapping with the gate can be greatly reduced, thereby further reducing the gate-source voltage Cgs and reducing production costs. Figures 8-13This is a schematic diagram of the structure formed in each step of a method for fabricating a gate structure according to an embodiment of the present invention. See also... Figures 8-13 The specific fabrication method involving the source field plate is as follows:

[0079] S210, A first passivation layer 220 is formed on the contact metal layer 310.

[0080] S220, a source field plate 410 is formed on the first and second passivation layers 220.

[0081] Since the source field plate 410 does not require climbing steps, its thickness is relatively thin. For example, the thickness of the source field plate 410 ranges from 40 nm to 50 nm. For metal layers of tens of nanometers, metal sputtering can be used. Therefore, optionally, the process for forming the source field plate 410 includes at least one of a metal sputtering-etching process and a peel-off process. The beneficial effects of the metal sputtering process are similar to those in the aforementioned embodiments and will not be repeated here. Specifically, the metal sputtering-etching process can involve first forming a complete metal layer on the passivation layer 220 by metal sputtering, and then using an etching process to remove the excess metal layer, retaining the pattern of the source field plate 410. The peel-off process can be specifically as follows: first, a whole layer of photoresist is formed on the second passivation layer 220, and the photoresist is exposed and developed to expose the opening where the source field plate 410 needs to be formed; then, the source field plate 410 is formed in the opening by metal sputtering; finally, the photoresist and the metal layer on the photoresist are removed.

[0082] S230, a second passivation layer 230 is formed on the source field plate 410.

[0083] S240, A first opening 321 is formed on the two second passivation layers, exposing the contact metal layer 310; and a photoresist 510 is formed on the second passivation layer 230, and the photoresist 510 is exposed and developed to form a second opening 520, with the first opening 321 and the second opening 520 overlapping.

[0084] S250, fill the first opening 321 with conductive material to form a connecting post 320; and remove the photoresist 520 and the metal layer on the photoresist 520.

[0085] As can be seen from the above steps, the process for forming the connecting post 320 is a metal sputtering-etching process.

[0086] S260, A gate body 330 is formed on the connecting post 320; the connecting post 320 connects the contact metal layer 310 and the gate body 330.

[0087] Optionally, the process for forming the gate body 330 includes at least one of a lift-off process and a deposition-etching process. Specifically, the deposition-etching process may involve first depositing a full-length metal layer on the first passivation layer 210, and then using an etching process to remove excess metal, retaining the pattern of the gate body 330. The lift-off process may involve first forming a full-length photoresist layer on the connecting pillar 320, and then exposing and developing the photoresist to expose the opening where the gate body 330 will be formed; then depositing a contact metal layer 310 within this opening; and finally removing the photoresist and the metal layer on top of it.

[0088] In summary, the embodiments of the present invention, by configuring the gate as a multi-layered stacked structure, including a contact metal layer 310, connecting pillars 320, and a gate body 330, elevate the gate body 330 to a side away from the semiconductor layer 100. This configuration has several advantages. First, it reduces the ramp height of the dielectric layers such as the first passivation layer 210 and the second passivation layer, which facilitates improving the quality and density of the dielectric layers with lower process costs and complexity. Second, it reduces the metal volume of the gate near the surface of the semiconductor layer 100. For example, it can prevent the stress generated by the gate body 330 after heating from affecting the semiconductor layer 100, thereby mitigating the impact of thermomechanical stress on the semiconductor layer 100 and improving the device's instability (leakage) and reliability caused by thermo-mechanical factors. Third, the greater distance between the gate body 330 and the semiconductor layer 100 reduces the parasitic capacitance between the gate and the semiconductor layer 100, thus improving the high-frequency performance of the device. Fourthly, the ramp height of the source field plate 410 is reduced, which helps to avoid the source field plate 410 climbing steps, thereby greatly reducing the thickness of the source field plate 410; at the same time, the area overlapping with the gate can be greatly reduced, thereby further reducing the gate-source voltage Cgs and reducing production costs.

[0089] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0090] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gate structure, characterized in that, include: A contact metal layer, connecting pillars, and gate body are stacked together; The contact metal layer includes a Schottky contact portion and an edge portion; the Schottky contact portion forms a Schottky contact with the semiconductor layer; and at least one first passivation layer is disposed between the edge portion and the semiconductor layer. At least one second passivation layer is disposed between the gate body and the contact metal layer; the second passivation layer is provided with a first opening; the connecting post fills the first opening and connects the contact metal layer and the gate body; The positional relationship between the contact metal layer and the source field plate is such that the projection of the contact metal layer on the semiconductor layer overlaps with the projection of the source field plate on the semiconductor layer.

2. The gate structure according to claim 1, characterized in that, The thickness of the contact metal layer is less than half the thickness of the first passivation layer.

3. The gate structure according to claim 1, characterized in that, The thickness of the contact metal layer ranges from 40 nm to 50 nm.

4. The gate structure according to claim 1, characterized in that, The projection of the connecting post onto the semiconductor layer is a first projection, and the projection of the contact metal layer onto the semiconductor layer is a second projection; The first projection is located within the second projection, and the area of ​​the first projection is smaller than the area of ​​the second projection.

5. The gate structure according to claim 4, characterized in that, The first projection is located within the projection of the Schottky contact on the semiconductor layer.

6. The gate structure according to claim 5, characterized in that, The area of ​​the first projection is smaller than the projected area of ​​the Schottky contact on the semiconductor layer.

7. The gate structure according to claim 1, characterized in that, The projection of the contact metal layer onto the semiconductor layer is a second projection, and the projection of the gate body onto the semiconductor layer is a third projection. The area of ​​the third projection is smaller than the area of ​​the second projection; and the volume of the gate body is larger than the volume of the contact metal layer.

8. The gate structure according to claim 1, characterized in that, The projection of the connecting post onto the semiconductor layer is the first projection, and the projection of the gate body onto the semiconductor layer is the third projection. The area of ​​the third projection is greater than the area of ​​the first projection; and the volume of the gate body is greater than the volume of the connecting post.

9. The gate structure according to claim 1, characterized in that, Also includes: At least one metal bonding layer; The metal connection layer is located between the contact metal layer and the connecting post; And / or, the metal interconnect layer is located between the interconnect post and the gate body.

10. The gate structure according to claim 1, characterized in that, The material of the contact metal layer includes at least one of nickel or tungsten; And / or, the material of the connecting post includes: tungsten; And / or, the material of the gate body includes at least one of gold or aluminum.

11. A method for fabricating a gate structure, characterized in that, include: A contact metal layer is formed, a portion of which forms a Schottky contact with a semiconductor layer to form a Schottky contact portion of the contact metal layer, and another portion of which is located on at least one first passivation layer to form an edge portion of the contact metal layer. At least one second passivation layer is formed on the contact metal layer, and a first opening is formed on the second passivation layer, the first opening exposing the contact metal layer; The first opening is filled with conductive material to form a connecting post; A gate body is formed on the connecting post; The connecting post connects the contact metal layer and the gate body; A source field plate is formed on the second passivation layer of the first layer. The positional relationship between the contact metal layer and the source field plate is such that the projection of the contact metal layer on the semiconductor layer overlaps with the projection of the source field plate on the semiconductor layer.

12. The method for fabricating the gate structure according to claim 11, characterized in that, The process for forming the contact metal layer includes at least one of a metal sputtering-etching process and a peeling-stripping process; And / or, the process for forming the connecting post includes: metal sputtering-etching process; And / or, the process for forming the gate body includes at least one of a peel-off process and a deposition-etch forming process.

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