Semiconductor device and method of manufacturing the same
By employing an alternating stacked structure of metal and isolation layers in semiconductor devices, combined with a design of unequal-height metal oxide layers, barrier layers, and a first insulating layer, the problems of leakage current and insufficient performance in semiconductor devices are solved, achieving higher electrical performance and yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2024-04-12
- Publication Date
- 2026-07-21
AI Technical Summary
As the feature size of semiconductor devices shrinks, manufacturing costs become high and yields become low. Existing semiconductor devices suffer from leakage current and insufficient performance.
The stacked structure employs alternating metal layers and isolation layers to form a connection structure that runs through the stacked structure. This structure includes a metal core, a metal oxide layer, and a barrier layer. The top surfaces of the metal oxide layer and the barrier layer are not at the same height, and the metal core is isolated by direct contact with the sidewall of the metal core through the first insulating layer, thereby reducing leakage current.
It effectively prevents the diffusion of metal ions within the metal core, improves the electrical performance and reliability of semiconductor devices, reduces leakage current, and enhances the overall performance of the device.
Smart Images
Figure CN118354604B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] With the continuous development of technology, semiconductor devices are being used more and more widely. For example, semiconductor devices can include transistors, which typically include a source region, a drain region, a channel region located between the source and drain regions, a gate dielectric layer located at least on the channel region, and a gate located on the gate dielectric layer. The transistor uses the electric field formed by the gate to control the amount of induced charge in the channel region, thereby changing the state of the channel region and thus achieving the effect of controlling the drain current.
[0003] As the feature size of semiconductor devices shrinks, manufacturing costs are increasing and yields are decreasing. The development of planar semiconductor devices has reached a bottleneck, and three-dimensional semiconductor devices, such as 3D NAND flash memory, have become the mainstream development trend. However, existing semiconductor devices still have many shortcomings and require further improvement to effectively enhance their performance and reliability. Summary of the Invention
[0004] In view of the above problems, this application provides a semiconductor device and a method for manufacturing the same, so as to reduce the leakage current of the semiconductor device and improve the performance of the semiconductor device.
[0005] According to some embodiments, a first aspect of this application provides a semiconductor device comprising: a stacked structure including alternating metal layers and isolation layers; a connection structure extending through the stacked structure, the connection structure including a metal core located within the stacked structure, a metal oxide layer located on a sidewall of the metal core, and a barrier layer located between the metal oxide layer and the metal core; and a first insulating layer directly contacting the sidewall of the metal core; wherein the top surfaces of the metal oxide layer and the barrier layer are not at the same height, and the metal oxide layer is in direct contact with the stacked structure.
[0006] According to some embodiments, a second aspect of this application provides a method for fabricating a semiconductor device, comprising: forming a stacked structure, the stacked structure including alternating metal layers and isolation layers; forming a connection structure extending through the stacked structure, the connection structure including a metal core located within the stacked structure, a metal oxide layer located on a sidewall of the metal core, and a barrier layer located between the metal oxide layer and the metal core, wherein the top surfaces of the metal oxide layer and the barrier layer are not of equal height, and the metal oxide layer is in direct contact with the stacked structure; and forming a first insulating layer, the first insulating layer being in direct contact with the sidewall of the metal core.
[0007] The semiconductor device and its fabrication method provided in this application embodiment utilize a connection structure that penetrates the stacked structure. The connection structure includes a metal core within the stacked structure, a metal oxide layer on the sidewall of the metal core, and a barrier layer between the metal oxide layer and the metal core. The barrier layer prevents metal ions within the metal core from diffusing into the metal oxide layer, thereby ensuring the performance of the metal oxide layer. The top surfaces of the metal oxide layer and the barrier layer are not of equal height and are in direct contact with the stacked structure. A first insulating layer directly contacts the sidewall of the metal core. Using the first insulating layer to isolate the metal cores reduces leakage current and improves the performance of the semiconductor device. Attached Figure Description
[0008] Figure 1 This is a schematic diagram of a semiconductor device in one embodiment of this application;
[0009] Figure 2 This is another schematic diagram of a semiconductor device according to an embodiment of this application;
[0010] Figure 3 This is a first partial enlarged view of the metal oxide layer and the barrier layer in an embodiment of this application;
[0011] Figure 4 This is a second partial enlarged view of the metal oxide layer and the barrier layer in one embodiment of this application;
[0012] Figure 5 This is a third partial enlarged view of the metal oxide layer and the barrier layer in one embodiment of this application;
[0013] Figure 6 This is a fourth partial enlarged view of the metal oxide layer and barrier layer in one embodiment of this application;
[0014] Figure 7 This is a fifth partial enlarged view of the metal oxide layer and barrier layer in one embodiment of this application;
[0015] Figure 8 This is a sixth partial enlarged view of the metal oxide layer and barrier layer in one embodiment of this application;
[0016] Figure 9 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;
[0017] Figure 10 This is a schematic diagram of the stacked structure formed in one embodiment of this application;
[0018] Figure 11 This is a schematic diagram of the hole structure formed in one embodiment of this application;
[0019] Figure 12This is a schematic diagram of the sacrificial material after its formation in one embodiment of this application;
[0020] Figure 13 This is a schematic diagram of the metal oxide layer after its formation in one embodiment of this application;
[0021] Figure 14 This is a schematic diagram of the metal material after its formation in one embodiment of this application;
[0022] Figure 15 This is a schematic diagram showing the formation of the protective material in one embodiment of this application;
[0023] Figure 16 This is a schematic diagram showing the formation of a recess in one embodiment of this application;
[0024] Figure 17 This is a schematic diagram showing the formation of the first insulating layer in one embodiment of this application;
[0025] Figure 18 for Figure 17 A magnified view of a portion of point A in the middle.
[0026] Explanation of reference numerals in the attached figures:
[0027] 10-Stacked structure; 11-Metal layer;
[0028] 12-Isolation layer; 13-Porous structure;
[0029] 14-Metal oxide materials; 15-Barrier materials;
[0030] 16-Metallic materials; 17-Sacrificial materials;
[0031] 18 - Third hole; 19 - Protective material;
[0032] 20 - Connection structure; 21 - Metal core;
[0033] 22-Barrier layer; 23-Metal oxide layer;
[0034] 24 - Depression; 30 - First insulating layer;
[0035] 40 - Second insulating layer; 50 - Third insulating layer;
[0036] 60 - Transistor; 70 - Protective layer. Detailed Implementation
[0037] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0038] See Figure 1 , Figure 1 This is a schematic diagram of a semiconductor device according to an embodiment of the present application. The semiconductor device includes a stacked structure 10, a connection structure 20, and a first insulating layer 30. The stacked structure 10 includes alternately arranged metal layers 11 and insulating layers 12, and the stacking direction can be vertical, such as... Figure 1 The Z direction is shown.
[0039] Both the metal layer 11 and the insulating layer 12 can be provided with at least two layers. For example, such as... Figure 1 As shown, the metal layer 11 has four layers and the isolation layer 12 has five layers. The four metal layers 11 and the five isolation layers 12 are arranged alternately in the vertical direction. There is a metal layer 11 between two adjacent isolation layers 12 and an isolation layer 12 between two adjacent metal layers 11.
[0040] The metal layer 11 is made of a metallic material, such as tungsten or its alloys. The insulating layer 12 is made of an insulating material to isolate the adjacent metal layer 11. For example, the insulating layer 12 is made of silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, etc. Silicon oxide can be generated by tetraethoxysilane (TEOS).
[0041] In some possible embodiments, the stacked structure 10 is located above a substrate (not shown), which may include, but is not limited to, a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, an epitaxial silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, or a substrate made of other suitable materials. Those skilled in the art will readily understand that various desired active and / or passive components may be further formed on or within the substrate according to actual device requirements.
[0042] A second insulating layer 40 may be disposed between the stacked structure 10 and the substrate. A device structure may also be formed within the second insulating layer 40, such as at least one transistor 60. In some possible examples, the second insulating layer 40 comprises at least two layers of different materials. For example, the material of the layer closer to the substrate may include silicon oxide, silicon nitride, etc., while the material of the layer farther from the substrate may include aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, etc. The transistor 60 includes a source, a drain, a gate, and a channel. The source and drain are disposed opposite to each other. For example, the drain is exposed on the top surface of the layer of the second insulating layer 40 closest to the substrate, and the source is located inside this layer and in contact with the substrate. The channel may be cylindrical, with its bottom in contact with the source and its opening in contact with the drain. For example, a portion of the drain extends into the opening, and an insulating material is filled between the source and drain. The gate surrounds the channel and is spaced apart from the channel.
[0043] Continue reading Figure 1 The connecting structure 20 penetrates the stacked structure 10 and includes a metal core 21, a metal oxide layer 23, and a barrier layer 22. The metal core 21 is located within and penetrates the stacked structure 10. Figure 1 As shown, the top surface of the metal core 21 is exposed to the top surface of the stacked structure 10, and the top end of the metal core 21 can extend outward from the stacked structure 10 for external connection. The bottom surface of the metal core 21 is exposed to the bottom surface of the stacked structure 10, and the bottom end of the metal core 21 can extend outward from the stacked structure 10. The metal core 21 can extend along the stacking direction of the stacked structure 10 to facilitate the fabrication of the metal core 21. The metal core 21 is made of a metallic material, such as tungsten and its alloys.
[0044] A metal oxide layer 23 is located on the sidewall of the metal core 21, and a barrier layer 22 is located between the metal oxide layer 23 and the metal core 21. By using the barrier layer 22 to separate the metal oxide layer 23 from the metal core 21, the diffusion of metal ions from the metal core 21 into the metal oxide layer 23 can be prevented, thereby ensuring the insulating properties of the metal oxide layer 23. The metal oxide layer 23 isolates the metal core 21 and / or the barrier layer 22 from the stacked structure 10, thereby ensuring the electrical performance of the semiconductor device.
[0045] In this structure, the barrier layer 22 is in direct contact with the sidewall of the metal core 21, and the metal oxide layer 23 is in direct contact with the sidewall of the barrier layer 22 away from the metal core 21 (i.e., the outer sidewall of the barrier layer 22). The material of the barrier layer 22 may include titanium nitride, tantalum nitride, etc. The metal oxide layer 23 is in direct contact with the stacked structure 10. For example, the sidewall of the metal oxide layer 23 away from the metal core 21 (i.e., the outer sidewall of the metal oxide layer 23) is in direct contact with the stacked structure 10, so as to use the metal oxide layer 23 to provide insulation and isolation for the stacked structure 10.
[0046] In some possible examples, the two ends of the metal oxide layer 23 are at least flush with the metal layers 11 located on both sides of the stacked structure 10, thereby ensuring that the metal oxide layer 23 can separate each metal layer 11 from the metal core 21 and / or the barrier layer 22. The material of the metal oxide layer 23 may include hafnium silicon oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide, etc. In this way, the metal oxide layer 23 has a high dielectric constant, which can improve its insulation performance.
[0047] Continue reading Figure 1 The top surfaces of the metal oxide layer 23 and the barrier layer 22 are not at the same height; that is, the top surfaces of the metal oxide layer 23 and the barrier layer 22 are not flush. Specifically, during the formation of the metal oxide layer 23 and the barrier layer 22, by adjusting the etching process parameters, the etching gas or etching solution can be used to etch the metal oxide layer 23 and the barrier layer 22 at different rates, thereby forming a metal oxide layer 23 and a barrier layer 22 with a height difference on their top surfaces.
[0048] In one embodiment, the top surface of the metal oxide layer 23 is higher than the top surface of the barrier layer 22, that is, the top surface of the barrier layer 22 is lower than the top surface of the metal oxide layer 23.
[0049] As another embodiment, see Figures 2 to 4 , Figure 2 This is another schematic diagram of a semiconductor device according to an embodiment of this application. Figure 3 This is a first partial enlarged view of the metal oxide layer and barrier layer in one embodiment of this application. Figure 4 This is a second partial enlarged view of the metal oxide layer and barrier layer in one embodiment of this application. (See attached image.) Figures 2 to 4 As shown, the top surface of the barrier layer 22 is higher than the top surface of the metal oxide layer 23, meaning the top surface of the metal oxide layer 23 is lower than the top surface of the barrier layer 22. This improves the barrier effect of the barrier layer 22 and effectively prevents the metal oxide layer 23 from contacting the metal core 21.
[0050] In some possible implementations, such as Figure 4 As shown, the barrier layer 22 directly contacts the top surface of the metal oxide layer 23. The outermost wall of the barrier layer 22 protrudes outwards away from the metal core 21, extending to the top surface of the metal oxide layer 23 to achieve contact with it. This allows for an increase in the width of both the barrier layer 22 and the metal core 21, thereby reducing their resistance. In the example where the topmost side of the stacked structure 10 is the isolation layer 12, this outermost wall can also extend above the stacked structure 10.
[0051] See Figure 5 , Figure 5This is a third partial enlarged view of the metal oxide layer and barrier layer in one embodiment of this application. In one embodiment, the top surface of the barrier layer 22 is higher than the top surface of the stacked structure 10, meaning the top end of the barrier layer 22 protrudes from the top end of the stacked structure 10. The top surface of the metal oxide layer 23 may or may not be at the same height as the top surface of the stacked structure 10.
[0052] See Figure 6 and Figure 7 , Figure 6 This is a fourth partial enlarged view of the metal oxide layer and barrier layer in one embodiment of this application. Figure 7 This is a fifth partial enlarged view of the metal oxide layer and barrier layer in one embodiment of this application. As one embodiment, the top surface of the metal oxide layer 23 is lower than the top surface of the stacked structure 10, that is, the top tip 24 of the metal oxide layer 23 is recessed at the top tip of the stacked structure 10, which facilitates the fabrication of the metal oxide layer 23. The top surface of the barrier layer 22 may be at the same height as or unequal to the top surface of the stacked structure 10. As an example, such as... Figure 6 As shown, the top surface of the barrier layer 22 is higher than the top surface of the stacked structure 10. As another example, such as... Figure 7 As shown, the top surface of the barrier layer 22 is lower than the top surface of the stacked structure 10.
[0053] Continue reading Figure 1 and Figure 2 The first insulating layer 30 directly contacts the sidewall of the metal core 21. Specifically, the first insulating layer 30 directly contacts the sidewall of the portion of the metal core 21 extending out of the stacked structure 10 to isolate that portion of the metal core 21. The top surface of the first insulating layer 30 can be flush with the top surface of the metal core 21, thus exposing the top surface of the metal core 21 for external connection.
[0054] In some possible examples, the first insulating layer 30 directly contacts the top surface of the barrier layer 22, that is, the top surface of the first insulating layer 30 is higher than the top surface of the barrier layer 22, so that the first insulating layer 30 covers the barrier layer 22, thereby preventing the barrier layer 22 from being exposed. For example, Figure 7 As shown, the top surface of the barrier layer 22 can be higher than the top surface of the metal oxide layer 23, so that the first insulating layer 30 also directly contacts the outer wall of the barrier layer 22. Alternatively, as... Figure 6 As shown, the top surface of the barrier layer 22 may be lower than or flush with the top surface of the metal oxide layer 23, and the first insulating layer 30 directly contacts only the top surface of the barrier layer 22.
[0055] In some possible examples, the first insulating layer 30 is also in direct contact with at least the top surface of the metal oxide layer 23, i.e., the top surface of the first insulating layer 30 is higher than the top surface of the metal oxide layer 23, so that the first insulating layer 30 covers the metal oxide layer 23. The top surface of the metal oxide layer 23 may be higher than the top surface of the stacked structure 10, so that the first insulating layer 30 directly contacts the top surface and outer sidewall of the metal oxide layer 23. Alternatively, the top surface of the metal oxide layer 23 may be lower than or flush with the top surface of the stacked structure 10, and the contact area between the first insulating layer 30 and the metal oxide layer 23 is related to the height of the top surface of the barrier layer 22. When the top surface of the barrier layer 22 is lower than the top surface of the metal oxide layer 23, the first insulating layer 30 also directly contacts the inner sidewall of the metal oxide layer 23, which refers to the sidewall of the metal oxide layer 23 near the metal core 21.
[0056] Continue reading Figure 1 and Figure 5 To increase the spacing between the metal cores 21, each metal core 21 has an inwardly extending recess 24, which is filled by the first insulating layer 30. The inward extension refers to extending towards the center of the metal core 21. Figure 1 and Figure 5 As shown, the metal core 21 includes a first portion located within the stacked structure 10 and a second portion extending outside the stacked structure 10, with the first and second portions being integral. The second portion is provided with the aforementioned recess 24, such that the first portion has a first width W1, and the second portion has a minimum second width W2, which is smaller than the first width W1, thereby increasing the spacing between the second portions. The first insulating layer 30 fills the recess 24, thereby reducing leakage current in the second portion, and further reducing leakage current in the metal core 21, thus improving the performance of the semiconductor device.
[0057] See Figure 8 , Figure 8 This is a sixth partial enlarged view of the metal oxide layer and barrier layer in one embodiment of this application. Along the direction near the top surface of the metal core 21, the depth of the recess 24 gradually increases. Thus, the portion of the metal core 21 extending outward from the stacked structure 10 gradually contracts upward, thereby gradually reducing the width of this portion of the metal core 21 upward, thus ensuring the spacing between the metal cores 21. The cross-sectional shape of the recess 24 is not limited; for example, the cross-sectional shape of the recess 24 can be trapezoidal, or it can be arc-shaped or curved.
[0058] Continue reading Figure 1Multiple stacked structures 10 can be provided, and the multiple stacked structures 10 are stacked sequentially. A third insulating layer 50 is provided between two adjacent stacked structures 10. The material of the third insulating layer 50 is different from the material of the isolation layer 12 in the stacked structure 10. For example, the material of the third insulating layer 50 includes aluminum oxide. The metal core 21 penetrates each stacked structure 10 and the third insulating layer 50 located between adjacent stacked structures 10 to make electrical connection with the substrate. The metal core 21 may protrude from the uppermost stacked structure 10 and directly contact the first insulating layer 30 on the stacked structure 10.
[0059] In summary, the semiconductor device in this embodiment includes a stacked structure 10, a connection structure 20, and a first insulating layer 30. The stacked structure 10 includes alternating metal layers 11 and isolation layers 12. The connection structure 20 penetrates the stacked structure 10 and includes a metal core 21 within the stacked structure 10, a metal oxide layer 23 on the sidewall of the metal core 21, and a barrier layer 22 between the metal oxide layer 23 and the metal core 21. The barrier layer 22 prevents metal ions within the metal core 21 from diffusing into the metal oxide layer 23, thereby ensuring the performance of the metal oxide layer 23. The top surfaces of the metal oxide layer 23 and the barrier layer 22 are not at the same height, and the metal oxide layer 23 is in direct contact with the stacked structure 10. The first insulating layer 30 directly contacts the sidewall of the metal core 21. By using the first insulating layer 30 to isolate the metal cores 21, leakage current in the metal cores 21 can be reduced, thereby improving the performance of the semiconductor device.
[0060] This application also provides a method for fabricating a semiconductor device, see embodiments below. Figure 9 , Figure 9 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. The fabrication method may specifically include the following steps:
[0061] Step S100: Form a stacked structure, which includes alternating metal layers and isolation layers.
[0062] See Figure 10 , Figure 10 Therefore, the stacked structure 10 can be formed on the second insulating layer 40 or the third insulating layer 50. The materials of the second insulating layer 40 and the third insulating layer 50 are different from the material of the stacked structure 10. The second insulating layer 40 or the third insulating layer 50 provides support for the stacked structure 10 and is separated from the underlying film layer. The stacking direction of the stacked structure 10 can be vertical. Figure 10 (As shown in the Z direction), along which the metal layer 11 and the insulating layer 12 are alternately arranged and in contact. Both the metal layer 11 and the insulating layer 12 may be provided in at least two layers.
[0063] For example, such as Figure 10As shown, four metal layers 11 and five isolation layers 12 are provided. Along the vertical direction, the four metal layers 11 and five isolation layers 12 are arranged alternately. A metal layer 11 is placed between two adjacent isolation layers 12, and an isolation layer 12 is placed between two adjacent metal layers 11. The metal layers 11 are made of metallic materials, such as tungsten or its alloys. The isolation layers 12 are made of insulating materials to isolate adjacent metal layers 11. For example, the materials of the isolation layers 12 include silicon oxide, silicon oxynitride, silicon nitride, and silicon carbonitride.
[0064] In some possible implementations, both the metal layer 11 and the isolation layer 12 can be formed by deposition processes, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). For example, the isolation layer 12 is made of silicon oxide, and its precursor includes tetraethoxysilane (TEOS).
[0065] Step S200: Form a connection structure that extends through the stacked structure. The connection structure includes a metal core located within the stacked structure, a metal oxide layer located on the sidewall of the metal core, and a barrier layer located between the metal oxide layer and the metal core. The top surfaces of the metal oxide layer and the barrier layer are not at the same height, and the metal oxide layer is in direct contact with the stacked structure.
[0066] The top surface of the metal core 21 is exposed to the top surface of the stacked structure 10 for external connection. The bottom surface of the metal core 21 is exposed to the bottom surface of the stacked structure 10 for electrical connection to the substrate. The metal core 21 may extend along the stacking direction of the stacked structure 10 to facilitate the fabrication of the metal core 21. The metal core 21 is made of a metallic material 16, such as tungsten and its alloys.
[0067] A metal oxide layer 23 is located on the sidewall of the metal core 21, and a barrier layer 22 is located between the metal oxide layer 23 and the metal core 21. By using the barrier layer 22 to separate the metal oxide layer 23 from the metal core 21, the diffusion of metal ions from the metal core 21 into the metal oxide layer 23 can be prevented, thereby ensuring the insulating properties of the metal oxide layer 23. The metal oxide layer 23 electrically isolates the metal core 21 and / or the barrier layer 22 from the stacked structure 10, thereby ensuring the electrical performance of the semiconductor device.
[0068] In this structure, the barrier layer 22 is in direct contact with the sidewall of the metal core 21, and the metal oxide layer 23 is in direct contact with the sidewall of the barrier layer 22 away from the metal core 21 (i.e., the outer sidewall of the barrier layer 22). The barrier layer 22 can be made of materials such as titanium nitride or tantalum nitride. The metal oxide layer 23 is in direct contact with the stacked structure 10. For example, the sidewall of the metal oxide layer 23 away from the metal core 21 (i.e., the outer sidewall of the metal oxide layer 23) is in direct contact with the stacked structure 10, thereby providing insulation for the stacked structure 10. The metal oxide layer 23 can be made of materials such as hafnium silicon oxide, hafnium oxide, zirconium oxide, tantalum oxide, or titanium oxide. Thus, the metal oxide layer 23 has a high dielectric constant, which improves its insulation performance.
[0069] The top surfaces of the metal oxide layer 23 and the barrier layer 22 are not at the same height; that is, the top surfaces of the metal oxide layer 23 and the barrier layer 22 are not flush. In one embodiment, the top surface of the metal oxide layer 23 is higher than the top surface of the barrier layer 22. This improves the isolation effect of the metal oxide layer 23 and effectively prevents the barrier layer 22 from contacting the stacked structure 10, especially preventing contact between the barrier layer 22 and the metal layer 11. In another embodiment, the top surface of the barrier layer 22 is higher than the top surface of the metal oxide layer 23. This improves the blocking effect of the barrier layer 22 and effectively prevents contact between the metal oxide layer 23 and the metal core 21.
[0070] Step S300: Form a first insulating layer, which directly contacts the sidewall of the metal core.
[0071] The first insulating layer 30 can be formed by a deposition process and directly contacts the sidewall of the metal core 21. Specifically, the first insulating layer 30 directly contacts the sidewall of the portion of the metal core 21 extending out of the stacked structure 10 to isolate that portion of the metal core 21. The top surface of the first insulating layer 30 can be flush with the top surface of the metal core 21, thus exposing the top surface of the metal core 21 for external connection.
[0072] The first insulating layer 30 directly contacts the top surface of the barrier layer 22, meaning the top surface of the first insulating layer 30 is higher than the top surface of the barrier layer 22. This allows the first insulating layer 30 to cover the barrier layer 22, preventing the barrier layer 22 from being exposed and reducing oxidation of the barrier layer 22. The first insulating layer 30 may also cover at least the top surface of the stacked structure 10 and the top surface of the metal oxide layer 23, meaning the top surface of the first insulating layer 30 is higher than both the top surfaces of the stacked structure 10 and the metal oxide layer 23. In this way, the barrier layer 22, the stacked structure 10, and the metal oxide layer 23 are all located below the first insulating layer 30, allowing the first insulating layer 30 to isolate and protect them.
[0073] As one possible example, the top surface of the barrier layer 22 is higher than the top surface of the metal oxide layer 23, and the first insulating layer 30 also covers the outer sidewall of the barrier layer 22. As another possible example, the top surface of the metal oxide layer 23 is higher than the top surface of the stacked structure 10, and the first insulating layer 30 also covers the outer sidewall of the metal oxide layer 23. As yet another possible example, the top surface of the metal oxide layer 23 is higher than the top surface of the barrier layer 22, and the first insulating layer 30 also covers the inner sidewall of the metal oxide layer 23. Here, the outer sidewall refers to the sidewall away from the metal core 21, and the inner sidewall refers to the sidewall closer to the metal core 21.
[0074] See Figures 11 to 18 , Figures 11 to 18 This is a schematic diagram of the formation of a connection structure in one embodiment of the present application. Forming the connection structure 20 (step S200) may include:
[0075] Step S201: Etch the stacked structure 10 to form a hole structure 13 that penetrates the stacked structure 10.
[0076] like Figure 10 and Figure 11 As shown, each metal layer 11 and each isolation layer 12 are etched using either dry etching or wet etching to form a via structure 13, which penetrates each metal layer 11 and each isolation layer 12. As a possible example, the via structure 13 may also extend to a second insulating layer 40 or a third insulating layer 50 beneath the stacked structure 10. The via structure 13 includes a plurality of spaced-apart first holes, the cross-sectional shape and arrangement of which are not limited.
[0077] Step S202: A metal oxide layer 23 is formed on the sidewall of the porous structure 13, and a barrier material 15 and a metal material 16 are deposited in sequence, with the top surface of the metal material 16 being higher than the top surface of the stacked structure 10.
[0078] As one possible implementation, the metal oxide layer 23 can be formed through the following process:
[0079] See Figure 11 and Figure 12 A metal oxide material 14 is deposited, covering the sidewalls and bottom wall of the pore structure 13, as well as the top surface of the stacked structure 10. The metal oxide material 14 does not completely fill the pore structure 13; the metal oxide material 14 located within the pore structure 13 forms a second pore.
[0080] Sacrificial material 17 is deposited, covering metal oxide material 14. Specifically, sacrificial material 17 covers the sidewalls and bottom wall of the second hole, as well as the metal oxide material 14 located above the stacked structure 10. Sacrificial material 17 does not completely fill the second hole; the sacrificial material 17 located within the second hole encloses and forms a third hole 18.
[0081] See Figure 12 and Figure 13 The sacrificial material 17 and the metal oxide material 14 are etched back to remove the metal oxide material 14 and sacrificial material 17 above the stacked structure 10, as well as the metal oxide material 14 and sacrificial material 17 at the bottom of the third hole 18. The metal oxide material 14 and sacrificial material 17 located on the sidewalls of the hole structure 13 are retained, and the remaining metal oxide material 14 forms the metal oxide layer 23. The third hole 18 may also penetrate the second insulating layer 40 or the third insulating layer 50 below the stacked structure 10 to facilitate electrical connection with the substrate.
[0082] Remove the remaining sacrificial material 17 to expose the metal oxide layer 23. The sacrificial material 17 can be polysilicon, so that the sacrificial material 17 and the metal oxide layer 23 have a certain etching selectivity, reducing the impact on the metal oxide layer 23 when removing the sacrificial material 17, thereby maintaining the metal oxide layer 23 covering the sidewalls of the hole structure 13.
[0083] See Figure 14 After forming the metal oxide layer 23, a barrier material 15 is deposited. The barrier material 15 covers the top surface of the stacked structure 10, the top surface and sidewalls of the metal oxide layer 23, and the bottom wall of the pore structure 13. The barrier material 15 does not completely fill the remaining pore structure 13. Then, a metal material 16 is deposited, covering the barrier material 15 and filling the remaining pore structure 13. The top surface of the metal material 16 is higher than the top surface of the barrier material 15. In this way, the top surface of the metal material 16 is relatively flat, which facilitates the deposition of other film layers.
[0084] Step S203: The barrier material 15 and the metal material 16 are processed by a patterning process to form a barrier layer 22 and a metal core 21, respectively. The top surface of the barrier layer 22 is higher than the top surface of the metal oxide layer 23.
[0085] See Figure 15 A protective material 19 is deposited to cover the metal material 16 to reduce the oxidation of the metal material 16. The protective material 19 can be silicon oxide, silicon nitride, silicon oxynitride, etc. (See also...) Figure 16 The protective material 19, the barrier material 15, and the metal material 16 are partially removed through processes such as coating, exposure, development, and etching. The remaining protective material 19 forms a protective layer 70, the remaining barrier material 15 forms a barrier layer 22, and the remaining metal material 16 forms a metal core 21. The protective layer 70 is located on the top surface of the metal core 21, and the barrier layer 22 is located on the sidewall of the metal core 21, with the protective layer 70, the barrier layer 22, and the sidewall of the metal core 21 being substantially aligned.
[0086] In some possible examples, the barrier layer 22 is in direct contact with the top surface of the metal oxide layer 23, meaning that a portion of the barrier layer 22 extends onto the metal oxide layer 23, and correspondingly, a portion of the metal core 21 and a portion of the protective layer 70 are located on top of the metal oxide layer 23. In other possible examples, the barrier layer 22 is offset from the metal oxide layer 23, meaning that the barrier layer 22 is not in contact with the top surface of the metal oxide layer 23.
[0087] See Figure 16 As one possible embodiment, forming the connection structure 20 (step S200) may further include: etching at least the metal core 21, wherein the metal core 21 has inwardly extending recesses 24, thereby increasing the spacing of the portions of the metal core 21 extending outward from the stacked structure 10. Thus, see... Figure 17 and Figure 18 After the first insulating layer 30 is formed, it also fills the recess 24, thereby reducing the leakage current of the metal core 21 and improving the performance of the semiconductor device.
[0088] Along the direction near the top surface of the metal core 21, the depth of the recess 24 gradually increases. This causes the portion of the metal core 21 extending outward from the stacked structure 10 to gradually contract upwards, thereby reducing the width of this portion of the metal core 21 and ensuring the spacing between the metal cores 21. The cross-sectional shape of the recess 24 is not limited; for example, the cross-sectional shape of the recess 24 can be trapezoidal, arc-shaped, or curved.
[0089] It is understood that by controlling the process parameters of etching the metal core 21, such as the composition of the etching gas and the etching temperature, the barrier layer 22 and the metal oxide layer 23 can be formed in different states. In some possible examples, the metal core 21 and the barrier layer 22 are etched, and the metal core 21 forms an inwardly extending recess 24, while the top surface of the barrier layer 22 is lowered. The top surface of the etched barrier layer 22 may still be higher than the top surface of the metal oxide layer 23, and / or higher than the top surface of the stacked structure 10. In other possible examples, the metal core 21, the barrier layer 22, and the metal oxide layer 23 are etched, and the metal core 21 forms an inwardly extending recess 24, while the top surfaces of the barrier layer 22 and the metal oxide layer 23 are lowered. When the etching rate of the barrier layer 22 is higher than the etching rate of the metal oxide layer 23, the top surface of the barrier layer 22 is lower than the top surface of the metal oxide layer 23; when the etching rate of the metal oxide layer 23 is higher than the etching rate of the barrier layer 22, the top surface of the barrier layer 22 is higher than the top surface of the metal oxide layer 23.
[0090] In summary, the semiconductor device fabrication method in this application embodiment forms a stacked structure 10 including alternating metal layers 11 and isolation layers 12, and a connection structure 20 penetrating the stacked structure 10, as well as a first insulating layer 30 directly contacting the sidewall of the metal core 21. The connection structure 20 includes a metal core 21, a metal oxide layer 23, and a barrier layer 22 located within the stacked structure 10. The metal oxide layer 23 is located on the sidewall of the metal core 21, and the barrier layer 22 is located between the metal oxide layer 23 and the metal core 21 to reduce or even prevent the diffusion of metal ions from the metal core 21 into the metal oxide layer 23, thus ensuring the performance of the metal oxide layer 23. The top surfaces of the metal oxide layer 23 and the barrier layer 22 are not at the same height, and the metal oxide layer 23 is also in direct contact with the stacked structure 10, thereby preventing the stacked structure 10 from making contact with the metal core 21 and / or the barrier layer 22, thus ensuring the performance of the semiconductor device. Using the first insulating layer 30 to isolate the metal cores 21 reduces leakage current in the metal cores 21, thereby improving the performance of the semiconductor device.
[0091] The embodiments or implementation methods described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.
[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A semiconductor device, characterized in that, include: The stacked structure includes alternating metal layers and insulating layers; A connecting structure extends through the stacked structure, the connecting structure comprising a metal core located within the stacked structure, a metal oxide layer located on the sidewall of the metal core, and a barrier layer located between the metal oxide layer and the metal core; the top surface of the metal core is higher than the top surface of the stacked structure; the barrier layer comprises titanium nitride or tantalum nitride; The first insulating layer is located on the stacked structure and directly contacts the sidewall of the metal core; The metal oxide layer and the top surface of the barrier layer are not at the same height. The metal oxide layer is in direct contact with the stacked structure. The first insulating layer is in direct contact with the top surface of the metal oxide layer and the barrier layer. The barrier layer is in direct contact with the sidewall and bottom surface of the metal core, and the top surface of the barrier layer is lower than the top surface of the metal core.
2. The semiconductor device according to claim 1, characterized in that, The metal core has an inwardly extending recess, which is filled by the first insulating layer.
3. The semiconductor device according to claim 2, characterized in that, The depth of the recess gradually increases along the direction close to the top surface of the metal core.
4. The semiconductor device according to claim 1, characterized in that, The top surface of the metal oxide layer is lower than the top surface of the stacked structure.
5. The semiconductor device according to claim 1, characterized in that, The top surface of the barrier layer is lower than the top surface of the metal oxide layer.
6. The semiconductor device according to claim 1, characterized in that, The top surface of the barrier layer is higher than the top surface of the stacked structure.
7. A method for fabricating a semiconductor device, characterized in that, include: A stacked structure is formed, the stacked structure comprising alternating metal layers and insulating layers; A connecting structure is formed, which extends through the stacked structure. The connecting structure includes a metal core located within the stacked structure, a metal oxide layer located on the sidewall of the metal core, and a barrier layer located between the metal oxide layer and the metal core. The top surfaces of the metal oxide layer and the barrier layer are not at the same height, and the metal oxide layer is in direct contact with the stacked structure. The top surface of the metal core is higher than the top surface of the stacked structure. The barrier layer includes titanium nitride or tantalum nitride. A first insulating layer is formed on the stacked structure and directly contacts the sidewall of the metal core; the first insulating layer directly contacts the top surface of the metal oxide layer and the barrier layer; the barrier layer directly contacts the sidewall and bottom surface of the metal core, and the top surface of the barrier layer is lower than the top surface of the metal core.
8. The manufacturing method according to claim 7, characterized in that, The connection structure includes: The stacked structure is etched to form a hole structure that penetrates the stacked structure; A metal oxide layer is formed on the sidewall of the porous structure, and a barrier material and a metal material are deposited sequentially, with the top surface of the metal material being higher than the top surface of the stacked structure; The barrier material and the metal material are processed by a patterning process to form the barrier layer and the metal core, respectively, with the top surface of the barrier layer being higher than the top surface of the metal oxide layer.
9. The manufacturing method according to claim 7, characterized in that, The connection structure also includes: At least the metal core is etched, forming an inwardly extending recess in the metal core.
10. The manufacturing method according to claim 9, characterized in that, The depth of the recess gradually increases along the direction close to the top surface of the metal core.